2 * dts file for AppliedMicro (APM) X-Gene Storm SOC
4 * Copyright (C) 2013, Applied Micro Circuits Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
13 compatible = "apm,xgene-storm";
14 interrupt-parent = <&gic>;
24 compatible = "apm,potenza", "arm,armv8";
26 enable-method = "spin-table";
27 cpu-release-addr = <0x1 0x0000fff8>;
31 compatible = "apm,potenza", "arm,armv8";
33 enable-method = "spin-table";
34 cpu-release-addr = <0x1 0x0000fff8>;
38 compatible = "apm,potenza", "arm,armv8";
40 enable-method = "spin-table";
41 cpu-release-addr = <0x1 0x0000fff8>;
45 compatible = "apm,potenza", "arm,armv8";
47 enable-method = "spin-table";
48 cpu-release-addr = <0x1 0x0000fff8>;
52 compatible = "apm,potenza", "arm,armv8";
54 enable-method = "spin-table";
55 cpu-release-addr = <0x1 0x0000fff8>;
59 compatible = "apm,potenza", "arm,armv8";
61 enable-method = "spin-table";
62 cpu-release-addr = <0x1 0x0000fff8>;
66 compatible = "apm,potenza", "arm,armv8";
68 enable-method = "spin-table";
69 cpu-release-addr = <0x1 0x0000fff8>;
73 compatible = "apm,potenza", "arm,armv8";
75 enable-method = "spin-table";
76 cpu-release-addr = <0x1 0x0000fff8>;
80 gic: interrupt-controller@78010000 {
81 compatible = "arm,cortex-a15-gic";
82 #interrupt-cells = <3>;
84 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
85 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
86 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
87 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
88 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
92 compatible = "arm,armv8-timer";
93 interrupts = <1 0 0xff01>, /* Secure Phys IRQ */
94 <1 13 0xff01>, /* Non-secure Phys IRQ */
95 <1 14 0xff01>, /* Virt IRQ */
96 <1 15 0xff01>; /* Hyp IRQ */
97 clock-frequency = <50000000>;
101 compatible = "simple-bus";
102 #address-cells = <2>;
107 #address-cells = <2>;
111 compatible = "fixed-clock";
113 clock-frequency = <100000000>;
114 clock-output-names = "refclk";
117 pcppll: pcppll@17000100 {
118 compatible = "apm,xgene-pcppll-clock";
120 clocks = <&refclk 0>;
121 clock-names = "pcppll";
122 reg = <0x0 0x17000100 0x0 0x1000>;
123 clock-output-names = "pcppll";
127 socpll: socpll@17000120 {
128 compatible = "apm,xgene-socpll-clock";
130 clocks = <&refclk 0>;
131 clock-names = "socpll";
132 reg = <0x0 0x17000120 0x0 0x1000>;
133 clock-output-names = "socpll";
137 socplldiv2: socplldiv2 {
138 compatible = "fixed-factor-clock";
140 clocks = <&socpll 0>;
141 clock-names = "socplldiv2";
144 clock-output-names = "socplldiv2";
148 compatible = "apm,xgene-device-clock";
150 clocks = <&socplldiv2 0>;
151 clock-names = "qmlclk";
152 reg = <0x0 0x1703C000 0x0 0x1000>;
153 reg-names = "csr-reg";
154 clock-output-names = "qmlclk";
158 compatible = "apm,xgene-device-clock";
160 clocks = <&socplldiv2 0>;
161 clock-names = "ethclk";
162 reg = <0x0 0x17000000 0x0 0x1000>;
163 reg-names = "div-reg";
164 divider-offset = <0x238>;
165 divider-width = <0x9>;
166 divider-shift = <0x0>;
167 clock-output-names = "ethclk";
171 compatible = "apm,xgene-device-clock";
173 clocks = <ðclk 0>;
174 clock-names = "eth8clk";
175 reg = <0x0 0x1702C000 0x0 0x1000>;
176 reg-names = "csr-reg";
177 clock-output-names = "eth8clk";
180 sataphy1clk: sataphy1clk@1f21c000 {
181 compatible = "apm,xgene-device-clock";
183 clocks = <&socplldiv2 0>;
184 reg = <0x0 0x1f21c000 0x0 0x1000>;
185 reg-names = "csr-reg";
186 clock-output-names = "sataphy1clk";
190 enable-offset = <0x0>;
191 enable-mask = <0x06>;
194 sataphy2clk: sataphy1clk@1f22c000 {
195 compatible = "apm,xgene-device-clock";
197 clocks = <&socplldiv2 0>;
198 reg = <0x0 0x1f22c000 0x0 0x1000>;
199 reg-names = "csr-reg";
200 clock-output-names = "sataphy2clk";
204 enable-offset = <0x0>;
205 enable-mask = <0x06>;
208 sataphy3clk: sataphy1clk@1f23c000 {
209 compatible = "apm,xgene-device-clock";
211 clocks = <&socplldiv2 0>;
212 reg = <0x0 0x1f23c000 0x0 0x1000>;
213 reg-names = "csr-reg";
214 clock-output-names = "sataphy3clk";
218 enable-offset = <0x0>;
219 enable-mask = <0x06>;
222 sata01clk: sata01clk@1f21c000 {
223 compatible = "apm,xgene-device-clock";
225 clocks = <&socplldiv2 0>;
226 reg = <0x0 0x1f21c000 0x0 0x1000>;
227 reg-names = "csr-reg";
228 clock-output-names = "sata01clk";
231 enable-offset = <0x0>;
232 enable-mask = <0x39>;
235 sata23clk: sata23clk@1f22c000 {
236 compatible = "apm,xgene-device-clock";
238 clocks = <&socplldiv2 0>;
239 reg = <0x0 0x1f22c000 0x0 0x1000>;
240 reg-names = "csr-reg";
241 clock-output-names = "sata23clk";
244 enable-offset = <0x0>;
245 enable-mask = <0x39>;
248 sata45clk: sata45clk@1f23c000 {
249 compatible = "apm,xgene-device-clock";
251 clocks = <&socplldiv2 0>;
252 reg = <0x0 0x1f23c000 0x0 0x1000>;
253 reg-names = "csr-reg";
254 clock-output-names = "sata45clk";
257 enable-offset = <0x0>;
258 enable-mask = <0x39>;
261 rtcclk: rtcclk@17000000 {
262 compatible = "apm,xgene-device-clock";
264 clocks = <&socplldiv2 0>;
265 reg = <0x0 0x17000000 0x0 0x2000>;
266 reg-names = "csr-reg";
269 enable-offset = <0x10>;
271 clock-output-names = "rtcclk";
275 serial0: serial@1c020000 {
277 device_type = "serial";
278 compatible = "ns16550a";
279 reg = <0 0x1c020000 0x0 0x1000>;
281 clock-frequency = <10000000>; /* Updated by bootloader */
282 interrupt-parent = <&gic>;
283 interrupts = <0x0 0x4c 0x4>;
286 serial1: serial@1c021000 {
288 device_type = "serial";
289 compatible = "ns16550a";
290 reg = <0 0x1c021000 0x0 0x1000>;
292 clock-frequency = <10000000>; /* Updated by bootloader */
293 interrupt-parent = <&gic>;
294 interrupts = <0x0 0x4d 0x4>;
297 serial2: serial@1c022000 {
299 device_type = "serial";
300 compatible = "ns16550a";
301 reg = <0 0x1c022000 0x0 0x1000>;
303 clock-frequency = <10000000>; /* Updated by bootloader */
304 interrupt-parent = <&gic>;
305 interrupts = <0x0 0x4e 0x4>;
308 serial3: serial@1c023000 {
310 device_type = "serial";
311 compatible = "ns16550a";
312 reg = <0 0x1c023000 0x0 0x1000>;
314 clock-frequency = <10000000>; /* Updated by bootloader */
315 interrupt-parent = <&gic>;
316 interrupts = <0x0 0x4f 0x4>;
320 compatible = "apm,xgene-phy";
321 reg = <0x0 0x1f21a000 0x0 0x100>;
323 clocks = <&sataphy1clk 0>;
325 apm,tx-boost-gain = <30 30 30 30 30 30>;
326 apm,tx-eye-tuning = <2 10 10 2 10 10>;
330 compatible = "apm,xgene-phy";
331 reg = <0x0 0x1f22a000 0x0 0x100>;
333 clocks = <&sataphy2clk 0>;
335 apm,tx-boost-gain = <30 30 30 30 30 30>;
336 apm,tx-eye-tuning = <1 10 10 2 10 10>;
340 compatible = "apm,xgene-phy";
341 reg = <0x0 0x1f23a000 0x0 0x100>;
343 clocks = <&sataphy3clk 0>;
345 apm,tx-boost-gain = <31 31 31 31 31 31>;
346 apm,tx-eye-tuning = <2 10 10 2 10 10>;
349 sata1: sata@1a000000 {
350 compatible = "apm,xgene-ahci";
351 reg = <0x0 0x1a000000 0x0 0x1000>,
352 <0x0 0x1f210000 0x0 0x1000>,
353 <0x0 0x1f21d000 0x0 0x1000>,
354 <0x0 0x1f21e000 0x0 0x1000>,
355 <0x0 0x1f217000 0x0 0x1000>;
356 interrupts = <0x0 0x86 0x4>;
358 clocks = <&sata01clk 0>;
360 phy-names = "sata-phy";
363 sata2: sata@1a400000 {
364 compatible = "apm,xgene-ahci";
365 reg = <0x0 0x1a400000 0x0 0x1000>,
366 <0x0 0x1f220000 0x0 0x1000>,
367 <0x0 0x1f22d000 0x0 0x1000>,
368 <0x0 0x1f22e000 0x0 0x1000>,
369 <0x0 0x1f227000 0x0 0x1000>;
370 interrupts = <0x0 0x87 0x4>;
372 clocks = <&sata23clk 0>;
374 phy-names = "sata-phy";
377 sata3: sata@1a800000 {
378 compatible = "apm,xgene-ahci";
379 reg = <0x0 0x1a800000 0x0 0x1000>,
380 <0x0 0x1f230000 0x0 0x1000>,
381 <0x0 0x1f23d000 0x0 0x1000>,
382 <0x0 0x1f23e000 0x0 0x1000>;
383 interrupts = <0x0 0x88 0x4>;
385 clocks = <&sata45clk 0>;
387 phy-names = "sata-phy";
391 compatible = "apm,xgene-rtc";
392 reg = <0x0 0x10510000 0x0 0x400>;
393 interrupts = <0x0 0x46 0x4>;
395 clocks = <&rtcclk 0>;