3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
16 select ARCH_HAS_UBSAN_SANITIZE_ALL
20 select AUDIT_ARCH_COMPAT_GENERIC
21 select ARM_GIC_V2M if PCI_MSI
23 select ARM_GIC_V3_ITS if PCI_MSI
25 select BUILDTIME_EXTABLE_SORT
26 select CLONE_BACKWARDS
28 select CPU_PM if (SUSPEND || CPU_IDLE)
29 select DCACHE_WORD_ACCESS
32 select GENERIC_ALLOCATOR
33 select GENERIC_CLOCKEVENTS
34 select GENERIC_CLOCKEVENTS_BROADCAST
35 select GENERIC_CPU_AUTOPROBE
36 select GENERIC_EARLY_IOREMAP
37 select GENERIC_IDLE_POLL_SETUP
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_SHOW_LEVEL
41 select GENERIC_PCI_IOMAP
42 select GENERIC_SCHED_CLOCK
43 select GENERIC_SMP_IDLE_THREAD
44 select GENERIC_STRNCPY_FROM_USER
45 select GENERIC_STRNLEN_USER
46 select GENERIC_TIME_VSYSCALL
47 select HANDLE_DOMAIN_IRQ
48 select HARDIRQS_SW_RESEND
49 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
50 select HAVE_ARCH_AUDITSYSCALL
51 select HAVE_ARCH_BITREVERSE
52 select HAVE_ARCH_HARDENED_USERCOPY
53 select HAVE_ARCH_HUGE_VMAP
54 select HAVE_ARCH_JUMP_LABEL
55 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
57 select HAVE_ARCH_SECCOMP_FILTER
58 select HAVE_ARCH_TRACEHOOK
60 select HAVE_C_RECORDMCOUNT
61 select HAVE_CC_STACKPROTECTOR
62 select HAVE_CMPXCHG_DOUBLE
63 select HAVE_CMPXCHG_LOCAL
64 select HAVE_DEBUG_BUGVERBOSE
65 select HAVE_DEBUG_KMEMLEAK
66 select HAVE_DMA_API_DEBUG
68 select HAVE_DMA_CONTIGUOUS
69 select HAVE_DYNAMIC_FTRACE
70 select HAVE_EFFICIENT_UNALIGNED_ACCESS
71 select HAVE_FTRACE_MCOUNT_RECORD
72 select HAVE_FUNCTION_TRACER
73 select HAVE_FUNCTION_GRAPH_TRACER
74 select HAVE_GENERIC_DMA_COHERENT
75 select HAVE_HW_BREAKPOINT if PERF_EVENTS
76 select HAVE_IRQ_TIME_ACCOUNTING
78 select HAVE_PATA_PLATFORM
79 select HAVE_PERF_EVENTS
81 select HAVE_PERF_USER_STACK_DUMP
82 select HAVE_RCU_TABLE_FREE
83 select HAVE_SYSCALL_TRACEPOINTS
84 select IOMMU_DMA if IOMMU_SUPPORT
86 select IRQ_FORCED_THREADING
87 select MODULES_USE_ELF_RELA
90 select OF_EARLY_FLATTREE
91 select OF_RESERVED_MEM
92 select PERF_USE_VMALLOC
97 select SYSCTL_EXCEPTION_TRACE
98 select HAVE_CONTEXT_TRACKING
100 ARM 64-bit (AArch64) Linux support.
105 config ARCH_PHYS_ADDR_T_64BIT
114 config STACKTRACE_SUPPORT
117 config ILLEGAL_POINTER_VALUE
119 default 0xdead000000000000
121 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
127 config RWSEM_XCHGADD_ALGORITHM
134 config GENERIC_BUG_RELATIVE_POINTERS
136 depends on GENERIC_BUG
138 config GENERIC_HWEIGHT
144 config GENERIC_CALIBRATE_DELAY
150 config HAVE_GENERIC_RCU_GUP
153 config ARCH_DMA_ADDR_T_64BIT
156 config NEED_DMA_MAP_STATE
159 config NEED_SG_DMA_LENGTH
171 config KERNEL_MODE_NEON
174 config FIX_EARLYCON_MEM
177 config PGTABLE_LEVELS
179 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
180 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
181 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
182 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
183 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
184 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
186 source "init/Kconfig"
188 source "kernel/Kconfig.freezer"
190 source "arch/arm64/Kconfig.platforms"
197 This feature enables support for PCI bus system. If you say Y
198 here, the kernel will include drivers and infrastructure code
199 to support PCI bus devices.
204 config PCI_DOMAINS_GENERIC
210 source "drivers/pci/Kconfig"
211 source "drivers/pci/pcie/Kconfig"
212 source "drivers/pci/hotplug/Kconfig"
216 menu "Kernel Features"
218 menu "ARM errata workarounds via the alternatives framework"
220 config ARM64_ERRATUM_826319
221 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
224 This option adds an alternative code sequence to work around ARM
225 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
226 AXI master interface and an L2 cache.
228 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
229 and is unable to accept a certain write via this interface, it will
230 not progress on read data presented on the read data channel and the
233 The workaround promotes data cache clean instructions to
234 data cache clean-and-invalidate.
235 Please note that this does not necessarily enable the workaround,
236 as it depends on the alternative framework, which will only patch
237 the kernel if an affected CPU is detected.
241 config ARM64_ERRATUM_827319
242 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
245 This option adds an alternative code sequence to work around ARM
246 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
247 master interface and an L2 cache.
249 Under certain conditions this erratum can cause a clean line eviction
250 to occur at the same time as another transaction to the same address
251 on the AMBA 5 CHI interface, which can cause data corruption if the
252 interconnect reorders the two transactions.
254 The workaround promotes data cache clean instructions to
255 data cache clean-and-invalidate.
256 Please note that this does not necessarily enable the workaround,
257 as it depends on the alternative framework, which will only patch
258 the kernel if an affected CPU is detected.
262 config ARM64_ERRATUM_824069
263 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
266 This option adds an alternative code sequence to work around ARM
267 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
268 to a coherent interconnect.
270 If a Cortex-A53 processor is executing a store or prefetch for
271 write instruction at the same time as a processor in another
272 cluster is executing a cache maintenance operation to the same
273 address, then this erratum might cause a clean cache line to be
274 incorrectly marked as dirty.
276 The workaround promotes data cache clean instructions to
277 data cache clean-and-invalidate.
278 Please note that this option does not necessarily enable the
279 workaround, as it depends on the alternative framework, which will
280 only patch the kernel if an affected CPU is detected.
284 config ARM64_ERRATUM_819472
285 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
288 This option adds an alternative code sequence to work around ARM
289 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
290 present when it is connected to a coherent interconnect.
292 If the processor is executing a load and store exclusive sequence at
293 the same time as a processor in another cluster is executing a cache
294 maintenance operation to the same address, then this erratum might
295 cause data corruption.
297 The workaround promotes data cache clean instructions to
298 data cache clean-and-invalidate.
299 Please note that this does not necessarily enable the workaround,
300 as it depends on the alternative framework, which will only patch
301 the kernel if an affected CPU is detected.
305 config ARM64_ERRATUM_832075
306 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
309 This option adds an alternative code sequence to work around ARM
310 erratum 832075 on Cortex-A57 parts up to r1p2.
312 Affected Cortex-A57 parts might deadlock when exclusive load/store
313 instructions to Write-Back memory are mixed with Device loads.
315 The workaround is to promote device loads to use Load-Acquire
317 Please note that this does not necessarily enable the workaround,
318 as it depends on the alternative framework, which will only patch
319 the kernel if an affected CPU is detected.
323 config ARM64_ERRATUM_834220
324 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
328 This option adds an alternative code sequence to work around ARM
329 erratum 834220 on Cortex-A57 parts up to r1p2.
331 Affected Cortex-A57 parts might report a Stage 2 translation
332 fault as the result of a Stage 1 fault for load crossing a
333 page boundary when there is a permission or device memory
334 alignment fault at Stage 1 and a translation fault at Stage 2.
336 The workaround is to verify that the Stage 1 translation
337 doesn't generate a fault before handling the Stage 2 fault.
338 Please note that this does not necessarily enable the workaround,
339 as it depends on the alternative framework, which will only patch
340 the kernel if an affected CPU is detected.
344 config ARM64_ERRATUM_845719
345 bool "Cortex-A53: 845719: a load might read incorrect data"
349 This option adds an alternative code sequence to work around ARM
350 erratum 845719 on Cortex-A53 parts up to r0p4.
352 When running a compat (AArch32) userspace on an affected Cortex-A53
353 part, a load at EL0 from a virtual address that matches the bottom 32
354 bits of the virtual address used by a recent load at (AArch64) EL1
355 might return incorrect data.
357 The workaround is to write the contextidr_el1 register on exception
358 return to a 32-bit task.
359 Please note that this does not necessarily enable the workaround,
360 as it depends on the alternative framework, which will only patch
361 the kernel if an affected CPU is detected.
365 config ARM64_ERRATUM_843419
366 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
369 select ARM64_MODULE_CMODEL_LARGE
371 This option builds kernel modules using the large memory model in
372 order to avoid the use of the ADRP instruction, which can cause
373 a subsequent memory access to use an incorrect address on Cortex-A53
376 Note that the kernel itself must be linked with a version of ld
377 which fixes potentially affected ADRP instructions through the
382 config CAVIUM_ERRATUM_22375
383 bool "Cavium erratum 22375, 24313"
386 Enable workaround for erratum 22375, 24313.
388 This implements two gicv3-its errata workarounds for ThunderX. Both
389 with small impact affecting only ITS table allocation.
391 erratum 22375: only alloc 8MB table size
392 erratum 24313: ignore memory access type
394 The fixes are in ITS initialization and basically ignore memory access
395 type and table size provided by the TYPER and BASER registers.
399 config CAVIUM_ERRATUM_23144
400 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
404 ITS SYNC command hang for cross node io and collections/cpu mapping.
408 config CAVIUM_ERRATUM_23154
409 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
412 The gicv3 of ThunderX requires a modified version for
413 reading the IAR status to ensure data synchronization
414 (access to icc_iar1_el1 is not sync'ed before and after).
418 config CAVIUM_ERRATUM_27456
419 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
422 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
423 instructions may cause the icache to become corrupted if it
424 contains data for a non-current ASID. The fix is to
425 invalidate the icache when changing the mm context.
434 default ARM64_4K_PAGES
436 Page size (translation granule) configuration.
438 config ARM64_4K_PAGES
441 This feature enables 4KB pages support.
443 config ARM64_16K_PAGES
446 The system will use 16KB pages support. AArch32 emulation
447 requires applications compiled with 16K (or a multiple of 16K)
450 config ARM64_64K_PAGES
453 This feature enables 64KB pages support (4KB by default)
454 allowing only two levels of page tables and faster TLB
455 look-up. AArch32 emulation requires applications compiled
456 with 64K aligned segments.
461 prompt "Virtual address space size"
462 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
463 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
464 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
466 Allows choosing one of multiple possible virtual address
467 space sizes. The level of translation table is determined by
468 a combination of page size and virtual address space size.
470 config ARM64_VA_BITS_36
471 bool "36-bit" if EXPERT
472 depends on ARM64_16K_PAGES
474 config ARM64_VA_BITS_39
476 depends on ARM64_4K_PAGES
478 config ARM64_VA_BITS_42
480 depends on ARM64_64K_PAGES
482 config ARM64_VA_BITS_47
484 depends on ARM64_16K_PAGES
486 config ARM64_VA_BITS_48
493 default 36 if ARM64_VA_BITS_36
494 default 39 if ARM64_VA_BITS_39
495 default 42 if ARM64_VA_BITS_42
496 default 47 if ARM64_VA_BITS_47
497 default 48 if ARM64_VA_BITS_48
499 config CPU_BIG_ENDIAN
500 bool "Build big-endian kernel"
502 Say Y if you plan on running a kernel in big-endian mode.
505 bool "Multi-core scheduler support"
507 Multi-core scheduler support improves the CPU scheduler's decision
508 making when dealing with multi-core CPU chips at a cost of slightly
509 increased overhead in some places. If unsure say N here.
512 bool "SMT scheduler support"
514 Improves the CPU scheduler's decision making when dealing with
515 MultiThreading at a cost of slightly increased overhead in some
516 places. If unsure say N here.
519 int "Maximum number of CPUs (2-4096)"
521 # These have to remain sorted largest to smallest
525 bool "Support for hot-pluggable CPUs"
526 select GENERIC_IRQ_MIGRATION
528 Say Y here to experiment with turning CPUs off and on. CPUs
529 can be controlled through /sys/devices/system/cpu.
531 source kernel/Kconfig.preempt
532 source kernel/Kconfig.hz
534 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
537 config ARCH_HAS_HOLES_MEMORYMODEL
538 def_bool y if SPARSEMEM
540 config ARCH_SPARSEMEM_ENABLE
542 select SPARSEMEM_VMEMMAP_ENABLE
544 config ARCH_SPARSEMEM_DEFAULT
545 def_bool ARCH_SPARSEMEM_ENABLE
547 config ARCH_SELECT_MEMORY_MODEL
548 def_bool ARCH_SPARSEMEM_ENABLE
550 config HAVE_ARCH_PFN_VALID
551 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
553 config HW_PERF_EVENTS
557 config SYS_SUPPORTS_HUGETLBFS
560 config ARCH_WANT_HUGE_PMD_SHARE
561 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
563 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
566 config ARCH_HAS_CACHE_LINE_SIZE
572 bool "Enable seccomp to safely compute untrusted bytecode"
574 This kernel feature is useful for number crunching applications
575 that may need to compute untrusted bytecode during their
576 execution. By using pipes or other transports made available to
577 the process as file descriptors supporting the read/write
578 syscalls, it's possible to isolate those applications in
579 their own address space using seccomp. Once seccomp is
580 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
581 and the task is only allowed to execute a few safe syscalls
582 defined by each seccomp mode.
589 bool "Xen guest support on ARM64"
590 depends on ARM64 && OF
593 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
595 config FORCE_MAX_ZONEORDER
597 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
598 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
601 The kernel memory allocator divides physically contiguous memory
602 blocks into "zones", where each zone is a power of two number of
603 pages. This option selects the largest power of two that the kernel
604 keeps in the memory allocator. If you need to allocate very large
605 blocks of physically contiguous memory, then you may need to
608 This config option is actually maximum order plus one. For example,
609 a value of 11 means that the largest free memory block is 2^10 pages.
611 We make sure that we can allocate upto a HugePage size for each configuration.
613 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
615 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
616 4M allocations matching the default size used by generic code.
618 menuconfig ARMV8_DEPRECATED
619 bool "Emulate deprecated/obsolete ARMv8 instructions"
622 Legacy software support may require certain instructions
623 that have been deprecated or obsoleted in the architecture.
625 Enable this config to enable selective emulation of these
633 bool "Emulate SWP/SWPB instructions"
635 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
636 they are always undefined. Say Y here to enable software
637 emulation of these instructions for userspace using LDXR/STXR.
639 In some older versions of glibc [<=2.8] SWP is used during futex
640 trylock() operations with the assumption that the code will not
641 be preempted. This invalid assumption may be more likely to fail
642 with SWP emulation enabled, leading to deadlock of the user
645 NOTE: when accessing uncached shared regions, LDXR/STXR rely
646 on an external transaction monitoring block called a global
647 monitor to maintain update atomicity. If your system does not
648 implement a global monitor, this option can cause programs that
649 perform SWP operations to uncached memory to deadlock.
653 config CP15_BARRIER_EMULATION
654 bool "Emulate CP15 Barrier instructions"
656 The CP15 barrier instructions - CP15ISB, CP15DSB, and
657 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
658 strongly recommended to use the ISB, DSB, and DMB
659 instructions instead.
661 Say Y here to enable software emulation of these
662 instructions for AArch32 userspace code. When this option is
663 enabled, CP15 barrier usage is traced which can help
664 identify software that needs updating.
668 config SETEND_EMULATION
669 bool "Emulate SETEND instruction"
671 The SETEND instruction alters the data-endianness of the
672 AArch32 EL0, and is deprecated in ARMv8.
674 Say Y here to enable software emulation of the instruction
675 for AArch32 userspace code.
677 Note: All the cpus on the system must have mixed endian support at EL0
678 for this feature to be enabled. If a new CPU - which doesn't support mixed
679 endian - is hotplugged in after this feature has been enabled, there could
680 be unexpected results in the applications.
685 menu "ARMv8.1 architectural features"
687 config ARM64_HW_AFDBM
688 bool "Support for hardware updates of the Access and Dirty page flags"
691 The ARMv8.1 architecture extensions introduce support for
692 hardware updates of the access and dirty information in page
693 table entries. When enabled in TCR_EL1 (HA and HD bits) on
694 capable processors, accesses to pages with PTE_AF cleared will
695 set this bit instead of raising an access flag fault.
696 Similarly, writes to read-only pages with the DBM bit set will
697 clear the read-only bit (AP[2]) instead of raising a
700 Kernels built with this configuration option enabled continue
701 to work on pre-ARMv8.1 hardware and the performance impact is
702 minimal. If unsure, say Y.
705 bool "Enable support for Privileged Access Never (PAN)"
708 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
709 prevents the kernel or hypervisor from accessing user-space (EL0)
712 Choosing this option will cause any unprotected (not using
713 copy_to_user et al) memory access to fail with a permission fault.
715 The feature is detected at runtime, and will remain as a 'nop'
716 instruction if the cpu does not implement the feature.
718 config ARM64_LSE_ATOMICS
719 bool "Atomic instructions"
721 As part of the Large System Extensions, ARMv8.1 introduces new
722 atomic instructions that are designed specifically to scale in
725 Say Y here to make use of these instructions for the in-kernel
726 atomic routines. This incurs a small overhead on CPUs that do
727 not support these instructions and requires the kernel to be
728 built with binutils >= 2.25.
733 bool "Enable support for User Access Override (UAO)"
736 User Access Override (UAO; part of the ARMv8.2 Extensions)
737 causes the 'unprivileged' variant of the load/store instructions to
738 be overriden to be privileged.
740 This option changes get_user() and friends to use the 'unprivileged'
741 variant of the load/store instructions. This ensures that user-space
742 really did have access to the supplied memory. When addr_limit is
743 set to kernel memory the UAO bit will be set, allowing privileged
744 access to kernel memory.
746 Choosing this option will cause copy_to_user() et al to use user-space
749 The feature is detected at runtime, the kernel will use the
750 regular load/store instructions if the cpu does not implement the
753 config ARM64_MODULE_CMODEL_LARGE
756 config ARM64_MODULE_PLTS
758 select ARM64_MODULE_CMODEL_LARGE
759 select HAVE_MOD_ARCH_SPECIFIC
764 This builds the kernel as a Position Independent Executable (PIE),
765 which retains all relocation metadata required to relocate the
766 kernel binary at runtime to a different virtual address than the
767 address it was linked at.
768 Since AArch64 uses the RELA relocation format, this requires a
769 relocation pass at runtime even if the kernel is loaded at the
770 same address it was linked at.
772 config RANDOMIZE_BASE
773 bool "Randomize the address of the kernel image"
774 select ARM64_MODULE_PLTS
777 Randomizes the virtual address at which the kernel image is
778 loaded, as a security feature that deters exploit attempts
779 relying on knowledge of the location of kernel internals.
781 It is the bootloader's job to provide entropy, by passing a
782 random u64 value in /chosen/kaslr-seed at kernel entry.
784 When booting via the UEFI stub, it will invoke the firmware's
785 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
786 to the kernel proper. In addition, it will randomise the physical
787 location of the kernel Image as well.
791 config RANDOMIZE_MODULE_REGION_FULL
792 bool "Randomize the module region independently from the core kernel"
793 depends on RANDOMIZE_BASE
796 Randomizes the location of the module region without considering the
797 location of the core kernel. This way, it is impossible for modules
798 to leak information about the location of core kernel data structures
799 but it does imply that function calls between modules and the core
800 kernel will need to be resolved via veneers in the module PLT.
802 When this option is not set, the module region will be randomized over
803 a limited range that contains the [_stext, _etext] interval of the
804 core kernel, so branch relocations are always in range.
810 config ARM64_ACPI_PARKING_PROTOCOL
811 bool "Enable support for the ARM64 ACPI parking protocol"
814 Enable support for the ARM64 ACPI parking protocol. If disabled
815 the kernel will not allow booting through the ARM64 ACPI parking
816 protocol even if the corresponding data is present in the ACPI
820 string "Default kernel command string"
823 Provide a set of default command-line options at build time by
824 entering them here. As a minimum, you should specify the the
825 root device (e.g. root=/dev/nfs).
828 bool "Always use the default kernel command string"
830 Always use the default kernel command string, even if the boot
831 loader passes other arguments to the kernel.
832 This is useful if you cannot or don't want to change the
833 command-line options your boot loader passes to the kernel.
839 bool "UEFI runtime support"
840 depends on OF && !CPU_BIG_ENDIAN
843 select EFI_PARAMS_FROM_FDT
844 select EFI_RUNTIME_WRAPPERS
849 This option provides support for runtime services provided
850 by UEFI firmware (such as non-volatile variables, realtime
851 clock, and platform reset). A UEFI stub is also provided to
852 allow the kernel to be booted as an EFI application. This
853 is only useful on systems that have UEFI firmware.
856 bool "Enable support for SMBIOS (DMI) tables"
860 This enables SMBIOS/DMI feature for systems.
862 This option is only useful on systems that have UEFI firmware.
863 However, even with this option, the resultant kernel should
864 continue to boot on existing non-UEFI platforms.
868 menu "Userspace binary formats"
870 source "fs/Kconfig.binfmt"
873 bool "Kernel support for 32-bit EL0"
874 depends on ARM64_4K_PAGES || EXPERT
875 select COMPAT_BINFMT_ELF
877 select OLD_SIGSUSPEND3
878 select COMPAT_OLD_SIGACTION
880 This option enables support for a 32-bit EL0 running under a 64-bit
881 kernel at EL1. AArch32-specific components such as system calls,
882 the user helper functions, VFP support and the ptrace interface are
883 handled appropriately by the kernel.
885 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
886 that you will only be able to execute AArch32 binaries that were compiled
887 with page size aligned segments.
889 If you want to execute 32-bit userspace applications, say Y.
891 config SYSVIPC_COMPAT
893 depends on COMPAT && SYSVIPC
897 menu "Power management options"
899 source "kernel/power/Kconfig"
901 config ARCH_SUSPEND_POSSIBLE
906 menu "CPU Power Management"
908 source "drivers/cpuidle/Kconfig"
910 source "drivers/cpufreq/Kconfig"
916 source "drivers/Kconfig"
918 source "drivers/firmware/Kconfig"
920 source "drivers/acpi/Kconfig"
924 source "arch/arm64/kvm/Kconfig"
926 source "arch/arm64/Kconfig.debug"
928 source "security/Kconfig"
930 source "crypto/Kconfig"
932 source "arch/arm64/crypto/Kconfig"