3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
19 select AUDIT_ARCH_COMPAT_GENERIC
20 select ARM_GIC_V2M if PCI_MSI
22 select ARM_GIC_V3_ITS if PCI_MSI
24 select BUILDTIME_EXTABLE_SORT
25 select CLONE_BACKWARDS
27 select CPU_PM if (SUSPEND || CPU_IDLE)
28 select DCACHE_WORD_ACCESS
31 select GENERIC_ALLOCATOR
32 select GENERIC_CLOCKEVENTS
33 select GENERIC_CLOCKEVENTS_BROADCAST
34 select GENERIC_CPU_AUTOPROBE
35 select GENERIC_EARLY_IOREMAP
36 select GENERIC_IDLE_POLL_SETUP
37 select GENERIC_IRQ_PROBE
38 select GENERIC_IRQ_SHOW
39 select GENERIC_IRQ_SHOW_LEVEL
40 select GENERIC_PCI_IOMAP
41 select GENERIC_SCHED_CLOCK
42 select GENERIC_SMP_IDLE_THREAD
43 select GENERIC_STRNCPY_FROM_USER
44 select GENERIC_STRNLEN_USER
45 select GENERIC_TIME_VSYSCALL
46 select HANDLE_DOMAIN_IRQ
47 select HARDIRQS_SW_RESEND
48 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
49 select HAVE_ARCH_AUDITSYSCALL
50 select HAVE_ARCH_BITREVERSE
51 select HAVE_ARCH_JUMP_LABEL
52 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
54 select HAVE_ARCH_SECCOMP_FILTER
55 select HAVE_ARCH_TRACEHOOK
57 select HAVE_C_RECORDMCOUNT
58 select HAVE_CC_STACKPROTECTOR
59 select HAVE_CMPXCHG_DOUBLE
60 select HAVE_CMPXCHG_LOCAL
61 select HAVE_DEBUG_BUGVERBOSE
62 select HAVE_DEBUG_KMEMLEAK
63 select HAVE_DMA_API_DEBUG
65 select HAVE_DMA_CONTIGUOUS
66 select HAVE_DYNAMIC_FTRACE
67 select HAVE_EFFICIENT_UNALIGNED_ACCESS
68 select HAVE_FTRACE_MCOUNT_RECORD
69 select HAVE_FUNCTION_TRACER
70 select HAVE_FUNCTION_GRAPH_TRACER
71 select HAVE_GENERIC_DMA_COHERENT
72 select HAVE_HW_BREAKPOINT if PERF_EVENTS
74 select HAVE_PATA_PLATFORM
75 select HAVE_PERF_EVENTS
77 select HAVE_PERF_USER_STACK_DUMP
78 select HAVE_REGS_AND_STACK_ACCESS_API
79 select HAVE_RCU_TABLE_FREE
80 select HAVE_SYSCALL_TRACEPOINTS
82 select HAVE_KRETPROBES if HAVE_KPROBES
83 select IOMMU_DMA if IOMMU_SUPPORT
85 select IRQ_FORCED_THREADING
86 select MODULES_USE_ELF_RELA
89 select OF_EARLY_FLATTREE
90 select OF_RESERVED_MEM
91 select PERF_USE_VMALLOC
96 select SYSCTL_EXCEPTION_TRACE
97 select HAVE_CONTEXT_TRACKING
100 ARM 64-bit (AArch64) Linux support.
105 config ARCH_PHYS_ADDR_T_64BIT
114 config STACKTRACE_SUPPORT
117 config ILLEGAL_POINTER_VALUE
119 default 0xdead000000000000
121 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
127 config RWSEM_XCHGADD_ALGORITHM
134 config GENERIC_BUG_RELATIVE_POINTERS
136 depends on GENERIC_BUG
138 config GENERIC_HWEIGHT
144 config GENERIC_CALIBRATE_DELAY
150 config HAVE_GENERIC_RCU_GUP
153 config ARCH_DMA_ADDR_T_64BIT
156 config NEED_DMA_MAP_STATE
159 config NEED_SG_DMA_LENGTH
171 config KERNEL_MODE_NEON
174 config FIX_EARLYCON_MEM
177 config PGTABLE_LEVELS
179 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
180 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
181 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
182 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
183 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
184 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
186 source "init/Kconfig"
188 source "kernel/Kconfig.freezer"
190 source "arch/arm64/Kconfig.platforms"
197 This feature enables support for PCI bus system. If you say Y
198 here, the kernel will include drivers and infrastructure code
199 to support PCI bus devices.
204 config PCI_DOMAINS_GENERIC
210 source "drivers/pci/Kconfig"
211 source "drivers/pci/pcie/Kconfig"
212 source "drivers/pci/hotplug/Kconfig"
216 menu "Kernel Features"
218 menu "ARM errata workarounds via the alternatives framework"
220 config ARM64_ERRATUM_826319
221 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
224 This option adds an alternative code sequence to work around ARM
225 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
226 AXI master interface and an L2 cache.
228 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
229 and is unable to accept a certain write via this interface, it will
230 not progress on read data presented on the read data channel and the
233 The workaround promotes data cache clean instructions to
234 data cache clean-and-invalidate.
235 Please note that this does not necessarily enable the workaround,
236 as it depends on the alternative framework, which will only patch
237 the kernel if an affected CPU is detected.
241 config ARM64_ERRATUM_827319
242 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
245 This option adds an alternative code sequence to work around ARM
246 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
247 master interface and an L2 cache.
249 Under certain conditions this erratum can cause a clean line eviction
250 to occur at the same time as another transaction to the same address
251 on the AMBA 5 CHI interface, which can cause data corruption if the
252 interconnect reorders the two transactions.
254 The workaround promotes data cache clean instructions to
255 data cache clean-and-invalidate.
256 Please note that this does not necessarily enable the workaround,
257 as it depends on the alternative framework, which will only patch
258 the kernel if an affected CPU is detected.
262 config ARM64_ERRATUM_824069
263 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
266 This option adds an alternative code sequence to work around ARM
267 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
268 to a coherent interconnect.
270 If a Cortex-A53 processor is executing a store or prefetch for
271 write instruction at the same time as a processor in another
272 cluster is executing a cache maintenance operation to the same
273 address, then this erratum might cause a clean cache line to be
274 incorrectly marked as dirty.
276 The workaround promotes data cache clean instructions to
277 data cache clean-and-invalidate.
278 Please note that this option does not necessarily enable the
279 workaround, as it depends on the alternative framework, which will
280 only patch the kernel if an affected CPU is detected.
284 config ARM64_ERRATUM_819472
285 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
288 This option adds an alternative code sequence to work around ARM
289 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
290 present when it is connected to a coherent interconnect.
292 If the processor is executing a load and store exclusive sequence at
293 the same time as a processor in another cluster is executing a cache
294 maintenance operation to the same address, then this erratum might
295 cause data corruption.
297 The workaround promotes data cache clean instructions to
298 data cache clean-and-invalidate.
299 Please note that this does not necessarily enable the workaround,
300 as it depends on the alternative framework, which will only patch
301 the kernel if an affected CPU is detected.
305 config ARM64_ERRATUM_832075
306 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
309 This option adds an alternative code sequence to work around ARM
310 erratum 832075 on Cortex-A57 parts up to r1p2.
312 Affected Cortex-A57 parts might deadlock when exclusive load/store
313 instructions to Write-Back memory are mixed with Device loads.
315 The workaround is to promote device loads to use Load-Acquire
317 Please note that this does not necessarily enable the workaround,
318 as it depends on the alternative framework, which will only patch
319 the kernel if an affected CPU is detected.
323 config ARM64_ERRATUM_834220
324 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
328 This option adds an alternative code sequence to work around ARM
329 erratum 834220 on Cortex-A57 parts up to r1p2.
331 Affected Cortex-A57 parts might report a Stage 2 translation
332 fault as the result of a Stage 1 fault for load crossing a
333 page boundary when there is a permission or device memory
334 alignment fault at Stage 1 and a translation fault at Stage 2.
336 The workaround is to verify that the Stage 1 translation
337 doesn't generate a fault before handling the Stage 2 fault.
338 Please note that this does not necessarily enable the workaround,
339 as it depends on the alternative framework, which will only patch
340 the kernel if an affected CPU is detected.
344 config ARM64_ERRATUM_845719
345 bool "Cortex-A53: 845719: a load might read incorrect data"
349 This option adds an alternative code sequence to work around ARM
350 erratum 845719 on Cortex-A53 parts up to r0p4.
352 When running a compat (AArch32) userspace on an affected Cortex-A53
353 part, a load at EL0 from a virtual address that matches the bottom 32
354 bits of the virtual address used by a recent load at (AArch64) EL1
355 might return incorrect data.
357 The workaround is to write the contextidr_el1 register on exception
358 return to a 32-bit task.
359 Please note that this does not necessarily enable the workaround,
360 as it depends on the alternative framework, which will only patch
361 the kernel if an affected CPU is detected.
365 config ARM64_ERRATUM_843419
366 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
370 This option builds kernel modules using the large memory model in
371 order to avoid the use of the ADRP instruction, which can cause
372 a subsequent memory access to use an incorrect address on Cortex-A53
375 Note that the kernel itself must be linked with a version of ld
376 which fixes potentially affected ADRP instructions through the
381 config CAVIUM_ERRATUM_22375
382 bool "Cavium erratum 22375, 24313"
385 Enable workaround for erratum 22375, 24313.
387 This implements two gicv3-its errata workarounds for ThunderX. Both
388 with small impact affecting only ITS table allocation.
390 erratum 22375: only alloc 8MB table size
391 erratum 24313: ignore memory access type
393 The fixes are in ITS initialization and basically ignore memory access
394 type and table size provided by the TYPER and BASER registers.
398 config CAVIUM_ERRATUM_23144
399 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
403 ITS SYNC command hang for cross node io and collections/cpu mapping.
407 config CAVIUM_ERRATUM_23154
408 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
411 The gicv3 of ThunderX requires a modified version for
412 reading the IAR status to ensure data synchronization
413 (access to icc_iar1_el1 is not sync'ed before and after).
417 config CAVIUM_ERRATUM_27456
418 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
421 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
422 instructions may cause the icache to become corrupted if it
423 contains data for a non-current ASID. The fix is to
424 invalidate the icache when changing the mm context.
433 default ARM64_4K_PAGES
435 Page size (translation granule) configuration.
437 config ARM64_4K_PAGES
440 This feature enables 4KB pages support.
442 config ARM64_16K_PAGES
445 The system will use 16KB pages support. AArch32 emulation
446 requires applications compiled with 16K (or a multiple of 16K)
449 config ARM64_64K_PAGES
452 This feature enables 64KB pages support (4KB by default)
453 allowing only two levels of page tables and faster TLB
454 look-up. AArch32 emulation requires applications compiled
455 with 64K aligned segments.
460 prompt "Virtual address space size"
461 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
462 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
463 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
465 Allows choosing one of multiple possible virtual address
466 space sizes. The level of translation table is determined by
467 a combination of page size and virtual address space size.
469 config ARM64_VA_BITS_36
470 bool "36-bit" if EXPERT
471 depends on ARM64_16K_PAGES
473 config ARM64_VA_BITS_39
475 depends on ARM64_4K_PAGES
477 config ARM64_VA_BITS_42
479 depends on ARM64_64K_PAGES
481 config ARM64_VA_BITS_47
483 depends on ARM64_16K_PAGES
485 config ARM64_VA_BITS_48
492 default 36 if ARM64_VA_BITS_36
493 default 39 if ARM64_VA_BITS_39
494 default 42 if ARM64_VA_BITS_42
495 default 47 if ARM64_VA_BITS_47
496 default 48 if ARM64_VA_BITS_48
498 config CPU_BIG_ENDIAN
499 bool "Build big-endian kernel"
501 Say Y if you plan on running a kernel in big-endian mode.
504 bool "Multi-core scheduler support"
506 Multi-core scheduler support improves the CPU scheduler's decision
507 making when dealing with multi-core CPU chips at a cost of slightly
508 increased overhead in some places. If unsure say N here.
511 bool "SMT scheduler support"
513 Improves the CPU scheduler's decision making when dealing with
514 MultiThreading at a cost of slightly increased overhead in some
515 places. If unsure say N here.
518 int "Maximum number of CPUs (2-4096)"
520 # These have to remain sorted largest to smallest
524 bool "Support for hot-pluggable CPUs"
525 select GENERIC_IRQ_MIGRATION
527 Say Y here to experiment with turning CPUs off and on. CPUs
528 can be controlled through /sys/devices/system/cpu.
530 source kernel/Kconfig.preempt
531 source kernel/Kconfig.hz
533 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
536 config ARCH_HAS_HOLES_MEMORYMODEL
537 def_bool y if SPARSEMEM
539 config ARCH_SPARSEMEM_ENABLE
541 select SPARSEMEM_VMEMMAP_ENABLE
543 config ARCH_SPARSEMEM_DEFAULT
544 def_bool ARCH_SPARSEMEM_ENABLE
546 config ARCH_SELECT_MEMORY_MODEL
547 def_bool ARCH_SPARSEMEM_ENABLE
549 config HAVE_ARCH_PFN_VALID
550 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
552 config HW_PERF_EVENTS
556 config SYS_SUPPORTS_HUGETLBFS
559 config ARCH_WANT_GENERAL_HUGETLB
562 config ARCH_WANT_HUGE_PMD_SHARE
563 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
565 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
568 config ARCH_HAS_CACHE_LINE_SIZE
574 bool "Enable seccomp to safely compute untrusted bytecode"
576 This kernel feature is useful for number crunching applications
577 that may need to compute untrusted bytecode during their
578 execution. By using pipes or other transports made available to
579 the process as file descriptors supporting the read/write
580 syscalls, it's possible to isolate those applications in
581 their own address space using seccomp. Once seccomp is
582 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
583 and the task is only allowed to execute a few safe syscalls
584 defined by each seccomp mode.
591 bool "Xen guest support on ARM64"
592 depends on ARM64 && OF
595 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
597 config FORCE_MAX_ZONEORDER
599 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
600 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
603 The kernel memory allocator divides physically contiguous memory
604 blocks into "zones", where each zone is a power of two number of
605 pages. This option selects the largest power of two that the kernel
606 keeps in the memory allocator. If you need to allocate very large
607 blocks of physically contiguous memory, then you may need to
610 This config option is actually maximum order plus one. For example,
611 a value of 11 means that the largest free memory block is 2^10 pages.
613 We make sure that we can allocate upto a HugePage size for each configuration.
615 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
617 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
618 4M allocations matching the default size used by generic code.
620 menuconfig ARMV8_DEPRECATED
621 bool "Emulate deprecated/obsolete ARMv8 instructions"
624 Legacy software support may require certain instructions
625 that have been deprecated or obsoleted in the architecture.
627 Enable this config to enable selective emulation of these
635 bool "Emulate SWP/SWPB instructions"
637 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
638 they are always undefined. Say Y here to enable software
639 emulation of these instructions for userspace using LDXR/STXR.
641 In some older versions of glibc [<=2.8] SWP is used during futex
642 trylock() operations with the assumption that the code will not
643 be preempted. This invalid assumption may be more likely to fail
644 with SWP emulation enabled, leading to deadlock of the user
647 NOTE: when accessing uncached shared regions, LDXR/STXR rely
648 on an external transaction monitoring block called a global
649 monitor to maintain update atomicity. If your system does not
650 implement a global monitor, this option can cause programs that
651 perform SWP operations to uncached memory to deadlock.
655 config CP15_BARRIER_EMULATION
656 bool "Emulate CP15 Barrier instructions"
658 The CP15 barrier instructions - CP15ISB, CP15DSB, and
659 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
660 strongly recommended to use the ISB, DSB, and DMB
661 instructions instead.
663 Say Y here to enable software emulation of these
664 instructions for AArch32 userspace code. When this option is
665 enabled, CP15 barrier usage is traced which can help
666 identify software that needs updating.
670 config SETEND_EMULATION
671 bool "Emulate SETEND instruction"
673 The SETEND instruction alters the data-endianness of the
674 AArch32 EL0, and is deprecated in ARMv8.
676 Say Y here to enable software emulation of the instruction
677 for AArch32 userspace code.
679 Note: All the cpus on the system must have mixed endian support at EL0
680 for this feature to be enabled. If a new CPU - which doesn't support mixed
681 endian - is hotplugged in after this feature has been enabled, there could
682 be unexpected results in the applications.
687 menu "ARMv8.1 architectural features"
689 config ARM64_HW_AFDBM
690 bool "Support for hardware updates of the Access and Dirty page flags"
693 The ARMv8.1 architecture extensions introduce support for
694 hardware updates of the access and dirty information in page
695 table entries. When enabled in TCR_EL1 (HA and HD bits) on
696 capable processors, accesses to pages with PTE_AF cleared will
697 set this bit instead of raising an access flag fault.
698 Similarly, writes to read-only pages with the DBM bit set will
699 clear the read-only bit (AP[2]) instead of raising a
702 Kernels built with this configuration option enabled continue
703 to work on pre-ARMv8.1 hardware and the performance impact is
704 minimal. If unsure, say Y.
707 bool "Enable support for Privileged Access Never (PAN)"
710 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
711 prevents the kernel or hypervisor from accessing user-space (EL0)
714 Choosing this option will cause any unprotected (not using
715 copy_to_user et al) memory access to fail with a permission fault.
717 The feature is detected at runtime, and will remain as a 'nop'
718 instruction if the cpu does not implement the feature.
720 config ARM64_LSE_ATOMICS
721 bool "Atomic instructions"
723 As part of the Large System Extensions, ARMv8.1 introduces new
724 atomic instructions that are designed specifically to scale in
727 Say Y here to make use of these instructions for the in-kernel
728 atomic routines. This incurs a small overhead on CPUs that do
729 not support these instructions and requires the kernel to be
730 built with binutils >= 2.25.
738 config ARM64_ACPI_PARKING_PROTOCOL
739 bool "Enable support for the ARM64 ACPI parking protocol"
742 Enable support for the ARM64 ACPI parking protocol. If disabled
743 the kernel will not allow booting through the ARM64 ACPI parking
744 protocol even if the corresponding data is present in the ACPI
748 string "Default kernel command string"
751 Provide a set of default command-line options at build time by
752 entering them here. As a minimum, you should specify the the
753 root device (e.g. root=/dev/nfs).
756 bool "Always use the default kernel command string"
758 Always use the default kernel command string, even if the boot
759 loader passes other arguments to the kernel.
760 This is useful if you cannot or don't want to change the
761 command-line options your boot loader passes to the kernel.
767 bool "UEFI runtime support"
768 depends on OF && !CPU_BIG_ENDIAN
771 select EFI_PARAMS_FROM_FDT
772 select EFI_RUNTIME_WRAPPERS
777 This option provides support for runtime services provided
778 by UEFI firmware (such as non-volatile variables, realtime
779 clock, and platform reset). A UEFI stub is also provided to
780 allow the kernel to be booted as an EFI application. This
781 is only useful on systems that have UEFI firmware.
784 bool "Enable support for SMBIOS (DMI) tables"
788 This enables SMBIOS/DMI feature for systems.
790 This option is only useful on systems that have UEFI firmware.
791 However, even with this option, the resultant kernel should
792 continue to boot on existing non-UEFI platforms.
796 menu "Userspace binary formats"
798 source "fs/Kconfig.binfmt"
801 bool "Kernel support for 32-bit EL0"
802 depends on ARM64_4K_PAGES || EXPERT
803 select COMPAT_BINFMT_ELF
805 select OLD_SIGSUSPEND3
806 select COMPAT_OLD_SIGACTION
808 This option enables support for a 32-bit EL0 running under a 64-bit
809 kernel at EL1. AArch32-specific components such as system calls,
810 the user helper functions, VFP support and the ptrace interface are
811 handled appropriately by the kernel.
813 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
814 that you will only be able to execute AArch32 binaries that were compiled
815 with page size aligned segments.
817 If you want to execute 32-bit userspace applications, say Y.
819 config SYSVIPC_COMPAT
821 depends on COMPAT && SYSVIPC
825 menu "Power management options"
827 source "kernel/power/Kconfig"
829 config ARCH_HIBERNATION_POSSIBLE
833 config ARCH_HIBERNATION_HEADER
835 depends on HIBERNATION
837 config ARCH_SUSPEND_POSSIBLE
842 menu "CPU Power Management"
844 source "drivers/cpuidle/Kconfig"
846 source "drivers/cpufreq/Kconfig"
852 source "drivers/Kconfig"
854 source "drivers/firmware/Kconfig"
856 source "drivers/acpi/Kconfig"
860 source "arch/arm64/kvm/Kconfig"
862 source "arch/arm64/Kconfig.debug"
864 source "security/Kconfig"
866 source "crypto/Kconfig"
868 source "arch/arm64/crypto/Kconfig"