3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
16 select ARCH_HAS_UBSAN_SANITIZE_ALL
20 select AUDIT_ARCH_COMPAT_GENERIC
21 select ARM_GIC_V2M if PCI_MSI
23 select ARM_GIC_V3_ITS if PCI_MSI
25 select BUILDTIME_EXTABLE_SORT
26 select CLONE_BACKWARDS
28 select CPU_PM if (SUSPEND || CPU_IDLE)
29 select DCACHE_WORD_ACCESS
32 select GENERIC_ALLOCATOR
33 select GENERIC_CLOCKEVENTS
34 select GENERIC_CLOCKEVENTS_BROADCAST
35 select GENERIC_CPU_AUTOPROBE
36 select GENERIC_EARLY_IOREMAP
37 select GENERIC_IDLE_POLL_SETUP
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_SHOW_LEVEL
41 select GENERIC_PCI_IOMAP
42 select GENERIC_SCHED_CLOCK
43 select GENERIC_SMP_IDLE_THREAD
44 select GENERIC_STRNCPY_FROM_USER
45 select GENERIC_STRNLEN_USER
46 select GENERIC_TIME_VSYSCALL
47 select HANDLE_DOMAIN_IRQ
48 select HARDIRQS_SW_RESEND
49 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
50 select HAVE_ARCH_AUDITSYSCALL
51 select HAVE_ARCH_BITREVERSE
52 select HAVE_ARCH_HARDENED_USERCOPY
53 select HAVE_ARCH_HUGE_VMAP
54 select HAVE_ARCH_JUMP_LABEL
55 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
57 select HAVE_ARCH_SECCOMP_FILTER
58 select HAVE_ARCH_TRACEHOOK
60 select HAVE_C_RECORDMCOUNT
61 select HAVE_CC_STACKPROTECTOR
62 select HAVE_CMPXCHG_DOUBLE
63 select HAVE_CMPXCHG_LOCAL
64 select HAVE_DEBUG_BUGVERBOSE
65 select HAVE_DEBUG_KMEMLEAK
66 select HAVE_DMA_API_DEBUG
68 select HAVE_DMA_CONTIGUOUS
69 select HAVE_DYNAMIC_FTRACE
70 select HAVE_EFFICIENT_UNALIGNED_ACCESS
71 select HAVE_FTRACE_MCOUNT_RECORD
72 select HAVE_FUNCTION_TRACER
73 select HAVE_FUNCTION_GRAPH_TRACER
74 select HAVE_GENERIC_DMA_COHERENT
75 select HAVE_HW_BREAKPOINT if PERF_EVENTS
76 select HAVE_IRQ_TIME_ACCOUNTING
78 select HAVE_PATA_PLATFORM
79 select HAVE_PERF_EVENTS
81 select HAVE_PERF_USER_STACK_DUMP
82 select HAVE_REGS_AND_STACK_ACCESS_API
83 select HAVE_RCU_TABLE_FREE
84 select HAVE_SYSCALL_TRACEPOINTS
86 select HAVE_KRETPROBES if HAVE_KPROBES
87 select IOMMU_DMA if IOMMU_SUPPORT
89 select IRQ_FORCED_THREADING
90 select MODULES_USE_ELF_RELA
93 select OF_EARLY_FLATTREE
94 select OF_RESERVED_MEM
95 select PERF_USE_VMALLOC
100 select SYSCTL_EXCEPTION_TRACE
101 select HAVE_CONTEXT_TRACKING
103 ARM 64-bit (AArch64) Linux support.
108 config ARCH_PHYS_ADDR_T_64BIT
117 config STACKTRACE_SUPPORT
120 config ILLEGAL_POINTER_VALUE
122 default 0xdead000000000000
124 config LOCKDEP_SUPPORT
127 config TRACE_IRQFLAGS_SUPPORT
130 config RWSEM_XCHGADD_ALGORITHM
137 config GENERIC_BUG_RELATIVE_POINTERS
139 depends on GENERIC_BUG
141 config GENERIC_HWEIGHT
147 config GENERIC_CALIBRATE_DELAY
153 config HAVE_GENERIC_RCU_GUP
156 config ARCH_DMA_ADDR_T_64BIT
159 config NEED_DMA_MAP_STATE
162 config NEED_SG_DMA_LENGTH
174 config KERNEL_MODE_NEON
177 config FIX_EARLYCON_MEM
180 config PGTABLE_LEVELS
182 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
183 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
184 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
185 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
186 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
187 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
189 source "init/Kconfig"
191 source "kernel/Kconfig.freezer"
193 source "arch/arm64/Kconfig.platforms"
200 This feature enables support for PCI bus system. If you say Y
201 here, the kernel will include drivers and infrastructure code
202 to support PCI bus devices.
207 config PCI_DOMAINS_GENERIC
213 source "drivers/pci/Kconfig"
214 source "drivers/pci/pcie/Kconfig"
215 source "drivers/pci/hotplug/Kconfig"
219 menu "Kernel Features"
221 menu "ARM errata workarounds via the alternatives framework"
223 config ARM64_ERRATUM_826319
224 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
227 This option adds an alternative code sequence to work around ARM
228 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
229 AXI master interface and an L2 cache.
231 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
232 and is unable to accept a certain write via this interface, it will
233 not progress on read data presented on the read data channel and the
236 The workaround promotes data cache clean instructions to
237 data cache clean-and-invalidate.
238 Please note that this does not necessarily enable the workaround,
239 as it depends on the alternative framework, which will only patch
240 the kernel if an affected CPU is detected.
244 config ARM64_ERRATUM_827319
245 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
248 This option adds an alternative code sequence to work around ARM
249 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
250 master interface and an L2 cache.
252 Under certain conditions this erratum can cause a clean line eviction
253 to occur at the same time as another transaction to the same address
254 on the AMBA 5 CHI interface, which can cause data corruption if the
255 interconnect reorders the two transactions.
257 The workaround promotes data cache clean instructions to
258 data cache clean-and-invalidate.
259 Please note that this does not necessarily enable the workaround,
260 as it depends on the alternative framework, which will only patch
261 the kernel if an affected CPU is detected.
265 config ARM64_ERRATUM_824069
266 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
269 This option adds an alternative code sequence to work around ARM
270 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
271 to a coherent interconnect.
273 If a Cortex-A53 processor is executing a store or prefetch for
274 write instruction at the same time as a processor in another
275 cluster is executing a cache maintenance operation to the same
276 address, then this erratum might cause a clean cache line to be
277 incorrectly marked as dirty.
279 The workaround promotes data cache clean instructions to
280 data cache clean-and-invalidate.
281 Please note that this option does not necessarily enable the
282 workaround, as it depends on the alternative framework, which will
283 only patch the kernel if an affected CPU is detected.
287 config ARM64_ERRATUM_819472
288 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
291 This option adds an alternative code sequence to work around ARM
292 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
293 present when it is connected to a coherent interconnect.
295 If the processor is executing a load and store exclusive sequence at
296 the same time as a processor in another cluster is executing a cache
297 maintenance operation to the same address, then this erratum might
298 cause data corruption.
300 The workaround promotes data cache clean instructions to
301 data cache clean-and-invalidate.
302 Please note that this does not necessarily enable the workaround,
303 as it depends on the alternative framework, which will only patch
304 the kernel if an affected CPU is detected.
308 config ARM64_ERRATUM_832075
309 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
312 This option adds an alternative code sequence to work around ARM
313 erratum 832075 on Cortex-A57 parts up to r1p2.
315 Affected Cortex-A57 parts might deadlock when exclusive load/store
316 instructions to Write-Back memory are mixed with Device loads.
318 The workaround is to promote device loads to use Load-Acquire
320 Please note that this does not necessarily enable the workaround,
321 as it depends on the alternative framework, which will only patch
322 the kernel if an affected CPU is detected.
326 config ARM64_ERRATUM_834220
327 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
331 This option adds an alternative code sequence to work around ARM
332 erratum 834220 on Cortex-A57 parts up to r1p2.
334 Affected Cortex-A57 parts might report a Stage 2 translation
335 fault as the result of a Stage 1 fault for load crossing a
336 page boundary when there is a permission or device memory
337 alignment fault at Stage 1 and a translation fault at Stage 2.
339 The workaround is to verify that the Stage 1 translation
340 doesn't generate a fault before handling the Stage 2 fault.
341 Please note that this does not necessarily enable the workaround,
342 as it depends on the alternative framework, which will only patch
343 the kernel if an affected CPU is detected.
347 config ARM64_ERRATUM_845719
348 bool "Cortex-A53: 845719: a load might read incorrect data"
352 This option adds an alternative code sequence to work around ARM
353 erratum 845719 on Cortex-A53 parts up to r0p4.
355 When running a compat (AArch32) userspace on an affected Cortex-A53
356 part, a load at EL0 from a virtual address that matches the bottom 32
357 bits of the virtual address used by a recent load at (AArch64) EL1
358 might return incorrect data.
360 The workaround is to write the contextidr_el1 register on exception
361 return to a 32-bit task.
362 Please note that this does not necessarily enable the workaround,
363 as it depends on the alternative framework, which will only patch
364 the kernel if an affected CPU is detected.
368 config ARM64_ERRATUM_843419
369 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
372 select ARM64_MODULE_CMODEL_LARGE
374 This option builds kernel modules using the large memory model in
375 order to avoid the use of the ADRP instruction, which can cause
376 a subsequent memory access to use an incorrect address on Cortex-A53
379 Note that the kernel itself must be linked with a version of ld
380 which fixes potentially affected ADRP instructions through the
385 config CAVIUM_ERRATUM_22375
386 bool "Cavium erratum 22375, 24313"
389 Enable workaround for erratum 22375, 24313.
391 This implements two gicv3-its errata workarounds for ThunderX. Both
392 with small impact affecting only ITS table allocation.
394 erratum 22375: only alloc 8MB table size
395 erratum 24313: ignore memory access type
397 The fixes are in ITS initialization and basically ignore memory access
398 type and table size provided by the TYPER and BASER registers.
402 config CAVIUM_ERRATUM_23144
403 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
407 ITS SYNC command hang for cross node io and collections/cpu mapping.
411 config CAVIUM_ERRATUM_23154
412 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
415 The gicv3 of ThunderX requires a modified version for
416 reading the IAR status to ensure data synchronization
417 (access to icc_iar1_el1 is not sync'ed before and after).
421 config CAVIUM_ERRATUM_27456
422 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
425 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
426 instructions may cause the icache to become corrupted if it
427 contains data for a non-current ASID. The fix is to
428 invalidate the icache when changing the mm context.
437 default ARM64_4K_PAGES
439 Page size (translation granule) configuration.
441 config ARM64_4K_PAGES
444 This feature enables 4KB pages support.
446 config ARM64_16K_PAGES
449 The system will use 16KB pages support. AArch32 emulation
450 requires applications compiled with 16K (or a multiple of 16K)
453 config ARM64_64K_PAGES
456 This feature enables 64KB pages support (4KB by default)
457 allowing only two levels of page tables and faster TLB
458 look-up. AArch32 emulation requires applications compiled
459 with 64K aligned segments.
464 prompt "Virtual address space size"
465 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
466 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
467 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
469 Allows choosing one of multiple possible virtual address
470 space sizes. The level of translation table is determined by
471 a combination of page size and virtual address space size.
473 config ARM64_VA_BITS_36
474 bool "36-bit" if EXPERT
475 depends on ARM64_16K_PAGES
477 config ARM64_VA_BITS_39
479 depends on ARM64_4K_PAGES
481 config ARM64_VA_BITS_42
483 depends on ARM64_64K_PAGES
485 config ARM64_VA_BITS_47
487 depends on ARM64_16K_PAGES
489 config ARM64_VA_BITS_48
496 default 36 if ARM64_VA_BITS_36
497 default 39 if ARM64_VA_BITS_39
498 default 42 if ARM64_VA_BITS_42
499 default 47 if ARM64_VA_BITS_47
500 default 48 if ARM64_VA_BITS_48
502 config CPU_BIG_ENDIAN
503 bool "Build big-endian kernel"
505 Say Y if you plan on running a kernel in big-endian mode.
508 bool "Multi-core scheduler support"
510 Multi-core scheduler support improves the CPU scheduler's decision
511 making when dealing with multi-core CPU chips at a cost of slightly
512 increased overhead in some places. If unsure say N here.
515 bool "SMT scheduler support"
517 Improves the CPU scheduler's decision making when dealing with
518 MultiThreading at a cost of slightly increased overhead in some
519 places. If unsure say N here.
522 int "Maximum number of CPUs (2-4096)"
524 # These have to remain sorted largest to smallest
528 bool "Support for hot-pluggable CPUs"
529 select GENERIC_IRQ_MIGRATION
531 Say Y here to experiment with turning CPUs off and on. CPUs
532 can be controlled through /sys/devices/system/cpu.
534 source kernel/Kconfig.preempt
535 source kernel/Kconfig.hz
537 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
540 config ARCH_HAS_HOLES_MEMORYMODEL
541 def_bool y if SPARSEMEM
543 config ARCH_SPARSEMEM_ENABLE
545 select SPARSEMEM_VMEMMAP_ENABLE
547 config ARCH_SPARSEMEM_DEFAULT
548 def_bool ARCH_SPARSEMEM_ENABLE
550 config ARCH_SELECT_MEMORY_MODEL
551 def_bool ARCH_SPARSEMEM_ENABLE
553 config HAVE_ARCH_PFN_VALID
554 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
556 config HW_PERF_EVENTS
560 config SYS_SUPPORTS_HUGETLBFS
563 config ARCH_WANT_HUGE_PMD_SHARE
564 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
566 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
569 config ARCH_HAS_CACHE_LINE_SIZE
575 bool "Enable seccomp to safely compute untrusted bytecode"
577 This kernel feature is useful for number crunching applications
578 that may need to compute untrusted bytecode during their
579 execution. By using pipes or other transports made available to
580 the process as file descriptors supporting the read/write
581 syscalls, it's possible to isolate those applications in
582 their own address space using seccomp. Once seccomp is
583 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
584 and the task is only allowed to execute a few safe syscalls
585 defined by each seccomp mode.
592 bool "Xen guest support on ARM64"
593 depends on ARM64 && OF
596 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
598 config FORCE_MAX_ZONEORDER
600 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
601 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
604 The kernel memory allocator divides physically contiguous memory
605 blocks into "zones", where each zone is a power of two number of
606 pages. This option selects the largest power of two that the kernel
607 keeps in the memory allocator. If you need to allocate very large
608 blocks of physically contiguous memory, then you may need to
611 This config option is actually maximum order plus one. For example,
612 a value of 11 means that the largest free memory block is 2^10 pages.
614 We make sure that we can allocate upto a HugePage size for each configuration.
616 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
618 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
619 4M allocations matching the default size used by generic code.
621 menuconfig ARMV8_DEPRECATED
622 bool "Emulate deprecated/obsolete ARMv8 instructions"
625 Legacy software support may require certain instructions
626 that have been deprecated or obsoleted in the architecture.
628 Enable this config to enable selective emulation of these
636 bool "Emulate SWP/SWPB instructions"
638 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
639 they are always undefined. Say Y here to enable software
640 emulation of these instructions for userspace using LDXR/STXR.
642 In some older versions of glibc [<=2.8] SWP is used during futex
643 trylock() operations with the assumption that the code will not
644 be preempted. This invalid assumption may be more likely to fail
645 with SWP emulation enabled, leading to deadlock of the user
648 NOTE: when accessing uncached shared regions, LDXR/STXR rely
649 on an external transaction monitoring block called a global
650 monitor to maintain update atomicity. If your system does not
651 implement a global monitor, this option can cause programs that
652 perform SWP operations to uncached memory to deadlock.
656 config CP15_BARRIER_EMULATION
657 bool "Emulate CP15 Barrier instructions"
659 The CP15 barrier instructions - CP15ISB, CP15DSB, and
660 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
661 strongly recommended to use the ISB, DSB, and DMB
662 instructions instead.
664 Say Y here to enable software emulation of these
665 instructions for AArch32 userspace code. When this option is
666 enabled, CP15 barrier usage is traced which can help
667 identify software that needs updating.
671 config SETEND_EMULATION
672 bool "Emulate SETEND instruction"
674 The SETEND instruction alters the data-endianness of the
675 AArch32 EL0, and is deprecated in ARMv8.
677 Say Y here to enable software emulation of the instruction
678 for AArch32 userspace code.
680 Note: All the cpus on the system must have mixed endian support at EL0
681 for this feature to be enabled. If a new CPU - which doesn't support mixed
682 endian - is hotplugged in after this feature has been enabled, there could
683 be unexpected results in the applications.
688 menu "ARMv8.1 architectural features"
690 config ARM64_HW_AFDBM
691 bool "Support for hardware updates of the Access and Dirty page flags"
694 The ARMv8.1 architecture extensions introduce support for
695 hardware updates of the access and dirty information in page
696 table entries. When enabled in TCR_EL1 (HA and HD bits) on
697 capable processors, accesses to pages with PTE_AF cleared will
698 set this bit instead of raising an access flag fault.
699 Similarly, writes to read-only pages with the DBM bit set will
700 clear the read-only bit (AP[2]) instead of raising a
703 Kernels built with this configuration option enabled continue
704 to work on pre-ARMv8.1 hardware and the performance impact is
705 minimal. If unsure, say Y.
708 bool "Enable support for Privileged Access Never (PAN)"
711 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
712 prevents the kernel or hypervisor from accessing user-space (EL0)
715 Choosing this option will cause any unprotected (not using
716 copy_to_user et al) memory access to fail with a permission fault.
718 The feature is detected at runtime, and will remain as a 'nop'
719 instruction if the cpu does not implement the feature.
721 config ARM64_LSE_ATOMICS
722 bool "Atomic instructions"
724 As part of the Large System Extensions, ARMv8.1 introduces new
725 atomic instructions that are designed specifically to scale in
728 Say Y here to make use of these instructions for the in-kernel
729 atomic routines. This incurs a small overhead on CPUs that do
730 not support these instructions and requires the kernel to be
731 built with binutils >= 2.25.
736 bool "Enable support for User Access Override (UAO)"
739 User Access Override (UAO; part of the ARMv8.2 Extensions)
740 causes the 'unprivileged' variant of the load/store instructions to
741 be overriden to be privileged.
743 This option changes get_user() and friends to use the 'unprivileged'
744 variant of the load/store instructions. This ensures that user-space
745 really did have access to the supplied memory. When addr_limit is
746 set to kernel memory the UAO bit will be set, allowing privileged
747 access to kernel memory.
749 Choosing this option will cause copy_to_user() et al to use user-space
752 The feature is detected at runtime, the kernel will use the
753 regular load/store instructions if the cpu does not implement the
756 config ARM64_MODULE_CMODEL_LARGE
759 config ARM64_MODULE_PLTS
761 select ARM64_MODULE_CMODEL_LARGE
762 select HAVE_MOD_ARCH_SPECIFIC
767 This builds the kernel as a Position Independent Executable (PIE),
768 which retains all relocation metadata required to relocate the
769 kernel binary at runtime to a different virtual address than the
770 address it was linked at.
771 Since AArch64 uses the RELA relocation format, this requires a
772 relocation pass at runtime even if the kernel is loaded at the
773 same address it was linked at.
775 config RANDOMIZE_BASE
776 bool "Randomize the address of the kernel image"
777 select ARM64_MODULE_PLTS
780 Randomizes the virtual address at which the kernel image is
781 loaded, as a security feature that deters exploit attempts
782 relying on knowledge of the location of kernel internals.
784 It is the bootloader's job to provide entropy, by passing a
785 random u64 value in /chosen/kaslr-seed at kernel entry.
787 When booting via the UEFI stub, it will invoke the firmware's
788 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
789 to the kernel proper. In addition, it will randomise the physical
790 location of the kernel Image as well.
794 config RANDOMIZE_MODULE_REGION_FULL
795 bool "Randomize the module region independently from the core kernel"
796 depends on RANDOMIZE_BASE
799 Randomizes the location of the module region without considering the
800 location of the core kernel. This way, it is impossible for modules
801 to leak information about the location of core kernel data structures
802 but it does imply that function calls between modules and the core
803 kernel will need to be resolved via veneers in the module PLT.
805 When this option is not set, the module region will be randomized over
806 a limited range that contains the [_stext, _etext] interval of the
807 core kernel, so branch relocations are always in range.
813 config ARM64_ACPI_PARKING_PROTOCOL
814 bool "Enable support for the ARM64 ACPI parking protocol"
817 Enable support for the ARM64 ACPI parking protocol. If disabled
818 the kernel will not allow booting through the ARM64 ACPI parking
819 protocol even if the corresponding data is present in the ACPI
823 string "Default kernel command string"
826 Provide a set of default command-line options at build time by
827 entering them here. As a minimum, you should specify the the
828 root device (e.g. root=/dev/nfs).
831 bool "Always use the default kernel command string"
833 Always use the default kernel command string, even if the boot
834 loader passes other arguments to the kernel.
835 This is useful if you cannot or don't want to change the
836 command-line options your boot loader passes to the kernel.
842 bool "UEFI runtime support"
843 depends on OF && !CPU_BIG_ENDIAN
846 select EFI_PARAMS_FROM_FDT
847 select EFI_RUNTIME_WRAPPERS
852 This option provides support for runtime services provided
853 by UEFI firmware (such as non-volatile variables, realtime
854 clock, and platform reset). A UEFI stub is also provided to
855 allow the kernel to be booted as an EFI application. This
856 is only useful on systems that have UEFI firmware.
859 bool "Enable support for SMBIOS (DMI) tables"
863 This enables SMBIOS/DMI feature for systems.
865 This option is only useful on systems that have UEFI firmware.
866 However, even with this option, the resultant kernel should
867 continue to boot on existing non-UEFI platforms.
871 menu "Userspace binary formats"
873 source "fs/Kconfig.binfmt"
876 bool "Kernel support for 32-bit EL0"
877 depends on ARM64_4K_PAGES || EXPERT
878 select COMPAT_BINFMT_ELF
880 select OLD_SIGSUSPEND3
881 select COMPAT_OLD_SIGACTION
883 This option enables support for a 32-bit EL0 running under a 64-bit
884 kernel at EL1. AArch32-specific components such as system calls,
885 the user helper functions, VFP support and the ptrace interface are
886 handled appropriately by the kernel.
888 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
889 that you will only be able to execute AArch32 binaries that were compiled
890 with page size aligned segments.
892 If you want to execute 32-bit userspace applications, say Y.
894 config SYSVIPC_COMPAT
896 depends on COMPAT && SYSVIPC
900 menu "Power management options"
902 source "kernel/power/Kconfig"
904 config ARCH_SUSPEND_POSSIBLE
909 menu "CPU Power Management"
911 source "drivers/cpuidle/Kconfig"
913 source "drivers/cpufreq/Kconfig"
919 source "drivers/Kconfig"
921 source "drivers/firmware/Kconfig"
923 source "drivers/acpi/Kconfig"
927 source "arch/arm64/kvm/Kconfig"
929 source "arch/arm64/Kconfig.debug"
931 source "security/Kconfig"
933 source "crypto/Kconfig"
935 source "arch/arm64/crypto/Kconfig"