3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
16 select ARCH_HAS_UBSAN_SANITIZE_ALL
20 select AUDIT_ARCH_COMPAT_GENERIC
21 select ARM_GIC_V2M if PCI_MSI
23 select ARM_GIC_V3_ITS if PCI_MSI
25 select BUILDTIME_EXTABLE_SORT
26 select CLONE_BACKWARDS
28 select CPU_PM if (SUSPEND || CPU_IDLE)
29 select DCACHE_WORD_ACCESS
32 select GENERIC_ALLOCATOR
33 select GENERIC_CLOCKEVENTS
34 select GENERIC_CLOCKEVENTS_BROADCAST
35 select GENERIC_CPU_AUTOPROBE
36 select GENERIC_EARLY_IOREMAP
37 select GENERIC_IDLE_POLL_SETUP
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_IRQ_SHOW_LEVEL
41 select GENERIC_PCI_IOMAP
42 select GENERIC_SCHED_CLOCK
43 select GENERIC_SMP_IDLE_THREAD
44 select GENERIC_STRNCPY_FROM_USER
45 select GENERIC_STRNLEN_USER
46 select GENERIC_TIME_VSYSCALL
47 select HANDLE_DOMAIN_IRQ
48 select HARDIRQS_SW_RESEND
49 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
50 select HAVE_ARCH_AUDITSYSCALL
51 select HAVE_ARCH_BITREVERSE
52 select HAVE_ARCH_JUMP_LABEL
53 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
55 select HAVE_ARCH_SECCOMP_FILTER
56 select HAVE_ARCH_TRACEHOOK
58 select HAVE_C_RECORDMCOUNT
59 select HAVE_CC_STACKPROTECTOR
60 select HAVE_CMPXCHG_DOUBLE
61 select HAVE_CMPXCHG_LOCAL
62 select HAVE_DEBUG_BUGVERBOSE
63 select HAVE_DEBUG_KMEMLEAK
64 select HAVE_DMA_API_DEBUG
66 select HAVE_DMA_CONTIGUOUS
67 select HAVE_DYNAMIC_FTRACE
68 select HAVE_EFFICIENT_UNALIGNED_ACCESS
69 select HAVE_FTRACE_MCOUNT_RECORD
70 select HAVE_FUNCTION_TRACER
71 select HAVE_FUNCTION_GRAPH_TRACER
72 select HAVE_GENERIC_DMA_COHERENT
73 select HAVE_HW_BREAKPOINT if PERF_EVENTS
74 select HAVE_IRQ_TIME_ACCOUNTING
76 select HAVE_PATA_PLATFORM
77 select HAVE_PERF_EVENTS
79 select HAVE_PERF_USER_STACK_DUMP
80 select HAVE_RCU_TABLE_FREE
81 select HAVE_SYSCALL_TRACEPOINTS
82 select IOMMU_DMA if IOMMU_SUPPORT
84 select IRQ_FORCED_THREADING
85 select MODULES_USE_ELF_RELA
88 select OF_EARLY_FLATTREE
89 select OF_RESERVED_MEM
90 select PERF_USE_VMALLOC
95 select SYSCTL_EXCEPTION_TRACE
96 select HAVE_CONTEXT_TRACKING
98 ARM 64-bit (AArch64) Linux support.
103 config ARCH_PHYS_ADDR_T_64BIT
112 config STACKTRACE_SUPPORT
115 config ILLEGAL_POINTER_VALUE
117 default 0xdead000000000000
119 config LOCKDEP_SUPPORT
122 config TRACE_IRQFLAGS_SUPPORT
125 config RWSEM_XCHGADD_ALGORITHM
132 config GENERIC_BUG_RELATIVE_POINTERS
134 depends on GENERIC_BUG
136 config GENERIC_HWEIGHT
142 config GENERIC_CALIBRATE_DELAY
148 config HAVE_GENERIC_RCU_GUP
151 config ARCH_DMA_ADDR_T_64BIT
154 config NEED_DMA_MAP_STATE
157 config NEED_SG_DMA_LENGTH
169 config KERNEL_MODE_NEON
172 config FIX_EARLYCON_MEM
175 config PGTABLE_LEVELS
177 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
178 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
179 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
180 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
181 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
182 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
184 source "init/Kconfig"
186 source "kernel/Kconfig.freezer"
188 source "arch/arm64/Kconfig.platforms"
195 This feature enables support for PCI bus system. If you say Y
196 here, the kernel will include drivers and infrastructure code
197 to support PCI bus devices.
202 config PCI_DOMAINS_GENERIC
208 source "drivers/pci/Kconfig"
209 source "drivers/pci/pcie/Kconfig"
210 source "drivers/pci/hotplug/Kconfig"
214 menu "Kernel Features"
216 menu "ARM errata workarounds via the alternatives framework"
218 config ARM64_ERRATUM_826319
219 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
222 This option adds an alternative code sequence to work around ARM
223 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
224 AXI master interface and an L2 cache.
226 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
227 and is unable to accept a certain write via this interface, it will
228 not progress on read data presented on the read data channel and the
231 The workaround promotes data cache clean instructions to
232 data cache clean-and-invalidate.
233 Please note that this does not necessarily enable the workaround,
234 as it depends on the alternative framework, which will only patch
235 the kernel if an affected CPU is detected.
239 config ARM64_ERRATUM_827319
240 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
243 This option adds an alternative code sequence to work around ARM
244 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
245 master interface and an L2 cache.
247 Under certain conditions this erratum can cause a clean line eviction
248 to occur at the same time as another transaction to the same address
249 on the AMBA 5 CHI interface, which can cause data corruption if the
250 interconnect reorders the two transactions.
252 The workaround promotes data cache clean instructions to
253 data cache clean-and-invalidate.
254 Please note that this does not necessarily enable the workaround,
255 as it depends on the alternative framework, which will only patch
256 the kernel if an affected CPU is detected.
260 config ARM64_ERRATUM_824069
261 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
264 This option adds an alternative code sequence to work around ARM
265 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
266 to a coherent interconnect.
268 If a Cortex-A53 processor is executing a store or prefetch for
269 write instruction at the same time as a processor in another
270 cluster is executing a cache maintenance operation to the same
271 address, then this erratum might cause a clean cache line to be
272 incorrectly marked as dirty.
274 The workaround promotes data cache clean instructions to
275 data cache clean-and-invalidate.
276 Please note that this option does not necessarily enable the
277 workaround, as it depends on the alternative framework, which will
278 only patch the kernel if an affected CPU is detected.
282 config ARM64_ERRATUM_819472
283 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
286 This option adds an alternative code sequence to work around ARM
287 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
288 present when it is connected to a coherent interconnect.
290 If the processor is executing a load and store exclusive sequence at
291 the same time as a processor in another cluster is executing a cache
292 maintenance operation to the same address, then this erratum might
293 cause data corruption.
295 The workaround promotes data cache clean instructions to
296 data cache clean-and-invalidate.
297 Please note that this does not necessarily enable the workaround,
298 as it depends on the alternative framework, which will only patch
299 the kernel if an affected CPU is detected.
303 config ARM64_ERRATUM_832075
304 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
307 This option adds an alternative code sequence to work around ARM
308 erratum 832075 on Cortex-A57 parts up to r1p2.
310 Affected Cortex-A57 parts might deadlock when exclusive load/store
311 instructions to Write-Back memory are mixed with Device loads.
313 The workaround is to promote device loads to use Load-Acquire
315 Please note that this does not necessarily enable the workaround,
316 as it depends on the alternative framework, which will only patch
317 the kernel if an affected CPU is detected.
321 config ARM64_ERRATUM_834220
322 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
326 This option adds an alternative code sequence to work around ARM
327 erratum 834220 on Cortex-A57 parts up to r1p2.
329 Affected Cortex-A57 parts might report a Stage 2 translation
330 fault as the result of a Stage 1 fault for load crossing a
331 page boundary when there is a permission or device memory
332 alignment fault at Stage 1 and a translation fault at Stage 2.
334 The workaround is to verify that the Stage 1 translation
335 doesn't generate a fault before handling the Stage 2 fault.
336 Please note that this does not necessarily enable the workaround,
337 as it depends on the alternative framework, which will only patch
338 the kernel if an affected CPU is detected.
342 config ARM64_ERRATUM_845719
343 bool "Cortex-A53: 845719: a load might read incorrect data"
347 This option adds an alternative code sequence to work around ARM
348 erratum 845719 on Cortex-A53 parts up to r0p4.
350 When running a compat (AArch32) userspace on an affected Cortex-A53
351 part, a load at EL0 from a virtual address that matches the bottom 32
352 bits of the virtual address used by a recent load at (AArch64) EL1
353 might return incorrect data.
355 The workaround is to write the contextidr_el1 register on exception
356 return to a 32-bit task.
357 Please note that this does not necessarily enable the workaround,
358 as it depends on the alternative framework, which will only patch
359 the kernel if an affected CPU is detected.
363 config ARM64_ERRATUM_843419
364 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
368 This option builds kernel modules using the large memory model in
369 order to avoid the use of the ADRP instruction, which can cause
370 a subsequent memory access to use an incorrect address on Cortex-A53
373 Note that the kernel itself must be linked with a version of ld
374 which fixes potentially affected ADRP instructions through the
379 config CAVIUM_ERRATUM_22375
380 bool "Cavium erratum 22375, 24313"
383 Enable workaround for erratum 22375, 24313.
385 This implements two gicv3-its errata workarounds for ThunderX. Both
386 with small impact affecting only ITS table allocation.
388 erratum 22375: only alloc 8MB table size
389 erratum 24313: ignore memory access type
391 The fixes are in ITS initialization and basically ignore memory access
392 type and table size provided by the TYPER and BASER registers.
396 config CAVIUM_ERRATUM_23154
397 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
400 The gicv3 of ThunderX requires a modified version for
401 reading the IAR status to ensure data synchronization
402 (access to icc_iar1_el1 is not sync'ed before and after).
411 default ARM64_4K_PAGES
413 Page size (translation granule) configuration.
415 config ARM64_4K_PAGES
418 This feature enables 4KB pages support.
420 config ARM64_16K_PAGES
423 The system will use 16KB pages support. AArch32 emulation
424 requires applications compiled with 16K (or a multiple of 16K)
427 config ARM64_64K_PAGES
430 This feature enables 64KB pages support (4KB by default)
431 allowing only two levels of page tables and faster TLB
432 look-up. AArch32 emulation requires applications compiled
433 with 64K aligned segments.
438 prompt "Virtual address space size"
439 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
440 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
441 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
443 Allows choosing one of multiple possible virtual address
444 space sizes. The level of translation table is determined by
445 a combination of page size and virtual address space size.
447 config ARM64_VA_BITS_36
448 bool "36-bit" if EXPERT
449 depends on ARM64_16K_PAGES
451 config ARM64_VA_BITS_39
453 depends on ARM64_4K_PAGES
455 config ARM64_VA_BITS_42
457 depends on ARM64_64K_PAGES
459 config ARM64_VA_BITS_47
461 depends on ARM64_16K_PAGES
463 config ARM64_VA_BITS_48
470 default 36 if ARM64_VA_BITS_36
471 default 39 if ARM64_VA_BITS_39
472 default 42 if ARM64_VA_BITS_42
473 default 47 if ARM64_VA_BITS_47
474 default 48 if ARM64_VA_BITS_48
476 config CPU_BIG_ENDIAN
477 bool "Build big-endian kernel"
479 Say Y if you plan on running a kernel in big-endian mode.
482 bool "Multi-core scheduler support"
484 Multi-core scheduler support improves the CPU scheduler's decision
485 making when dealing with multi-core CPU chips at a cost of slightly
486 increased overhead in some places. If unsure say N here.
489 bool "SMT scheduler support"
491 Improves the CPU scheduler's decision making when dealing with
492 MultiThreading at a cost of slightly increased overhead in some
493 places. If unsure say N here.
496 int "Maximum number of CPUs (2-4096)"
498 # These have to remain sorted largest to smallest
502 bool "Support for hot-pluggable CPUs"
503 select GENERIC_IRQ_MIGRATION
505 Say Y here to experiment with turning CPUs off and on. CPUs
506 can be controlled through /sys/devices/system/cpu.
508 source kernel/Kconfig.preempt
509 source kernel/Kconfig.hz
511 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
514 config ARCH_HAS_HOLES_MEMORYMODEL
515 def_bool y if SPARSEMEM
517 config ARCH_SPARSEMEM_ENABLE
519 select SPARSEMEM_VMEMMAP_ENABLE
521 config ARCH_SPARSEMEM_DEFAULT
522 def_bool ARCH_SPARSEMEM_ENABLE
524 config ARCH_SELECT_MEMORY_MODEL
525 def_bool ARCH_SPARSEMEM_ENABLE
527 config HAVE_ARCH_PFN_VALID
528 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
530 config HW_PERF_EVENTS
534 config SYS_SUPPORTS_HUGETLBFS
537 config ARCH_WANT_HUGE_PMD_SHARE
538 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
540 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
543 config ARCH_HAS_CACHE_LINE_SIZE
549 bool "Enable seccomp to safely compute untrusted bytecode"
551 This kernel feature is useful for number crunching applications
552 that may need to compute untrusted bytecode during their
553 execution. By using pipes or other transports made available to
554 the process as file descriptors supporting the read/write
555 syscalls, it's possible to isolate those applications in
556 their own address space using seccomp. Once seccomp is
557 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
558 and the task is only allowed to execute a few safe syscalls
559 defined by each seccomp mode.
566 bool "Xen guest support on ARM64"
567 depends on ARM64 && OF
570 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
572 config FORCE_MAX_ZONEORDER
574 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
575 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
578 The kernel memory allocator divides physically contiguous memory
579 blocks into "zones", where each zone is a power of two number of
580 pages. This option selects the largest power of two that the kernel
581 keeps in the memory allocator. If you need to allocate very large
582 blocks of physically contiguous memory, then you may need to
585 This config option is actually maximum order plus one. For example,
586 a value of 11 means that the largest free memory block is 2^10 pages.
588 We make sure that we can allocate upto a HugePage size for each configuration.
590 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
592 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
593 4M allocations matching the default size used by generic code.
595 menuconfig ARMV8_DEPRECATED
596 bool "Emulate deprecated/obsolete ARMv8 instructions"
599 Legacy software support may require certain instructions
600 that have been deprecated or obsoleted in the architecture.
602 Enable this config to enable selective emulation of these
610 bool "Emulate SWP/SWPB instructions"
612 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
613 they are always undefined. Say Y here to enable software
614 emulation of these instructions for userspace using LDXR/STXR.
616 In some older versions of glibc [<=2.8] SWP is used during futex
617 trylock() operations with the assumption that the code will not
618 be preempted. This invalid assumption may be more likely to fail
619 with SWP emulation enabled, leading to deadlock of the user
622 NOTE: when accessing uncached shared regions, LDXR/STXR rely
623 on an external transaction monitoring block called a global
624 monitor to maintain update atomicity. If your system does not
625 implement a global monitor, this option can cause programs that
626 perform SWP operations to uncached memory to deadlock.
630 config CP15_BARRIER_EMULATION
631 bool "Emulate CP15 Barrier instructions"
633 The CP15 barrier instructions - CP15ISB, CP15DSB, and
634 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
635 strongly recommended to use the ISB, DSB, and DMB
636 instructions instead.
638 Say Y here to enable software emulation of these
639 instructions for AArch32 userspace code. When this option is
640 enabled, CP15 barrier usage is traced which can help
641 identify software that needs updating.
645 config SETEND_EMULATION
646 bool "Emulate SETEND instruction"
648 The SETEND instruction alters the data-endianness of the
649 AArch32 EL0, and is deprecated in ARMv8.
651 Say Y here to enable software emulation of the instruction
652 for AArch32 userspace code.
654 Note: All the cpus on the system must have mixed endian support at EL0
655 for this feature to be enabled. If a new CPU - which doesn't support mixed
656 endian - is hotplugged in after this feature has been enabled, there could
657 be unexpected results in the applications.
662 menu "ARMv8.1 architectural features"
664 config ARM64_HW_AFDBM
665 bool "Support for hardware updates of the Access and Dirty page flags"
668 The ARMv8.1 architecture extensions introduce support for
669 hardware updates of the access and dirty information in page
670 table entries. When enabled in TCR_EL1 (HA and HD bits) on
671 capable processors, accesses to pages with PTE_AF cleared will
672 set this bit instead of raising an access flag fault.
673 Similarly, writes to read-only pages with the DBM bit set will
674 clear the read-only bit (AP[2]) instead of raising a
677 Kernels built with this configuration option enabled continue
678 to work on pre-ARMv8.1 hardware and the performance impact is
679 minimal. If unsure, say Y.
682 bool "Enable support for Privileged Access Never (PAN)"
685 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
686 prevents the kernel or hypervisor from accessing user-space (EL0)
689 Choosing this option will cause any unprotected (not using
690 copy_to_user et al) memory access to fail with a permission fault.
692 The feature is detected at runtime, and will remain as a 'nop'
693 instruction if the cpu does not implement the feature.
695 config ARM64_LSE_ATOMICS
696 bool "Atomic instructions"
698 As part of the Large System Extensions, ARMv8.1 introduces new
699 atomic instructions that are designed specifically to scale in
702 Say Y here to make use of these instructions for the in-kernel
703 atomic routines. This incurs a small overhead on CPUs that do
704 not support these instructions and requires the kernel to be
705 built with binutils >= 2.25.
713 config ARM64_ACPI_PARKING_PROTOCOL
714 bool "Enable support for the ARM64 ACPI parking protocol"
717 Enable support for the ARM64 ACPI parking protocol. If disabled
718 the kernel will not allow booting through the ARM64 ACPI parking
719 protocol even if the corresponding data is present in the ACPI
723 string "Default kernel command string"
726 Provide a set of default command-line options at build time by
727 entering them here. As a minimum, you should specify the the
728 root device (e.g. root=/dev/nfs).
731 bool "Always use the default kernel command string"
733 Always use the default kernel command string, even if the boot
734 loader passes other arguments to the kernel.
735 This is useful if you cannot or don't want to change the
736 command-line options your boot loader passes to the kernel.
742 bool "UEFI runtime support"
743 depends on OF && !CPU_BIG_ENDIAN
746 select EFI_PARAMS_FROM_FDT
747 select EFI_RUNTIME_WRAPPERS
752 This option provides support for runtime services provided
753 by UEFI firmware (such as non-volatile variables, realtime
754 clock, and platform reset). A UEFI stub is also provided to
755 allow the kernel to be booted as an EFI application. This
756 is only useful on systems that have UEFI firmware.
759 bool "Enable support for SMBIOS (DMI) tables"
763 This enables SMBIOS/DMI feature for systems.
765 This option is only useful on systems that have UEFI firmware.
766 However, even with this option, the resultant kernel should
767 continue to boot on existing non-UEFI platforms.
771 menu "Userspace binary formats"
773 source "fs/Kconfig.binfmt"
776 bool "Kernel support for 32-bit EL0"
777 depends on ARM64_4K_PAGES || EXPERT
778 select COMPAT_BINFMT_ELF
780 select OLD_SIGSUSPEND3
781 select COMPAT_OLD_SIGACTION
783 This option enables support for a 32-bit EL0 running under a 64-bit
784 kernel at EL1. AArch32-specific components such as system calls,
785 the user helper functions, VFP support and the ptrace interface are
786 handled appropriately by the kernel.
788 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
789 that you will only be able to execute AArch32 binaries that were compiled
790 with page size aligned segments.
792 If you want to execute 32-bit userspace applications, say Y.
794 config SYSVIPC_COMPAT
796 depends on COMPAT && SYSVIPC
800 menu "Power management options"
802 source "kernel/power/Kconfig"
804 config ARCH_SUSPEND_POSSIBLE
809 menu "CPU Power Management"
811 source "drivers/cpuidle/Kconfig"
813 source "drivers/cpufreq/Kconfig"
819 source "drivers/Kconfig"
821 source "drivers/firmware/Kconfig"
823 source "drivers/acpi/Kconfig"
827 source "arch/arm64/kvm/Kconfig"
829 source "arch/arm64/Kconfig.debug"
831 source "security/Kconfig"
833 source "crypto/Kconfig"
835 source "arch/arm64/crypto/Kconfig"