arch/arm/mach-vexpress/ct-ca9x4.c

   1 /*
   2  * Versatile Express Core Tile Cortex A9x4 Support
   3  */
   4 #include <linux/init.h>
   5 #include <linux/gfp.h>
   6 #include <linux/device.h>
   7 #include <linux/dma-mapping.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/amba/bus.h>
  10 #include <linux/amba/clcd.h>
  11 #include <linux/clkdev.h>
  12 #include <linux/vexpress.h>
  13 #include <linux/irqchip/arm-gic.h>
  14
  15 #include <asm/hardware/arm_timer.h>
  16 #include <asm/hardware/cache-l2x0.h>
  17 #include <asm/smp_scu.h>
  18 #include <asm/smp_twd.h>
  19
  20 #include <mach/ct-ca9x4.h>
  21
  22 #include <asm/hardware/timer-sp.h>
  23
  24 #include <asm/mach/map.h>
  25 #include <asm/mach/time.h>
  26
  27 #include "core.h"
  28
  29 #include <mach/motherboard.h>
  30 #include <mach/irqs.h>
  31
  32 #include <plat/clcd.h>
  33
  34 static struct map_desc ct_ca9x4_io_desc[] __initdata = {
  35         {
  36                 .virtual        = V2T_PERIPH,
  37                 .pfn            = __phys_to_pfn(CT_CA9X4_MPIC),
  38                 .length         = SZ_8K,
  39                 .type           = MT_DEVICE,
  40         },
  41 };
  42
  43 static void __init ct_ca9x4_map_io(void)
  44 {
  45         iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
  46 }
  47
  48 #ifdef CONFIG_HAVE_ARM_TWD
  49 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, A9_MPCORE_TWD, IRQ_LOCALTIMER);
  50
  51 static void __init ca9x4_twd_init(void)
  52 {
  53         int err = twd_local_timer_register(&twd_local_timer);
  54         if (err)
  55                 pr_err("twd_local_timer_register failed %d\n", err);
  56 }
  57 #else
  58 #define ca9x4_twd_init()        do {} while(0)
  59 #endif
  60
  61 static void __init ct_ca9x4_init_irq(void)
  62 {
  63         gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),
  64                  ioremap(A9_MPCORE_GIC_CPU, SZ_256));
  65         ca9x4_twd_init();
  66 }
  67
  68 static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
  69 {
  70         unsigned long framesize = 1024 * 768 * 2;
  71
  72         fb->panel = versatile_clcd_get_panel("XVGA");
  73         if (!fb->panel)
  74                 return -EINVAL;
  75
  76         return versatile_clcd_setup_dma(fb, framesize);
  77 }
  78
  79 static struct clcd_board ct_ca9x4_clcd_data = {
  80         .name           = "CT-CA9X4",
  81         .caps           = CLCD_CAP_5551 | CLCD_CAP_565,
  82         .check          = clcdfb_check,
  83         .decode         = clcdfb_decode,
  84         .setup          = ct_ca9x4_clcd_setup,
  85         .mmap           = versatile_clcd_mmap_dma,
  86         .remove         = versatile_clcd_remove_dma,
  87 };
  88
  89 static AMBA_AHB_DEVICE(clcd, "ct:clcd", 0, CT_CA9X4_CLCDC, IRQ_CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
  90 static AMBA_APB_DEVICE(dmc, "ct:dmc", 0, CT_CA9X4_DMC, IRQ_CT_CA9X4_DMC, NULL);
  91 static AMBA_APB_DEVICE(smc, "ct:smc", 0, CT_CA9X4_SMC, IRQ_CT_CA9X4_SMC, NULL);
  92 static AMBA_APB_DEVICE(gpio, "ct:gpio", 0, CT_CA9X4_GPIO, IRQ_CT_CA9X4_GPIO, NULL);
  93
  94 static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
  95         &clcd_device,
  96         &dmc_device,
  97         &smc_device,
  98         &gpio_device,
  99 };
 100
 101 static struct resource pmu_resources[] = {
 102         [0] = {
 103                 .start  = IRQ_CT_CA9X4_PMU_CPU0,
 104                 .end    = IRQ_CT_CA9X4_PMU_CPU0,
 105                 .flags  = IORESOURCE_IRQ,
 106         },
 107         [1] = {
 108                 .start  = IRQ_CT_CA9X4_PMU_CPU1,
 109                 .end    = IRQ_CT_CA9X4_PMU_CPU1,
 110                 .flags  = IORESOURCE_IRQ,
 111         },
 112         [2] = {
 113                 .start  = IRQ_CT_CA9X4_PMU_CPU2,
 114                 .end    = IRQ_CT_CA9X4_PMU_CPU2,
 115                 .flags  = IORESOURCE_IRQ,
 116         },
 117         [3] = {
 118                 .start  = IRQ_CT_CA9X4_PMU_CPU3,
 119                 .end    = IRQ_CT_CA9X4_PMU_CPU3,
 120                 .flags  = IORESOURCE_IRQ,
 121         },
 122 };
 123
 124 static struct platform_device pmu_device = {
 125         .name           = "arm-pmu",
 126         .id             = -1,
 127         .num_resources  = ARRAY_SIZE(pmu_resources),
 128         .resource       = pmu_resources,
 129 };
 130
 131 static struct platform_device osc1_device = {
 132         .name           = "vexpress-osc",
 133         .id             = 1,
 134         .num_resources  = 1,
 135         .resource       = (struct resource []) {
 136                 VEXPRESS_RES_FUNC(0xf, 1),
 137         },
 138 };
 139
 140 static void __init ct_ca9x4_init(void)
 141 {
 142         int i;
 143
 144 #ifdef CONFIG_CACHE_L2X0
 145         void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
 146
 147         /* set RAM latencies to 1 cycle for this core tile. */
 148         writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
 149         writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
 150
 151         l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
 152 #endif
 153
 154         for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
 155                 amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
 156
 157         platform_device_register(&pmu_device);
 158         platform_device_register(&osc1_device);
 159
 160         WARN_ON(clk_register_clkdev(vexpress_osc_setup(&osc1_device.dev),
 161                         NULL, "ct:clcd"));
 162 }
 163
 164 #ifdef CONFIG_SMP
 165 static void *ct_ca9x4_scu_base __initdata;
 166
 167 static void __init ct_ca9x4_init_cpu_map(void)
 168 {
 169         int i, ncores;
 170
 171         ct_ca9x4_scu_base = ioremap(A9_MPCORE_SCU, SZ_128);
 172         if (WARN_ON(!ct_ca9x4_scu_base))
 173                 return;
 174
 175         ncores = scu_get_core_count(ct_ca9x4_scu_base);
 176
 177         if (ncores > nr_cpu_ids) {
 178                 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
 179                         ncores, nr_cpu_ids);
 180                 ncores = nr_cpu_ids;
 181         }
 182
 183         for (i = 0; i < ncores; ++i)
 184                 set_cpu_possible(i, true);
 185 }
 186
 187 static void __init ct_ca9x4_smp_enable(unsigned int max_cpus)
 188 {
 189         scu_enable(ct_ca9x4_scu_base);
 190 }
 191 #endif
 192
 193 struct ct_desc ct_ca9x4_desc __initdata = {
 194         .id             = V2M_CT_ID_CA9,
 195         .name           = "CA9x4",
 196         .map_io         = ct_ca9x4_map_io,
 197         .init_irq       = ct_ca9x4_init_irq,
 198         .init_tile      = ct_ca9x4_init,
 199 #ifdef CONFIG_SMP
 200         .init_cpu_map   = ct_ca9x4_init_cpu_map,
 201         .smp_enable     = ct_ca9x4_smp_enable,
 202 #endif
 203 };