arch/arm/mach-rockchip/vcodec_service.c

   1 /**
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  * author: chenhengming chm@rock-chips.com
   4  *         Alpha Lin, alpha.lin@rock-chips.com
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/fs.h>
  25 #include <linux/ioport.h>
  26 #include <linux/miscdevice.h>
  27 #include <linux/mm.h>
  28 #include <linux/poll.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/sched.h>
  31 #include <linux/slab.h>
  32 #include <linux/wakelock.h>
  33 #include <linux/cdev.h>
  34 #include <linux/of.h>
  35 #include <linux/of_platform.h>
  36 #include <linux/of_irq.h>
  37 #include <linux/rockchip/cpu.h>
  38 #include <linux/rockchip/cru.h>
  39 #ifdef CONFIG_MFD_SYSCON
  40 #include <linux/regmap.h>
  41 #endif
  42 #include <linux/mfd/syscon.h>
  43
  44 #include <asm/cacheflush.h>
  45 #include <linux/uaccess.h>
  46 #include <linux/rockchip/grf.h>
  47
  48 #if defined(CONFIG_ION_ROCKCHIP)
  49 #include <linux/rockchip_ion.h>
  50 #endif
  51
  52 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)
  53 #define CONFIG_VCODEC_MMU
  54 #endif
  55
  56 #ifdef CONFIG_VCODEC_MMU
  57 #include <linux/rockchip-iovmm.h>
  58 #include <linux/dma-buf.h>
  59 #endif
  60
  61 #ifdef CONFIG_DEBUG_FS
  62 #include <linux/debugfs.h>
  63 #endif
  64
  65 #if defined(CONFIG_ARCH_RK319X)
  66 #include <mach/grf.h>
  67 #endif
  68
  69 #include "vcodec_service.h"
  70
  71 static int debug;
  72 module_param(debug, int, S_IRUGO | S_IWUSR);
  73 MODULE_PARM_DESC(debug,
  74                  "Debug level - higher value produces more verbose messages");
  75
  76 #define HEVC_TEST_ENABLE        0
  77 #define VCODEC_CLOCK_ENABLE     1
  78
  79 typedef enum {
  80         VPU_DEC_ID_9190         = 0x6731,
  81         VPU_ID_8270             = 0x8270,
  82         VPU_ID_4831             = 0x4831,
  83         HEVC_ID                 = 0x6867,
  84 } VPU_HW_ID;
  85
  86 enum VPU_HW_SPEC {
  87         VPU_TYPE_VPU,
  88         VPU_TYPE_HEVC,
  89         VPU_TYPE_COMBO_NOENC,
  90         VPU_TYPE_COMBO
  91 };
  92
  93 typedef enum {
  94         VPU_DEC_TYPE_9190       = 0,
  95         VPU_ENC_TYPE_8270       = 0x100,
  96         VPU_ENC_TYPE_4831       ,
  97 } VPU_HW_TYPE_E;
  98
  99 typedef enum VPU_FREQ {
 100         VPU_FREQ_200M,
 101         VPU_FREQ_266M,
 102         VPU_FREQ_300M,
 103         VPU_FREQ_400M,
 104         VPU_FREQ_500M,
 105         VPU_FREQ_600M,
 106         VPU_FREQ_DEFAULT,
 107         VPU_FREQ_BUT,
 108 } VPU_FREQ;
 109
 110 typedef struct {
 111         VPU_HW_ID               hw_id;
 112         unsigned long           hw_addr;
 113         unsigned long           enc_offset;
 114         unsigned long           enc_reg_num;
 115         unsigned long           enc_io_size;
 116         unsigned long           dec_offset;
 117         unsigned long           dec_reg_num;
 118         unsigned long           dec_io_size;
 119 } VPU_HW_INFO_E;
 120
 121 struct extra_info_elem {
 122         u32 index;
 123         u32 offset;
 124 };
 125
 126 #define EXTRA_INFO_MAGIC        0x4C4A46
 127
 128 struct extra_info_for_iommu {
 129         u32 magic;
 130         u32 cnt;
 131         struct extra_info_elem elem[20];
 132 };
 133
 134 #define VPU_SERVICE_SHOW_TIME                   0
 135
 136 #if VPU_SERVICE_SHOW_TIME
 137 static struct timeval enc_start, enc_end;
 138 static struct timeval dec_start, dec_end;
 139 static struct timeval pp_start,  pp_end;
 140 #endif
 141
 142 #define MHZ                                     (1000*1000)
 143
 144 #define REG_NUM_9190_DEC                        (60)
 145 #define REG_NUM_9190_PP                         (41)
 146 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 147
 148 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 149
 150 #define REG_NUM_ENC_8270                        (96)
 151 #define REG_SIZE_ENC_8270                       (0x200)
 152 #define REG_NUM_ENC_4831                        (164)
 153 #define REG_SIZE_ENC_4831                       (0x400)
 154
 155 #define REG_NUM_HEVC_DEC                        (68)
 156
 157 #define SIZE_REG(reg)                           ((reg)*4)
 158
 159 static VPU_HW_INFO_E vpu_hw_set[] = {
 160         [0] = {
 161                 .hw_id          = VPU_ID_8270,
 162                 .hw_addr        = 0,
 163                 .enc_offset     = 0x0,
 164                 .enc_reg_num    = REG_NUM_ENC_8270,
 165                 .enc_io_size    = REG_NUM_ENC_8270 * 4,
 166                 .dec_offset     = REG_SIZE_ENC_8270,
 167                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 168                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 169         },
 170         [1] = {
 171                 .hw_id          = VPU_ID_4831,
 172                 .hw_addr        = 0,
 173                 .enc_offset     = 0x0,
 174                 .enc_reg_num    = REG_NUM_ENC_4831,
 175                 .enc_io_size    = REG_NUM_ENC_4831 * 4,
 176                 .dec_offset     = REG_SIZE_ENC_4831,
 177                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 178                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 179         },
 180         [2] = {
 181                 .hw_id          = HEVC_ID,
 182                 .hw_addr        = 0,
 183                 .dec_offset     = 0x0,
 184                 .dec_reg_num    = REG_NUM_HEVC_DEC,
 185                 .dec_io_size    = REG_NUM_HEVC_DEC * 4,
 186         },
 187         [3] = {
 188                 .hw_id          = VPU_DEC_ID_9190,
 189                 .hw_addr        = 0,
 190                 .enc_offset     = 0x0,
 191                 .enc_reg_num    = 0,
 192                 .enc_io_size    = 0,
 193                 .dec_offset     = 0,
 194                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 195                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 196         },
 197 };
 198
 199
 200 #define DEC_INTERRUPT_REGISTER                  1
 201 #define PP_INTERRUPT_REGISTER                   60
 202 #define ENC_INTERRUPT_REGISTER                  1
 203
 204 #define DEC_INTERRUPT_BIT                       0x100
 205 #define DEC_BUFFER_EMPTY_BIT                    0x4000
 206 #define PP_INTERRUPT_BIT                        0x100
 207 #define ENC_INTERRUPT_BIT                       0x1
 208
 209 #define HEVC_DEC_INT_RAW_BIT                    0x200
 210 #define HEVC_DEC_STR_ERROR_BIT                  0x4000
 211 #define HEVC_DEC_BUS_ERROR_BIT                  0x2000
 212 #define HEVC_DEC_BUFFER_EMPTY_BIT               0x10000
 213
 214 #define VPU_REG_EN_ENC                          14
 215 #define VPU_REG_ENC_GATE                        2
 216 #define VPU_REG_ENC_GATE_BIT                    (1<<4)
 217
 218 #define VPU_REG_EN_DEC                          1
 219 #define VPU_REG_DEC_GATE                        2
 220 #define VPU_REG_DEC_GATE_BIT                    (1<<10)
 221 #define VPU_REG_EN_PP                           0
 222 #define VPU_REG_PP_GATE                         1
 223 #define VPU_REG_PP_GATE_BIT                     (1<<8)
 224 #define VPU_REG_EN_DEC_PP                       1
 225 #define VPU_REG_DEC_PP_GATE                     61
 226 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)
 227
 228 #define DEBUG
 229 #ifdef DEBUG
 230 #define vpu_debug(level, fmt, args...)                          \
 231         do {                                                    \
 232                 if (debug >= level)                             \
 233                         pr_info("%s:%d: " fmt,                  \
 234                                  __func__, __LINE__, ##args);   \
 235         } while (0)
 236 #else
 237 #define vpu_debug(level, fmt, args...)
 238 #endif
 239
 240 #define vpu_debug_enter() vpu_debug(4, "enter\n")
 241 #define vpu_debug_leave() vpu_debug(4, "leave\n")
 242
 243 #define vpu_err(fmt, args...)                           \
 244                 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
 245
 246 #if defined(CONFIG_VCODEC_MMU)
 247 static u8 addr_tbl_vpu_h264dec[] = {
 248         12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
 249         25, 26, 27, 28, 29, 40, 41
 250 };
 251
 252 static u8 addr_tbl_vpu_vp8dec[] = {
 253         10, 12, 13, 14, 18, 19, 22, 23, 24, 25, 26, 27, 28, 29, 40
 254 };
 255
 256 static u8 addr_tbl_vpu_vp6dec[] = {
 257         12, 13, 14, 18, 27, 40
 258 };
 259
 260 static u8 addr_tbl_vpu_vc1dec[] = {
 261         12, 13, 14, 15, 16, 17, 27, 41
 262 };
 263
 264 static u8 addr_tbl_vpu_jpegdec[] = {
 265         12, 40, 66, 67
 266 };
 267
 268 static u8 addr_tbl_vpu_defaultdec[] = {
 269         12, 13, 14, 15, 16, 17, 40, 41
 270 };
 271
 272 static u8 addr_tbl_vpu_enc[] = {
 273         5, 6, 7, 8, 9, 10, 11, 12, 13, 51
 274 };
 275
 276 static u8 addr_tbl_hevc_dec[] = {
 277         4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
 278         21, 22, 23, 24, 42, 43
 279 };
 280 #endif
 281
 282 enum VPU_DEC_FMT {
 283         VPU_DEC_FMT_H264,
 284         VPU_DEC_FMT_MPEG4,
 285         VPU_DEC_FMT_H263,
 286         VPU_DEC_FMT_JPEG,
 287         VPU_DEC_FMT_VC1,
 288         VPU_DEC_FMT_MPEG2,
 289         VPU_DEC_FMT_MPEG1,
 290         VPU_DEC_FMT_VP6,
 291         VPU_DEC_FMT_RV,
 292         VPU_DEC_FMT_VP7,
 293         VPU_DEC_FMT_VP8,
 294         VPU_DEC_FMT_AVS,
 295         VPU_DEC_FMT_SVC,
 296         VPU_DEC_FMT_VC2,
 297         VPU_DEC_FMT_MVC,
 298         VPU_DEC_FMT_THEORA,
 299         VPU_DEC_FMT_RES
 300 };
 301
 302 /**
 303  * struct for process session which connect to vpu
 304  *
 305  * @author ChenHengming (2011-5-3)
 306  */
 307 typedef struct vpu_session {
 308         enum VPU_CLIENT_TYPE type;
 309         /* a linked list of data so we can access them for debugging */
 310         struct list_head list_session;
 311         /* a linked list of register data waiting for process */
 312         struct list_head waiting;
 313         /* a linked list of register data in processing */
 314         struct list_head running;
 315         /* a linked list of register data processed */
 316         struct list_head done;
 317         wait_queue_head_t wait;
 318         pid_t pid;
 319         atomic_t task_running;
 320 } vpu_session;
 321
 322 /**
 323  * struct for process register set
 324  *
 325  * @author ChenHengming (2011-5-4)
 326  */
 327 typedef struct vpu_reg {
 328         enum VPU_CLIENT_TYPE type;
 329         VPU_FREQ freq;
 330         vpu_session *session;
 331         struct list_head session_link;          /* link to vpu service session */
 332         struct list_head status_link;           /* link to register set list */
 333         unsigned long size;
 334 #if defined(CONFIG_VCODEC_MMU)
 335         struct list_head mem_region_list;
 336 #endif
 337         unsigned long *reg;
 338 } vpu_reg;
 339
 340 typedef struct vpu_device {
 341         atomic_t                irq_count_codec;
 342         atomic_t                irq_count_pp;
 343         unsigned long           iobaseaddr;
 344         unsigned int            iosize;
 345         volatile u32            *hwregs;
 346 } vpu_device;
 347
 348 enum vcodec_device_id {
 349         VCODEC_DEVICE_ID_VPU,
 350         VCODEC_DEVICE_ID_HEVC,
 351         VCODEC_DEVICE_ID_COMBO
 352 };
 353
 354 enum VCODEC_RUNNING_MODE {
 355         VCODEC_RUNNING_MODE_NONE = -1,
 356         VCODEC_RUNNING_MODE_VPU,
 357         VCODEC_RUNNING_MODE_HEVC,
 358 };
 359
 360 struct vcodec_mem_region {
 361         struct list_head srv_lnk;
 362         struct list_head reg_lnk;
 363         struct list_head session_lnk;
 364         unsigned long iova;     /* virtual address for iommu */
 365         unsigned long len;
 366         u32 reg_idx;
 367         struct ion_handle *hdl;
 368 };
 369
 370 enum vpu_ctx_state {
 371         MMU_ACTIVATED   = BIT(0)
 372 };
 373
 374 struct vpu_subdev_data {
 375         struct cdev cdev;
 376         dev_t dev_t;
 377         struct class *cls;
 378         struct device *child_dev;
 379
 380         int irq_enc;
 381         int irq_dec;
 382         struct vpu_service_info *pservice;
 383
 384         u32 *regs;
 385         enum VCODEC_RUNNING_MODE mode;
 386         struct list_head lnk_service;
 387
 388         struct device *dev;
 389
 390         vpu_device enc_dev;
 391         vpu_device dec_dev;
 392         VPU_HW_INFO_E *hw_info;
 393
 394         u32 reg_size;
 395         unsigned long state;
 396
 397 #ifdef CONFIG_DEBUG_FS
 398         struct dentry *debugfs_dir;
 399         struct dentry *debugfs_file_regs;
 400 #endif
 401
 402 #if defined(CONFIG_VCODEC_MMU)
 403         struct device *mmu_dev;
 404 #endif
 405 };
 406
 407 typedef struct vpu_service_info {
 408         struct wake_lock wake_lock;
 409         struct delayed_work power_off_work;
 410         struct mutex lock;
 411         struct list_head waiting;               /* link to link_reg in struct vpu_reg */
 412         struct list_head running;               /* link to link_reg in struct vpu_reg */
 413         struct list_head done;                  /* link to link_reg in struct vpu_reg */
 414         struct list_head session;               /* link to list_session in struct vpu_session */
 415         atomic_t total_running;
 416         bool enabled;
 417         vpu_reg *reg_codec;
 418         vpu_reg *reg_pproc;
 419         vpu_reg *reg_resev;
 420         struct vpu_dec_config dec_config;
 421         struct vpu_enc_config enc_config;
 422
 423         bool auto_freq;
 424         bool bug_dec_addr;
 425         atomic_t freq_status;
 426
 427         struct clk *aclk_vcodec;
 428         struct clk *hclk_vcodec;
 429         struct clk *clk_core;
 430         struct clk *clk_cabac;
 431         struct clk *pd_video;
 432
 433         struct device *dev;
 434
 435         u32 irq_status;
 436 #if defined(CONFIG_VCODEC_MMU)
 437         struct ion_client *ion_client;
 438         struct list_head mem_region_list;
 439 #endif
 440
 441         enum vcodec_device_id dev_id;
 442
 443         enum VCODEC_RUNNING_MODE curr_mode;
 444         u32 prev_mode;
 445
 446         struct delayed_work simulate_work;
 447
 448         u32 mode_bit;
 449         u32 mode_ctrl;
 450         u32 *reg_base;
 451         u32 ioaddr;
 452 #ifdef CONFIG_MFD_SYSCON
 453         struct regmap *grf_base;
 454 #else
 455         u32 *grf_base;
 456 #endif
 457         char *name;
 458
 459         u32 subcnt;
 460         struct list_head subdev_list;
 461 } vpu_service_info;
 462
 463 struct vcodec_combo {
 464         struct vpu_service_info *vpu_srv;
 465         struct vpu_service_info *hevc_srv;
 466         struct list_head waiting;
 467         struct list_head running;
 468         struct mutex run_lock;
 469         vpu_reg *reg_codec;
 470         enum vcodec_device_id current_hw_mode;
 471 };
 472
 473 typedef struct vpu_request {
 474         unsigned long *req;
 475         u32 size;
 476 } vpu_request;
 477
 478 /* debugfs root directory for all device (vpu, hevc).*/
 479 static struct dentry *parent;
 480
 481 #ifdef CONFIG_DEBUG_FS
 482 static int vcodec_debugfs_init(void);
 483 static void vcodec_debugfs_exit(void);
 484 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);
 485 static int debug_vcodec_open(struct inode *inode, struct file *file);
 486
 487 static const struct file_operations debug_vcodec_fops = {
 488         .open = debug_vcodec_open,
 489         .read = seq_read,
 490         .llseek = seq_lseek,
 491         .release = single_release,
 492 };
 493 #endif
 494
 495 #define VDPU_SOFT_RESET_REG     101
 496 #define VDPU_CLEAN_CACHE_REG    516
 497 #define VEPU_CLEAN_CACHE_REG    772
 498 #define HEVC_CLEAN_CACHE_REG    260
 499
 500 #define VPU_REG_ENABLE(base, reg)       do { \
 501                                                 base[reg] = 1; \
 502                                         } while (0)
 503
 504 #define VDPU_SOFT_RESET(base)   VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
 505 #define VDPU_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, VDPU_CLEAN_CACHE_REG)
 506 #define VEPU_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, VEPU_CLEAN_CACHE_REG)
 507 #define HEVC_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, HEVC_CLEAN_CACHE_REG)
 508
 509 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */
 510 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */
 511
 512 static void vcodec_enter_mode(struct vpu_subdev_data *data)
 513 {
 514         int bits;
 515         u32 raw = 0;
 516         struct vpu_service_info *pservice = data->pservice;
 517         struct vpu_subdev_data *subdata, *n;
 518         if (pservice->subcnt < 2 || pservice->curr_mode == data->mode) {
 519                 pservice->prev_mode = pservice->curr_mode;
 520                 return;
 521         }
 522         vpu_debug(3, "vcodec enter mode %d\n", data->mode);
 523 #if defined(CONFIG_VCODEC_MMU)
 524         list_for_each_entry_safe(subdata, n, &pservice->subdev_list, lnk_service) {
 525                 if (data != subdata && subdata->mmu_dev &&
 526                     test_bit(MMU_ACTIVATED, &subdata->state)) {
 527                         clear_bit(MMU_ACTIVATED, &subdata->state);
 528                         rockchip_iovmm_deactivate(subdata->dev);
 529                 }
 530         }
 531 #endif
 532         bits = 1 << pservice->mode_bit;
 533 #ifdef CONFIG_MFD_SYSCON
 534         regmap_read(pservice->grf_base, pservice->mode_ctrl, &raw);
 535
 536         if (data->mode == VCODEC_RUNNING_MODE_HEVC)
 537                 regmap_write(pservice->grf_base, pservice->mode_ctrl,
 538                         raw | bits | (bits << 16));
 539         else
 540                 regmap_write(pservice->grf_base, pservice->mode_ctrl,
 541                         (raw & (~bits)) | (bits << 16));
 542 #else
 543         raw = readl_relaxed(pservice->grf_base + pservice->mode_ctrl / 4);
 544         if (data->mode == VCODEC_RUNNING_MODE_HEVC)
 545                 writel_relaxed(raw | bits | (bits << 16),
 546                         pservice->grf_base + pservice->mode_ctrl / 4);
 547         else
 548                 writel_relaxed((raw & (~bits)) | (bits << 16),
 549                         pservice->grf_base + pservice->mode_ctrl / 4);
 550 #endif
 551 #if defined(CONFIG_VCODEC_MMU)
 552         if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
 553                 set_bit(MMU_ACTIVATED, &data->state);
 554                 BUG_ON(!pservice->enabled);
 555                 if (pservice->enabled)
 556                         rockchip_iovmm_activate(data->dev);
 557         }
 558 #endif
 559         pservice->prev_mode = pservice->curr_mode;
 560         pservice->curr_mode = data->mode;
 561 }
 562
 563 static void vcodec_exit_mode(struct vpu_service_info *pservice)
 564 {
 565
 566 }
 567
 568 static int vpu_get_clk(struct vpu_service_info *pservice)
 569 {
 570 #if VCODEC_CLOCK_ENABLE
 571         switch (pservice->dev_id) {
 572         case VCODEC_DEVICE_ID_HEVC:
 573                 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");
 574                 if (IS_ERR(pservice->clk_cabac)) {
 575                         dev_err(pservice->dev, "failed on clk_get clk_cabac\n");
 576                         return -1;
 577                 }
 578
 579                 pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");
 580                 if (IS_ERR(pservice->pd_video)) {
 581                         dev_err(pservice->dev, "failed on clk_get pd_hevc\n");
 582                         return -1;
 583                 }
 584         case VCODEC_DEVICE_ID_COMBO:
 585                 pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");
 586                 if (IS_ERR(pservice->clk_core)) {
 587                         dev_err(pservice->dev, "failed on clk_get clk_core\n");
 588                         return -1;
 589                 }
 590         case VCODEC_DEVICE_ID_VPU:
 591                 pservice->aclk_vcodec = devm_clk_get(pservice->dev, "aclk_vcodec");
 592                 if (IS_ERR(pservice->aclk_vcodec)) {
 593                         dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");
 594                         return -1;
 595                 }
 596
 597                 pservice->hclk_vcodec = devm_clk_get(pservice->dev, "hclk_vcodec");
 598                 if (IS_ERR(pservice->hclk_vcodec)) {
 599                         dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");
 600                         return -1;
 601                 }
 602                 if (pservice->pd_video == NULL) {
 603                         pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
 604                         if (IS_ERR(pservice->pd_video))
 605                                 pservice->pd_video = NULL;
 606                 }
 607                 break;
 608         default:
 609                 ;
 610         }
 611
 612         return 0;
 613 #else
 614         return 0;
 615 #endif
 616 }
 617
 618 static void vpu_put_clk(struct vpu_service_info *pservice)
 619 {
 620 #if VCODEC_CLOCK_ENABLE
 621         if (pservice->pd_video)
 622                 devm_clk_put(pservice->dev, pservice->pd_video);
 623         if (pservice->aclk_vcodec)
 624                 devm_clk_put(pservice->dev, pservice->aclk_vcodec);
 625         if (pservice->hclk_vcodec)
 626                 devm_clk_put(pservice->dev, pservice->hclk_vcodec);
 627         if (pservice->clk_core)
 628                 devm_clk_put(pservice->dev, pservice->clk_core);
 629         if (pservice->clk_cabac)
 630                 devm_clk_put(pservice->dev, pservice->clk_cabac);
 631 #endif
 632 }
 633
 634 static void vpu_reset(struct vpu_subdev_data *data)
 635 {
 636         struct vpu_service_info *pservice = data->pservice;
 637 #if defined(CONFIG_ARCH_RK29)
 638         clk_disable(aclk_ddr_vepu);
 639         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
 640         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
 641         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
 642         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
 643         mdelay(10);
 644         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
 645         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
 646         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
 647         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
 648         clk_enable(aclk_ddr_vepu);
 649 #elif defined(CONFIG_ARCH_RK30)
 650         pmu_set_idle_request(IDLE_REQ_VIDEO, true);
 651         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
 652         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
 653         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
 654         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
 655         mdelay(1);
 656         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
 657         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
 658         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
 659         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
 660         pmu_set_idle_request(IDLE_REQ_VIDEO, false);
 661 #endif
 662         pservice->reg_codec = NULL;
 663         pservice->reg_pproc = NULL;
 664         pservice->reg_resev = NULL;
 665
 666 #if defined(CONFIG_VCODEC_MMU)
 667         if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
 668                 set_bit(MMU_ACTIVATED, &data->state);
 669                 BUG_ON(!pservice->enabled);
 670                 if (pservice->enabled)
 671                         rockchip_iovmm_activate(data->dev);
 672         }
 673 #endif
 674 }
 675
 676 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg);
 677 static void vpu_service_session_clear(struct vpu_subdev_data *data, vpu_session *session)
 678 {
 679         vpu_reg *reg, *n;
 680         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
 681                 reg_deinit(data, reg);
 682         }
 683         list_for_each_entry_safe(reg, n, &session->running, session_link) {
 684                 reg_deinit(data, reg);
 685         }
 686         list_for_each_entry_safe(reg, n, &session->done, session_link) {
 687                 reg_deinit(data, reg);
 688         }
 689 }
 690
 691 static void vpu_service_dump(struct vpu_service_info *pservice)
 692 {
 693 }
 694
 695 static void vpu_service_power_off(struct vpu_service_info *pservice)
 696 {
 697         int total_running;
 698         struct vpu_subdev_data *data = NULL, *n;
 699         if (!pservice->enabled)
 700                 return;
 701
 702         pservice->enabled = false;
 703         total_running = atomic_read(&pservice->total_running);
 704         if (total_running) {
 705                 pr_alert("alert: power off when %d task running!!\n", total_running);
 706                 mdelay(50);
 707                 pr_alert("alert: delay 50 ms for running task\n");
 708                 vpu_service_dump(pservice);
 709         }
 710
 711         pr_info("%s: power off...", dev_name(pservice->dev));
 712         udelay(10);
 713 #if defined(CONFIG_VCODEC_MMU)
 714         list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
 715                 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
 716                         clear_bit(MMU_ACTIVATED, &data->state);
 717                         rockchip_iovmm_deactivate(data->dev);
 718                 }
 719         }
 720         pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
 721 #endif
 722
 723 #if VCODEC_CLOCK_ENABLE
 724         if (pservice->pd_video)
 725                 clk_disable_unprepare(pservice->pd_video);
 726         if (pservice->hclk_vcodec)
 727                 clk_disable_unprepare(pservice->hclk_vcodec);
 728         if (pservice->aclk_vcodec)
 729                 clk_disable_unprepare(pservice->aclk_vcodec);
 730         if (pservice->clk_core)
 731                 clk_disable_unprepare(pservice->clk_core);
 732         if (pservice->clk_cabac)
 733                 clk_disable_unprepare(pservice->clk_cabac);
 734 #endif
 735
 736         wake_unlock(&pservice->wake_lock);
 737         pr_info("done\n");
 738 }
 739
 740 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
 741 {
 742         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);
 743 }
 744
 745 static void vpu_power_off_work(struct work_struct *work_s)
 746 {
 747         struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
 748         struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);
 749
 750         if (mutex_trylock(&pservice->lock)) {
 751                 vpu_service_power_off(pservice);
 752                 mutex_unlock(&pservice->lock);
 753         } else {
 754                 /* Come back later if the device is busy... */
 755                 vpu_queue_power_off_work(pservice);
 756         }
 757 }
 758
 759 static void vpu_service_power_on(struct vpu_service_info *pservice)
 760 {
 761         static ktime_t last;
 762         ktime_t now = ktime_get();
 763         if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
 764                 cancel_delayed_work_sync(&pservice->power_off_work);
 765                 vpu_queue_power_off_work(pservice);
 766                 last = now;
 767         }
 768         if (pservice->enabled)
 769                 return ;
 770
 771         pservice->enabled = true;
 772         pr_info("%s: power on\n", dev_name(pservice->dev));
 773
 774 #define BIT_VCODEC_CLK_SEL      (1<<10)
 775         if (cpu_is_rk312x())
 776                 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |
 777                         BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
 778                         RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
 779
 780 #if VCODEC_CLOCK_ENABLE
 781         if (pservice->aclk_vcodec)
 782                 clk_prepare_enable(pservice->aclk_vcodec);
 783         if (pservice->hclk_vcodec)
 784                 clk_prepare_enable(pservice->hclk_vcodec);
 785         if (pservice->clk_core)
 786                 clk_prepare_enable(pservice->clk_core);
 787         if (pservice->clk_cabac)
 788                 clk_prepare_enable(pservice->clk_cabac);
 789         if (pservice->pd_video)
 790                 clk_prepare_enable(pservice->pd_video);
 791 #endif
 792
 793         udelay(10);
 794         wake_lock(&pservice->wake_lock);
 795 }
 796
 797 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
 798 {
 799         unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;
 800         return ((type == 8) || (type == 4));
 801 }
 802
 803 static inline bool reg_check_interlace(vpu_reg *reg)
 804 {
 805         unsigned long type = (reg->reg[3] & (1 << 23));
 806         return (type > 0);
 807 }
 808
 809 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)
 810 {
 811         enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);
 812         return type;
 813 }
 814
 815 static inline int reg_probe_width(vpu_reg *reg)
 816 {
 817         int width_in_mb = reg->reg[4] >> 23;
 818         return width_in_mb * 16;
 819 }
 820
 821 #if defined(CONFIG_VCODEC_MMU)
 822 static int vcodec_fd_to_iova(struct vpu_subdev_data *data, vpu_reg *reg,int fd)
 823 {
 824         struct vpu_service_info *pservice = data->pservice;
 825         struct ion_handle *hdl;
 826         int ret = 0;
 827         struct vcodec_mem_region *mem_region;
 828
 829         hdl = ion_import_dma_buf(pservice->ion_client, fd);
 830         if (IS_ERR(hdl)) {
 831                 vpu_err("import dma-buf from fd %d failed\n", fd);
 832                 return PTR_ERR(hdl);
 833         }
 834         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
 835
 836         if (mem_region == NULL) {
 837                 vpu_err("allocate memory for iommu memory region failed\n");
 838                 ion_free(pservice->ion_client, hdl);
 839                 return -1;
 840         }
 841
 842         mem_region->hdl = hdl;
 843         vcodec_enter_mode(data);
 844         ret = ion_map_iommu(data->dev, pservice->ion_client,
 845                 mem_region->hdl, &mem_region->iova, &mem_region->len);
 846         vcodec_exit_mode(pservice);
 847
 848         if (ret < 0) {
 849                 vpu_err("ion map iommu failed\n");
 850                 kfree(mem_region);
 851                 ion_free(pservice->ion_client, hdl);
 852                 return ret;
 853         }
 854         INIT_LIST_HEAD(&mem_region->reg_lnk);
 855         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
 856         return mem_region->iova;
 857 }
 858
 859 static int vcodec_bufid_to_iova(struct vpu_subdev_data *data, u8 *tbl,
 860                                 int size, vpu_reg *reg,
 861                                 struct extra_info_for_iommu *ext_inf)
 862 {
 863         struct vpu_service_info *pservice = data->pservice;
 864         int i;
 865         int usr_fd = 0;
 866         int offset = 0;
 867
 868         if (tbl == NULL || size <= 0) {
 869                 dev_err(pservice->dev, "input arguments invalidate\n");
 870                 return -1;
 871         }
 872
 873         vpu_service_power_on(pservice);
 874
 875         for (i = 0; i < size; i++) {
 876                 usr_fd = reg->reg[tbl[i]] & 0x3FF;
 877
 878                 if (tbl[i] == 41 && data->hw_info->hw_id != HEVC_ID &&
 879                     (reg->type == VPU_DEC || reg->type == VPU_DEC_PP))
 880                         /* special for vpu dec num 41 regitster */
 881                         offset = reg->reg[tbl[i]] >> 10 << 4;
 882                 else
 883                         offset = reg->reg[tbl[i]] >> 10;
 884
 885                 if (usr_fd != 0) {
 886                         struct ion_handle *hdl;
 887                         int ret = 0;
 888                         struct vcodec_mem_region *mem_region;
 889
 890                         hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);
 891                         if (IS_ERR(hdl)) {
 892                                 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);
 893                                 return PTR_ERR(hdl);
 894                         }
 895
 896                         if (tbl[i] == 42 && data->hw_info->hw_id == HEVC_ID){
 897                                 int i = 0;
 898                                 char *pps;
 899                                 pps = (char *)ion_map_kernel(pservice->ion_client,hdl);
 900                                 for (i=0; i<64; i++) {
 901                                         u32 scaling_offset;
 902                                         u32 tmp;
 903                                         int scaling_fd= 0;
 904                                         scaling_offset = (u32)pps[i*80+74];
 905                                         scaling_offset += (u32)pps[i*80+75] << 8;
 906                                         scaling_offset += (u32)pps[i*80+76] << 16;
 907                                         scaling_offset += (u32)pps[i*80+77] << 24;
 908                                         scaling_fd = scaling_offset&0x3ff;
 909                                         scaling_offset = scaling_offset >> 10;
 910                                         if(scaling_fd > 0) {
 911                                                 tmp = vcodec_fd_to_iova(data, reg, scaling_fd);
 912                                                 tmp += scaling_offset;
 913                                                 pps[i*80+74] = tmp & 0xff;
 914                                                 pps[i*80+75] = (tmp >> 8) & 0xff;
 915                                                 pps[i*80+76] = (tmp >> 16) & 0xff;
 916                                                 pps[i*80+77] = (tmp >> 24) & 0xff;
 917                                         }
 918                                 }
 919                         }
 920
 921                         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
 922
 923                         if (mem_region == NULL) {
 924                                 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");
 925                                 ion_free(pservice->ion_client, hdl);
 926                                 return -1;
 927                         }
 928
 929                         mem_region->hdl = hdl;
 930                         mem_region->reg_idx = tbl[i];
 931                         vcodec_enter_mode(data);
 932                         ret = ion_map_iommu(data->dev,
 933                                             pservice->ion_client,
 934                                             mem_region->hdl,
 935                                             &mem_region->iova,
 936                                             &mem_region->len);
 937                         vcodec_exit_mode(pservice);
 938
 939                         if (ret < 0) {
 940                                 dev_err(pservice->dev, "ion map iommu failed\n");
 941                                 kfree(mem_region);
 942                                 ion_free(pservice->ion_client, hdl);
 943                                 return ret;
 944                         }
 945                         reg->reg[tbl[i]] = mem_region->iova + offset;
 946                         INIT_LIST_HEAD(&mem_region->reg_lnk);
 947                         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
 948                 }
 949         }
 950
 951         if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {
 952                 for (i=0; i<ext_inf->cnt; i++) {
 953                         vpu_debug(3, "reg[%d] + offset %d\n",
 954                                   ext_inf->elem[i].index,
 955                                   ext_inf->elem[i].offset);
 956                         reg->reg[ext_inf->elem[i].index] +=
 957                                 ext_inf->elem[i].offset;
 958                 }
 959         }
 960
 961         return 0;
 962 }
 963
 964 static int vcodec_reg_address_translate(struct vpu_subdev_data *data,
 965                                         vpu_reg *reg,
 966                                         struct extra_info_for_iommu *ext_inf)
 967 {
 968         VPU_HW_ID hw_id;
 969         u8 *tbl;
 970         int size = 0;
 971
 972         hw_id = data->hw_info->hw_id;
 973
 974         if (hw_id == HEVC_ID) {
 975                 tbl = addr_tbl_hevc_dec;
 976                 size = sizeof(addr_tbl_hevc_dec);
 977         } else {
 978                 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
 979                         switch (reg_check_fmt(reg)) {
 980                         case VPU_DEC_FMT_H264:
 981                                 {
 982                                         tbl = addr_tbl_vpu_h264dec;
 983                                         size = sizeof(addr_tbl_vpu_h264dec);
 984                                         break;
 985                                 }
 986                         case VPU_DEC_FMT_VP8:
 987                         case VPU_DEC_FMT_VP7:
 988                                 {
 989                                         tbl = addr_tbl_vpu_vp8dec;
 990                                         size = sizeof(addr_tbl_vpu_vp8dec);
 991                                         break;
 992                                 }
 993
 994                         case VPU_DEC_FMT_VP6:
 995                                 {
 996                                         tbl = addr_tbl_vpu_vp6dec;
 997                                         size = sizeof(addr_tbl_vpu_vp6dec);
 998                                         break;
 999                                 }
1000                         case VPU_DEC_FMT_VC1:
1001                                 {
1002                                         tbl = addr_tbl_vpu_vc1dec;
1003                                         size = sizeof(addr_tbl_vpu_vc1dec);
1004                                         break;
1005                                 }
1006
1007                         case VPU_DEC_FMT_JPEG:
1008                                 {
1009                                         tbl = addr_tbl_vpu_jpegdec;
1010                                         size = sizeof(addr_tbl_vpu_jpegdec);
1011                                         break;
1012                                 }
1013                         default:
1014                                 tbl = addr_tbl_vpu_defaultdec;
1015                                 size = sizeof(addr_tbl_vpu_defaultdec);
1016                                 break;
1017                         }
1018                 } else if (reg->type == VPU_ENC) {
1019                         tbl = addr_tbl_vpu_enc;
1020                         size = sizeof(addr_tbl_vpu_enc);
1021                 }
1022         }
1023
1024         if (size != 0) {
1025                 return vcodec_bufid_to_iova(data, tbl, size, reg, ext_inf);
1026         } else {
1027                 return -1;
1028         }
1029 }
1030 #endif
1031
1032 static vpu_reg *reg_init(struct vpu_subdev_data *data,
1033         vpu_session *session, void __user *src, u32 size)
1034 {
1035         struct vpu_service_info *pservice = data->pservice;
1036         int extra_size = 0;
1037         struct extra_info_for_iommu extra_info;
1038         vpu_reg *reg = kmalloc(sizeof(vpu_reg) + data->reg_size, GFP_KERNEL);
1039
1040         vpu_debug_enter();
1041
1042         if (NULL == reg) {
1043                 vpu_err("error: kmalloc fail in reg_init\n");
1044                 return NULL;
1045         }
1046
1047         if (size > data->reg_size) {
1048                 /*printk("warning: vpu reg size %lu is larger than hw reg size %lu\n",
1049                   size, pservice->reg_size);
1050                 size = pservice->reg_size;*/
1051                 extra_size = size - data->reg_size;
1052                 size = data->reg_size;
1053         }
1054         reg->session = session;
1055         reg->type = session->type;
1056         reg->size = size;
1057         reg->freq = VPU_FREQ_DEFAULT;
1058         reg->reg = (unsigned long *)&reg[1];
1059         INIT_LIST_HEAD(&reg->session_link);
1060         INIT_LIST_HEAD(&reg->status_link);
1061
1062 #if defined(CONFIG_VCODEC_MMU)
1063         if (data->mmu_dev)
1064                 INIT_LIST_HEAD(&reg->mem_region_list);
1065 #endif
1066
1067         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {
1068                 vpu_err("error: copy_from_user failed in reg_init\n");
1069                 kfree(reg);
1070                 return NULL;
1071         }
1072
1073         if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {
1074                 vpu_err("error: copy_from_user failed in reg_init\n");
1075                 kfree(reg);
1076                 return NULL;
1077         }
1078
1079 #if defined(CONFIG_VCODEC_MMU)
1080         if (data->mmu_dev &&
1081             0 > vcodec_reg_address_translate(data, reg, &extra_info)) {
1082                 vpu_err("error: translate reg address failed\n");
1083                 kfree(reg);
1084                 return NULL;
1085         }
1086 #endif
1087
1088         mutex_lock(&pservice->lock);
1089         list_add_tail(&reg->status_link, &pservice->waiting);
1090         list_add_tail(&reg->session_link, &session->waiting);
1091         mutex_unlock(&pservice->lock);
1092
1093         if (pservice->auto_freq) {
1094                 if (!soc_is_rk2928g()) {
1095                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1096                                 if (reg_check_rmvb_wmv(reg)) {
1097                                         reg->freq = VPU_FREQ_200M;
1098                                 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
1099                                         if (reg_probe_width(reg) > 3200) {
1100                                                 // raise frequency for 4k avc.
1101                                                 reg->freq = VPU_FREQ_500M;
1102                                         }
1103                                 } else {
1104                                         if (reg_check_interlace(reg)) {
1105                                                 reg->freq = VPU_FREQ_400M;
1106                                         }
1107                                 }
1108                         }
1109                         if (reg->type == VPU_PP) {
1110                                 reg->freq = VPU_FREQ_400M;
1111                         }
1112                 }
1113         }
1114         vpu_debug_leave();
1115         return reg;
1116 }
1117
1118 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg)
1119 {
1120         struct vpu_service_info *pservice = data->pservice;
1121 #if defined(CONFIG_VCODEC_MMU)
1122         struct vcodec_mem_region *mem_region = NULL, *n;
1123 #endif
1124
1125         list_del_init(&reg->session_link);
1126         list_del_init(&reg->status_link);
1127         if (reg == pservice->reg_codec)
1128                 pservice->reg_codec = NULL;
1129         if (reg == pservice->reg_pproc)
1130                 pservice->reg_pproc = NULL;
1131
1132 #if defined(CONFIG_VCODEC_MMU)
1133         /* release memory region attach to this registers table. */
1134         if (data->mmu_dev) {
1135                 list_for_each_entry_safe(mem_region, n,
1136                         &reg->mem_region_list, reg_lnk) {
1137                         /* do not unmap iommu manually,
1138                            unmap will proccess when memory release */
1139                         /*vcodec_enter_mode(data);
1140                         ion_unmap_iommu(data->dev,
1141                                         pservice->ion_client,
1142                                         mem_region->hdl);
1143                         vcodec_exit_mode();*/
1144                         ion_free(pservice->ion_client, mem_region->hdl);
1145                         list_del_init(&mem_region->reg_lnk);
1146                         kfree(mem_region);
1147                 }
1148         }
1149 #endif
1150
1151         kfree(reg);
1152 }
1153
1154 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)
1155 {
1156         vpu_debug_enter();
1157         list_del_init(&reg->status_link);
1158         list_add_tail(&reg->status_link, &pservice->running);
1159
1160         list_del_init(&reg->session_link);
1161         list_add_tail(&reg->session_link, &reg->session->running);
1162         vpu_debug_leave();
1163 }
1164
1165 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
1166 {
1167         int i;
1168         u32 *dst = (u32 *)&reg->reg[0];
1169         vpu_debug_enter();
1170         for (i = 0; i < count; i++)
1171                 *dst++ = *src++;
1172         vpu_debug_leave();
1173 }
1174
1175 static void reg_from_run_to_done(struct vpu_subdev_data *data,
1176         vpu_reg *reg)
1177 {
1178         struct vpu_service_info *pservice = data->pservice;
1179         int irq_reg = -1;
1180
1181         vpu_debug_enter();
1182
1183         list_del_init(&reg->status_link);
1184         list_add_tail(&reg->status_link, &pservice->done);
1185
1186         list_del_init(&reg->session_link);
1187         list_add_tail(&reg->session_link, &reg->session->done);
1188
1189         vcodec_enter_mode(data);
1190         switch (reg->type) {
1191         case VPU_ENC : {
1192                 pservice->reg_codec = NULL;
1193                 reg_copy_from_hw(reg, data->enc_dev.hwregs, data->hw_info->enc_reg_num);
1194                 irq_reg = ENC_INTERRUPT_REGISTER;
1195                 break;
1196         }
1197         case VPU_DEC : {
1198                 int reg_len = REG_NUM_9190_DEC;
1199                 pservice->reg_codec = NULL;
1200                 reg_copy_from_hw(reg, data->dec_dev.hwregs, reg_len);
1201                 irq_reg = DEC_INTERRUPT_REGISTER;
1202                 break;
1203         }
1204         case VPU_PP : {
1205                 pservice->reg_pproc = NULL;
1206                 reg_copy_from_hw(reg, data->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
1207                 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1208                 break;
1209         }
1210         case VPU_DEC_PP : {
1211                 pservice->reg_codec = NULL;
1212                 pservice->reg_pproc = NULL;
1213                 reg_copy_from_hw(reg, data->dec_dev.hwregs, REG_NUM_9190_DEC_PP);
1214                 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1215                 break;
1216         }
1217         default : {
1218                 vpu_err("error: copy reg from hw with unknown type %d\n", reg->type);
1219                 break;
1220         }
1221         }
1222         vcodec_exit_mode(pservice);
1223
1224         if (irq_reg != -1)
1225                 reg->reg[irq_reg] = pservice->irq_status;
1226
1227         atomic_sub(1, &reg->session->task_running);
1228         atomic_sub(1, &pservice->total_running);
1229         wake_up(&reg->session->wait);
1230
1231         vpu_debug_leave();
1232 }
1233
1234 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)
1235 {
1236         VPU_FREQ curr = atomic_read(&pservice->freq_status);
1237         if (curr == reg->freq)
1238                 return;
1239         atomic_set(&pservice->freq_status, reg->freq);
1240         switch (reg->freq) {
1241         case VPU_FREQ_200M : {
1242                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
1243         } break;
1244         case VPU_FREQ_266M : {
1245                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
1246         } break;
1247         case VPU_FREQ_300M : {
1248                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1249         } break;
1250         case VPU_FREQ_400M : {
1251                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1252         } break;
1253         case VPU_FREQ_500M : {
1254                 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
1255         } break;
1256         case VPU_FREQ_600M : {
1257                 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
1258         } break;
1259         default : {
1260                 if (soc_is_rk2928g())
1261                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1262                 else
1263                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1264         } break;
1265         }
1266 }
1267
1268 static void reg_copy_to_hw(struct vpu_subdev_data *data, vpu_reg *reg)
1269 {
1270         struct vpu_service_info *pservice = data->pservice;
1271         int i;
1272         u32 *src = (u32 *)&reg->reg[0];
1273         vpu_debug_enter();
1274
1275         atomic_add(1, &pservice->total_running);
1276         atomic_add(1, &reg->session->task_running);
1277         if (pservice->auto_freq)
1278                 vpu_service_set_freq(pservice, reg);
1279
1280         vcodec_enter_mode(data);
1281
1282         switch (reg->type) {
1283         case VPU_ENC : {
1284                 int enc_count = data->hw_info->enc_reg_num;
1285                 u32 *dst = (u32 *)data->enc_dev.hwregs;
1286
1287                 pservice->reg_codec = reg;
1288
1289                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
1290
1291                 for (i = 0; i < VPU_REG_EN_ENC; i++)
1292                         dst[i] = src[i];
1293
1294                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
1295                         dst[i] = src[i];
1296
1297                 VEPU_CLEAN_CACHE(dst);
1298
1299                 dsb();
1300
1301                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
1302                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];
1303
1304 #if VPU_SERVICE_SHOW_TIME
1305                 do_gettimeofday(&enc_start);
1306 #endif
1307
1308         } break;
1309         case VPU_DEC : {
1310                 u32 *dst = (u32 *)data->dec_dev.hwregs;
1311
1312                 pservice->reg_codec = reg;
1313
1314                 if (data->hw_info->hw_id != HEVC_ID) {
1315                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
1316                                 dst[i] = src[i];
1317                         VDPU_CLEAN_CACHE(dst);
1318                 } else {
1319                         for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--)
1320                                 dst[i] = src[i];
1321                         HEVC_CLEAN_CACHE(dst);
1322                 }
1323
1324                 dsb();
1325
1326                 if (data->hw_info->hw_id != HEVC_ID) {
1327                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1328                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1329                 } else {
1330                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1331                 }
1332                 dsb();
1333                 dmb();
1334 #if VPU_SERVICE_SHOW_TIME
1335                 do_gettimeofday(&dec_start);
1336 #endif
1337         } break;
1338         case VPU_PP : {
1339                 u32 *dst = (u32 *)data->dec_dev.hwregs + PP_INTERRUPT_REGISTER;
1340                 pservice->reg_pproc = reg;
1341
1342                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
1343
1344                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
1345                         dst[i] = src[i];
1346
1347                 dsb();
1348
1349                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
1350 #if VPU_SERVICE_SHOW_TIME
1351                 do_gettimeofday(&pp_start);
1352 #endif
1353
1354         } break;
1355         case VPU_DEC_PP : {
1356                 u32 *dst = (u32 *)data->dec_dev.hwregs;
1357                 pservice->reg_codec = reg;
1358                 pservice->reg_pproc = reg;
1359
1360                 VDPU_SOFT_RESET(dst);
1361                 VDPU_CLEAN_CACHE(dst);
1362
1363                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
1364                         dst[i] = src[i];
1365
1366                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;
1367                 dsb();
1368
1369                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
1370                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;
1371                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];
1372 #if VPU_SERVICE_SHOW_TIME
1373                 do_gettimeofday(&dec_start);
1374 #endif
1375         } break;
1376         default : {
1377                 vpu_err("error: unsupport session type %d", reg->type);
1378                 atomic_sub(1, &pservice->total_running);
1379                 atomic_sub(1, &reg->session->task_running);
1380                 break;
1381         }
1382         }
1383
1384         vcodec_exit_mode(pservice);
1385         vpu_debug_leave();
1386 }
1387
1388 static void try_set_reg(struct vpu_subdev_data *data)
1389 {
1390         struct vpu_service_info *pservice = data->pservice;
1391         vpu_debug_enter();
1392         if (!list_empty(&pservice->waiting)) {
1393                 int can_set = 0;
1394                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);
1395
1396                 vpu_service_power_on(pservice);
1397
1398                 switch (reg->type) {
1399                 case VPU_ENC : {
1400                         if ((NULL == pservice->reg_codec) &&  (NULL == pservice->reg_pproc))
1401                                 can_set = 1;
1402                 } break;
1403                 case VPU_DEC : {
1404                         if (NULL == pservice->reg_codec)
1405                                 can_set = 1;
1406                         if (pservice->auto_freq && (NULL != pservice->reg_pproc))
1407                                 can_set = 0;
1408                 } break;
1409                 case VPU_PP : {
1410                         if (NULL == pservice->reg_codec) {
1411                                 if (NULL == pservice->reg_pproc)
1412                                         can_set = 1;
1413                         } else {
1414                                 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))
1415                                         can_set = 1;
1416                                 /* can not charge frequency when vpu is working */
1417                                 if (pservice->auto_freq)
1418                                         can_set = 0;
1419                         }
1420                 } break;
1421                 case VPU_DEC_PP : {
1422                         if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))
1423                                 can_set = 1;
1424                         } break;
1425                 default : {
1426                         printk("undefined reg type %d\n", reg->type);
1427                 } break;
1428                 }
1429                 if (can_set) {
1430                         reg_from_wait_to_run(pservice, reg);
1431                         reg_copy_to_hw(data, reg);
1432                 }
1433         }
1434         vpu_debug_leave();
1435 }
1436
1437 static int return_reg(struct vpu_subdev_data *data,
1438         vpu_reg *reg, u32 __user *dst)
1439 {
1440         int ret = 0;
1441         vpu_debug_enter();
1442         switch (reg->type) {
1443         case VPU_ENC : {
1444                 if (copy_to_user(dst, &reg->reg[0], data->hw_info->enc_io_size))
1445                         ret = -EFAULT;
1446                 break;
1447         }
1448         case VPU_DEC : {
1449                 int reg_len = data->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1450                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(reg_len)))
1451                         ret = -EFAULT;
1452                 break;
1453         }
1454         case VPU_PP : {
1455                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))
1456                         ret = -EFAULT;
1457                 break;
1458         }
1459         case VPU_DEC_PP : {
1460                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
1461                         ret = -EFAULT;
1462                 break;
1463         }
1464         default : {
1465                 ret = -EFAULT;
1466                 vpu_err("error: copy reg to user with unknown type %d\n", reg->type);
1467                 break;
1468         }
1469         }
1470         reg_deinit(data, reg);
1471         vpu_debug_leave();
1472         return ret;
1473 }
1474
1475 static long vpu_service_ioctl(struct file *filp, unsigned int cmd,
1476         unsigned long arg)
1477 {
1478         struct vpu_subdev_data *data =
1479                 container_of(filp->f_dentry->d_inode->i_cdev,
1480                         struct vpu_subdev_data, cdev);
1481         struct vpu_service_info *pservice = data->pservice;
1482         vpu_session *session = (vpu_session *)filp->private_data;
1483         vpu_debug_enter();
1484         vpu_debug(3, "cmd %x, VPU_IOC_SET_CLIENT_TYPE %x\n", cmd, (u32)VPU_IOC_SET_CLIENT_TYPE);
1485         if (NULL == session)
1486                 return -EINVAL;
1487
1488         switch (cmd) {
1489         case VPU_IOC_SET_CLIENT_TYPE : {
1490                 session->type = (enum VPU_CLIENT_TYPE)arg;
1491                 break;
1492         }
1493         case VPU_IOC_GET_HW_FUSE_STATUS : {
1494                 vpu_request req;
1495                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
1496                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
1497                         return -EFAULT;
1498                 } else {
1499                         if (VPU_ENC != session->type) {
1500                                 if (copy_to_user((void __user *)req.req,
1501                                         &pservice->dec_config,
1502                                         sizeof(struct vpu_dec_config))) {
1503                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1504                                                 session->type);
1505                                         return -EFAULT;
1506                                 }
1507                         } else {
1508                                 if (copy_to_user((void __user *)req.req,
1509                                         &pservice->enc_config,
1510                                         sizeof(struct vpu_enc_config ))) {
1511                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1512                                                 session->type);
1513                                         return -EFAULT;
1514                                 }
1515                         }
1516                 }
1517
1518                 break;
1519         }
1520         case VPU_IOC_SET_REG : {
1521                 vpu_request req;
1522                 vpu_reg *reg;
1523                 if (copy_from_user(&req, (void __user *)arg,
1524                         sizeof(vpu_request))) {
1525                         vpu_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
1526                         return -EFAULT;
1527                 }
1528                 reg = reg_init(data, session,
1529                         (void __user *)req.req, req.size);
1530                 if (NULL == reg) {
1531                         return -EFAULT;
1532                 } else {
1533                         mutex_lock(&pservice->lock);
1534                         try_set_reg(data);
1535                         mutex_unlock(&pservice->lock);
1536                 }
1537
1538                 break;
1539         }
1540         case VPU_IOC_GET_REG : {
1541                 vpu_request req;
1542                 vpu_reg *reg;
1543                 if (copy_from_user(&req, (void __user *)arg,
1544                         sizeof(vpu_request))) {
1545                         vpu_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
1546                         return -EFAULT;
1547                 } else {
1548                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1549                         if (!list_empty(&session->done)) {
1550                                 if (ret < 0) {
1551                                         vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1552                                 }
1553                                 ret = 0;
1554                         } else {
1555                                 if (unlikely(ret < 0)) {
1556                                         vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1557                                 } else if (0 == ret) {
1558                                         vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1559                                         ret = -ETIMEDOUT;
1560                                 }
1561                         }
1562                         if (ret < 0) {
1563                                 int task_running = atomic_read(&session->task_running);
1564                                 mutex_lock(&pservice->lock);
1565                                 vpu_service_dump(pservice);
1566                                 if (task_running) {
1567                                         atomic_set(&session->task_running, 0);
1568                                         atomic_sub(task_running, &pservice->total_running);
1569                                         printk("%d task is running but not return, reset hardware...", task_running);
1570                                         vpu_reset(data);
1571                                         printk("done\n");
1572                                 }
1573                                 vpu_service_session_clear(data, session);
1574                                 mutex_unlock(&pservice->lock);
1575                                 return ret;
1576                         }
1577                 }
1578                 mutex_lock(&pservice->lock);
1579                 reg = list_entry(session->done.next, vpu_reg, session_link);
1580                 return_reg(data, reg, (u32 __user *)req.req);
1581                 mutex_unlock(&pservice->lock);
1582                 break;
1583         }
1584         case VPU_IOC_PROBE_IOMMU_STATUS: {
1585                 int iommu_enable = 0;
1586
1587 #if defined(CONFIG_VCODEC_MMU)
1588                 iommu_enable = data->mmu_dev ? 1 : 0;
1589 #endif
1590
1591                 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {
1592                         vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1593                         return -EFAULT;
1594                 }
1595                 break;
1596         }
1597         default : {
1598                 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1599                 break;
1600         }
1601         }
1602         vpu_debug_leave();
1603         return 0;
1604 }
1605
1606 #ifdef CONFIG_COMPAT
1607 static long compat_vpu_service_ioctl(struct file *filp, unsigned int cmd,
1608         unsigned long arg)
1609 {
1610         struct vpu_subdev_data *data =
1611                 container_of(filp->f_dentry->d_inode->i_cdev,
1612                         struct vpu_subdev_data, cdev);
1613         struct vpu_service_info *pservice = data->pservice;
1614         vpu_session *session = (vpu_session *)filp->private_data;
1615         vpu_debug_enter();
1616         vpu_debug(3, "cmd %x, COMPAT_VPU_IOC_SET_CLIENT_TYPE %x\n", cmd,
1617                   (u32)COMPAT_VPU_IOC_SET_CLIENT_TYPE);
1618         if (NULL == session)
1619                 return -EINVAL;
1620
1621         switch (cmd) {
1622         case COMPAT_VPU_IOC_SET_CLIENT_TYPE : {
1623                 session->type = (enum VPU_CLIENT_TYPE)arg;
1624                 break;
1625         }
1626         case COMPAT_VPU_IOC_GET_HW_FUSE_STATUS : {
1627                 vpu_request req;
1628                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1629                                    sizeof(vpu_request))) {
1630                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1631                                 " copy_from_user failed\n");
1632                         return -EFAULT;
1633                 } else {
1634                         if (VPU_ENC != session->type) {
1635                                 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1636                                                  &pservice->dec_config,
1637                                                  sizeof(struct vpu_dec_config))) {
1638                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS "
1639                                                 "copy_to_user failed type %d\n",
1640                                                 session->type);
1641                                         return -EFAULT;
1642                                 }
1643                         } else {
1644                                 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1645                                                  &pservice->enc_config,
1646                                                  sizeof(struct vpu_enc_config ))) {
1647                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1648                                                 " copy_to_user failed type %d\n",
1649                                                 session->type);
1650                                         return -EFAULT;
1651                                 }
1652                         }
1653                 }
1654
1655                 break;
1656         }
1657         case COMPAT_VPU_IOC_SET_REG : {
1658                 vpu_request req;
1659                 vpu_reg *reg;
1660                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1661                                    sizeof(vpu_request))) {
1662                         vpu_err("VPU_IOC_SET_REG copy_from_user failed\n");
1663                         return -EFAULT;
1664                 }
1665                 reg = reg_init(data, session,
1666                                compat_ptr((compat_uptr_t)req.req), req.size);
1667                 if (NULL == reg) {
1668                         return -EFAULT;
1669                 } else {
1670                         mutex_lock(&pservice->lock);
1671                         try_set_reg(data);
1672                         mutex_unlock(&pservice->lock);
1673                 }
1674
1675                 break;
1676         }
1677         case COMPAT_VPU_IOC_GET_REG : {
1678                 vpu_request req;
1679                 vpu_reg *reg;
1680                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1681                                    sizeof(vpu_request))) {
1682                         vpu_err("VPU_IOC_GET_REG copy_from_user failed\n");
1683                         return -EFAULT;
1684                 } else {
1685                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1686                         if (!list_empty(&session->done)) {
1687                                 if (ret < 0) {
1688                                         vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1689                                 }
1690                                 ret = 0;
1691                         } else {
1692                                 if (unlikely(ret < 0)) {
1693                                         vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1694                                 } else if (0 == ret) {
1695                                         vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1696                                         ret = -ETIMEDOUT;
1697                                 }
1698                         }
1699                         if (ret < 0) {
1700                                 int task_running = atomic_read(&session->task_running);
1701                                 mutex_lock(&pservice->lock);
1702                                 vpu_service_dump(pservice);
1703                                 if (task_running) {
1704                                         atomic_set(&session->task_running, 0);
1705                                         atomic_sub(task_running, &pservice->total_running);
1706                                         printk("%d task is running but not return, reset hardware...", task_running);
1707                                         vpu_reset(data);
1708                                         printk("done\n");
1709                                 }
1710                                 vpu_service_session_clear(data, session);
1711                                 mutex_unlock(&pservice->lock);
1712                                 return ret;
1713                         }
1714                 }
1715                 mutex_lock(&pservice->lock);
1716                 reg = list_entry(session->done.next, vpu_reg, session_link);
1717                 return_reg(data, reg, compat_ptr((compat_uptr_t)req.req));
1718                 mutex_unlock(&pservice->lock);
1719                 break;
1720         }
1721         case COMPAT_VPU_IOC_PROBE_IOMMU_STATUS : {
1722                 int iommu_enable = 0;
1723
1724 #if defined(CONFIG_VCODEC_MMU)
1725                 iommu_enable = data->mmu_dev ? 1 : 0;
1726 #endif
1727
1728                 if (copy_to_user(compat_ptr((compat_uptr_t)arg), &iommu_enable, sizeof(int))) {
1729                         vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1730                         return -EFAULT;
1731                 }
1732                 break;
1733         }
1734         default : {
1735                 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1736                 break;
1737         }
1738         }
1739         vpu_debug_leave();
1740         return 0;
1741 }
1742 #endif
1743
1744 static int vpu_service_check_hw(struct vpu_subdev_data *data, u32 hw_addr)
1745 {
1746         int ret = -EINVAL, i = 0;
1747         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
1748         u32 enc_id = *tmp;
1749
1750         enc_id = (enc_id >> 16) & 0xFFFF;
1751         pr_info("checking hw id %x\n", enc_id);
1752         data->hw_info = NULL;
1753         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
1754                 if (enc_id == vpu_hw_set[i].hw_id) {
1755                         data->hw_info = &vpu_hw_set[i];
1756                         ret = 0;
1757                         break;
1758                 }
1759         }
1760         iounmap((void *)tmp);
1761         return ret;
1762 }
1763
1764 static int vpu_service_open(struct inode *inode, struct file *filp)
1765 {
1766         struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1767         struct vpu_service_info *pservice = data->pservice;
1768         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
1769
1770         vpu_debug_enter();
1771
1772         if (NULL == session) {
1773                 vpu_err("error: unable to allocate memory for vpu_session.");
1774                 return -ENOMEM;
1775         }
1776
1777         session->type   = VPU_TYPE_BUTT;
1778         session->pid    = current->pid;
1779         INIT_LIST_HEAD(&session->waiting);
1780         INIT_LIST_HEAD(&session->running);
1781         INIT_LIST_HEAD(&session->done);
1782         INIT_LIST_HEAD(&session->list_session);
1783         init_waitqueue_head(&session->wait);
1784         atomic_set(&session->task_running, 0);
1785         mutex_lock(&pservice->lock);
1786         list_add_tail(&session->list_session, &pservice->session);
1787         filp->private_data = (void *)session;
1788         mutex_unlock(&pservice->lock);
1789
1790         pr_debug("dev opened\n");
1791         vpu_debug_leave();
1792         return nonseekable_open(inode, filp);
1793 }
1794
1795 static int vpu_service_release(struct inode *inode, struct file *filp)
1796 {
1797         struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1798         struct vpu_service_info *pservice = data->pservice;
1799         int task_running;
1800         vpu_session *session = (vpu_session *)filp->private_data;
1801         vpu_debug_enter();
1802         if (NULL == session)
1803                 return -EINVAL;
1804
1805         task_running = atomic_read(&session->task_running);
1806         if (task_running) {
1807                 vpu_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
1808                 msleep(50);
1809         }
1810         wake_up(&session->wait);
1811
1812         mutex_lock(&pservice->lock);
1813         /* remove this filp from the asynchronusly notified filp's */
1814         list_del_init(&session->list_session);
1815         vpu_service_session_clear(data, session);
1816         kfree(session);
1817         filp->private_data = NULL;
1818         mutex_unlock(&pservice->lock);
1819
1820         pr_debug("dev closed\n");
1821         vpu_debug_leave();
1822         return 0;
1823 }
1824
1825 static const struct file_operations vpu_service_fops = {
1826         .unlocked_ioctl = vpu_service_ioctl,
1827         .open           = vpu_service_open,
1828         .release        = vpu_service_release,
1829 #ifdef CONFIG_COMPAT
1830         .compat_ioctl   = compat_vpu_service_ioctl,
1831 #endif
1832         //.fasync       = vpu_service_fasync,
1833 };
1834
1835 static irqreturn_t vdpu_irq(int irq, void *dev_id);
1836 static irqreturn_t vdpu_isr(int irq, void *dev_id);
1837 static irqreturn_t vepu_irq(int irq, void *dev_id);
1838 static irqreturn_t vepu_isr(int irq, void *dev_id);
1839 static void get_hw_info(struct vpu_subdev_data *data);
1840
1841 #ifdef CONFIG_VCODEC_MMU
1842 static struct device *rockchip_get_sysmmu_dev(const char *compt)
1843 {
1844         struct device_node *dn = NULL;
1845         struct platform_device *pd = NULL;
1846         struct device *ret = NULL ;
1847
1848         dn = of_find_compatible_node(NULL,NULL,compt);
1849         if(!dn) {
1850                 printk("can't find device node %s \r\n",compt);
1851                 return NULL;
1852         }
1853
1854         pd = of_find_device_by_node(dn);
1855         if(!pd) {
1856                 printk("can't find platform device in device node %s\n",compt);
1857                 return  NULL;
1858         }
1859         ret = &pd->dev;
1860
1861         return ret;
1862
1863 }
1864 #ifdef CONFIG_IOMMU_API
1865 static inline void platform_set_sysmmu(struct device *iommu,
1866         struct device *dev)
1867 {
1868         dev->archdata.iommu = iommu;
1869 }
1870 #else
1871 static inline void platform_set_sysmmu(struct device *iommu,
1872         struct device *dev)
1873 {
1874 }
1875 #endif
1876
1877 int vcodec_sysmmu_fault_hdl(struct device *dev,
1878                                 enum rk_iommu_inttype itype,
1879                                 unsigned long pgtable_base,
1880                                 unsigned long fault_addr, unsigned int status)
1881 {
1882         struct platform_device *pdev;
1883         struct vpu_subdev_data *data;
1884         struct vpu_service_info *pservice;
1885
1886         vpu_debug_enter();
1887
1888         pdev = container_of(dev, struct platform_device, dev);
1889
1890         data = platform_get_drvdata(pdev);
1891         pservice = data->pservice;
1892
1893         if (pservice->reg_codec) {
1894                 struct vcodec_mem_region *mem, *n;
1895                 int i = 0;
1896                 vpu_debug(3, "vcodec, fault addr 0x%08x\n", (u32)fault_addr);
1897                 list_for_each_entry_safe(mem, n,
1898                                          &pservice->reg_codec->mem_region_list,
1899                                          reg_lnk) {
1900                         vpu_debug(3, "vcodec, reg[%02u] mem region [%02d] 0x%08x %ld\n",
1901                                 mem->reg_idx, i, (u32)mem->iova, mem->len);
1902                         i++;
1903                 }
1904
1905                 pr_alert("vcodec, page fault occur, reset hw\n");
1906                 pservice->reg_codec->reg[101] = 1;
1907                 vpu_reset(data);
1908         }
1909
1910         return 0;
1911 }
1912 #endif
1913
1914 #if HEVC_TEST_ENABLE
1915 static int hevc_test_case0(vpu_service_info *pservice);
1916 #endif
1917 #if defined(CONFIG_ION_ROCKCHIP)
1918 extern struct ion_client *rockchip_ion_client_create(const char * name);
1919 #endif
1920
1921 static int vcodec_subdev_probe(struct platform_device *pdev,
1922         struct vpu_service_info *pservice)
1923 {
1924         int ret = 0;
1925         struct resource *res = NULL;
1926         u32 ioaddr = 0;
1927         struct device *dev = &pdev->dev;
1928         char *name = (char*)dev_name(dev);
1929         struct device_node *np = pdev->dev.of_node;
1930         struct vpu_subdev_data *data =
1931                 devm_kzalloc(dev, sizeof(struct vpu_subdev_data), GFP_KERNEL);
1932 #if defined(CONFIG_VCODEC_MMU)
1933         u32 iommu_en = 0;
1934         char mmu_dev_dts_name[40];
1935         of_property_read_u32(np, "iommu_enabled", &iommu_en);
1936 #endif
1937         pr_info("probe device %s\n", dev_name(dev));
1938
1939         data->pservice = pservice;
1940         data->dev = dev;
1941
1942         of_property_read_string(np, "name", (const char**)&name);
1943         of_property_read_u32(np, "dev_mode", (u32*)&data->mode);
1944         dev_set_name(dev, name);
1945
1946         if (pservice->reg_base == 0) {
1947                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1948                 data->regs = devm_ioremap_resource(dev, res);
1949                 if (IS_ERR(data->regs)) {
1950                         ret = PTR_ERR(data->regs);
1951                         goto err;
1952                 }
1953                 ioaddr = res->start;
1954         } else {
1955                 data->regs = pservice->reg_base;
1956                 ioaddr = pservice->ioaddr;
1957         }
1958
1959         clear_bit(MMU_ACTIVATED, &data->state);
1960         vcodec_enter_mode(data);
1961         ret = vpu_service_check_hw(data, ioaddr);
1962         if (ret < 0) {
1963                 vpu_err("error: hw info check faild\n");
1964                 goto err;
1965         }
1966
1967         data->dec_dev.iosize = data->hw_info->dec_io_size;
1968         data->dec_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->dec_offset);
1969         data->reg_size = data->dec_dev.iosize;
1970
1971         if (data->mode == VCODEC_RUNNING_MODE_VPU) {
1972                 data->enc_dev.iosize = data->hw_info->enc_io_size;
1973                 data->reg_size = data->reg_size > data->enc_dev.iosize ? data->reg_size : data->enc_dev.iosize;
1974                 data->enc_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->enc_offset);
1975         }
1976
1977         data->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
1978         if (data->irq_enc > 0) {
1979                 ret = devm_request_threaded_irq(dev,
1980                         data->irq_enc, vepu_irq, vepu_isr,
1981                         IRQF_SHARED, dev_name(dev),
1982                         (void *)data);
1983                 if (ret) {
1984                         dev_err(dev,
1985                                 "error: can't request vepu irq %d\n",
1986                                 data->irq_enc);
1987                         goto err;
1988                 }
1989         }
1990         data->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
1991         if (data->irq_dec > 0) {
1992                 ret = devm_request_threaded_irq(dev,
1993                         data->irq_dec, vdpu_irq, vdpu_isr,
1994                         IRQF_SHARED, dev_name(dev),
1995                         (void *)data);
1996                 if (ret) {
1997                         dev_err(dev,
1998                                 "error: can't request vdpu irq %d\n",
1999                                 data->irq_dec);
2000                         goto err;
2001                 }
2002         }
2003         atomic_set(&data->dec_dev.irq_count_codec, 0);
2004         atomic_set(&data->dec_dev.irq_count_pp, 0);
2005         atomic_set(&data->enc_dev.irq_count_codec, 0);
2006         atomic_set(&data->enc_dev.irq_count_pp, 0);
2007 #if defined(CONFIG_VCODEC_MMU)
2008         if (iommu_en) {
2009                 vcodec_enter_mode(data);
2010                 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
2011                         sprintf(mmu_dev_dts_name,
2012                                 HEVC_IOMMU_COMPATIBLE_NAME);
2013                 else
2014                         sprintf(mmu_dev_dts_name,
2015                                 VPU_IOMMU_COMPATIBLE_NAME);
2016
2017                 data->mmu_dev =
2018                         rockchip_get_sysmmu_dev(mmu_dev_dts_name);
2019
2020                 if (data->mmu_dev)
2021                         platform_set_sysmmu(data->mmu_dev, dev);
2022
2023                 rockchip_iovmm_set_fault_handler(dev, vcodec_sysmmu_fault_hdl);
2024         }
2025 #endif
2026         /* create device node */
2027         ret = alloc_chrdev_region(&data->dev_t, 0, 1, dev_name(dev));
2028         if (ret) {
2029                 dev_err(dev, "alloc dev_t failed\n");
2030                 goto err;
2031         }
2032
2033         cdev_init(&data->cdev, &vpu_service_fops);
2034
2035         data->cdev.owner = THIS_MODULE;
2036         data->cdev.ops = &vpu_service_fops;
2037
2038         ret = cdev_add(&data->cdev, data->dev_t, 1);
2039
2040         if (ret) {
2041                 dev_err(dev, "add dev_t failed\n");
2042                 goto err;
2043         }
2044
2045         data->cls = class_create(THIS_MODULE, dev_name(dev));
2046
2047         if (IS_ERR(data->cls)) {
2048                 ret = PTR_ERR(data->cls);
2049                 dev_err(dev, "class_create err:%d\n", ret);
2050                 goto err;
2051         }
2052
2053         data->child_dev = device_create(data->cls, dev,
2054                 data->dev_t, NULL, dev_name(dev));
2055
2056         get_hw_info(data);
2057
2058         platform_set_drvdata(pdev, data);
2059
2060         INIT_LIST_HEAD(&data->lnk_service);
2061         list_add_tail(&data->lnk_service, &pservice->subdev_list);
2062
2063 #ifdef CONFIG_DEBUG_FS
2064         data->debugfs_dir =
2065                 vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);
2066         if (data->debugfs_dir == NULL)
2067                 vpu_err("create debugfs dir %s failed\n", dev_name(dev));
2068
2069         data->debugfs_file_regs =
2070                 debugfs_create_file("regs", 0664,
2071                                     data->debugfs_dir, data,
2072                                     &debug_vcodec_fops);
2073 #endif
2074         return 0;
2075 err:
2076         if (data->irq_enc > 0)
2077                 free_irq(data->irq_enc, (void *)data);
2078         if (data->irq_dec > 0)
2079                 free_irq(data->irq_dec, (void *)data);
2080
2081         if (data->child_dev) {
2082                 device_destroy(data->cls, data->dev_t);
2083                 cdev_del(&data->cdev);
2084                 unregister_chrdev_region(data->dev_t, 1);
2085         }
2086
2087         if (data->cls)
2088                 class_destroy(data->cls);
2089         return -1;
2090 }
2091
2092 static void vcodec_subdev_remove(struct vpu_subdev_data *data)
2093 {
2094         device_destroy(data->cls, data->dev_t);
2095         class_destroy(data->cls);
2096         cdev_del(&data->cdev);
2097         unregister_chrdev_region(data->dev_t, 1);
2098
2099         free_irq(data->irq_enc, (void *)&data);
2100         free_irq(data->irq_dec, (void *)&data);
2101
2102 #ifdef CONFIG_DEBUG_FS
2103         debugfs_remove(data->debugfs_file_regs);
2104         debugfs_remove(data->debugfs_dir);
2105 #endif
2106 }
2107
2108 static void vcodec_read_property(struct device_node *np,
2109         struct vpu_service_info *pservice)
2110 {
2111         pservice->mode_bit = 0;
2112         pservice->mode_ctrl = 0;
2113         pservice->subcnt = 0;
2114
2115         of_property_read_u32(np, "subcnt", &pservice->subcnt);
2116
2117         if (pservice->subcnt > 1) {
2118                 of_property_read_u32(np, "mode_bit", &pservice->mode_bit);
2119                 of_property_read_u32(np, "mode_ctrl", &pservice->mode_ctrl);
2120         }
2121 #ifdef CONFIG_MFD_SYSCON
2122         pservice->grf_base = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
2123 #else
2124         pservice->grf_base = (u32*)RK_GRF_VIRT;
2125 #endif
2126         if (IS_ERR(pservice->grf_base)) {
2127                 vpu_err("can't find vpu grf property\n");
2128                 return;
2129         }
2130         of_property_read_string(np, "name", (const char**)&pservice->name);
2131 }
2132
2133 static void vcodec_init_drvdata(struct vpu_service_info *pservice)
2134 {
2135         pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2136         pservice->curr_mode = -1;
2137
2138         wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
2139         INIT_LIST_HEAD(&pservice->waiting);
2140         INIT_LIST_HEAD(&pservice->running);
2141         mutex_init(&pservice->lock);
2142
2143         INIT_LIST_HEAD(&pservice->done);
2144         INIT_LIST_HEAD(&pservice->session);
2145         INIT_LIST_HEAD(&pservice->subdev_list);
2146
2147         pservice->reg_pproc     = NULL;
2148         atomic_set(&pservice->total_running, 0);
2149         pservice->enabled = false;
2150
2151         INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
2152
2153         pservice->ion_client = rockchip_ion_client_create("vpu");
2154         if (IS_ERR(pservice->ion_client)) {
2155                 vpu_err("failed to create ion client for vcodec ret %ld\n",
2156                         PTR_ERR(pservice->ion_client));
2157         } else {
2158                 vpu_debug(3, "vcodec ion client create success!\n");
2159         }
2160 }
2161
2162 static int vcodec_probe(struct platform_device *pdev)
2163 {
2164         int i;
2165         int ret = 0;
2166         struct resource *res = NULL;
2167         struct device *dev = &pdev->dev;
2168         struct device_node *np = pdev->dev.of_node;
2169         struct vpu_service_info *pservice =
2170                 devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);
2171
2172         pr_info("probe device %s\n", dev_name(dev));
2173
2174         vcodec_read_property(np, pservice);
2175         vcodec_init_drvdata(pservice);
2176
2177         if (strncmp(pservice->name, "hevc_service", 12) == 0)
2178                 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
2179         else if (strncmp(pservice->name, "vpu_service", 11) == 0)
2180                 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2181         else
2182                 pservice->dev_id = VCODEC_DEVICE_ID_COMBO;
2183
2184         pservice->dev = dev;
2185
2186         if (0 > vpu_get_clk(pservice))
2187                 goto err;
2188
2189         vpu_service_power_on(pservice);
2190
2191         if (of_property_read_bool(np, "reg")) {
2192                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2193
2194                 pservice->reg_base = devm_ioremap_resource(pservice->dev, res);
2195                 if (IS_ERR(pservice->reg_base)) {
2196                         vpu_err("ioremap registers base failed\n");
2197                         ret = PTR_ERR(pservice->reg_base);
2198                         goto err;
2199                 }
2200                 pservice->ioaddr = res->start;
2201         } else {
2202                 pservice->reg_base = 0;
2203         }
2204
2205         if (of_property_read_bool(np, "subcnt")) {
2206                 for (i = 0; i<pservice->subcnt; i++) {
2207                         struct device_node *sub_np;
2208                         struct platform_device *sub_pdev;
2209                         sub_np = of_parse_phandle(np, "rockchip,sub", i);
2210                         sub_pdev = of_find_device_by_node(sub_np);
2211
2212                         vcodec_subdev_probe(sub_pdev, pservice);
2213                 }
2214         } else {
2215                 vcodec_subdev_probe(pdev, pservice);
2216         }
2217         platform_set_drvdata(pdev, pservice);
2218
2219         vpu_service_power_off(pservice);
2220
2221         pr_info("init success\n");
2222
2223         return 0;
2224
2225 err:
2226         pr_info("init failed\n");
2227         vpu_service_power_off(pservice);
2228         vpu_put_clk(pservice);
2229         wake_lock_destroy(&pservice->wake_lock);
2230
2231         if (res)
2232                 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2233
2234         return ret;
2235 }
2236
2237 static int vcodec_remove(struct platform_device *pdev)
2238 {
2239         struct vpu_service_info *pservice = platform_get_drvdata(pdev);
2240         struct resource *res;
2241         struct vpu_subdev_data *data, *n;
2242
2243         list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
2244                 vcodec_subdev_remove(data);
2245         }
2246
2247         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2248         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2249         vpu_put_clk(pservice);
2250         wake_lock_destroy(&pservice->wake_lock);
2251
2252         return 0;
2253 }
2254
2255 #if defined(CONFIG_OF)
2256 static const struct of_device_id vcodec_service_dt_ids[] = {
2257         {.compatible = "vpu_service",},
2258         {.compatible = "rockchip,hevc_service",},
2259         {.compatible = "rockchip,vpu_combo",},
2260         {},
2261 };
2262 #endif
2263
2264 static struct platform_driver vcodec_driver = {
2265         .probe = vcodec_probe,
2266         .remove = vcodec_remove,
2267         .driver = {
2268                 .name = "vcodec",
2269                 .owner = THIS_MODULE,
2270 #if defined(CONFIG_OF)
2271                 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
2272 #endif
2273         },
2274 };
2275
2276 static void get_hw_info(struct vpu_subdev_data *data)
2277 {
2278         struct vpu_service_info *pservice = data->pservice;
2279         struct vpu_dec_config *dec = &pservice->dec_config;
2280         struct vpu_enc_config *enc = &pservice->enc_config;
2281         if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2282                 u32 configReg   = data->dec_dev.hwregs[VPU_DEC_HWCFG0];
2283                 u32 asicID      = data->dec_dev.hwregs[0];
2284
2285                 dec->h264_support    = (configReg >> DWL_H264_E) & 0x3U;
2286                 dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;
2287                 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
2288                         dec->jpegSupport = JPEG_PROGRESSIVE;
2289                 dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;
2290                 dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;
2291                 dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;
2292                 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
2293                 dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;
2294                 dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;
2295
2296                 dec->maxDecPicWidth = 4096;
2297
2298                 /* 2nd Config register */
2299                 configReg   = data->dec_dev.hwregs[VPU_DEC_HWCFG1];
2300                 if (dec->refBufSupport) {
2301                         if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
2302                                 dec->refBufSupport |= 2;
2303                         if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
2304                                 dec->refBufSupport |= 4;
2305                 }
2306                 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
2307                 dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;
2308                 dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;
2309                 dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;
2310
2311                 /* JPEG xtensions */
2312                 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))
2313                         dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
2314                 else
2315                         dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
2316
2317                 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) )
2318                         dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
2319                 else
2320                         dec->rvSupport = RV_NOT_SUPPORTED;
2321                 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
2322
2323                 if (dec->refBufSupport && (asicID >> 16) == 0x6731U )
2324                         dec->refBufSupport |= 8; /* enable HW support for offset */
2325
2326                 if (!cpu_is_rk3036()) {
2327                         configReg = data->enc_dev.hwregs[63];
2328                         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
2329                         enc->h264Enabled = (configReg >> 27) & 1;
2330                         enc->mpeg4Enabled = (configReg >> 26) & 1;
2331                         enc->jpegEnabled = (configReg >> 25) & 1;
2332                         enc->vsEnabled = (configReg >> 24) & 1;
2333                         enc->rgbEnabled = (configReg >> 28) & 1;
2334                         enc->reg_size = data->reg_size;
2335                         enc->reserv[0] = enc->reserv[1] = 0;
2336                 }
2337                 pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926() || soc_is_rk3288();
2338                 if (pservice->auto_freq) {
2339                         vpu_debug(3, "vpu_service set to auto frequency mode\n");
2340                         atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2341                 }
2342
2343                 pservice->bug_dec_addr = cpu_is_rk30xx();
2344         } else {
2345                 if (cpu_is_rk3036()  || cpu_is_rk312x())
2346                         dec->maxDecPicWidth = 1920;
2347                 else
2348                         dec->maxDecPicWidth = 4096;
2349                 /* disable frequency switch in hevc.*/
2350                 pservice->auto_freq = false;
2351         }
2352 }
2353
2354 static irqreturn_t vdpu_irq(int irq, void *dev_id)
2355 {
2356         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2357         struct vpu_service_info *pservice = data->pservice;
2358         vpu_device *dev = &data->dec_dev;
2359         u32 raw_status;
2360         u32 irq_status;
2361
2362         vcodec_enter_mode(data);
2363
2364         irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2365
2366         vpu_debug(3, "%s status %08x\n", __func__, raw_status);
2367
2368         if (irq_status & DEC_INTERRUPT_BIT) {
2369                 pr_debug("dec_isr dec %x\n", irq_status);
2370                 if ((irq_status & 0x40001) == 0x40001) {
2371                         do {
2372                                 irq_status =
2373                                         readl(dev->hwregs +
2374                                                 DEC_INTERRUPT_REGISTER);
2375                         } while ((irq_status & 0x40001) == 0x40001);
2376                 }
2377
2378                 writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);
2379                 atomic_add(1, &dev->irq_count_codec);
2380         }
2381
2382         if (data->hw_info->hw_id != HEVC_ID) {
2383                 irq_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
2384                 if (irq_status & PP_INTERRUPT_BIT) {
2385                         pr_debug("vdpu_isr pp  %x\n", irq_status);
2386                         /* clear pp IRQ */
2387                         writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
2388                         atomic_add(1, &dev->irq_count_pp);
2389                 }
2390         }
2391
2392         pservice->irq_status = raw_status;
2393
2394         vcodec_exit_mode(pservice);
2395
2396         return IRQ_WAKE_THREAD;
2397 }
2398
2399 static irqreturn_t vdpu_isr(int irq, void *dev_id)
2400 {
2401         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2402         struct vpu_service_info *pservice = data->pservice;
2403         vpu_device *dev = &data->dec_dev;
2404
2405         mutex_lock(&pservice->lock);
2406         if (atomic_read(&dev->irq_count_codec)) {
2407 #if VPU_SERVICE_SHOW_TIME
2408                 do_gettimeofday(&dec_end);
2409                 vpu_debug(3, "dec task: %ld ms\n",
2410                         (dec_end.tv_sec  - dec_start.tv_sec)  * 1000 +
2411                         (dec_end.tv_usec - dec_start.tv_usec) / 1000);
2412 #endif
2413                 atomic_sub(1, &dev->irq_count_codec);
2414                 if (NULL == pservice->reg_codec) {
2415                         vpu_err("error: dec isr with no task waiting\n");
2416                 } else {
2417                         reg_from_run_to_done(data, pservice->reg_codec);
2418                 }
2419         }
2420
2421         if (atomic_read(&dev->irq_count_pp)) {
2422 #if VPU_SERVICE_SHOW_TIME
2423                 do_gettimeofday(&pp_end);
2424                 printk("pp  task: %ld ms\n",
2425                         (pp_end.tv_sec  - pp_start.tv_sec)  * 1000 +
2426                         (pp_end.tv_usec - pp_start.tv_usec) / 1000);
2427 #endif
2428                 atomic_sub(1, &dev->irq_count_pp);
2429                 if (NULL == pservice->reg_pproc) {
2430                         vpu_err("error: pp isr with no task waiting\n");
2431                 } else {
2432                         reg_from_run_to_done(data, pservice->reg_pproc);
2433                 }
2434         }
2435         try_set_reg(data);
2436         mutex_unlock(&pservice->lock);
2437         return IRQ_HANDLED;
2438 }
2439
2440 static irqreturn_t vepu_irq(int irq, void *dev_id)
2441 {
2442         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2443         struct vpu_service_info *pservice = data->pservice;
2444         vpu_device *dev = &data->enc_dev;
2445         u32 irq_status;
2446
2447         vcodec_enter_mode(data);
2448         irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
2449
2450         pr_debug("vepu_irq irq status %x\n", irq_status);
2451
2452 #if VPU_SERVICE_SHOW_TIME
2453         do_gettimeofday(&enc_end);
2454         vpu_debug(3, "enc task: %ld ms\n",
2455                 (enc_end.tv_sec  - enc_start.tv_sec)  * 1000 +
2456                 (enc_end.tv_usec - enc_start.tv_usec) / 1000);
2457 #endif
2458         if (likely(irq_status & ENC_INTERRUPT_BIT)) {
2459                 /* clear enc IRQ */
2460                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
2461                 atomic_add(1, &dev->irq_count_codec);
2462         }
2463
2464         pservice->irq_status = irq_status;
2465
2466         vcodec_exit_mode(pservice);
2467
2468         return IRQ_WAKE_THREAD;
2469 }
2470
2471 static irqreturn_t vepu_isr(int irq, void *dev_id)
2472 {
2473         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2474         struct vpu_service_info *pservice = data->pservice;
2475         vpu_device *dev = &data->enc_dev;
2476
2477         mutex_lock(&pservice->lock);
2478         if (atomic_read(&dev->irq_count_codec)) {
2479                 atomic_sub(1, &dev->irq_count_codec);
2480                 if (NULL == pservice->reg_codec) {
2481                         vpu_err("error: enc isr with no task waiting\n");
2482                 } else {
2483                         reg_from_run_to_done(data, pservice->reg_codec);
2484                 }
2485         }
2486         try_set_reg(data);
2487         mutex_unlock(&pservice->lock);
2488         return IRQ_HANDLED;
2489 }
2490
2491 static int __init vcodec_service_init(void)
2492 {
2493         int ret;
2494
2495         if ((ret = platform_driver_register(&vcodec_driver)) != 0) {
2496                 vpu_err("Platform device register failed (%d).\n", ret);
2497                 return ret;
2498         }
2499
2500 #ifdef CONFIG_DEBUG_FS
2501         vcodec_debugfs_init();
2502 #endif
2503
2504         return ret;
2505 }
2506
2507 static void __exit vcodec_service_exit(void)
2508 {
2509 #ifdef CONFIG_DEBUG_FS
2510         vcodec_debugfs_exit();
2511 #endif
2512
2513         platform_driver_unregister(&vcodec_driver);
2514 }
2515
2516 module_init(vcodec_service_init);
2517 module_exit(vcodec_service_exit);
2518
2519 #ifdef CONFIG_DEBUG_FS
2520 #include <linux/seq_file.h>
2521
2522 static int vcodec_debugfs_init()
2523 {
2524         parent = debugfs_create_dir("vcodec", NULL);
2525         if (!parent)
2526                 return -1;
2527
2528         return 0;
2529 }
2530
2531 static void vcodec_debugfs_exit()
2532 {
2533         debugfs_remove(parent);
2534 }
2535
2536 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)
2537 {
2538         return debugfs_create_dir(dirname, parent);
2539 }
2540
2541 static int debug_vcodec_show(struct seq_file *s, void *unused)
2542 {
2543         struct vpu_subdev_data *data = s->private;
2544         struct vpu_service_info *pservice = data->pservice;
2545         unsigned int i, n;
2546         vpu_reg *reg, *reg_tmp;
2547         vpu_session *session, *session_tmp;
2548
2549         mutex_lock(&pservice->lock);
2550         vpu_service_power_on(pservice);
2551         if (data->hw_info->hw_id != HEVC_ID) {
2552                 seq_printf(s, "\nENC Registers:\n");
2553                 n = data->enc_dev.iosize >> 2;
2554                 for (i = 0; i < n; i++)
2555                         seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->enc_dev.hwregs + i));
2556         }
2557         seq_printf(s, "\nDEC Registers:\n");
2558         n = data->dec_dev.iosize >> 2;
2559         for (i = 0; i < n; i++)
2560                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2561
2562         seq_printf(s, "\nvpu service status:\n");
2563         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
2564                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
2565                 /*seq_printf(s, "waiting reg set %d\n");*/
2566                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
2567                         seq_printf(s, "waiting register set\n");
2568                 }
2569                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
2570                         seq_printf(s, "running register set\n");
2571                 }
2572                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
2573                         seq_printf(s, "done    register set\n");
2574                 }
2575         }
2576         mutex_unlock(&pservice->lock);
2577
2578         return 0;
2579 }
2580
2581 static int debug_vcodec_open(struct inode *inode, struct file *file)
2582 {
2583         return single_open(file, debug_vcodec_show, inode->i_private);
2584 }
2585
2586 #endif
2587
2588 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)
2589 #include "hevc_test_inc/pps_00.h"
2590 #include "hevc_test_inc/register_00.h"
2591 #include "hevc_test_inc/rps_00.h"
2592 #include "hevc_test_inc/scaling_list_00.h"
2593 #include "hevc_test_inc/stream_00.h"
2594
2595 #include "hevc_test_inc/pps_01.h"
2596 #include "hevc_test_inc/register_01.h"
2597 #include "hevc_test_inc/rps_01.h"
2598 #include "hevc_test_inc/scaling_list_01.h"
2599 #include "hevc_test_inc/stream_01.h"
2600
2601 #include "hevc_test_inc/cabac.h"
2602
2603 extern struct ion_client *rockchip_ion_client_create(const char * name);
2604
2605 static struct ion_client *ion_client = NULL;
2606 u8* get_align_ptr(u8* tbl, int len, u32 *phy)
2607 {
2608         int size = (len+15) & (~15);
2609         struct ion_handle *handle;
2610         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);
2611
2612         if (ion_client == NULL)
2613                 ion_client = rockchip_ion_client_create("vcodec");
2614
2615         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2616
2617         ptr = ion_map_kernel(ion_client, handle);
2618
2619         ion_phys(ion_client, handle, phy, &size);
2620
2621         memcpy(ptr, tbl, len);
2622
2623         return ptr;
2624 }
2625
2626 u8* get_align_ptr_no_copy(int len, u32 *phy)
2627 {
2628         int size = (len+15) & (~15);
2629         struct ion_handle *handle;
2630         u8 *ptr;
2631
2632         if (ion_client == NULL)
2633                 ion_client = rockchip_ion_client_create("vcodec");
2634
2635         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2636
2637         ptr = ion_map_kernel(ion_client, handle);
2638
2639         ion_phys(ion_client, handle, phy, &size);
2640
2641         return ptr;
2642 }
2643
2644 #define TEST_CNT    2
2645 static int hevc_test_case0(vpu_service_info *pservice)
2646 {
2647         vpu_session session;
2648         vpu_reg *reg;
2649         unsigned long size = 272;//sizeof(register_00); // registers array length
2650         int testidx = 0;
2651         int ret = 0;
2652         u8 *pps_tbl[TEST_CNT];
2653         u8 *register_tbl[TEST_CNT];
2654         u8 *rps_tbl[TEST_CNT];
2655         u8 *scaling_list_tbl[TEST_CNT];
2656         u8 *stream_tbl[TEST_CNT];
2657
2658         int stream_size[2];
2659         int pps_size[2];
2660         int rps_size[2];
2661         int scl_size[2];
2662         int cabac_size[2];
2663
2664         u32 phy_pps;
2665         u32 phy_rps;
2666         u32 phy_scl;
2667         u32 phy_str;
2668         u32 phy_yuv;
2669         u32 phy_ref;
2670         u32 phy_cabac;
2671
2672         volatile u8 *stream_buf;
2673         volatile u8 *pps_buf;
2674         volatile u8 *rps_buf;
2675         volatile u8 *scl_buf;
2676         volatile u8 *yuv_buf;
2677         volatile u8 *cabac_buf;
2678         volatile u8 *ref_buf;
2679
2680         u8 *pps;
2681         u8 *yuv[2];
2682         int i;
2683
2684         pps_tbl[0] = pps_00;
2685         pps_tbl[1] = pps_01;
2686
2687         register_tbl[0] = register_00;
2688         register_tbl[1] = register_01;
2689
2690         rps_tbl[0] = rps_00;
2691         rps_tbl[1] = rps_01;
2692
2693         scaling_list_tbl[0] = scaling_list_00;
2694         scaling_list_tbl[1] = scaling_list_01;
2695
2696         stream_tbl[0] = stream_00;
2697         stream_tbl[1] = stream_01;
2698
2699         stream_size[0] = sizeof(stream_00);
2700         stream_size[1] = sizeof(stream_01);
2701
2702         pps_size[0] = sizeof(pps_00);
2703         pps_size[1] = sizeof(pps_01);
2704
2705         rps_size[0] = sizeof(rps_00);
2706         rps_size[1] = sizeof(rps_01);
2707
2708         scl_size[0] = sizeof(scaling_list_00);
2709         scl_size[1] = sizeof(scaling_list_01);
2710
2711         cabac_size[0] = sizeof(Cabac_table);
2712         cabac_size[1] = sizeof(Cabac_table);
2713
2714         /* create session */
2715         session.pid = current->pid;
2716         session.type = VPU_DEC;
2717         INIT_LIST_HEAD(&session.waiting);
2718         INIT_LIST_HEAD(&session.running);
2719         INIT_LIST_HEAD(&session.done);
2720         INIT_LIST_HEAD(&session.list_session);
2721         init_waitqueue_head(&session.wait);
2722         atomic_set(&session.task_running, 0);
2723         list_add_tail(&session.list_session, &pservice->session);
2724
2725         yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);
2726         yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);
2727
2728         while (testidx < TEST_CNT) {
2729                 /* create registers */
2730                 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
2731                 if (NULL == reg) {
2732                         vpu_err("error: kmalloc fail in reg_init\n");
2733                         return -1;
2734                 }
2735
2736                 if (size > pservice->reg_size) {
2737                         printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
2738                         size = pservice->reg_size;
2739                 }
2740                 reg->session = &session;
2741                 reg->type = session.type;
2742                 reg->size = size;
2743                 reg->freq = VPU_FREQ_DEFAULT;
2744                 reg->reg = (unsigned long *)&reg[1];
2745                 INIT_LIST_HEAD(&reg->session_link);
2746                 INIT_LIST_HEAD(&reg->status_link);
2747
2748                 /* TODO: stuff registers */
2749                 memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);
2750
2751                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);
2752                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);
2753                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);
2754                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);
2755                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);
2756
2757                 pps = pps_buf;
2758
2759                 /* TODO: replace reigster address */
2760                 for (i=0; i<64; i++) {
2761                         u32 scaling_offset;
2762                         u32 tmp;
2763
2764                         scaling_offset = (u32)pps[i*80+74];
2765                         scaling_offset += (u32)pps[i*80+75] << 8;
2766                         scaling_offset += (u32)pps[i*80+76] << 16;
2767                         scaling_offset += (u32)pps[i*80+77] << 24;
2768
2769                         tmp = phy_scl + scaling_offset;
2770
2771                         pps[i*80+74] = tmp & 0xff;
2772                         pps[i*80+75] = (tmp >> 8) & 0xff;
2773                         pps[i*80+76] = (tmp >> 16) & 0xff;
2774                         pps[i*80+77] = (tmp >> 24) & 0xff;
2775                 }
2776
2777                 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n",
2778                         __func__, __LINE__, phy_str, phy_pps, phy_rps);
2779
2780                 reg->reg[1] = 0x21;
2781                 reg->reg[4] = phy_str;
2782                 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;
2783                 reg->reg[6] = phy_cabac;
2784                 reg->reg[7] = testidx?phy_ref:phy_yuv;
2785                 reg->reg[42] = phy_pps;
2786                 reg->reg[43] = phy_rps;
2787                 for (i = 10; i <= 24; i++)
2788                         reg->reg[i] = phy_yuv;
2789
2790                 mutex_lock(pservice->lock);
2791                 list_add_tail(&reg->status_link, &pservice->waiting);
2792                 list_add_tail(&reg->session_link, &session.waiting);
2793                 mutex_unlock(pservice->lock);
2794
2795                 /* stuff hardware */
2796                 try_set_reg(data);
2797
2798                 /* wait for result */
2799                 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);
2800                 if (!list_empty(&session.done)) {
2801                         if (ret < 0)
2802                                 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);
2803                         ret = 0;
2804                 } else {
2805                         if (unlikely(ret < 0)) {
2806                                 vpu_err("error: pid %d wait task ret %d\n", session.pid, ret);
2807                         } else if (0 == ret) {
2808                                 vpu_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));
2809                                 ret = -ETIMEDOUT;
2810                         }
2811                 }
2812                 if (ret < 0) {
2813                         int task_running = atomic_read(&session.task_running);
2814                         int n;
2815                         mutex_lock(pservice->lock);
2816                         vpu_service_dump(pservice);
2817                         if (task_running) {
2818                                 atomic_set(&session.task_running, 0);
2819                                 atomic_sub(task_running, &pservice->total_running);
2820                                 printk("%d task is running but not return, reset hardware...", task_running);
2821                                 vpu_reset(data);
2822                                 printk("done\n");
2823                         }
2824                         vpu_service_session_clear(pservice, &session);
2825                         mutex_unlock(pservice->lock);
2826
2827                         printk("\nDEC Registers:\n");
2828                         n = data->dec_dev.iosize >> 2;
2829                         for (i=0; i<n; i++)
2830                                 printk("\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2831
2832                         vpu_err("test index %d failed\n", testidx);
2833                         break;
2834                 } else {
2835                         vpu_debug(3, "test index %d success\n", testidx);
2836
2837                         vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);
2838
2839                         for (i=0; i<68; i++) {
2840                                 if (i % 4 == 0)
2841                                         printk("%02d: ", i);
2842                                 printk("%08x ", reg->reg[i]);
2843                                 if ((i+1) % 4 == 0)
2844                                         printk("\n");
2845                         }
2846
2847                         testidx++;
2848                 }
2849
2850                 reg_deinit(data, reg);
2851         }
2852
2853         return 0;
2854 }
2855
2856 #endif
2857