arch/arm/mach-rockchip/vcodec_service.c

   1 /**
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  * author: chenhengming chm@rock-chips.com
   4  *         Alpha Lin, alpha.lin@rock-chips.com
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/fs.h>
  25 #include <linux/ioport.h>
  26 #include <linux/miscdevice.h>
  27 #include <linux/mm.h>
  28 #include <linux/poll.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/sched.h>
  31 #include <linux/slab.h>
  32 #include <linux/wakelock.h>
  33 #include <linux/cdev.h>
  34 #include <linux/of.h>
  35 #include <linux/of_platform.h>
  36 #include <linux/of_irq.h>
  37 #include <linux/rockchip/cpu.h>
  38 #include <linux/rockchip/cru.h>
  39 #ifdef CONFIG_MFD_SYSCON
  40 #include <linux/regmap.h>
  41 #endif
  42 #include <linux/mfd/syscon.h>
  43
  44 #include <asm/cacheflush.h>
  45 #include <linux/uaccess.h>
  46 #include <linux/rockchip/grf.h>
  47
  48 #if defined(CONFIG_ION_ROCKCHIP)
  49 #include <linux/rockchip_ion.h>
  50 #endif
  51
  52 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)
  53 #define CONFIG_VCODEC_MMU
  54 #endif
  55
  56 #ifdef CONFIG_VCODEC_MMU
  57 #include <linux/rockchip-iovmm.h>
  58 #include <linux/dma-buf.h>
  59 #endif
  60
  61 #ifdef CONFIG_DEBUG_FS
  62 #include <linux/debugfs.h>
  63 #endif
  64
  65 #if defined(CONFIG_ARCH_RK319X)
  66 #include <mach/grf.h>
  67 #endif
  68
  69 #include "vcodec_service.h"
  70
  71 static int debug;
  72 module_param(debug, int, S_IRUGO | S_IWUSR);
  73 MODULE_PARM_DESC(debug,
  74                  "Debug level - higher value produces more verbose messages");
  75
  76 #define HEVC_TEST_ENABLE        0
  77 #define VCODEC_CLOCK_ENABLE     1
  78
  79 typedef enum {
  80         VPU_DEC_ID_9190         = 0x6731,
  81         VPU_ID_8270             = 0x8270,
  82         VPU_ID_4831             = 0x4831,
  83         HEVC_ID                 = 0x6867,
  84 } VPU_HW_ID;
  85
  86 enum VPU_HW_SPEC {
  87         VPU_TYPE_VPU,
  88         VPU_TYPE_HEVC,
  89         VPU_TYPE_COMBO_NOENC,
  90         VPU_TYPE_COMBO
  91 };
  92
  93 typedef enum {
  94         VPU_DEC_TYPE_9190       = 0,
  95         VPU_ENC_TYPE_8270       = 0x100,
  96         VPU_ENC_TYPE_4831       ,
  97 } VPU_HW_TYPE_E;
  98
  99 typedef enum VPU_FREQ {
 100         VPU_FREQ_200M,
 101         VPU_FREQ_266M,
 102         VPU_FREQ_300M,
 103         VPU_FREQ_400M,
 104         VPU_FREQ_500M,
 105         VPU_FREQ_600M,
 106         VPU_FREQ_DEFAULT,
 107         VPU_FREQ_BUT,
 108 } VPU_FREQ;
 109
 110 typedef struct {
 111         VPU_HW_ID               hw_id;
 112         unsigned long           hw_addr;
 113         unsigned long           enc_offset;
 114         unsigned long           enc_reg_num;
 115         unsigned long           enc_io_size;
 116         unsigned long           dec_offset;
 117         unsigned long           dec_reg_num;
 118         unsigned long           dec_io_size;
 119 } VPU_HW_INFO_E;
 120
 121 struct extra_info_elem {
 122         u32 index;
 123         u32 offset;
 124 };
 125
 126 #define EXTRA_INFO_MAGIC        0x4C4A46
 127
 128 struct extra_info_for_iommu {
 129         u32 magic;
 130         u32 cnt;
 131         struct extra_info_elem elem[20];
 132 };
 133
 134 #define VPU_SERVICE_SHOW_TIME                   0
 135
 136 #if VPU_SERVICE_SHOW_TIME
 137 static struct timeval enc_start, enc_end;
 138 static struct timeval dec_start, dec_end;
 139 static struct timeval pp_start,  pp_end;
 140 #endif
 141
 142 #define MHZ                                     (1000*1000)
 143
 144 #define REG_NUM_9190_DEC                        (60)
 145 #define REG_NUM_9190_PP                         (41)
 146 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 147
 148 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 149
 150 #define REG_NUM_ENC_8270                        (96)
 151 #define REG_SIZE_ENC_8270                       (0x200)
 152 #define REG_NUM_ENC_4831                        (164)
 153 #define REG_SIZE_ENC_4831                       (0x400)
 154
 155 #define REG_NUM_HEVC_DEC                        (68)
 156
 157 #define SIZE_REG(reg)                           ((reg)*4)
 158
 159 static VPU_HW_INFO_E vpu_hw_set[] = {
 160         [0] = {
 161                 .hw_id          = VPU_ID_8270,
 162                 .hw_addr        = 0,
 163                 .enc_offset     = 0x0,
 164                 .enc_reg_num    = REG_NUM_ENC_8270,
 165                 .enc_io_size    = REG_NUM_ENC_8270 * 4,
 166                 .dec_offset     = REG_SIZE_ENC_8270,
 167                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 168                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 169         },
 170         [1] = {
 171                 .hw_id          = VPU_ID_4831,
 172                 .hw_addr        = 0,
 173                 .enc_offset     = 0x0,
 174                 .enc_reg_num    = REG_NUM_ENC_4831,
 175                 .enc_io_size    = REG_NUM_ENC_4831 * 4,
 176                 .dec_offset     = REG_SIZE_ENC_4831,
 177                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 178                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 179         },
 180         [2] = {
 181                 .hw_id          = HEVC_ID,
 182                 .hw_addr        = 0,
 183                 .dec_offset     = 0x0,
 184                 .dec_reg_num    = REG_NUM_HEVC_DEC,
 185                 .dec_io_size    = REG_NUM_HEVC_DEC * 4,
 186         },
 187         [3] = {
 188                 .hw_id          = VPU_DEC_ID_9190,
 189                 .hw_addr        = 0,
 190                 .enc_offset     = 0x0,
 191                 .enc_reg_num    = 0,
 192                 .enc_io_size    = 0,
 193                 .dec_offset     = 0,
 194                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 195                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 196         },
 197 };
 198
 199
 200 #define DEC_INTERRUPT_REGISTER                  1
 201 #define PP_INTERRUPT_REGISTER                   60
 202 #define ENC_INTERRUPT_REGISTER                  1
 203
 204 #define DEC_INTERRUPT_BIT                       0x100
 205 #define DEC_BUFFER_EMPTY_BIT                    0x4000
 206 #define PP_INTERRUPT_BIT                        0x100
 207 #define ENC_INTERRUPT_BIT                       0x1
 208
 209 #define HEVC_DEC_INT_RAW_BIT                    0x200
 210 #define HEVC_DEC_STR_ERROR_BIT                  0x4000
 211 #define HEVC_DEC_BUS_ERROR_BIT                  0x2000
 212 #define HEVC_DEC_BUFFER_EMPTY_BIT               0x10000
 213
 214 #define VPU_REG_EN_ENC                          14
 215 #define VPU_REG_ENC_GATE                        2
 216 #define VPU_REG_ENC_GATE_BIT                    (1<<4)
 217
 218 #define VPU_REG_EN_DEC                          1
 219 #define VPU_REG_DEC_GATE                        2
 220 #define VPU_REG_DEC_GATE_BIT                    (1<<10)
 221 #define VPU_REG_EN_PP                           0
 222 #define VPU_REG_PP_GATE                         1
 223 #define VPU_REG_PP_GATE_BIT                     (1<<8)
 224 #define VPU_REG_EN_DEC_PP                       1
 225 #define VPU_REG_DEC_PP_GATE                     61
 226 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)
 227
 228 #define DEBUG
 229 #ifdef DEBUG
 230 #define vpu_debug(level, fmt, args...)                          \
 231         do {                                                    \
 232                 if (debug >= level)                             \
 233                         pr_info("%s:%d: " fmt,                  \
 234                                  __func__, __LINE__, ##args);   \
 235         } while (0)
 236 #else
 237 #define vpu_debug(level, fmt, args...)
 238 #endif
 239
 240 #define vpu_debug_enter() vpu_debug(4, "enter\n")
 241 #define vpu_debug_leave() vpu_debug(4, "leave\n")
 242
 243 #define vpu_err(fmt, args...)                           \
 244                 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
 245
 246 #if defined(CONFIG_VCODEC_MMU)
 247 static u8 addr_tbl_vpu_h264dec[] = {
 248         12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
 249         25, 26, 27, 28, 29, 40, 41
 250 };
 251
 252 static u8 addr_tbl_vpu_vp8dec[] = {
 253         10, 12, 13, 14, 18, 19, 22, 23, 24, 25, 26, 27, 28, 29, 40
 254 };
 255
 256 static u8 addr_tbl_vpu_vp6dec[] = {
 257         12, 13, 14, 18, 27, 40
 258 };
 259
 260 static u8 addr_tbl_vpu_vc1dec[] = {
 261         12, 13, 14, 15, 16, 17, 27, 41
 262 };
 263
 264 static u8 addr_tbl_vpu_jpegdec[] = {
 265         12, 40, 66, 67
 266 };
 267
 268 static u8 addr_tbl_vpu_defaultdec[] = {
 269         12, 13, 14, 15, 16, 17, 40, 41
 270 };
 271
 272 static u8 addr_tbl_vpu_enc[] = {
 273         5, 6, 7, 8, 9, 10, 11, 12, 13, 51
 274 };
 275
 276 static u8 addr_tbl_hevc_dec[] = {
 277         4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
 278         21, 22, 23, 24, 42, 43
 279 };
 280 #endif
 281
 282 enum VPU_DEC_FMT {
 283         VPU_DEC_FMT_H264,
 284         VPU_DEC_FMT_MPEG4,
 285         VPU_DEC_FMT_H263,
 286         VPU_DEC_FMT_JPEG,
 287         VPU_DEC_FMT_VC1,
 288         VPU_DEC_FMT_MPEG2,
 289         VPU_DEC_FMT_MPEG1,
 290         VPU_DEC_FMT_VP6,
 291         VPU_DEC_FMT_RV,
 292         VPU_DEC_FMT_VP7,
 293         VPU_DEC_FMT_VP8,
 294         VPU_DEC_FMT_AVS,
 295         VPU_DEC_FMT_SVC,
 296         VPU_DEC_FMT_VC2,
 297         VPU_DEC_FMT_MVC,
 298         VPU_DEC_FMT_THEORA,
 299         VPU_DEC_FMT_RES
 300 };
 301
 302 /**
 303  * struct for process session which connect to vpu
 304  *
 305  * @author ChenHengming (2011-5-3)
 306  */
 307 typedef struct vpu_session {
 308         enum VPU_CLIENT_TYPE type;
 309         /* a linked list of data so we can access them for debugging */
 310         struct list_head list_session;
 311         /* a linked list of register data waiting for process */
 312         struct list_head waiting;
 313         /* a linked list of register data in processing */
 314         struct list_head running;
 315         /* a linked list of register data processed */
 316         struct list_head done;
 317         wait_queue_head_t wait;
 318         pid_t pid;
 319         atomic_t task_running;
 320 } vpu_session;
 321
 322 /**
 323  * struct for process register set
 324  *
 325  * @author ChenHengming (2011-5-4)
 326  */
 327 typedef struct vpu_reg {
 328         enum VPU_CLIENT_TYPE type;
 329         VPU_FREQ freq;
 330         vpu_session *session;
 331         struct list_head session_link;          /* link to vpu service session */
 332         struct list_head status_link;           /* link to register set list */
 333         unsigned long size;
 334 #if defined(CONFIG_VCODEC_MMU)
 335         struct list_head mem_region_list;
 336 #endif
 337         u32 *reg;
 338 } vpu_reg;
 339
 340 typedef struct vpu_device {
 341         atomic_t                irq_count_codec;
 342         atomic_t                irq_count_pp;
 343         unsigned long           iobaseaddr;
 344         unsigned int            iosize;
 345         volatile u32            *hwregs;
 346 } vpu_device;
 347
 348 enum vcodec_device_id {
 349         VCODEC_DEVICE_ID_VPU,
 350         VCODEC_DEVICE_ID_HEVC,
 351         VCODEC_DEVICE_ID_COMBO
 352 };
 353
 354 enum VCODEC_RUNNING_MODE {
 355         VCODEC_RUNNING_MODE_NONE = -1,
 356         VCODEC_RUNNING_MODE_VPU,
 357         VCODEC_RUNNING_MODE_HEVC,
 358 };
 359
 360 struct vcodec_mem_region {
 361         struct list_head srv_lnk;
 362         struct list_head reg_lnk;
 363         struct list_head session_lnk;
 364         unsigned long iova;     /* virtual address for iommu */
 365         unsigned long len;
 366         u32 reg_idx;
 367         struct ion_handle *hdl;
 368 };
 369
 370 enum vpu_ctx_state {
 371         MMU_ACTIVATED   = BIT(0)
 372 };
 373
 374 struct vpu_subdev_data {
 375         struct cdev cdev;
 376         dev_t dev_t;
 377         struct class *cls;
 378         struct device *child_dev;
 379
 380         int irq_enc;
 381         int irq_dec;
 382         struct vpu_service_info *pservice;
 383
 384         u32 *regs;
 385         enum VCODEC_RUNNING_MODE mode;
 386         struct list_head lnk_service;
 387
 388         struct device *dev;
 389
 390         vpu_device enc_dev;
 391         vpu_device dec_dev;
 392         VPU_HW_INFO_E *hw_info;
 393
 394         u32 reg_size;
 395         unsigned long state;
 396
 397 #ifdef CONFIG_DEBUG_FS
 398         struct dentry *debugfs_dir;
 399         struct dentry *debugfs_file_regs;
 400 #endif
 401
 402 #if defined(CONFIG_VCODEC_MMU)
 403         struct device *mmu_dev;
 404 #endif
 405 };
 406
 407 typedef struct vpu_service_info {
 408         struct wake_lock wake_lock;
 409         struct delayed_work power_off_work;
 410         struct mutex lock;
 411         struct list_head waiting;               /* link to link_reg in struct vpu_reg */
 412         struct list_head running;               /* link to link_reg in struct vpu_reg */
 413         struct list_head done;                  /* link to link_reg in struct vpu_reg */
 414         struct list_head session;               /* link to list_session in struct vpu_session */
 415         atomic_t total_running;
 416         bool enabled;
 417         vpu_reg *reg_codec;
 418         vpu_reg *reg_pproc;
 419         vpu_reg *reg_resev;
 420         struct vpu_dec_config dec_config;
 421         struct vpu_enc_config enc_config;
 422
 423         bool auto_freq;
 424         bool bug_dec_addr;
 425         atomic_t freq_status;
 426
 427         struct clk *aclk_vcodec;
 428         struct clk *hclk_vcodec;
 429         struct clk *clk_core;
 430         struct clk *clk_cabac;
 431         struct clk *pd_video;
 432
 433         struct device *dev;
 434
 435         u32 irq_status;
 436 #if defined(CONFIG_VCODEC_MMU)
 437         struct ion_client *ion_client;
 438         struct list_head mem_region_list;
 439 #endif
 440
 441         enum vcodec_device_id dev_id;
 442
 443         enum VCODEC_RUNNING_MODE curr_mode;
 444         u32 prev_mode;
 445
 446         struct delayed_work simulate_work;
 447
 448         u32 mode_bit;
 449         u32 mode_ctrl;
 450         u32 *reg_base;
 451         u32 ioaddr;
 452 #ifdef CONFIG_MFD_SYSCON
 453         struct regmap *grf_base;
 454 #else
 455         u32 *grf_base;
 456 #endif
 457         char *name;
 458
 459         u32 subcnt;
 460         struct list_head subdev_list;
 461 } vpu_service_info;
 462
 463 struct vcodec_combo {
 464         struct vpu_service_info *vpu_srv;
 465         struct vpu_service_info *hevc_srv;
 466         struct list_head waiting;
 467         struct list_head running;
 468         struct mutex run_lock;
 469         vpu_reg *reg_codec;
 470         enum vcodec_device_id current_hw_mode;
 471 };
 472
 473 typedef struct vpu_request {
 474         unsigned long *req;
 475         u32 size;
 476 } vpu_request;
 477
 478 /* debugfs root directory for all device (vpu, hevc).*/
 479 static struct dentry *parent;
 480
 481 #ifdef CONFIG_DEBUG_FS
 482 static int vcodec_debugfs_init(void);
 483 static void vcodec_debugfs_exit(void);
 484 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);
 485 static int debug_vcodec_open(struct inode *inode, struct file *file);
 486
 487 static const struct file_operations debug_vcodec_fops = {
 488         .open = debug_vcodec_open,
 489         .read = seq_read,
 490         .llseek = seq_lseek,
 491         .release = single_release,
 492 };
 493 #endif
 494
 495 #define VDPU_SOFT_RESET_REG     101
 496 #define VDPU_CLEAN_CACHE_REG    516
 497 #define VEPU_CLEAN_CACHE_REG    772
 498 #define HEVC_CLEAN_CACHE_REG    260
 499
 500 #define VPU_REG_ENABLE(base, reg)       do { \
 501                                                 base[reg] = 1; \
 502                                         } while (0)
 503
 504 #define VDPU_SOFT_RESET(base)   VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
 505 #define VDPU_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, VDPU_CLEAN_CACHE_REG)
 506 #define VEPU_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, VEPU_CLEAN_CACHE_REG)
 507 #define HEVC_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, HEVC_CLEAN_CACHE_REG)
 508
 509 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */
 510 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */
 511
 512 static void vcodec_enter_mode(struct vpu_subdev_data *data)
 513 {
 514         int bits;
 515         u32 raw = 0;
 516         struct vpu_service_info *pservice = data->pservice;
 517         struct vpu_subdev_data *subdata, *n;
 518         if (pservice->subcnt < 2) {
 519 #if defined(CONFIG_VCODEC_MMU)
 520                 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
 521                         set_bit(MMU_ACTIVATED, &data->state);
 522                         BUG_ON(!pservice->enabled);
 523                         if (pservice->enabled)
 524                                 rockchip_iovmm_activate(data->dev);
 525                 }
 526 #endif
 527                 return;
 528         }
 529
 530         if (pservice->curr_mode == data->mode)
 531                 return;
 532
 533         vpu_debug(3, "vcodec enter mode %d\n", data->mode);
 534 #if defined(CONFIG_VCODEC_MMU)
 535         list_for_each_entry_safe(subdata, n, &pservice->subdev_list, lnk_service) {
 536                 if (data != subdata && subdata->mmu_dev &&
 537                     test_bit(MMU_ACTIVATED, &subdata->state)) {
 538                         clear_bit(MMU_ACTIVATED, &subdata->state);
 539                         rockchip_iovmm_deactivate(subdata->dev);
 540                 }
 541         }
 542 #endif
 543         bits = 1 << pservice->mode_bit;
 544 #ifdef CONFIG_MFD_SYSCON
 545         regmap_read(pservice->grf_base, pservice->mode_ctrl, &raw);
 546
 547         if (data->mode == VCODEC_RUNNING_MODE_HEVC)
 548                 regmap_write(pservice->grf_base, pservice->mode_ctrl,
 549                         raw | bits | (bits << 16));
 550         else
 551                 regmap_write(pservice->grf_base, pservice->mode_ctrl,
 552                         (raw & (~bits)) | (bits << 16));
 553 #else
 554         raw = readl_relaxed(pservice->grf_base + pservice->mode_ctrl / 4);
 555         if (data->mode == VCODEC_RUNNING_MODE_HEVC)
 556                 writel_relaxed(raw | bits | (bits << 16),
 557                         pservice->grf_base + pservice->mode_ctrl / 4);
 558         else
 559                 writel_relaxed((raw & (~bits)) | (bits << 16),
 560                         pservice->grf_base + pservice->mode_ctrl / 4);
 561 #endif
 562 #if defined(CONFIG_VCODEC_MMU)
 563         if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
 564                 set_bit(MMU_ACTIVATED, &data->state);
 565                 BUG_ON(!pservice->enabled);
 566                 if (pservice->enabled)
 567                         rockchip_iovmm_activate(data->dev);
 568         }
 569 #endif
 570         pservice->prev_mode = pservice->curr_mode;
 571         pservice->curr_mode = data->mode;
 572 }
 573
 574 static void vcodec_exit_mode(struct vpu_service_info *pservice)
 575 {
 576
 577 }
 578
 579 static int vpu_get_clk(struct vpu_service_info *pservice)
 580 {
 581 #if VCODEC_CLOCK_ENABLE
 582         switch (pservice->dev_id) {
 583         case VCODEC_DEVICE_ID_HEVC:
 584                 pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");
 585                 if (IS_ERR(pservice->pd_video)) {
 586                         dev_err(pservice->dev, "failed on clk_get pd_hevc\n");
 587                         return -1;
 588                 }
 589         case VCODEC_DEVICE_ID_COMBO:
 590                 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");
 591                 if (IS_ERR(pservice->clk_cabac)) {
 592                         dev_err(pservice->dev, "failed on clk_get clk_cabac\n");
 593                         pservice->clk_cabac = NULL;
 594                 }
 595                 pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");
 596                 if (IS_ERR(pservice->clk_core)) {
 597                         dev_err(pservice->dev, "failed on clk_get clk_core\n");
 598                         return -1;
 599                 }
 600         case VCODEC_DEVICE_ID_VPU:
 601                 pservice->aclk_vcodec = devm_clk_get(pservice->dev, "aclk_vcodec");
 602                 if (IS_ERR(pservice->aclk_vcodec)) {
 603                         dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");
 604                         return -1;
 605                 }
 606
 607                 pservice->hclk_vcodec = devm_clk_get(pservice->dev, "hclk_vcodec");
 608                 if (IS_ERR(pservice->hclk_vcodec)) {
 609                         dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");
 610                         return -1;
 611                 }
 612                 if (pservice->pd_video == NULL) {
 613                         pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
 614                         if (IS_ERR(pservice->pd_video))
 615                                 pservice->pd_video = NULL;
 616                 }
 617                 break;
 618         default:
 619                 ;
 620         }
 621
 622         return 0;
 623 #else
 624         return 0;
 625 #endif
 626 }
 627
 628 static void vpu_put_clk(struct vpu_service_info *pservice)
 629 {
 630 #if VCODEC_CLOCK_ENABLE
 631         if (pservice->pd_video)
 632                 devm_clk_put(pservice->dev, pservice->pd_video);
 633         if (pservice->aclk_vcodec)
 634                 devm_clk_put(pservice->dev, pservice->aclk_vcodec);
 635         if (pservice->hclk_vcodec)
 636                 devm_clk_put(pservice->dev, pservice->hclk_vcodec);
 637         if (pservice->clk_core)
 638                 devm_clk_put(pservice->dev, pservice->clk_core);
 639         if (pservice->clk_cabac)
 640                 devm_clk_put(pservice->dev, pservice->clk_cabac);
 641 #endif
 642 }
 643
 644 static void vpu_reset(struct vpu_subdev_data *data)
 645 {
 646         struct vpu_service_info *pservice = data->pservice;
 647 #if defined(CONFIG_ARCH_RK29)
 648         clk_disable(aclk_ddr_vepu);
 649         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
 650         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
 651         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
 652         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
 653         mdelay(10);
 654         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
 655         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
 656         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
 657         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
 658         clk_enable(aclk_ddr_vepu);
 659 #elif defined(CONFIG_ARCH_RK30)
 660         pmu_set_idle_request(IDLE_REQ_VIDEO, true);
 661         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
 662         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
 663         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
 664         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
 665         mdelay(1);
 666         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
 667         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
 668         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
 669         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
 670         pmu_set_idle_request(IDLE_REQ_VIDEO, false);
 671 #endif
 672         pservice->reg_codec = NULL;
 673         pservice->reg_pproc = NULL;
 674         pservice->reg_resev = NULL;
 675
 676 #if defined(CONFIG_VCODEC_MMU)
 677         if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
 678                 clear_bit(MMU_ACTIVATED, &data->state);
 679                 BUG_ON(!pservice->enabled);
 680                 if (pservice->enabled)
 681                         rockchip_iovmm_deactivate(data->dev);
 682         }
 683 #endif
 684 }
 685
 686 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg);
 687 static void vpu_service_session_clear(struct vpu_subdev_data *data, vpu_session *session)
 688 {
 689         vpu_reg *reg, *n;
 690         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
 691                 reg_deinit(data, reg);
 692         }
 693         list_for_each_entry_safe(reg, n, &session->running, session_link) {
 694                 reg_deinit(data, reg);
 695         }
 696         list_for_each_entry_safe(reg, n, &session->done, session_link) {
 697                 reg_deinit(data, reg);
 698         }
 699 }
 700
 701 static void vpu_service_dump(struct vpu_service_info *pservice)
 702 {
 703 }
 704
 705 static void vpu_service_power_off(struct vpu_service_info *pservice)
 706 {
 707         int total_running;
 708         struct vpu_subdev_data *data = NULL, *n;
 709         if (!pservice->enabled)
 710                 return;
 711
 712         pservice->enabled = false;
 713         total_running = atomic_read(&pservice->total_running);
 714         if (total_running) {
 715                 pr_alert("alert: power off when %d task running!!\n", total_running);
 716                 mdelay(50);
 717                 pr_alert("alert: delay 50 ms for running task\n");
 718                 vpu_service_dump(pservice);
 719         }
 720
 721         pr_info("%s: power off...", dev_name(pservice->dev));
 722         udelay(10);
 723 #if defined(CONFIG_VCODEC_MMU)
 724         list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
 725                 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
 726                         clear_bit(MMU_ACTIVATED, &data->state);
 727                         rockchip_iovmm_deactivate(data->dev);
 728                 }
 729         }
 730         pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
 731 #endif
 732
 733 #if VCODEC_CLOCK_ENABLE
 734         if (pservice->pd_video)
 735                 clk_disable_unprepare(pservice->pd_video);
 736         if (pservice->hclk_vcodec)
 737                 clk_disable_unprepare(pservice->hclk_vcodec);
 738         if (pservice->aclk_vcodec)
 739                 clk_disable_unprepare(pservice->aclk_vcodec);
 740         if (pservice->clk_core)
 741                 clk_disable_unprepare(pservice->clk_core);
 742         if (pservice->clk_cabac)
 743                 clk_disable_unprepare(pservice->clk_cabac);
 744 #endif
 745
 746         wake_unlock(&pservice->wake_lock);
 747         pr_info("done\n");
 748 }
 749
 750 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
 751 {
 752         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);
 753 }
 754
 755 static void vpu_power_off_work(struct work_struct *work_s)
 756 {
 757         struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
 758         struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);
 759
 760         if (mutex_trylock(&pservice->lock)) {
 761                 vpu_service_power_off(pservice);
 762                 mutex_unlock(&pservice->lock);
 763         } else {
 764                 /* Come back later if the device is busy... */
 765                 vpu_queue_power_off_work(pservice);
 766         }
 767 }
 768
 769 static void vpu_service_power_on(struct vpu_service_info *pservice)
 770 {
 771         static ktime_t last;
 772         ktime_t now = ktime_get();
 773         if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
 774                 cancel_delayed_work_sync(&pservice->power_off_work);
 775                 vpu_queue_power_off_work(pservice);
 776                 last = now;
 777         }
 778         if (pservice->enabled)
 779                 return ;
 780
 781         pservice->enabled = true;
 782         pr_info("%s: power on\n", dev_name(pservice->dev));
 783
 784 #define BIT_VCODEC_CLK_SEL      (1<<10)
 785         if (cpu_is_rk312x())
 786                 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |
 787                         BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
 788                         RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
 789
 790 #if VCODEC_CLOCK_ENABLE
 791         if (pservice->aclk_vcodec)
 792                 clk_prepare_enable(pservice->aclk_vcodec);
 793         if (pservice->hclk_vcodec)
 794                 clk_prepare_enable(pservice->hclk_vcodec);
 795         if (pservice->clk_core)
 796                 clk_prepare_enable(pservice->clk_core);
 797         if (pservice->clk_cabac)
 798                 clk_prepare_enable(pservice->clk_cabac);
 799         if (pservice->pd_video)
 800                 clk_prepare_enable(pservice->pd_video);
 801 #endif
 802
 803         udelay(10);
 804         wake_lock(&pservice->wake_lock);
 805 }
 806
 807 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
 808 {
 809         u32 type = (reg->reg[3] & 0xF0000000) >> 28;
 810         return ((type == 8) || (type == 4));
 811 }
 812
 813 static inline bool reg_check_interlace(vpu_reg *reg)
 814 {
 815         u32 type = (reg->reg[3] & (1 << 23));
 816         return (type > 0);
 817 }
 818
 819 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)
 820 {
 821         enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);
 822         return type;
 823 }
 824
 825 static inline int reg_probe_width(vpu_reg *reg)
 826 {
 827         int width_in_mb = reg->reg[4] >> 23;
 828         return width_in_mb * 16;
 829 }
 830
 831 #if defined(CONFIG_VCODEC_MMU)
 832 static int vcodec_fd_to_iova(struct vpu_subdev_data *data, vpu_reg *reg,int fd)
 833 {
 834         struct vpu_service_info *pservice = data->pservice;
 835         struct ion_handle *hdl;
 836         int ret = 0;
 837         struct vcodec_mem_region *mem_region;
 838
 839         hdl = ion_import_dma_buf(pservice->ion_client, fd);
 840         if (IS_ERR(hdl)) {
 841                 vpu_err("import dma-buf from fd %d failed\n", fd);
 842                 return PTR_ERR(hdl);
 843         }
 844         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
 845
 846         if (mem_region == NULL) {
 847                 vpu_err("allocate memory for iommu memory region failed\n");
 848                 ion_free(pservice->ion_client, hdl);
 849                 return -1;
 850         }
 851
 852         mem_region->hdl = hdl;
 853         vcodec_enter_mode(data);
 854         ret = ion_map_iommu(data->dev, pservice->ion_client,
 855                 mem_region->hdl, &mem_region->iova, &mem_region->len);
 856         vcodec_exit_mode(pservice);
 857
 858         if (ret < 0) {
 859                 vpu_err("ion map iommu failed\n");
 860                 kfree(mem_region);
 861                 ion_free(pservice->ion_client, hdl);
 862                 return ret;
 863         }
 864         INIT_LIST_HEAD(&mem_region->reg_lnk);
 865         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
 866         return mem_region->iova;
 867 }
 868
 869 static int vcodec_bufid_to_iova(struct vpu_subdev_data *data, u8 *tbl,
 870                                 int size, vpu_reg *reg,
 871                                 struct extra_info_for_iommu *ext_inf)
 872 {
 873         struct vpu_service_info *pservice = data->pservice;
 874         int i;
 875         int usr_fd = 0;
 876         int offset = 0;
 877
 878         if (tbl == NULL || size <= 0) {
 879                 dev_err(pservice->dev, "input arguments invalidate\n");
 880                 return -1;
 881         }
 882
 883         vpu_service_power_on(pservice);
 884
 885         for (i = 0; i < size; i++) {
 886                 usr_fd = reg->reg[tbl[i]] & 0x3FF;
 887
 888                 if (tbl[i] == 41 && data->hw_info->hw_id != HEVC_ID &&
 889                     (reg->type == VPU_DEC || reg->type == VPU_DEC_PP))
 890                         /* special for vpu dec num 41 regitster */
 891                         offset = reg->reg[tbl[i]] >> 10 << 4;
 892                 else
 893                         offset = reg->reg[tbl[i]] >> 10;
 894
 895                 if (usr_fd != 0) {
 896                         struct ion_handle *hdl;
 897                         int ret = 0;
 898                         struct vcodec_mem_region *mem_region;
 899
 900                         hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);
 901                         if (IS_ERR(hdl)) {
 902                                 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);
 903                                 return PTR_ERR(hdl);
 904                         }
 905
 906                         if (tbl[i] == 42 && data->hw_info->hw_id == HEVC_ID){
 907                                 int i = 0;
 908                                 char *pps;
 909                                 pps = (char *)ion_map_kernel(pservice->ion_client,hdl);
 910                                 for (i=0; i<64; i++) {
 911                                         u32 scaling_offset;
 912                                         u32 tmp;
 913                                         int scaling_fd= 0;
 914                                         scaling_offset = (u32)pps[i*80+74];
 915                                         scaling_offset += (u32)pps[i*80+75] << 8;
 916                                         scaling_offset += (u32)pps[i*80+76] << 16;
 917                                         scaling_offset += (u32)pps[i*80+77] << 24;
 918                                         scaling_fd = scaling_offset&0x3ff;
 919                                         scaling_offset = scaling_offset >> 10;
 920                                         if(scaling_fd > 0) {
 921                                                 tmp = vcodec_fd_to_iova(data, reg, scaling_fd);
 922                                                 tmp += scaling_offset;
 923                                                 pps[i*80+74] = tmp & 0xff;
 924                                                 pps[i*80+75] = (tmp >> 8) & 0xff;
 925                                                 pps[i*80+76] = (tmp >> 16) & 0xff;
 926                                                 pps[i*80+77] = (tmp >> 24) & 0xff;
 927                                         }
 928                                 }
 929                         }
 930
 931                         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
 932
 933                         if (mem_region == NULL) {
 934                                 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");
 935                                 ion_free(pservice->ion_client, hdl);
 936                                 return -1;
 937                         }
 938
 939                         mem_region->hdl = hdl;
 940                         mem_region->reg_idx = tbl[i];
 941                         vcodec_enter_mode(data);
 942                         ret = ion_map_iommu(data->dev,
 943                                             pservice->ion_client,
 944                                             mem_region->hdl,
 945                                             &mem_region->iova,
 946                                             &mem_region->len);
 947                         vcodec_exit_mode(pservice);
 948
 949                         if (ret < 0) {
 950                                 dev_err(pservice->dev, "ion map iommu failed\n");
 951                                 kfree(mem_region);
 952                                 ion_free(pservice->ion_client, hdl);
 953                                 return ret;
 954                         }
 955                         reg->reg[tbl[i]] = mem_region->iova + offset;
 956                         INIT_LIST_HEAD(&mem_region->reg_lnk);
 957                         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
 958                 }
 959         }
 960
 961         if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {
 962                 for (i=0; i<ext_inf->cnt; i++) {
 963                         vpu_debug(3, "reg[%d] + offset %d\n",
 964                                   ext_inf->elem[i].index,
 965                                   ext_inf->elem[i].offset);
 966                         reg->reg[ext_inf->elem[i].index] +=
 967                                 ext_inf->elem[i].offset;
 968                 }
 969         }
 970
 971         return 0;
 972 }
 973
 974 static int vcodec_reg_address_translate(struct vpu_subdev_data *data,
 975                                         vpu_reg *reg,
 976                                         struct extra_info_for_iommu *ext_inf)
 977 {
 978         VPU_HW_ID hw_id;
 979         u8 *tbl;
 980         int size = 0;
 981
 982         hw_id = data->hw_info->hw_id;
 983
 984         if (hw_id == HEVC_ID) {
 985                 tbl = addr_tbl_hevc_dec;
 986                 size = sizeof(addr_tbl_hevc_dec);
 987         } else {
 988                 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
 989                         switch (reg_check_fmt(reg)) {
 990                         case VPU_DEC_FMT_H264:
 991                                 {
 992                                         tbl = addr_tbl_vpu_h264dec;
 993                                         size = sizeof(addr_tbl_vpu_h264dec);
 994                                         break;
 995                                 }
 996                         case VPU_DEC_FMT_VP8:
 997                         case VPU_DEC_FMT_VP7:
 998                                 {
 999                                         tbl = addr_tbl_vpu_vp8dec;
1000                                         size = sizeof(addr_tbl_vpu_vp8dec);
1001                                         break;
1002                                 }
1003
1004                         case VPU_DEC_FMT_VP6:
1005                                 {
1006                                         tbl = addr_tbl_vpu_vp6dec;
1007                                         size = sizeof(addr_tbl_vpu_vp6dec);
1008                                         break;
1009                                 }
1010                         case VPU_DEC_FMT_VC1:
1011                                 {
1012                                         tbl = addr_tbl_vpu_vc1dec;
1013                                         size = sizeof(addr_tbl_vpu_vc1dec);
1014                                         break;
1015                                 }
1016
1017                         case VPU_DEC_FMT_JPEG:
1018                                 {
1019                                         tbl = addr_tbl_vpu_jpegdec;
1020                                         size = sizeof(addr_tbl_vpu_jpegdec);
1021                                         break;
1022                                 }
1023                         default:
1024                                 tbl = addr_tbl_vpu_defaultdec;
1025                                 size = sizeof(addr_tbl_vpu_defaultdec);
1026                                 break;
1027                         }
1028                 } else if (reg->type == VPU_ENC) {
1029                         tbl = addr_tbl_vpu_enc;
1030                         size = sizeof(addr_tbl_vpu_enc);
1031                 }
1032         }
1033
1034         if (size != 0) {
1035                 return vcodec_bufid_to_iova(data, tbl, size, reg, ext_inf);
1036         } else {
1037                 return -1;
1038         }
1039 }
1040 #endif
1041
1042 static vpu_reg *reg_init(struct vpu_subdev_data *data,
1043         vpu_session *session, void __user *src, u32 size)
1044 {
1045         struct vpu_service_info *pservice = data->pservice;
1046         int extra_size = 0;
1047         struct extra_info_for_iommu extra_info;
1048         vpu_reg *reg = kmalloc(sizeof(vpu_reg) + data->reg_size, GFP_KERNEL);
1049
1050         vpu_debug_enter();
1051
1052         if (NULL == reg) {
1053                 vpu_err("error: kmalloc fail in reg_init\n");
1054                 return NULL;
1055         }
1056
1057         if (size > data->reg_size) {
1058                 /*printk("warning: vpu reg size %lu is larger than hw reg size %lu\n",
1059                   size, pservice->reg_size);
1060                 size = pservice->reg_size;*/
1061                 extra_size = size - data->reg_size;
1062                 size = data->reg_size;
1063         }
1064         reg->session = session;
1065         reg->type = session->type;
1066         reg->size = size;
1067         reg->freq = VPU_FREQ_DEFAULT;
1068         reg->reg = (u32 *)&reg[1];
1069         INIT_LIST_HEAD(&reg->session_link);
1070         INIT_LIST_HEAD(&reg->status_link);
1071
1072 #if defined(CONFIG_VCODEC_MMU)
1073         if (data->mmu_dev)
1074                 INIT_LIST_HEAD(&reg->mem_region_list);
1075 #endif
1076
1077         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {
1078                 vpu_err("error: copy_from_user failed in reg_init\n");
1079                 kfree(reg);
1080                 return NULL;
1081         }
1082
1083         if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {
1084                 vpu_err("error: copy_from_user failed in reg_init\n");
1085                 kfree(reg);
1086                 return NULL;
1087         }
1088
1089 #if defined(CONFIG_VCODEC_MMU)
1090         if (data->mmu_dev &&
1091             0 > vcodec_reg_address_translate(data, reg, &extra_info)) {
1092                 vpu_err("error: translate reg address failed\n");
1093                 kfree(reg);
1094                 return NULL;
1095         }
1096 #endif
1097
1098         mutex_lock(&pservice->lock);
1099         list_add_tail(&reg->status_link, &pservice->waiting);
1100         list_add_tail(&reg->session_link, &session->waiting);
1101         mutex_unlock(&pservice->lock);
1102
1103         if (pservice->auto_freq) {
1104                 if (!soc_is_rk2928g()) {
1105                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1106                                 if (reg_check_rmvb_wmv(reg)) {
1107                                         reg->freq = VPU_FREQ_200M;
1108                                 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
1109                                         if (reg_probe_width(reg) > 3200) {
1110                                                 // raise frequency for 4k avc.
1111                                                 reg->freq = VPU_FREQ_500M;
1112                                         }
1113                                 } else {
1114                                         if (reg_check_interlace(reg)) {
1115                                                 reg->freq = VPU_FREQ_400M;
1116                                         }
1117                                 }
1118                         }
1119                         if (reg->type == VPU_PP) {
1120                                 reg->freq = VPU_FREQ_400M;
1121                         }
1122                 }
1123         }
1124         vpu_debug_leave();
1125         return reg;
1126 }
1127
1128 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg)
1129 {
1130         struct vpu_service_info *pservice = data->pservice;
1131 #if defined(CONFIG_VCODEC_MMU)
1132         struct vcodec_mem_region *mem_region = NULL, *n;
1133 #endif
1134
1135         list_del_init(&reg->session_link);
1136         list_del_init(&reg->status_link);
1137         if (reg == pservice->reg_codec)
1138                 pservice->reg_codec = NULL;
1139         if (reg == pservice->reg_pproc)
1140                 pservice->reg_pproc = NULL;
1141
1142 #if defined(CONFIG_VCODEC_MMU)
1143         /* release memory region attach to this registers table. */
1144         if (data->mmu_dev) {
1145                 list_for_each_entry_safe(mem_region, n,
1146                         &reg->mem_region_list, reg_lnk) {
1147                         /* do not unmap iommu manually,
1148                            unmap will proccess when memory release */
1149                         /*vcodec_enter_mode(data);
1150                         ion_unmap_iommu(data->dev,
1151                                         pservice->ion_client,
1152                                         mem_region->hdl);
1153                         vcodec_exit_mode();*/
1154                         ion_free(pservice->ion_client, mem_region->hdl);
1155                         list_del_init(&mem_region->reg_lnk);
1156                         kfree(mem_region);
1157                 }
1158         }
1159 #endif
1160
1161         kfree(reg);
1162 }
1163
1164 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)
1165 {
1166         vpu_debug_enter();
1167         list_del_init(&reg->status_link);
1168         list_add_tail(&reg->status_link, &pservice->running);
1169
1170         list_del_init(&reg->session_link);
1171         list_add_tail(&reg->session_link, &reg->session->running);
1172         vpu_debug_leave();
1173 }
1174
1175 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
1176 {
1177         int i;
1178         u32 *dst = (u32 *)&reg->reg[0];
1179         vpu_debug_enter();
1180         for (i = 0; i < count; i++)
1181                 *dst++ = *src++;
1182         vpu_debug_leave();
1183 }
1184
1185 static void reg_from_run_to_done(struct vpu_subdev_data *data,
1186         vpu_reg *reg)
1187 {
1188         struct vpu_service_info *pservice = data->pservice;
1189         int irq_reg = -1;
1190
1191         vpu_debug_enter();
1192
1193         list_del_init(&reg->status_link);
1194         list_add_tail(&reg->status_link, &pservice->done);
1195
1196         list_del_init(&reg->session_link);
1197         list_add_tail(&reg->session_link, &reg->session->done);
1198
1199         vcodec_enter_mode(data);
1200         switch (reg->type) {
1201         case VPU_ENC : {
1202                 pservice->reg_codec = NULL;
1203                 reg_copy_from_hw(reg, data->enc_dev.hwregs, data->hw_info->enc_reg_num);
1204                 irq_reg = ENC_INTERRUPT_REGISTER;
1205                 break;
1206         }
1207         case VPU_DEC : {
1208                 int reg_len = REG_NUM_9190_DEC;
1209                 pservice->reg_codec = NULL;
1210                 reg_copy_from_hw(reg, data->dec_dev.hwregs, reg_len);
1211                 irq_reg = DEC_INTERRUPT_REGISTER;
1212                 break;
1213         }
1214         case VPU_PP : {
1215                 pservice->reg_pproc = NULL;
1216                 reg_copy_from_hw(reg, data->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
1217                 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1218                 break;
1219         }
1220         case VPU_DEC_PP : {
1221                 pservice->reg_codec = NULL;
1222                 pservice->reg_pproc = NULL;
1223                 reg_copy_from_hw(reg, data->dec_dev.hwregs, REG_NUM_9190_DEC_PP);
1224                 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1225                 break;
1226         }
1227         default : {
1228                 vpu_err("error: copy reg from hw with unknown type %d\n", reg->type);
1229                 break;
1230         }
1231         }
1232         vcodec_exit_mode(pservice);
1233
1234         if (irq_reg != -1)
1235                 reg->reg[irq_reg] = pservice->irq_status;
1236
1237         atomic_sub(1, &reg->session->task_running);
1238         atomic_sub(1, &pservice->total_running);
1239         wake_up(&reg->session->wait);
1240
1241         vpu_debug_leave();
1242 }
1243
1244 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)
1245 {
1246         VPU_FREQ curr = atomic_read(&pservice->freq_status);
1247         if (curr == reg->freq)
1248                 return;
1249         atomic_set(&pservice->freq_status, reg->freq);
1250         switch (reg->freq) {
1251         case VPU_FREQ_200M : {
1252                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
1253         } break;
1254         case VPU_FREQ_266M : {
1255                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
1256         } break;
1257         case VPU_FREQ_300M : {
1258                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1259         } break;
1260         case VPU_FREQ_400M : {
1261                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1262         } break;
1263         case VPU_FREQ_500M : {
1264                 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
1265         } break;
1266         case VPU_FREQ_600M : {
1267                 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
1268         } break;
1269         default : {
1270                 if (soc_is_rk2928g())
1271                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1272                 else
1273                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1274         } break;
1275         }
1276 }
1277
1278 static void reg_copy_to_hw(struct vpu_subdev_data *data, vpu_reg *reg)
1279 {
1280         struct vpu_service_info *pservice = data->pservice;
1281         int i;
1282         u32 *src = (u32 *)&reg->reg[0];
1283         vpu_debug_enter();
1284
1285         atomic_add(1, &pservice->total_running);
1286         atomic_add(1, &reg->session->task_running);
1287         if (pservice->auto_freq)
1288                 vpu_service_set_freq(pservice, reg);
1289
1290         vcodec_enter_mode(data);
1291
1292         switch (reg->type) {
1293         case VPU_ENC : {
1294                 int enc_count = data->hw_info->enc_reg_num;
1295                 u32 *dst = (u32 *)data->enc_dev.hwregs;
1296
1297                 pservice->reg_codec = reg;
1298
1299                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
1300
1301                 for (i = 0; i < VPU_REG_EN_ENC; i++)
1302                         dst[i] = src[i];
1303
1304                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
1305                         dst[i] = src[i];
1306
1307                 VEPU_CLEAN_CACHE(dst);
1308
1309                 dsb();
1310
1311                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
1312                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];
1313
1314 #if VPU_SERVICE_SHOW_TIME
1315                 do_gettimeofday(&enc_start);
1316 #endif
1317
1318         } break;
1319         case VPU_DEC : {
1320                 u32 *dst = (u32 *)data->dec_dev.hwregs;
1321
1322                 pservice->reg_codec = reg;
1323
1324                 if (data->hw_info->hw_id != HEVC_ID) {
1325                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
1326                                 dst[i] = src[i];
1327                         VDPU_CLEAN_CACHE(dst);
1328                 } else {
1329                         for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--)
1330                                 dst[i] = src[i];
1331                         HEVC_CLEAN_CACHE(dst);
1332                 }
1333
1334                 dsb();
1335
1336                 if (data->hw_info->hw_id != HEVC_ID) {
1337                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1338                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1339                 } else {
1340                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1341                 }
1342                 dsb();
1343                 dmb();
1344 #if VPU_SERVICE_SHOW_TIME
1345                 do_gettimeofday(&dec_start);
1346 #endif
1347         } break;
1348         case VPU_PP : {
1349                 u32 *dst = (u32 *)data->dec_dev.hwregs + PP_INTERRUPT_REGISTER;
1350                 pservice->reg_pproc = reg;
1351
1352                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
1353
1354                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
1355                         dst[i] = src[i];
1356
1357                 dsb();
1358
1359                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
1360 #if VPU_SERVICE_SHOW_TIME
1361                 do_gettimeofday(&pp_start);
1362 #endif
1363
1364         } break;
1365         case VPU_DEC_PP : {
1366                 u32 *dst = (u32 *)data->dec_dev.hwregs;
1367                 pservice->reg_codec = reg;
1368                 pservice->reg_pproc = reg;
1369
1370                 VDPU_SOFT_RESET(dst);
1371                 VDPU_CLEAN_CACHE(dst);
1372
1373                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
1374                         dst[i] = src[i];
1375
1376                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;
1377                 dsb();
1378
1379                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
1380                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;
1381                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];
1382 #if VPU_SERVICE_SHOW_TIME
1383                 do_gettimeofday(&dec_start);
1384 #endif
1385         } break;
1386         default : {
1387                 vpu_err("error: unsupport session type %d", reg->type);
1388                 atomic_sub(1, &pservice->total_running);
1389                 atomic_sub(1, &reg->session->task_running);
1390                 break;
1391         }
1392         }
1393
1394         vcodec_exit_mode(pservice);
1395         vpu_debug_leave();
1396 }
1397
1398 static void try_set_reg(struct vpu_subdev_data *data)
1399 {
1400         struct vpu_service_info *pservice = data->pservice;
1401         vpu_debug_enter();
1402         if (!list_empty(&pservice->waiting)) {
1403                 int can_set = 0;
1404                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);
1405
1406                 vpu_service_power_on(pservice);
1407
1408                 switch (reg->type) {
1409                 case VPU_ENC : {
1410                         if ((NULL == pservice->reg_codec) &&  (NULL == pservice->reg_pproc))
1411                                 can_set = 1;
1412                 } break;
1413                 case VPU_DEC : {
1414                         if (NULL == pservice->reg_codec)
1415                                 can_set = 1;
1416                         if (pservice->auto_freq && (NULL != pservice->reg_pproc))
1417                                 can_set = 0;
1418                 } break;
1419                 case VPU_PP : {
1420                         if (NULL == pservice->reg_codec) {
1421                                 if (NULL == pservice->reg_pproc)
1422                                         can_set = 1;
1423                         } else {
1424                                 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))
1425                                         can_set = 1;
1426                                 /* can not charge frequency when vpu is working */
1427                                 if (pservice->auto_freq)
1428                                         can_set = 0;
1429                         }
1430                 } break;
1431                 case VPU_DEC_PP : {
1432                         if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))
1433                                 can_set = 1;
1434                         } break;
1435                 default : {
1436                         printk("undefined reg type %d\n", reg->type);
1437                 } break;
1438                 }
1439                 if (can_set) {
1440                         reg_from_wait_to_run(pservice, reg);
1441                         reg_copy_to_hw(data, reg);
1442                 }
1443         }
1444         vpu_debug_leave();
1445 }
1446
1447 static int return_reg(struct vpu_subdev_data *data,
1448         vpu_reg *reg, u32 __user *dst)
1449 {
1450         int ret = 0;
1451         vpu_debug_enter();
1452         switch (reg->type) {
1453         case VPU_ENC : {
1454                 if (copy_to_user(dst, &reg->reg[0], data->hw_info->enc_io_size))
1455                         ret = -EFAULT;
1456                 break;
1457         }
1458         case VPU_DEC : {
1459                 int reg_len = data->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1460                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(reg_len)))
1461                         ret = -EFAULT;
1462                 break;
1463         }
1464         case VPU_PP : {
1465                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))
1466                         ret = -EFAULT;
1467                 break;
1468         }
1469         case VPU_DEC_PP : {
1470                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
1471                         ret = -EFAULT;
1472                 break;
1473         }
1474         default : {
1475                 ret = -EFAULT;
1476                 vpu_err("error: copy reg to user with unknown type %d\n", reg->type);
1477                 break;
1478         }
1479         }
1480         reg_deinit(data, reg);
1481         vpu_debug_leave();
1482         return ret;
1483 }
1484
1485 static long vpu_service_ioctl(struct file *filp, unsigned int cmd,
1486         unsigned long arg)
1487 {
1488         struct vpu_subdev_data *data =
1489                 container_of(filp->f_dentry->d_inode->i_cdev,
1490                         struct vpu_subdev_data, cdev);
1491         struct vpu_service_info *pservice = data->pservice;
1492         vpu_session *session = (vpu_session *)filp->private_data;
1493         vpu_debug_enter();
1494         vpu_debug(3, "cmd %x, VPU_IOC_SET_CLIENT_TYPE %x\n", cmd, (u32)VPU_IOC_SET_CLIENT_TYPE);
1495         if (NULL == session)
1496                 return -EINVAL;
1497
1498         switch (cmd) {
1499         case VPU_IOC_SET_CLIENT_TYPE : {
1500                 session->type = (enum VPU_CLIENT_TYPE)arg;
1501                 break;
1502         }
1503         case VPU_IOC_GET_HW_FUSE_STATUS : {
1504                 vpu_request req;
1505                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
1506                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
1507                         return -EFAULT;
1508                 } else {
1509                         if (VPU_ENC != session->type) {
1510                                 if (copy_to_user((void __user *)req.req,
1511                                         &pservice->dec_config,
1512                                         sizeof(struct vpu_dec_config))) {
1513                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1514                                                 session->type);
1515                                         return -EFAULT;
1516                                 }
1517                         } else {
1518                                 if (copy_to_user((void __user *)req.req,
1519                                         &pservice->enc_config,
1520                                         sizeof(struct vpu_enc_config ))) {
1521                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1522                                                 session->type);
1523                                         return -EFAULT;
1524                                 }
1525                         }
1526                 }
1527
1528                 break;
1529         }
1530         case VPU_IOC_SET_REG : {
1531                 vpu_request req;
1532                 vpu_reg *reg;
1533                 if (copy_from_user(&req, (void __user *)arg,
1534                         sizeof(vpu_request))) {
1535                         vpu_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
1536                         return -EFAULT;
1537                 }
1538                 reg = reg_init(data, session,
1539                         (void __user *)req.req, req.size);
1540                 if (NULL == reg) {
1541                         return -EFAULT;
1542                 } else {
1543                         mutex_lock(&pservice->lock);
1544                         try_set_reg(data);
1545                         mutex_unlock(&pservice->lock);
1546                 }
1547
1548                 break;
1549         }
1550         case VPU_IOC_GET_REG : {
1551                 vpu_request req;
1552                 vpu_reg *reg;
1553                 if (copy_from_user(&req, (void __user *)arg,
1554                         sizeof(vpu_request))) {
1555                         vpu_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
1556                         return -EFAULT;
1557                 } else {
1558                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1559                         if (!list_empty(&session->done)) {
1560                                 if (ret < 0) {
1561                                         vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1562                                 }
1563                                 ret = 0;
1564                         } else {
1565                                 if (unlikely(ret < 0)) {
1566                                         vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1567                                 } else if (0 == ret) {
1568                                         vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1569                                         ret = -ETIMEDOUT;
1570                                 }
1571                         }
1572                         if (ret < 0) {
1573                                 int task_running = atomic_read(&session->task_running);
1574                                 mutex_lock(&pservice->lock);
1575                                 vpu_service_dump(pservice);
1576                                 if (task_running) {
1577                                         atomic_set(&session->task_running, 0);
1578                                         atomic_sub(task_running, &pservice->total_running);
1579                                         printk("%d task is running but not return, reset hardware...", task_running);
1580                                         vpu_reset(data);
1581                                         printk("done\n");
1582                                 }
1583                                 vpu_service_session_clear(data, session);
1584                                 mutex_unlock(&pservice->lock);
1585                                 return ret;
1586                         }
1587                 }
1588                 mutex_lock(&pservice->lock);
1589                 reg = list_entry(session->done.next, vpu_reg, session_link);
1590                 return_reg(data, reg, (u32 __user *)req.req);
1591                 mutex_unlock(&pservice->lock);
1592                 break;
1593         }
1594         case VPU_IOC_PROBE_IOMMU_STATUS: {
1595                 int iommu_enable = 0;
1596
1597 #if defined(CONFIG_VCODEC_MMU)
1598                 iommu_enable = data->mmu_dev ? 1 : 0;
1599 #endif
1600
1601                 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {
1602                         vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1603                         return -EFAULT;
1604                 }
1605                 break;
1606         }
1607         default : {
1608                 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1609                 break;
1610         }
1611         }
1612         vpu_debug_leave();
1613         return 0;
1614 }
1615
1616 #ifdef CONFIG_COMPAT
1617 static long compat_vpu_service_ioctl(struct file *filp, unsigned int cmd,
1618         unsigned long arg)
1619 {
1620         struct vpu_subdev_data *data =
1621                 container_of(filp->f_dentry->d_inode->i_cdev,
1622                         struct vpu_subdev_data, cdev);
1623         struct vpu_service_info *pservice = data->pservice;
1624         vpu_session *session = (vpu_session *)filp->private_data;
1625         vpu_debug_enter();
1626         vpu_debug(3, "cmd %x, COMPAT_VPU_IOC_SET_CLIENT_TYPE %x\n", cmd,
1627                   (u32)COMPAT_VPU_IOC_SET_CLIENT_TYPE);
1628         if (NULL == session)
1629                 return -EINVAL;
1630
1631         switch (cmd) {
1632         case COMPAT_VPU_IOC_SET_CLIENT_TYPE : {
1633                 session->type = (enum VPU_CLIENT_TYPE)arg;
1634                 break;
1635         }
1636         case COMPAT_VPU_IOC_GET_HW_FUSE_STATUS : {
1637                 vpu_request req;
1638                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1639                                    sizeof(vpu_request))) {
1640                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1641                                 " copy_from_user failed\n");
1642                         return -EFAULT;
1643                 } else {
1644                         if (VPU_ENC != session->type) {
1645                                 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1646                                                  &pservice->dec_config,
1647                                                  sizeof(struct vpu_dec_config))) {
1648                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS "
1649                                                 "copy_to_user failed type %d\n",
1650                                                 session->type);
1651                                         return -EFAULT;
1652                                 }
1653                         } else {
1654                                 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1655                                                  &pservice->enc_config,
1656                                                  sizeof(struct vpu_enc_config ))) {
1657                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1658                                                 " copy_to_user failed type %d\n",
1659                                                 session->type);
1660                                         return -EFAULT;
1661                                 }
1662                         }
1663                 }
1664
1665                 break;
1666         }
1667         case COMPAT_VPU_IOC_SET_REG : {
1668                 vpu_request req;
1669                 vpu_reg *reg;
1670                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1671                                    sizeof(vpu_request))) {
1672                         vpu_err("VPU_IOC_SET_REG copy_from_user failed\n");
1673                         return -EFAULT;
1674                 }
1675                 reg = reg_init(data, session,
1676                                compat_ptr((compat_uptr_t)req.req), req.size);
1677                 if (NULL == reg) {
1678                         return -EFAULT;
1679                 } else {
1680                         mutex_lock(&pservice->lock);
1681                         try_set_reg(data);
1682                         mutex_unlock(&pservice->lock);
1683                 }
1684
1685                 break;
1686         }
1687         case COMPAT_VPU_IOC_GET_REG : {
1688                 vpu_request req;
1689                 vpu_reg *reg;
1690                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1691                                    sizeof(vpu_request))) {
1692                         vpu_err("VPU_IOC_GET_REG copy_from_user failed\n");
1693                         return -EFAULT;
1694                 } else {
1695                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1696                         if (!list_empty(&session->done)) {
1697                                 if (ret < 0) {
1698                                         vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1699                                 }
1700                                 ret = 0;
1701                         } else {
1702                                 if (unlikely(ret < 0)) {
1703                                         vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1704                                 } else if (0 == ret) {
1705                                         vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1706                                         ret = -ETIMEDOUT;
1707                                 }
1708                         }
1709                         if (ret < 0) {
1710                                 int task_running = atomic_read(&session->task_running);
1711                                 mutex_lock(&pservice->lock);
1712                                 vpu_service_dump(pservice);
1713                                 if (task_running) {
1714                                         atomic_set(&session->task_running, 0);
1715                                         atomic_sub(task_running, &pservice->total_running);
1716                                         printk("%d task is running but not return, reset hardware...", task_running);
1717                                         vpu_reset(data);
1718                                         printk("done\n");
1719                                 }
1720                                 vpu_service_session_clear(data, session);
1721                                 mutex_unlock(&pservice->lock);
1722                                 return ret;
1723                         }
1724                 }
1725                 mutex_lock(&pservice->lock);
1726                 reg = list_entry(session->done.next, vpu_reg, session_link);
1727                 return_reg(data, reg, compat_ptr((compat_uptr_t)req.req));
1728                 mutex_unlock(&pservice->lock);
1729                 break;
1730         }
1731         case COMPAT_VPU_IOC_PROBE_IOMMU_STATUS : {
1732                 int iommu_enable = 0;
1733
1734 #if defined(CONFIG_VCODEC_MMU)
1735                 iommu_enable = data->mmu_dev ? 1 : 0;
1736 #endif
1737
1738                 if (copy_to_user(compat_ptr((compat_uptr_t)arg), &iommu_enable, sizeof(int))) {
1739                         vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1740                         return -EFAULT;
1741                 }
1742                 break;
1743         }
1744         default : {
1745                 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1746                 break;
1747         }
1748         }
1749         vpu_debug_leave();
1750         return 0;
1751 }
1752 #endif
1753
1754 static int vpu_service_check_hw(struct vpu_subdev_data *data, u32 hw_addr)
1755 {
1756         int ret = -EINVAL, i = 0;
1757         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
1758         u32 enc_id = *tmp;
1759
1760         enc_id = (enc_id >> 16) & 0xFFFF;
1761         pr_info("checking hw id %x\n", enc_id);
1762         data->hw_info = NULL;
1763         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
1764                 if (enc_id == vpu_hw_set[i].hw_id) {
1765                         data->hw_info = &vpu_hw_set[i];
1766                         ret = 0;
1767                         break;
1768                 }
1769         }
1770         iounmap((void *)tmp);
1771         return ret;
1772 }
1773
1774 static int vpu_service_open(struct inode *inode, struct file *filp)
1775 {
1776         struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1777         struct vpu_service_info *pservice = data->pservice;
1778         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
1779
1780         vpu_debug_enter();
1781
1782         if (NULL == session) {
1783                 vpu_err("error: unable to allocate memory for vpu_session.");
1784                 return -ENOMEM;
1785         }
1786
1787         session->type   = VPU_TYPE_BUTT;
1788         session->pid    = current->pid;
1789         INIT_LIST_HEAD(&session->waiting);
1790         INIT_LIST_HEAD(&session->running);
1791         INIT_LIST_HEAD(&session->done);
1792         INIT_LIST_HEAD(&session->list_session);
1793         init_waitqueue_head(&session->wait);
1794         atomic_set(&session->task_running, 0);
1795         mutex_lock(&pservice->lock);
1796         list_add_tail(&session->list_session, &pservice->session);
1797         filp->private_data = (void *)session;
1798         mutex_unlock(&pservice->lock);
1799
1800         pr_debug("dev opened\n");
1801         vpu_debug_leave();
1802         return nonseekable_open(inode, filp);
1803 }
1804
1805 static int vpu_service_release(struct inode *inode, struct file *filp)
1806 {
1807         struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1808         struct vpu_service_info *pservice = data->pservice;
1809         int task_running;
1810         vpu_session *session = (vpu_session *)filp->private_data;
1811         vpu_debug_enter();
1812         if (NULL == session)
1813                 return -EINVAL;
1814
1815         task_running = atomic_read(&session->task_running);
1816         if (task_running) {
1817                 vpu_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
1818                 msleep(50);
1819         }
1820         wake_up(&session->wait);
1821
1822         mutex_lock(&pservice->lock);
1823         /* remove this filp from the asynchronusly notified filp's */
1824         list_del_init(&session->list_session);
1825         vpu_service_session_clear(data, session);
1826         kfree(session);
1827         filp->private_data = NULL;
1828         mutex_unlock(&pservice->lock);
1829
1830         pr_debug("dev closed\n");
1831         vpu_debug_leave();
1832         return 0;
1833 }
1834
1835 static const struct file_operations vpu_service_fops = {
1836         .unlocked_ioctl = vpu_service_ioctl,
1837         .open           = vpu_service_open,
1838         .release        = vpu_service_release,
1839 #ifdef CONFIG_COMPAT
1840         .compat_ioctl   = compat_vpu_service_ioctl,
1841 #endif
1842         //.fasync       = vpu_service_fasync,
1843 };
1844
1845 static irqreturn_t vdpu_irq(int irq, void *dev_id);
1846 static irqreturn_t vdpu_isr(int irq, void *dev_id);
1847 static irqreturn_t vepu_irq(int irq, void *dev_id);
1848 static irqreturn_t vepu_isr(int irq, void *dev_id);
1849 static void get_hw_info(struct vpu_subdev_data *data);
1850
1851 #ifdef CONFIG_VCODEC_MMU
1852 static struct device *rockchip_get_sysmmu_dev(const char *compt)
1853 {
1854         struct device_node *dn = NULL;
1855         struct platform_device *pd = NULL;
1856         struct device *ret = NULL ;
1857
1858         dn = of_find_compatible_node(NULL,NULL,compt);
1859         if(!dn) {
1860                 printk("can't find device node %s \r\n",compt);
1861                 return NULL;
1862         }
1863
1864         pd = of_find_device_by_node(dn);
1865         if(!pd) {
1866                 printk("can't find platform device in device node %s\n",compt);
1867                 return  NULL;
1868         }
1869         ret = &pd->dev;
1870
1871         return ret;
1872
1873 }
1874 #ifdef CONFIG_IOMMU_API
1875 static inline void platform_set_sysmmu(struct device *iommu,
1876         struct device *dev)
1877 {
1878         dev->archdata.iommu = iommu;
1879 }
1880 #else
1881 static inline void platform_set_sysmmu(struct device *iommu,
1882         struct device *dev)
1883 {
1884 }
1885 #endif
1886
1887 int vcodec_sysmmu_fault_hdl(struct device *dev,
1888                                 enum rk_iommu_inttype itype,
1889                                 unsigned long pgtable_base,
1890                                 unsigned long fault_addr, unsigned int status)
1891 {
1892         struct platform_device *pdev;
1893         struct vpu_subdev_data *data;
1894         struct vpu_service_info *pservice;
1895
1896         vpu_debug_enter();
1897
1898         pdev = container_of(dev, struct platform_device, dev);
1899
1900         data = platform_get_drvdata(pdev);
1901         pservice = data->pservice;
1902
1903         if (pservice->reg_codec) {
1904                 struct vcodec_mem_region *mem, *n;
1905                 int i = 0;
1906                 vpu_debug(3, "vcodec, fault addr 0x%08x\n", (u32)fault_addr);
1907                 list_for_each_entry_safe(mem, n,
1908                                          &pservice->reg_codec->mem_region_list,
1909                                          reg_lnk) {
1910                         vpu_debug(3, "vcodec, reg[%02u] mem region [%02d] 0x%08x %ld\n",
1911                                 mem->reg_idx, i, (u32)mem->iova, mem->len);
1912                         i++;
1913                 }
1914
1915                 pr_alert("vcodec, page fault occur, reset hw\n");
1916                 pservice->reg_codec->reg[101] = 1;
1917                 vpu_reset(data);
1918         }
1919
1920         return 0;
1921 }
1922 #endif
1923
1924 #if HEVC_TEST_ENABLE
1925 static int hevc_test_case0(vpu_service_info *pservice);
1926 #endif
1927 #if defined(CONFIG_ION_ROCKCHIP)
1928 extern struct ion_client *rockchip_ion_client_create(const char * name);
1929 #endif
1930
1931 static int vcodec_subdev_probe(struct platform_device *pdev,
1932         struct vpu_service_info *pservice)
1933 {
1934         int ret = 0;
1935         struct resource *res = NULL;
1936         u32 ioaddr = 0;
1937         struct device *dev = &pdev->dev;
1938         char *name = (char*)dev_name(dev);
1939         struct device_node *np = pdev->dev.of_node;
1940         struct vpu_subdev_data *data =
1941                 devm_kzalloc(dev, sizeof(struct vpu_subdev_data), GFP_KERNEL);
1942 #if defined(CONFIG_VCODEC_MMU)
1943         u32 iommu_en = 0;
1944         char mmu_dev_dts_name[40];
1945         of_property_read_u32(np, "iommu_enabled", &iommu_en);
1946 #endif
1947         pr_info("probe device %s\n", dev_name(dev));
1948
1949         data->pservice = pservice;
1950         data->dev = dev;
1951
1952         of_property_read_string(np, "name", (const char**)&name);
1953         of_property_read_u32(np, "dev_mode", (u32*)&data->mode);
1954         dev_set_name(dev, name);
1955
1956         if (pservice->reg_base == 0) {
1957                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1958                 data->regs = devm_ioremap_resource(dev, res);
1959                 if (IS_ERR(data->regs)) {
1960                         ret = PTR_ERR(data->regs);
1961                         goto err;
1962                 }
1963                 ioaddr = res->start;
1964         } else {
1965                 data->regs = pservice->reg_base;
1966                 ioaddr = pservice->ioaddr;
1967         }
1968
1969         clear_bit(MMU_ACTIVATED, &data->state);
1970         vcodec_enter_mode(data);
1971         ret = vpu_service_check_hw(data, ioaddr);
1972         if (ret < 0) {
1973                 vpu_err("error: hw info check faild\n");
1974                 goto err;
1975         }
1976
1977         data->dec_dev.iosize = data->hw_info->dec_io_size;
1978         data->dec_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->dec_offset);
1979         data->reg_size = data->dec_dev.iosize;
1980
1981         if (data->mode == VCODEC_RUNNING_MODE_VPU) {
1982                 data->enc_dev.iosize = data->hw_info->enc_io_size;
1983                 data->reg_size = data->reg_size > data->enc_dev.iosize ? data->reg_size : data->enc_dev.iosize;
1984                 data->enc_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->enc_offset);
1985         }
1986
1987         data->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
1988         if (data->irq_enc > 0) {
1989                 ret = devm_request_threaded_irq(dev,
1990                         data->irq_enc, vepu_irq, vepu_isr,
1991                         IRQF_SHARED, dev_name(dev),
1992                         (void *)data);
1993                 if (ret) {
1994                         dev_err(dev,
1995                                 "error: can't request vepu irq %d\n",
1996                                 data->irq_enc);
1997                         goto err;
1998                 }
1999         }
2000         data->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
2001         if (data->irq_dec > 0) {
2002                 ret = devm_request_threaded_irq(dev,
2003                         data->irq_dec, vdpu_irq, vdpu_isr,
2004                         IRQF_SHARED, dev_name(dev),
2005                         (void *)data);
2006                 if (ret) {
2007                         dev_err(dev,
2008                                 "error: can't request vdpu irq %d\n",
2009                                 data->irq_dec);
2010                         goto err;
2011                 }
2012         }
2013         atomic_set(&data->dec_dev.irq_count_codec, 0);
2014         atomic_set(&data->dec_dev.irq_count_pp, 0);
2015         atomic_set(&data->enc_dev.irq_count_codec, 0);
2016         atomic_set(&data->enc_dev.irq_count_pp, 0);
2017 #if defined(CONFIG_VCODEC_MMU)
2018         if (iommu_en) {
2019                 vcodec_enter_mode(data);
2020                 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
2021                         sprintf(mmu_dev_dts_name,
2022                                 HEVC_IOMMU_COMPATIBLE_NAME);
2023                 else
2024                         sprintf(mmu_dev_dts_name,
2025                                 VPU_IOMMU_COMPATIBLE_NAME);
2026
2027                 data->mmu_dev =
2028                         rockchip_get_sysmmu_dev(mmu_dev_dts_name);
2029
2030                 if (data->mmu_dev)
2031                         platform_set_sysmmu(data->mmu_dev, dev);
2032
2033                 rockchip_iovmm_set_fault_handler(dev, vcodec_sysmmu_fault_hdl);
2034         }
2035 #endif
2036         /* create device node */
2037         ret = alloc_chrdev_region(&data->dev_t, 0, 1, dev_name(dev));
2038         if (ret) {
2039                 dev_err(dev, "alloc dev_t failed\n");
2040                 goto err;
2041         }
2042
2043         cdev_init(&data->cdev, &vpu_service_fops);
2044
2045         data->cdev.owner = THIS_MODULE;
2046         data->cdev.ops = &vpu_service_fops;
2047
2048         ret = cdev_add(&data->cdev, data->dev_t, 1);
2049
2050         if (ret) {
2051                 dev_err(dev, "add dev_t failed\n");
2052                 goto err;
2053         }
2054
2055         data->cls = class_create(THIS_MODULE, dev_name(dev));
2056
2057         if (IS_ERR(data->cls)) {
2058                 ret = PTR_ERR(data->cls);
2059                 dev_err(dev, "class_create err:%d\n", ret);
2060                 goto err;
2061         }
2062
2063         data->child_dev = device_create(data->cls, dev,
2064                 data->dev_t, NULL, dev_name(dev));
2065
2066         get_hw_info(data);
2067
2068         platform_set_drvdata(pdev, data);
2069
2070         INIT_LIST_HEAD(&data->lnk_service);
2071         list_add_tail(&data->lnk_service, &pservice->subdev_list);
2072
2073 #ifdef CONFIG_DEBUG_FS
2074         data->debugfs_dir =
2075                 vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);
2076         if (data->debugfs_dir == NULL)
2077                 vpu_err("create debugfs dir %s failed\n", dev_name(dev));
2078
2079         data->debugfs_file_regs =
2080                 debugfs_create_file("regs", 0664,
2081                                     data->debugfs_dir, data,
2082                                     &debug_vcodec_fops);
2083 #endif
2084         return 0;
2085 err:
2086         if (data->irq_enc > 0)
2087                 free_irq(data->irq_enc, (void *)data);
2088         if (data->irq_dec > 0)
2089                 free_irq(data->irq_dec, (void *)data);
2090
2091         if (data->child_dev) {
2092                 device_destroy(data->cls, data->dev_t);
2093                 cdev_del(&data->cdev);
2094                 unregister_chrdev_region(data->dev_t, 1);
2095         }
2096
2097         if (data->cls)
2098                 class_destroy(data->cls);
2099         return -1;
2100 }
2101
2102 static void vcodec_subdev_remove(struct vpu_subdev_data *data)
2103 {
2104         device_destroy(data->cls, data->dev_t);
2105         class_destroy(data->cls);
2106         cdev_del(&data->cdev);
2107         unregister_chrdev_region(data->dev_t, 1);
2108
2109         free_irq(data->irq_enc, (void *)&data);
2110         free_irq(data->irq_dec, (void *)&data);
2111
2112 #ifdef CONFIG_DEBUG_FS
2113         debugfs_remove(data->debugfs_file_regs);
2114         debugfs_remove(data->debugfs_dir);
2115 #endif
2116 }
2117
2118 static void vcodec_read_property(struct device_node *np,
2119         struct vpu_service_info *pservice)
2120 {
2121         pservice->mode_bit = 0;
2122         pservice->mode_ctrl = 0;
2123         pservice->subcnt = 0;
2124
2125         of_property_read_u32(np, "subcnt", &pservice->subcnt);
2126
2127         if (pservice->subcnt > 1) {
2128                 of_property_read_u32(np, "mode_bit", &pservice->mode_bit);
2129                 of_property_read_u32(np, "mode_ctrl", &pservice->mode_ctrl);
2130         }
2131 #ifdef CONFIG_MFD_SYSCON
2132         pservice->grf_base = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
2133 #else
2134         pservice->grf_base = (u32*)RK_GRF_VIRT;
2135 #endif
2136         if (IS_ERR(pservice->grf_base)) {
2137                 vpu_err("can't find vpu grf property\n");
2138                 return;
2139         }
2140         of_property_read_string(np, "name", (const char**)&pservice->name);
2141 }
2142
2143 static void vcodec_init_drvdata(struct vpu_service_info *pservice)
2144 {
2145         pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2146         pservice->curr_mode = -1;
2147
2148         wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
2149         INIT_LIST_HEAD(&pservice->waiting);
2150         INIT_LIST_HEAD(&pservice->running);
2151         mutex_init(&pservice->lock);
2152
2153         INIT_LIST_HEAD(&pservice->done);
2154         INIT_LIST_HEAD(&pservice->session);
2155         INIT_LIST_HEAD(&pservice->subdev_list);
2156
2157         pservice->reg_pproc     = NULL;
2158         atomic_set(&pservice->total_running, 0);
2159         pservice->enabled = false;
2160
2161         INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
2162
2163         pservice->ion_client = rockchip_ion_client_create("vpu");
2164         if (IS_ERR(pservice->ion_client)) {
2165                 vpu_err("failed to create ion client for vcodec ret %ld\n",
2166                         PTR_ERR(pservice->ion_client));
2167         } else {
2168                 vpu_debug(3, "vcodec ion client create success!\n");
2169         }
2170 }
2171
2172 static int vcodec_probe(struct platform_device *pdev)
2173 {
2174         int i;
2175         int ret = 0;
2176         struct resource *res = NULL;
2177         struct device *dev = &pdev->dev;
2178         struct device_node *np = pdev->dev.of_node;
2179         struct vpu_service_info *pservice =
2180                 devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);
2181
2182         pr_info("probe device %s\n", dev_name(dev));
2183
2184         vcodec_read_property(np, pservice);
2185         vcodec_init_drvdata(pservice);
2186
2187         if (strncmp(pservice->name, "hevc_service", 12) == 0)
2188                 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
2189         else if (strncmp(pservice->name, "vpu_service", 11) == 0)
2190                 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2191         else
2192                 pservice->dev_id = VCODEC_DEVICE_ID_COMBO;
2193
2194         pservice->dev = dev;
2195
2196         if (0 > vpu_get_clk(pservice))
2197                 goto err;
2198
2199         vpu_service_power_on(pservice);
2200
2201         if (of_property_read_bool(np, "reg")) {
2202                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2203
2204                 pservice->reg_base = devm_ioremap_resource(pservice->dev, res);
2205                 if (IS_ERR(pservice->reg_base)) {
2206                         vpu_err("ioremap registers base failed\n");
2207                         ret = PTR_ERR(pservice->reg_base);
2208                         goto err;
2209                 }
2210                 pservice->ioaddr = res->start;
2211         } else {
2212                 pservice->reg_base = 0;
2213         }
2214
2215         if (of_property_read_bool(np, "subcnt")) {
2216                 for (i = 0; i<pservice->subcnt; i++) {
2217                         struct device_node *sub_np;
2218                         struct platform_device *sub_pdev;
2219                         sub_np = of_parse_phandle(np, "rockchip,sub", i);
2220                         sub_pdev = of_find_device_by_node(sub_np);
2221
2222                         vcodec_subdev_probe(sub_pdev, pservice);
2223                 }
2224         } else {
2225                 vcodec_subdev_probe(pdev, pservice);
2226         }
2227         platform_set_drvdata(pdev, pservice);
2228
2229         vpu_service_power_off(pservice);
2230
2231         pr_info("init success\n");
2232
2233         return 0;
2234
2235 err:
2236         pr_info("init failed\n");
2237         vpu_service_power_off(pservice);
2238         vpu_put_clk(pservice);
2239         wake_lock_destroy(&pservice->wake_lock);
2240
2241         if (res)
2242                 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2243
2244         return ret;
2245 }
2246
2247 static int vcodec_remove(struct platform_device *pdev)
2248 {
2249         struct vpu_service_info *pservice = platform_get_drvdata(pdev);
2250         struct resource *res;
2251         struct vpu_subdev_data *data, *n;
2252
2253         list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
2254                 vcodec_subdev_remove(data);
2255         }
2256
2257         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2258         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2259         vpu_put_clk(pservice);
2260         wake_lock_destroy(&pservice->wake_lock);
2261
2262         return 0;
2263 }
2264
2265 #if defined(CONFIG_OF)
2266 static const struct of_device_id vcodec_service_dt_ids[] = {
2267         {.compatible = "vpu_service",},
2268         {.compatible = "rockchip,hevc_service",},
2269         {.compatible = "rockchip,vpu_combo",},
2270         {},
2271 };
2272 #endif
2273
2274 static struct platform_driver vcodec_driver = {
2275         .probe = vcodec_probe,
2276         .remove = vcodec_remove,
2277         .driver = {
2278                 .name = "vcodec",
2279                 .owner = THIS_MODULE,
2280 #if defined(CONFIG_OF)
2281                 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
2282 #endif
2283         },
2284 };
2285
2286 static void get_hw_info(struct vpu_subdev_data *data)
2287 {
2288         struct vpu_service_info *pservice = data->pservice;
2289         struct vpu_dec_config *dec = &pservice->dec_config;
2290         struct vpu_enc_config *enc = &pservice->enc_config;
2291         if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2292                 u32 configReg   = data->dec_dev.hwregs[VPU_DEC_HWCFG0];
2293                 u32 asicID      = data->dec_dev.hwregs[0];
2294
2295                 dec->h264_support    = (configReg >> DWL_H264_E) & 0x3U;
2296                 dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;
2297                 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
2298                         dec->jpegSupport = JPEG_PROGRESSIVE;
2299                 dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;
2300                 dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;
2301                 dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;
2302                 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
2303                 dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;
2304                 dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;
2305
2306                 dec->maxDecPicWidth = 4096;
2307
2308                 /* 2nd Config register */
2309                 configReg   = data->dec_dev.hwregs[VPU_DEC_HWCFG1];
2310                 if (dec->refBufSupport) {
2311                         if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
2312                                 dec->refBufSupport |= 2;
2313                         if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
2314                                 dec->refBufSupport |= 4;
2315                 }
2316                 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
2317                 dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;
2318                 dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;
2319                 dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;
2320
2321                 /* JPEG xtensions */
2322                 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))
2323                         dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
2324                 else
2325                         dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
2326
2327                 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) )
2328                         dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
2329                 else
2330                         dec->rvSupport = RV_NOT_SUPPORTED;
2331                 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
2332
2333                 if (dec->refBufSupport && (asicID >> 16) == 0x6731U )
2334                         dec->refBufSupport |= 8; /* enable HW support for offset */
2335
2336                 if (!cpu_is_rk3036()) {
2337                         configReg = data->enc_dev.hwregs[63];
2338                         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
2339                         enc->h264Enabled = (configReg >> 27) & 1;
2340                         enc->mpeg4Enabled = (configReg >> 26) & 1;
2341                         enc->jpegEnabled = (configReg >> 25) & 1;
2342                         enc->vsEnabled = (configReg >> 24) & 1;
2343                         enc->rgbEnabled = (configReg >> 28) & 1;
2344                         enc->reg_size = data->reg_size;
2345                         enc->reserv[0] = enc->reserv[1] = 0;
2346                 }
2347                 pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926() || soc_is_rk3288();
2348                 if (pservice->auto_freq) {
2349                         vpu_debug(3, "vpu_service set to auto frequency mode\n");
2350                         atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2351                 }
2352
2353                 pservice->bug_dec_addr = cpu_is_rk30xx();
2354         } else {
2355                 if (cpu_is_rk3036()  || cpu_is_rk312x())
2356                         dec->maxDecPicWidth = 1920;
2357                 else
2358                         dec->maxDecPicWidth = 4096;
2359                 /* disable frequency switch in hevc.*/
2360                 pservice->auto_freq = false;
2361         }
2362 }
2363
2364 static irqreturn_t vdpu_irq(int irq, void *dev_id)
2365 {
2366         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2367         struct vpu_service_info *pservice = data->pservice;
2368         vpu_device *dev = &data->dec_dev;
2369         u32 raw_status;
2370         u32 irq_status;
2371
2372         vcodec_enter_mode(data);
2373
2374         irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2375
2376         vpu_debug(3, "%s status %08x\n", __func__, raw_status);
2377
2378         if (irq_status & DEC_INTERRUPT_BIT) {
2379                 pr_debug("dec_isr dec %x\n", irq_status);
2380                 if ((irq_status & 0x40001) == 0x40001) {
2381                         do {
2382                                 irq_status =
2383                                         readl(dev->hwregs +
2384                                                 DEC_INTERRUPT_REGISTER);
2385                         } while ((irq_status & 0x40001) == 0x40001);
2386                 }
2387
2388                 writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);
2389                 atomic_add(1, &dev->irq_count_codec);
2390         }
2391
2392         if (data->hw_info->hw_id != HEVC_ID) {
2393                 irq_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
2394                 if (irq_status & PP_INTERRUPT_BIT) {
2395                         pr_debug("vdpu_isr pp  %x\n", irq_status);
2396                         /* clear pp IRQ */
2397                         writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
2398                         atomic_add(1, &dev->irq_count_pp);
2399                 }
2400         }
2401
2402         pservice->irq_status = raw_status;
2403
2404         vcodec_exit_mode(pservice);
2405
2406         return IRQ_WAKE_THREAD;
2407 }
2408
2409 static irqreturn_t vdpu_isr(int irq, void *dev_id)
2410 {
2411         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2412         struct vpu_service_info *pservice = data->pservice;
2413         vpu_device *dev = &data->dec_dev;
2414
2415         mutex_lock(&pservice->lock);
2416         if (atomic_read(&dev->irq_count_codec)) {
2417 #if VPU_SERVICE_SHOW_TIME
2418                 do_gettimeofday(&dec_end);
2419                 vpu_debug(3, "dec task: %ld ms\n",
2420                         (dec_end.tv_sec  - dec_start.tv_sec)  * 1000 +
2421                         (dec_end.tv_usec - dec_start.tv_usec) / 1000);
2422 #endif
2423                 atomic_sub(1, &dev->irq_count_codec);
2424                 if (NULL == pservice->reg_codec) {
2425                         vpu_err("error: dec isr with no task waiting\n");
2426                 } else {
2427                         reg_from_run_to_done(data, pservice->reg_codec);
2428                 }
2429         }
2430
2431         if (atomic_read(&dev->irq_count_pp)) {
2432 #if VPU_SERVICE_SHOW_TIME
2433                 do_gettimeofday(&pp_end);
2434                 printk("pp  task: %ld ms\n",
2435                         (pp_end.tv_sec  - pp_start.tv_sec)  * 1000 +
2436                         (pp_end.tv_usec - pp_start.tv_usec) / 1000);
2437 #endif
2438                 atomic_sub(1, &dev->irq_count_pp);
2439                 if (NULL == pservice->reg_pproc) {
2440                         vpu_err("error: pp isr with no task waiting\n");
2441                 } else {
2442                         reg_from_run_to_done(data, pservice->reg_pproc);
2443                 }
2444         }
2445         try_set_reg(data);
2446         mutex_unlock(&pservice->lock);
2447         return IRQ_HANDLED;
2448 }
2449
2450 static irqreturn_t vepu_irq(int irq, void *dev_id)
2451 {
2452         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2453         struct vpu_service_info *pservice = data->pservice;
2454         vpu_device *dev = &data->enc_dev;
2455         u32 irq_status;
2456
2457         vcodec_enter_mode(data);
2458         irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
2459
2460         pr_debug("vepu_irq irq status %x\n", irq_status);
2461
2462 #if VPU_SERVICE_SHOW_TIME
2463         do_gettimeofday(&enc_end);
2464         vpu_debug(3, "enc task: %ld ms\n",
2465                 (enc_end.tv_sec  - enc_start.tv_sec)  * 1000 +
2466                 (enc_end.tv_usec - enc_start.tv_usec) / 1000);
2467 #endif
2468         if (likely(irq_status & ENC_INTERRUPT_BIT)) {
2469                 /* clear enc IRQ */
2470                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
2471                 atomic_add(1, &dev->irq_count_codec);
2472         }
2473
2474         pservice->irq_status = irq_status;
2475
2476         vcodec_exit_mode(pservice);
2477
2478         return IRQ_WAKE_THREAD;
2479 }
2480
2481 static irqreturn_t vepu_isr(int irq, void *dev_id)
2482 {
2483         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2484         struct vpu_service_info *pservice = data->pservice;
2485         vpu_device *dev = &data->enc_dev;
2486
2487         mutex_lock(&pservice->lock);
2488         if (atomic_read(&dev->irq_count_codec)) {
2489                 atomic_sub(1, &dev->irq_count_codec);
2490                 if (NULL == pservice->reg_codec) {
2491                         vpu_err("error: enc isr with no task waiting\n");
2492                 } else {
2493                         reg_from_run_to_done(data, pservice->reg_codec);
2494                 }
2495         }
2496         try_set_reg(data);
2497         mutex_unlock(&pservice->lock);
2498         return IRQ_HANDLED;
2499 }
2500
2501 static int __init vcodec_service_init(void)
2502 {
2503         int ret;
2504
2505         if ((ret = platform_driver_register(&vcodec_driver)) != 0) {
2506                 vpu_err("Platform device register failed (%d).\n", ret);
2507                 return ret;
2508         }
2509
2510 #ifdef CONFIG_DEBUG_FS
2511         vcodec_debugfs_init();
2512 #endif
2513
2514         return ret;
2515 }
2516
2517 static void __exit vcodec_service_exit(void)
2518 {
2519 #ifdef CONFIG_DEBUG_FS
2520         vcodec_debugfs_exit();
2521 #endif
2522
2523         platform_driver_unregister(&vcodec_driver);
2524 }
2525
2526 module_init(vcodec_service_init);
2527 module_exit(vcodec_service_exit);
2528
2529 #ifdef CONFIG_DEBUG_FS
2530 #include <linux/seq_file.h>
2531
2532 static int vcodec_debugfs_init()
2533 {
2534         parent = debugfs_create_dir("vcodec", NULL);
2535         if (!parent)
2536                 return -1;
2537
2538         return 0;
2539 }
2540
2541 static void vcodec_debugfs_exit()
2542 {
2543         debugfs_remove(parent);
2544 }
2545
2546 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)
2547 {
2548         return debugfs_create_dir(dirname, parent);
2549 }
2550
2551 static int debug_vcodec_show(struct seq_file *s, void *unused)
2552 {
2553         struct vpu_subdev_data *data = s->private;
2554         struct vpu_service_info *pservice = data->pservice;
2555         unsigned int i, n;
2556         vpu_reg *reg, *reg_tmp;
2557         vpu_session *session, *session_tmp;
2558
2559         mutex_lock(&pservice->lock);
2560         vpu_service_power_on(pservice);
2561         if (data->hw_info->hw_id != HEVC_ID) {
2562                 seq_printf(s, "\nENC Registers:\n");
2563                 n = data->enc_dev.iosize >> 2;
2564                 for (i = 0; i < n; i++)
2565                         seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->enc_dev.hwregs + i));
2566         }
2567         seq_printf(s, "\nDEC Registers:\n");
2568         n = data->dec_dev.iosize >> 2;
2569         for (i = 0; i < n; i++)
2570                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2571
2572         seq_printf(s, "\nvpu service status:\n");
2573         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
2574                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
2575                 /*seq_printf(s, "waiting reg set %d\n");*/
2576                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
2577                         seq_printf(s, "waiting register set\n");
2578                 }
2579                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
2580                         seq_printf(s, "running register set\n");
2581                 }
2582                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
2583                         seq_printf(s, "done    register set\n");
2584                 }
2585         }
2586         mutex_unlock(&pservice->lock);
2587
2588         return 0;
2589 }
2590
2591 static int debug_vcodec_open(struct inode *inode, struct file *file)
2592 {
2593         return single_open(file, debug_vcodec_show, inode->i_private);
2594 }
2595
2596 #endif
2597
2598 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)
2599 #include "hevc_test_inc/pps_00.h"
2600 #include "hevc_test_inc/register_00.h"
2601 #include "hevc_test_inc/rps_00.h"
2602 #include "hevc_test_inc/scaling_list_00.h"
2603 #include "hevc_test_inc/stream_00.h"
2604
2605 #include "hevc_test_inc/pps_01.h"
2606 #include "hevc_test_inc/register_01.h"
2607 #include "hevc_test_inc/rps_01.h"
2608 #include "hevc_test_inc/scaling_list_01.h"
2609 #include "hevc_test_inc/stream_01.h"
2610
2611 #include "hevc_test_inc/cabac.h"
2612
2613 extern struct ion_client *rockchip_ion_client_create(const char * name);
2614
2615 static struct ion_client *ion_client = NULL;
2616 u8* get_align_ptr(u8* tbl, int len, u32 *phy)
2617 {
2618         int size = (len+15) & (~15);
2619         struct ion_handle *handle;
2620         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);
2621
2622         if (ion_client == NULL)
2623                 ion_client = rockchip_ion_client_create("vcodec");
2624
2625         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2626
2627         ptr = ion_map_kernel(ion_client, handle);
2628
2629         ion_phys(ion_client, handle, phy, &size);
2630
2631         memcpy(ptr, tbl, len);
2632
2633         return ptr;
2634 }
2635
2636 u8* get_align_ptr_no_copy(int len, u32 *phy)
2637 {
2638         int size = (len+15) & (~15);
2639         struct ion_handle *handle;
2640         u8 *ptr;
2641
2642         if (ion_client == NULL)
2643                 ion_client = rockchip_ion_client_create("vcodec");
2644
2645         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2646
2647         ptr = ion_map_kernel(ion_client, handle);
2648
2649         ion_phys(ion_client, handle, phy, &size);
2650
2651         return ptr;
2652 }
2653
2654 #define TEST_CNT    2
2655 static int hevc_test_case0(vpu_service_info *pservice)
2656 {
2657         vpu_session session;
2658         vpu_reg *reg;
2659         unsigned long size = 272;//sizeof(register_00); // registers array length
2660         int testidx = 0;
2661         int ret = 0;
2662         u8 *pps_tbl[TEST_CNT];
2663         u8 *register_tbl[TEST_CNT];
2664         u8 *rps_tbl[TEST_CNT];
2665         u8 *scaling_list_tbl[TEST_CNT];
2666         u8 *stream_tbl[TEST_CNT];
2667
2668         int stream_size[2];
2669         int pps_size[2];
2670         int rps_size[2];
2671         int scl_size[2];
2672         int cabac_size[2];
2673
2674         u32 phy_pps;
2675         u32 phy_rps;
2676         u32 phy_scl;
2677         u32 phy_str;
2678         u32 phy_yuv;
2679         u32 phy_ref;
2680         u32 phy_cabac;
2681
2682         volatile u8 *stream_buf;
2683         volatile u8 *pps_buf;
2684         volatile u8 *rps_buf;
2685         volatile u8 *scl_buf;
2686         volatile u8 *yuv_buf;
2687         volatile u8 *cabac_buf;
2688         volatile u8 *ref_buf;
2689
2690         u8 *pps;
2691         u8 *yuv[2];
2692         int i;
2693
2694         pps_tbl[0] = pps_00;
2695         pps_tbl[1] = pps_01;
2696
2697         register_tbl[0] = register_00;
2698         register_tbl[1] = register_01;
2699
2700         rps_tbl[0] = rps_00;
2701         rps_tbl[1] = rps_01;
2702
2703         scaling_list_tbl[0] = scaling_list_00;
2704         scaling_list_tbl[1] = scaling_list_01;
2705
2706         stream_tbl[0] = stream_00;
2707         stream_tbl[1] = stream_01;
2708
2709         stream_size[0] = sizeof(stream_00);
2710         stream_size[1] = sizeof(stream_01);
2711
2712         pps_size[0] = sizeof(pps_00);
2713         pps_size[1] = sizeof(pps_01);
2714
2715         rps_size[0] = sizeof(rps_00);
2716         rps_size[1] = sizeof(rps_01);
2717
2718         scl_size[0] = sizeof(scaling_list_00);
2719         scl_size[1] = sizeof(scaling_list_01);
2720
2721         cabac_size[0] = sizeof(Cabac_table);
2722         cabac_size[1] = sizeof(Cabac_table);
2723
2724         /* create session */
2725         session.pid = current->pid;
2726         session.type = VPU_DEC;
2727         INIT_LIST_HEAD(&session.waiting);
2728         INIT_LIST_HEAD(&session.running);
2729         INIT_LIST_HEAD(&session.done);
2730         INIT_LIST_HEAD(&session.list_session);
2731         init_waitqueue_head(&session.wait);
2732         atomic_set(&session.task_running, 0);
2733         list_add_tail(&session.list_session, &pservice->session);
2734
2735         yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);
2736         yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);
2737
2738         while (testidx < TEST_CNT) {
2739                 /* create registers */
2740                 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
2741                 if (NULL == reg) {
2742                         vpu_err("error: kmalloc fail in reg_init\n");
2743                         return -1;
2744                 }
2745
2746                 if (size > pservice->reg_size) {
2747                         printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
2748                         size = pservice->reg_size;
2749                 }
2750                 reg->session = &session;
2751                 reg->type = session.type;
2752                 reg->size = size;
2753                 reg->freq = VPU_FREQ_DEFAULT;
2754                 reg->reg = (unsigned long *)&reg[1];
2755                 INIT_LIST_HEAD(&reg->session_link);
2756                 INIT_LIST_HEAD(&reg->status_link);
2757
2758                 /* TODO: stuff registers */
2759                 memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);
2760
2761                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);
2762                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);
2763                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);
2764                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);
2765                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);
2766
2767                 pps = pps_buf;
2768
2769                 /* TODO: replace reigster address */
2770                 for (i=0; i<64; i++) {
2771                         u32 scaling_offset;
2772                         u32 tmp;
2773
2774                         scaling_offset = (u32)pps[i*80+74];
2775                         scaling_offset += (u32)pps[i*80+75] << 8;
2776                         scaling_offset += (u32)pps[i*80+76] << 16;
2777                         scaling_offset += (u32)pps[i*80+77] << 24;
2778
2779                         tmp = phy_scl + scaling_offset;
2780
2781                         pps[i*80+74] = tmp & 0xff;
2782                         pps[i*80+75] = (tmp >> 8) & 0xff;
2783                         pps[i*80+76] = (tmp >> 16) & 0xff;
2784                         pps[i*80+77] = (tmp >> 24) & 0xff;
2785                 }
2786
2787                 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n",
2788                         __func__, __LINE__, phy_str, phy_pps, phy_rps);
2789
2790                 reg->reg[1] = 0x21;
2791                 reg->reg[4] = phy_str;
2792                 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;
2793                 reg->reg[6] = phy_cabac;
2794                 reg->reg[7] = testidx?phy_ref:phy_yuv;
2795                 reg->reg[42] = phy_pps;
2796                 reg->reg[43] = phy_rps;
2797                 for (i = 10; i <= 24; i++)
2798                         reg->reg[i] = phy_yuv;
2799
2800                 mutex_lock(pservice->lock);
2801                 list_add_tail(&reg->status_link, &pservice->waiting);
2802                 list_add_tail(&reg->session_link, &session.waiting);
2803                 mutex_unlock(pservice->lock);
2804
2805                 /* stuff hardware */
2806                 try_set_reg(data);
2807
2808                 /* wait for result */
2809                 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);
2810                 if (!list_empty(&session.done)) {
2811                         if (ret < 0)
2812                                 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);
2813                         ret = 0;
2814                 } else {
2815                         if (unlikely(ret < 0)) {
2816                                 vpu_err("error: pid %d wait task ret %d\n", session.pid, ret);
2817                         } else if (0 == ret) {
2818                                 vpu_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));
2819                                 ret = -ETIMEDOUT;
2820                         }
2821                 }
2822                 if (ret < 0) {
2823                         int task_running = atomic_read(&session.task_running);
2824                         int n;
2825                         mutex_lock(pservice->lock);
2826                         vpu_service_dump(pservice);
2827                         if (task_running) {
2828                                 atomic_set(&session.task_running, 0);
2829                                 atomic_sub(task_running, &pservice->total_running);
2830                                 printk("%d task is running but not return, reset hardware...", task_running);
2831                                 vpu_reset(data);
2832                                 printk("done\n");
2833                         }
2834                         vpu_service_session_clear(pservice, &session);
2835                         mutex_unlock(pservice->lock);
2836
2837                         printk("\nDEC Registers:\n");
2838                         n = data->dec_dev.iosize >> 2;
2839                         for (i=0; i<n; i++)
2840                                 printk("\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2841
2842                         vpu_err("test index %d failed\n", testidx);
2843                         break;
2844                 } else {
2845                         vpu_debug(3, "test index %d success\n", testidx);
2846
2847                         vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);
2848
2849                         for (i=0; i<68; i++) {
2850                                 if (i % 4 == 0)
2851                                         printk("%02d: ", i);
2852                                 printk("%08x ", reg->reg[i]);
2853                                 if ((i+1) % 4 == 0)
2854                                         printk("\n");
2855                         }
2856
2857                         testidx++;
2858                 }
2859
2860                 reg_deinit(data, reg);
2861         }
2862
2863         return 0;
2864 }
2865
2866 #endif
2867