arch/arm/mach-rockchip/rk_fiq_debugger.c

   1 /*
   2  * arch/arm/plat-rk/rk_fiq_debugger.c
   3  *
   4  * Serial Debugger Interface for Rockchip
   5  *
   6  * Copyright (C) 2012 ROCKCHIP, Inc.
   7  * Copyright (C) 2008 Google, Inc.
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <stdarg.h>
  20 #include <linux/module.h>
  21 #include <linux/io.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/clk.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/irq.h>
  29 #include <linux/serial_reg.h>
  30 #include <linux/slab.h>
  31 #include <linux/stacktrace.h>
  32 #include <linux/uaccess.h>
  33 #include <linux/kfifo.h>
  34 #include <linux/kthread.h>
  35 #include <linux/sched/rt.h>
  36 #include <../drivers/staging/android/fiq_debugger/fiq_debugger.h>
  37 #include <linux/irqchip/arm-gic.h>
  38 #include <linux/clk.h>
  39 #include "rk_fiq_debugger.h"
  40
  41 #ifdef CONFIG_FIQ_DEBUGGER_EL3_TO_EL1
  42 #include "linux/rockchip/psci.h"
  43 #endif
  44
  45 #define UART_USR        0x1f    /* In: UART Status Register */
  46 #define UART_USR_RX_FIFO_FULL           0x10 /* Receive FIFO full */
  47 #define UART_USR_RX_FIFO_NOT_EMPTY      0x08 /* Receive FIFO not empty */
  48 #define UART_USR_TX_FIFO_EMPTY          0x04 /* Transmit FIFO empty */
  49 #define UART_USR_TX_FIFO_NOT_FULL       0x02 /* Transmit FIFO not full */
  50 #define UART_USR_BUSY                   0x01 /* UART busy indicator */
  51
  52 struct rk_fiq_debugger {
  53         int irq;
  54         int baudrate;
  55         struct fiq_debugger_pdata pdata;
  56         void __iomem *debug_port_base;
  57         bool break_seen;
  58 #ifdef CONFIG_RK_CONSOLE_THREAD
  59         struct task_struct *console_task;
  60 #endif
  61 };
  62
  63 static inline void rk_fiq_write(struct rk_fiq_debugger *t,
  64         unsigned int val, unsigned int off)
  65 {
  66         __raw_writel(val, t->debug_port_base + off * 4);
  67 }
  68
  69 static inline unsigned int rk_fiq_read(struct rk_fiq_debugger *t,
  70         unsigned int off)
  71 {
  72         return __raw_readl(t->debug_port_base + off * 4);
  73 }
  74
  75 static inline unsigned int rk_fiq_read_lsr(struct rk_fiq_debugger *t)
  76 {
  77         unsigned int lsr;
  78
  79         lsr = rk_fiq_read(t, UART_LSR);
  80         if (lsr & UART_LSR_BI)
  81                 t->break_seen = true;
  82
  83         return lsr;
  84 }
  85
  86 static int debug_port_init(struct platform_device *pdev)
  87 {
  88         int dll = 0, dlm = 0;
  89         struct rk_fiq_debugger *t;
  90
  91         t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
  92
  93         if (rk_fiq_read(t, UART_LSR) & UART_LSR_DR)
  94                 (void)rk_fiq_read(t, UART_RX);
  95
  96         switch (t->baudrate) {
  97         case 1500000:
  98                 dll = 0x1;
  99                 break;
 100         case 115200:
 101         default:
 102                 dll = 0xd;
 103                 break;
 104         }
 105
 106         rk_fiq_write(t, 0x83, UART_LCR);
 107         /* set baud rate */
 108         rk_fiq_write(t, dll, UART_DLL);
 109         rk_fiq_write(t, dlm, UART_DLM);
 110         rk_fiq_write(t, 0x03, UART_LCR);
 111
 112         /* enable rx and lsr interrupt */
 113         rk_fiq_write(t, UART_IER_RLSI | UART_IER_RDI, UART_IER);
 114         /* interrupt on every character when receive,but we can enable fifo for TX
 115         I found that if we enable the RX fifo, some problem may vanish such as when
 116         you continuously input characters in the command line the uart irq may be disable
 117         because of the uart irq is served when CPU is at IRQ exception,but it is
 118         found unregistered, so it is disable.
 119         hhb@rock-chips.com */
 120         rk_fiq_write(t, 0xc1, UART_FCR);
 121
 122         return 0;
 123 }
 124
 125 static int debug_getc(struct platform_device *pdev)
 126 {
 127         unsigned int lsr;
 128         struct rk_fiq_debugger *t;
 129         unsigned int temp;
 130         static unsigned int n;
 131         static char buf[32];
 132
 133         t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
 134
 135         lsr = rk_fiq_read_lsr(t);
 136
 137         if (lsr & UART_LSR_BI || t->break_seen) {
 138                 t->break_seen = false;
 139                 return FIQ_DEBUGGER_NO_CHAR;
 140         }
 141
 142         if (lsr & UART_LSR_DR) {
 143                 temp = rk_fiq_read(t, UART_RX);
 144                 buf[n & 0x1f] = temp;
 145                 n++;
 146                 if (temp == 'q' && n > 2) {
 147                         if ((buf[(n - 2) & 0x1f] == 'i') &&
 148                             (buf[(n - 3) & 0x1f] == 'f'))
 149                                 return FIQ_DEBUGGER_BREAK;
 150                         else
 151                                 return temp;
 152                 } else {
 153                         return temp;
 154                 }
 155         }
 156
 157         return FIQ_DEBUGGER_NO_CHAR;
 158 }
 159
 160 static void debug_putc(struct platform_device *pdev, unsigned int c)
 161 {
 162         struct rk_fiq_debugger *t;
 163
 164         t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
 165
 166         while (!(rk_fiq_read(t, UART_USR) & UART_USR_TX_FIFO_NOT_FULL))
 167                 cpu_relax();
 168         rk_fiq_write(t, c, UART_TX);
 169 }
 170
 171 static void debug_flush(struct platform_device *pdev)
 172 {
 173         struct rk_fiq_debugger *t;
 174         t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
 175
 176         while (!(rk_fiq_read_lsr(t) & UART_LSR_TEMT))
 177                 cpu_relax();
 178 }
 179
 180 #ifdef CONFIG_RK_CONSOLE_THREAD
 181 #define FIFO_SIZE SZ_64K
 182 static DEFINE_KFIFO(fifo, unsigned char, FIFO_SIZE);
 183 static bool console_thread_stop;
 184
 185 static int console_thread(void *data)
 186 {
 187         struct platform_device *pdev = data;
 188         struct rk_fiq_debugger *t;
 189         unsigned char c;
 190         t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
 191
 192         while (1) {
 193                 set_current_state(TASK_INTERRUPTIBLE);
 194                 schedule();
 195                 if (kthread_should_stop())
 196                         break;
 197                 set_current_state(TASK_RUNNING);
 198                 while (!console_thread_stop && kfifo_get(&fifo, &c))
 199                         debug_putc(pdev, c);
 200                 if (!console_thread_stop)
 201                         debug_flush(pdev);
 202         }
 203
 204         return 0;
 205 }
 206
 207 static void console_write(struct platform_device *pdev, const char *s, unsigned int count)
 208 {
 209         unsigned int fifo_count = FIFO_SIZE;
 210         unsigned char c, r = '\r';
 211         struct rk_fiq_debugger *t;
 212         t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
 213
 214         if (console_thread_stop ||
 215             oops_in_progress ||
 216             system_state == SYSTEM_HALT ||
 217             system_state == SYSTEM_POWER_OFF ||
 218             system_state == SYSTEM_RESTART) {
 219                 if (!console_thread_stop) {
 220                         console_thread_stop = true;
 221                         smp_wmb();
 222                         debug_flush(pdev);
 223                         while (fifo_count-- && kfifo_get(&fifo, &c))
 224                                 debug_putc(pdev, c);
 225                 }
 226                 while (count--) {
 227                         if (*s == '\n') {
 228                                 debug_putc(pdev, r);
 229                         }
 230                         debug_putc(pdev, *s++);
 231                 }
 232                 debug_flush(pdev);
 233         } else {
 234                 while (count--) {
 235                         if (*s == '\n') {
 236                                 kfifo_put(&fifo, &r);
 237                         }
 238                         kfifo_put(&fifo, s++);
 239                 }
 240                 wake_up_process(t->console_task);
 241         }
 242 }
 243 #endif
 244
 245
 246 static void fiq_enable(struct platform_device *pdev, unsigned int irq, bool on)
 247 {
 248         if (on)
 249                 enable_irq(irq);
 250         else
 251                 disable_irq(irq);
 252 }
 253
 254 #ifdef CONFIG_FIQ_DEBUGGER_EL3_TO_EL1
 255 static struct pt_regs fiq_pt_regs;
 256
 257 static void rk_fiq_debugger_switch_cpu(struct platform_device *pdev,
 258                                        unsigned int cpu)
 259 {
 260         psci_fiq_debugger_switch_cpu(cpu);
 261 }
 262
 263 static void rk_fiq_debugger_enable_debug(struct platform_device *pdev, bool val)
 264 {
 265         psci_fiq_debugger_enable_debug(val);
 266 }
 267
 268 static void fiq_debugger_uart_irq_tf(void *reg_base, u64 sp_el1)
 269 {
 270         memcpy(&fiq_pt_regs, reg_base, 8*31);
 271
 272         memcpy(&fiq_pt_regs.pstate, reg_base + 0x110, 8);
 273         if (fiq_pt_regs.pstate & 0x10)
 274                 memcpy(&fiq_pt_regs.sp, reg_base + 0xf8, 8);
 275         else
 276                 fiq_pt_regs.sp = sp_el1;
 277
 278         memcpy(&fiq_pt_regs.pc, reg_base + 0x118, 8);
 279
 280         fiq_debugger_fiq(&fiq_pt_regs);
 281 }
 282
 283 static int fiq_debugger_uart_dev_resume(struct platform_device *pdev)
 284 {
 285         struct rk_fiq_debugger *t;
 286
 287         t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
 288         psci_fiq_debugger_uart_irq_tf_init(t->irq, fiq_debugger_uart_irq_tf);
 289         return 0;
 290 }
 291 #endif
 292
 293 static int rk_fiq_debugger_id;
 294
 295 void rk_serial_debug_init(void __iomem *base, int irq, int signal_irq,
 296                           int wakeup_irq, unsigned int baudrate)
 297 {
 298         struct rk_fiq_debugger *t = NULL;
 299         struct platform_device *pdev = NULL;
 300         struct resource *res = NULL;
 301         int res_count = 0;
 302 #ifdef CONFIG_FIQ_DEBUGGER_EL3_TO_EL1
 303         /* tf means trust firmware*/
 304         int tf_ver = 0;
 305         bool tf_fiq_sup = false;
 306 #endif
 307
 308         if (!base) {
 309                 pr_err("Invalid fiq debugger uart base\n");
 310                 return;
 311         }
 312
 313         t = kzalloc(sizeof(struct rk_fiq_debugger), GFP_KERNEL);
 314         if (!t) {
 315                 pr_err("Failed to allocate for fiq debugger\n");
 316                 return;
 317         }
 318
 319         t->irq = irq;
 320         t->baudrate = baudrate;
 321         t->pdata.uart_init = debug_port_init;
 322         t->pdata.uart_getc = debug_getc;
 323         t->pdata.uart_putc = debug_putc;
 324 #ifndef CONFIG_RK_CONSOLE_THREAD
 325         t->pdata.uart_flush = debug_flush;
 326 #endif
 327         t->pdata.fiq_enable = fiq_enable;
 328         t->pdata.force_irq = NULL;  //force_irq;
 329         t->debug_port_base = base;
 330
 331         res = kzalloc(sizeof(struct resource) * 3, GFP_KERNEL);
 332         if (!res) {
 333                 pr_err("Failed to alloc fiq debugger resources\n");
 334                 goto out2;
 335         }
 336
 337         pdev = kzalloc(sizeof(struct platform_device), GFP_KERNEL);
 338         if (!pdev) {
 339                 pr_err("Failed to alloc fiq debugger platform device\n");
 340                 goto out3;
 341         };
 342
 343 #ifdef CONFIG_FIQ_DEBUGGER_EL3_TO_EL1
 344         tf_ver = rockchip_psci_smc_get_tf_ver();
 345
 346         if (tf_ver >= 0x00010005)
 347                 tf_fiq_sup = true;
 348         else
 349                 tf_fiq_sup = false;
 350
 351         if (tf_fiq_sup && (signal_irq > 0)) {
 352                 t->pdata.switch_cpu = rk_fiq_debugger_switch_cpu;
 353                 t->pdata.enable_debug = rk_fiq_debugger_enable_debug;
 354                 t->pdata.uart_dev_resume = fiq_debugger_uart_dev_resume;
 355                 psci_fiq_debugger_uart_irq_tf_init(irq,
 356                                                    fiq_debugger_uart_irq_tf);
 357         } else {
 358                 t->pdata.switch_cpu = NULL;
 359                 t->pdata.enable_debug = NULL;
 360         }
 361 #endif
 362
 363         if (irq > 0) {
 364                 res[0].flags = IORESOURCE_IRQ;
 365                 res[0].start = irq;
 366                 res[0].end = irq;
 367 #if defined(CONFIG_FIQ_GLUE)
 368                 if (signal_irq > 0)
 369                         res[0].name = "fiq";
 370                 else
 371                         res[0].name = "uart_irq";
 372 #elif defined(CONFIG_FIQ_DEBUGGER_EL3_TO_EL1)
 373                 if (tf_fiq_sup && (signal_irq > 0))
 374                         res[0].name = "fiq";
 375                 else
 376                         res[0].name = "uart_irq";
 377 #else
 378                 res[0].name = "uart_irq";
 379 #endif
 380                 res_count++;
 381         }
 382
 383         if (signal_irq > 0) {
 384                 res[1].flags = IORESOURCE_IRQ;
 385                 res[1].start = signal_irq;
 386                 res[1].end = signal_irq;
 387                 res[1].name = "signal";
 388                 res_count++;
 389         }
 390
 391         if (wakeup_irq > 0) {
 392                 res[2].flags = IORESOURCE_IRQ;
 393                 res[2].start = wakeup_irq;
 394                 res[2].end = wakeup_irq;
 395                 res[2].name = "wakeup";
 396                 res_count++;
 397         }
 398
 399 #ifdef CONFIG_RK_CONSOLE_THREAD
 400         t->console_task = kthread_create(console_thread, pdev, "kconsole");
 401         if (!IS_ERR(t->console_task))
 402                 t->pdata.console_write = console_write;
 403 #endif
 404
 405         pdev->name = "fiq_debugger";
 406         pdev->id = rk_fiq_debugger_id++;
 407         pdev->dev.platform_data = &t->pdata;
 408         pdev->resource = res;
 409         pdev->num_resources = res_count;
 410         if (platform_device_register(pdev)) {
 411                 pr_err("Failed to register fiq debugger\n");
 412                 goto out4;
 413         }
 414         return;
 415
 416 out4:
 417         kfree(pdev);
 418 out3:
 419         kfree(res);
 420 out2:
 421         kfree(t);
 422 }
 423
 424 static const struct of_device_id ids[] __initconst = {
 425         { .compatible = "rockchip,fiq-debugger" },
 426         {}
 427 };
 428
 429 static int __init rk_fiq_debugger_init(void) {
 430
 431         void __iomem *base;
 432         struct device_node *np;
 433         unsigned int i, id, serial_id, ok = 0;
 434         unsigned int irq, signal_irq = 0, wake_irq = 0;
 435         unsigned int baudrate = 0, irq_mode = 0;
 436         struct clk *clk;
 437         struct clk *pclk;
 438
 439         np = of_find_matching_node(NULL, ids);
 440
 441         if (!np) {
 442                 pr_err("fiq-debugger is missing in device tree!\n");
 443                 return -ENODEV;
 444         }
 445
 446         if (!of_device_is_available(np)) {
 447                 pr_err("fiq-debugger is disabled in device tree\n");
 448                 return -ENODEV;
 449         }
 450
 451         if (of_property_read_u32(np, "rockchip,serial-id", &serial_id))
 452                 return -EINVAL;
 453
 454         if (of_property_read_u32(np, "rockchip,irq-mode-enable", &irq_mode))
 455                 irq_mode = -1;
 456
 457         if (irq_mode == 1)
 458                 signal_irq = -1;
 459         else if (of_property_read_u32(np, "rockchip,signal-irq", &signal_irq))
 460                         signal_irq = -1;
 461
 462         if (of_property_read_u32(np, "rockchip,wake-irq", &wake_irq))
 463                 wake_irq = -1;
 464
 465         if (of_property_read_u32(np, "rockchip,baudrate", &baudrate))
 466                 baudrate = -1;
 467
 468         np = NULL;
 469         for (i = 0; i < 5; i++) {
 470                 np = of_find_node_by_name(np, "serial");
 471                 if (np) {
 472                         id = of_alias_get_id(np, "serial");
 473                         if (id == serial_id) {
 474                                 ok = 1;
 475                                 break;
 476                         }
 477                 }
 478         }
 479         if (!ok)
 480                 return -EINVAL;
 481
 482         pclk = of_clk_get_by_name(np, "pclk_uart");
 483         clk = of_clk_get_by_name(np, "sclk_uart");
 484         if (unlikely(IS_ERR(clk)) || unlikely(IS_ERR(pclk))) {
 485                 pr_err("fiq-debugger get clock fail\n");
 486                 return -EINVAL;
 487         }
 488
 489         clk_prepare_enable(clk);
 490         clk_prepare_enable(pclk);
 491
 492         irq = irq_of_parse_and_map(np, 0);
 493         if (!irq)
 494                 return -EINVAL;
 495
 496         base = of_iomap(np, 0);
 497         if (base)
 498                 rk_serial_debug_init(base, irq, signal_irq, wake_irq, baudrate);
 499
 500         return 0;
 501 }
 502 #ifdef CONFIG_FIQ_GLUE
 503 postcore_initcall_sync(rk_fiq_debugger_init);
 504 #else
 505 arch_initcall_sync(rk_fiq_debugger_init);
 506 #endif