arch/arm/mach-rockchip/rk3036.c

   1 /*
   2  * Device Tree support for Rockchip RK3036
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk-provider.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/cpuidle.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/irqchip.h>
  23 #include <linux/kernel.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/rockchip/common.h>
  27 #include <linux/rockchip/cpu.h>
  28 #include <linux/rockchip/cru.h>
  29 #include <linux/rockchip/dvfs.h>
  30 #include <linux/rockchip/grf.h>
  31 #include <linux/rockchip/iomap.h>
  32 #include <linux/rockchip/pmu.h>
  33 #include <asm/cpuidle.h>
  34 #include <asm/cputype.h>
  35 #include <asm/mach/arch.h>
  36 #include <asm/mach/map.h>
  37 #include "cpu_axi.h"
  38 #include "loader.h"
  39 #define CPU 3036
  40 #include "sram.h"
  41 #include "pm.h"
  42
  43 #define RK3036_DEVICE(name) \
  44         { \
  45                 .virtual        = (unsigned long) RK_##name##_VIRT, \
  46                 .pfn            = __phys_to_pfn(RK3036_##name##_PHYS), \
  47                 .length         = RK3036_##name##_SIZE, \
  48                 .type           = MT_DEVICE, \
  49         }
  50
  51 #define RK3036_IMEM_VIRT (RK_BOOTRAM_VIRT + SZ_32K)
  52 #define RK3036_TIMER5_VIRT (RK_TIMER_VIRT + 0xa0)
  53
  54
  55 static struct map_desc rk3036_io_desc[] __initdata = {
  56         RK3036_DEVICE(CRU),
  57         RK3036_DEVICE(GRF),
  58         RK3036_DEVICE(ROM),
  59         RK3036_DEVICE(EFUSE),
  60         RK_DEVICE(RK_DDR_VIRT, RK3036_DDR_PCTL_PHYS, RK3036_DDR_PCTL_SIZE),
  61         RK_DEVICE(RK_DDR_VIRT + RK3036_DDR_PCTL_SIZE, RK3036_DDR_PHY_PHYS, RK3036_DDR_PHY_SIZE),
  62         RK_DEVICE(RK_GPIO_VIRT(0), RK3036_GPIO0_PHYS, RK3036_GPIO_SIZE),
  63         RK_DEVICE(RK_GPIO_VIRT(1), RK3036_GPIO1_PHYS, RK3036_GPIO_SIZE),
  64         RK_DEVICE(RK_GPIO_VIRT(2), RK3036_GPIO2_PHYS, RK3036_GPIO_SIZE),
  65         RK_DEVICE(RK_DEBUG_UART_VIRT, RK3036_UART2_PHYS, RK3036_UART_SIZE),
  66         RK_DEVICE(RK_GIC_VIRT, RK3036_GIC_DIST_PHYS, RK3036_GIC_DIST_SIZE),
  67         RK_DEVICE(RK_GIC_VIRT + RK3036_GIC_DIST_SIZE,RK3036_GIC_CPU_PHYS, RK3036_GIC_CPU_SIZE),
  68         RK_DEVICE(RK3036_IMEM_VIRT, RK3036_IMEM_PHYS, SZ_4K),
  69         RK_DEVICE(RK_TIMER_VIRT, RK3036_TIMER_PHYS, RK3036_TIMER_SIZE),
  70 };
  71
  72 static void __init rk3036_boot_mode_init(void)
  73 {
  74         u32 flag = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_OS_REG0);
  75         u32 mode = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_OS_REG1);
  76         u32 rst_st = readl_relaxed(RK_CRU_VIRT + RK3036_CRU_RST_ST);
  77
  78         if (flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER))
  79                 mode = BOOT_MODE_RECOVERY;
  80         if (rst_st & ((1 << 2) | (1 << 3)))
  81                 mode = BOOT_MODE_WATCHDOG;
  82         rockchip_boot_mode_init(flag, mode);
  83 }
  84
  85 static void usb_uart_init(void)
  86 {
  87         u32 soc_status0 = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_STATUS0);
  88         writel_relaxed(0x34000000, RK_GRF_VIRT + RK3036_GRF_UOC1_CON4);
  89 #ifdef CONFIG_RK_USB_UART
  90         if (!(soc_status0 & (1 << 14)) && (soc_status0 & (1 << 17))) {
  91                 /* software control usb phy enable */
  92                 writel_relaxed(0x007f0055, RK_GRF_VIRT + RK3036_GRF_UOC0_CON5);
  93                 writel_relaxed(0x34003000, RK_GRF_VIRT + RK3036_GRF_UOC1_CON4);
  94         }
  95 #endif
  96 #ifdef RK_DEBUG_UART_VIRT
  97     writel_relaxed(0x07, RK_DEBUG_UART_VIRT + 0x88);
  98     writel_relaxed(0x07, RK_DEBUG_UART_VIRT + 0x88);
  99     writel_relaxed(0x00, RK_DEBUG_UART_VIRT + 0x04);
 100     writel_relaxed(0x83, RK_DEBUG_UART_VIRT + 0x0c);
 101     writel_relaxed(0x0d, RK_DEBUG_UART_VIRT + 0x00);
 102     writel_relaxed(0x00, RK_DEBUG_UART_VIRT + 0x04);
 103     writel_relaxed(0x03, RK_DEBUG_UART_VIRT + 0x0c);
 104 #endif //end of DEBUG_UART_BASE
 105 }
 106
 107 static void __init rk3036_dt_map_io(void)
 108 {
 109         rockchip_soc_id = ROCKCHIP_SOC_RK3036;
 110
 111         iotable_init(rk3036_io_desc, ARRAY_SIZE(rk3036_io_desc));
 112         debug_ll_io_init();
 113         usb_uart_init();
 114
 115         /* enable timer5 for core */
 116         writel_relaxed(0, RK3036_TIMER5_VIRT + 0x10);
 117         dsb();
 118         writel_relaxed(0xFFFFFFFF, RK3036_TIMER5_VIRT + 0x00);
 119         writel_relaxed(0xFFFFFFFF, RK3036_TIMER5_VIRT + 0x04);
 120         dsb();
 121         writel_relaxed(1, RK3036_TIMER5_VIRT + 0x10);
 122         dsb();
 123
 124         rk3036_boot_mode_init();
 125 }
 126
 127 static int rk3036_sys_set_power_domain(enum pmu_power_domain pd, bool on)
 128 {
 129     return 0;
 130 }
 131
 132 static bool rk3036_pmu_power_domain_is_on(enum pmu_power_domain pd)
 133 {
 134     return 1;
 135 }
 136
 137 static int rk3036_pmu_set_idle_request(enum pmu_idle_req req, bool idle)
 138 {
 139     return 0;
 140 }
 141
 142 static void __init rk3036_dt_init_timer(void)
 143 {
 144         rockchip_pmu_ops.set_power_domain = rk3036_sys_set_power_domain;
 145         rockchip_pmu_ops.power_domain_is_on = rk3036_pmu_power_domain_is_on;
 146         rockchip_pmu_ops.set_idle_request = rk3036_pmu_set_idle_request;
 147         of_clk_init(NULL);
 148         clocksource_of_init();
 149 }
 150
 151 static void __init rk3036_init_late(void)
 152 {
 153     return;
 154 }
 155
 156 static void __init rk3036_reserve(void)
 157 {
 158         /* reserve memory for ION */
 159         //rockchip_ion_reserve();
 160
 161     return;
 162 }
 163
 164 static void rk3036_restart(char mode, const char *cmd)
 165 {
 166         u32 boot_flag, boot_mode;
 167
 168         rockchip_restart_get_boot_mode(cmd, &boot_flag, &boot_mode);
 169
 170         writel_relaxed(boot_flag, RK_GRF_VIRT + RK3036_GRF_OS_REG0);    // for loader
 171         writel_relaxed(boot_mode, RK_GRF_VIRT + RK3036_GRF_OS_REG1);    // for linux
 172         dsb();
 173
 174         /* pll enter slow mode */
 175         writel_relaxed(0x30110000, RK_CRU_VIRT + RK3036_CRU_MODE_CON);
 176         dsb();
 177         writel_relaxed(0xeca8, RK_CRU_VIRT + RK3036_CRU_GLB_SRST_SND_VALUE);
 178         dsb();
 179 }
 180
 181 static const char * const rk3036_dt_compat[] __initconst = {
 182         "rockchip,rk3036",
 183         NULL,
 184 };
 185
 186 DT_MACHINE_START(RK3036_DT, "Rockchip RK3036")
 187         .dt_compat      = rk3036_dt_compat,
 188         .smp            = smp_ops(rockchip_smp_ops),
 189         .reserve        = rk3036_reserve,
 190         .map_io         = rk3036_dt_map_io,
 191         .init_time      = rk3036_dt_init_timer,
 192         .init_late      = rk3036_init_late,
 193         .reserve        = rk3036_reserve,
 194         .restart        = rk3036_restart,
 195 MACHINE_END