2 * Copyright (C) 2013-2014 ROCKCHIP, Inc.
3 * Copyright (c) 2013 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/delay.h>
18 #include <linux/init.h>
19 #include <linux/smp.h>
22 #include <linux/of_address.h>
23 #include <linux/rockchip/common.h>
24 #include <linux/rockchip/pmu.h>
26 #include <asm/cacheflush.h>
27 #include <asm/smp_scu.h>
28 #include <asm/smp_plat.h>
29 #include <asm/mach/map.h>
33 #define SCU_STANDBY_EN (1 << 5)
37 extern void secondary_startup(void);
38 extern void v7_invalidate_l1(void);
40 static void __naked rockchip_a9_secondary_startup(void)
46 static void __naked rockchip_secondary_trampoline(void)
50 ".globl rockchip_boot_fn\n"
57 * Handling of CPU cores
60 static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
61 struct task_struct *idle)
64 pr_err("%s: cpu %d outside maximum number of cpus %d\n",
65 __func__, cpu, ncores);
70 rockchip_pmu_ops.set_power_domain(PD_CPU_0 + cpu, true);
76 * rockchip_smp_prepare_bootram - populate necessary bootram block
77 * Starting cores execute the code residing at the start of the on-chip bootram
78 * after power-on. Therefore make sure, this sram region is reserved and
79 * big enough. After this check, copy the trampoline code that directs the
80 * core to the real startup code in ram into the sram-region.
82 static int __init rockchip_smp_prepare_bootram(void)
84 struct device_node *node;
85 void __iomem *bootram_base_addr;
87 node = of_find_compatible_node(NULL, NULL, "rockchip,bootram");
89 pr_err("%s: could not find bootram dt node\n", __func__);
93 bootram_base_addr = of_iomap(node, 0);
94 if (!bootram_base_addr) {
95 pr_err("%s: could not map bootram\n", __func__);
99 /* set the boot function for the bootram code */
100 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
101 rockchip_boot_fn = virt_to_phys(rockchip_a9_secondary_startup);
103 rockchip_boot_fn = virt_to_phys(secondary_startup);
105 /* copy the trampoline to bootram, that runs during startup of the core */
106 memcpy(bootram_base_addr, &rockchip_secondary_trampoline, 8);
108 iounmap(bootram_base_addr);
113 static void __init rockchip_a9_smp_prepare_cpus(unsigned int max_cpus)
115 void __iomem *scu_base_addr;
118 scu_base_addr = ioremap(scu_a9_get_base(), 0x100);
120 if (!scu_base_addr) {
121 pr_err("%s: could not map scu registers\n", __func__);
125 if (rockchip_smp_prepare_bootram())
129 * While the number of cpus is gathered from dt, also get the number
130 * of cores from the scu to verify this value when booting the cores.
132 ncores = scu_get_core_count(scu_base_addr);
134 writel_relaxed(readl_relaxed(scu_base_addr + SCU_CTRL) | SCU_STANDBY_EN, scu_base_addr + SCU_CTRL);
135 scu_enable(scu_base_addr);
137 cpu = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 0);
138 /* Make sure that all cores except myself are really off */
139 for (i = 0; i < ncores; i++) {
142 rockchip_pmu_ops.set_power_domain(PD_CPU_0 + i, false);
145 iounmap(scu_base_addr);
148 static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
151 unsigned long l2ctlr;
153 if (scu_a9_has_base())
154 return rockchip_a9_smp_prepare_cpus(max_cpus);
156 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr));
157 ncores = ((l2ctlr >> 24) & 3) + 1;
158 cpu = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 0);
159 /* Make sure that all cores except myself are really off */
160 for (i = 0; i < ncores; i++) {
163 rockchip_pmu_ops.set_power_domain(PD_CPU_0 + i, false);
167 struct smp_operations rockchip_smp_ops __initdata = {
168 .smp_prepare_cpus = rockchip_smp_prepare_cpus,
169 .smp_boot_secondary = rockchip_boot_secondary,
170 #ifdef CONFIG_HOTPLUG_CPU
171 .cpu_kill = rockchip_cpu_kill,
172 .cpu_die = rockchip_cpu_die,
173 .cpu_disable = rockchip_cpu_disable,