arch/arm/mach-rockchip/efuse.c

   1 /*
   2  * Copyright (C) 2013-2015 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/crc32.h>
  10 #include <linux/delay.h>
  11 #include <linux/of.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/rockchip/cpu.h>
  14 #include <linux/rockchip/iomap.h>
  15 #include <asm/compiler.h>
  16 #include <asm/psci.h>
  17 #include <asm/system_info.h>
  18 #include "efuse.h"
  19
  20 #ifdef CONFIG_ARM
  21 #define efuse_readl(offset) readl_relaxed(RK_EFUSE_VIRT + offset)
  22 #define efuse_writel(val, offset) writel_relaxed(val, RK_EFUSE_VIRT + offset)
  23 #endif
  24
  25 static u8 efuse_buf[32] = {};
  26
  27 struct rockchip_efuse {
  28         int (*get_leakage)(int ch);
  29         int (*get_temp)(int ch);
  30         int efuse_version;
  31         int process_version;
  32 };
  33
  34 static struct rockchip_efuse efuse;
  35
  36 #ifdef CONFIG_ARM64
  37 /****************************secure reg access****************************/
  38
  39 #define SEC_REG_RW_SHT (0x0)
  40 #define SEC_REG_RD (0x0)
  41 #define SEC_REG_WR (0x1)
  42
  43 #define SEC_REG_BITS_SHT (0x1)
  44 #define SEC_REG_32 (0x0)
  45 #define SEC_REG_64 (0x2)
  46
  47 #define SEC_REG_RD_32 (SEC_REG_RD | SEC_REG_32)
  48 #define SEC_REG_RD_64 (SEC_REG_RD | SEC_REG_64)
  49 #define SEC_REG_WR_32 (SEC_REG_WR | SEC_REG_32)
  50 #define SEC_REG_WR_64 (SEC_REG_WR | SEC_REG_64)
  51
  52 #define PSCI_SIP_ACCESS_REG             (0x82000002)
  53 #define PSCI_SIP_RKTF_VER               (0x82000001)
  54
  55 static phys_addr_t efuse_phys;
  56
  57 /*
  58  * arg2: rd/wr control, bit[0] 0-rd 1-rt, bit[1] 0-32bit, 1-64bit
  59  * arg1: base addr
  60  * arg0: read or write val
  61  * function_id: return fail/succes
  62  */
  63 static u32 reg_wr_fn_smc(u64 function_id, u64 arg0, u64 arg1, u64 arg2)
  64 {
  65         asm volatile(
  66                         __asmeq("%0", "x0")
  67                         __asmeq("%1", "x1")
  68                         __asmeq("%2", "x2")
  69                         __asmeq("%3", "x3")
  70                         "smc    #0\n"
  71                 : "+r" (function_id), "+r" (arg0)
  72                 : "r" (arg1), "r" (arg2));
  73
  74         return function_id;
  75 }
  76
  77 static u32 reg_rd_fn_smc(u64 function_id, u64 arg0, u64 arg1, u64 arg2,
  78                          u64 *val)
  79 {
  80         asm volatile(
  81                         __asmeq("%0", "x0")
  82                         __asmeq("%1", "x1")
  83                         __asmeq("%2", "x2")
  84                         __asmeq("%3", "x3")
  85                         "smc    #0\n"
  86                 : "+r" (function_id), "+r" (arg0)
  87                 : "r" (arg1), "r" (arg2));
  88
  89                 *val = arg0;
  90
  91         return function_id;
  92 }
  93
  94 static u32 (*reg_wr_fn)(u64, u64, u64, u64) = reg_wr_fn_smc;
  95 static u32 (*reg_rd_fn)(u64, u64, u64, u64, u64 *) = reg_rd_fn_smc;
  96
  97 static u32 secure_regs_rd_32(u64 addr_phy)
  98 {
  99         u64 val = 0;
 100
 101         reg_rd_fn(PSCI_SIP_ACCESS_REG, 0, addr_phy, SEC_REG_RD_32, &val);
 102         return val;
 103 }
 104
 105 static u32 secure_regs_wr_32(u64 addr_phy, u32 val)
 106 {
 107         u64 val_64 = val;
 108
 109         return reg_wr_fn(PSCI_SIP_ACCESS_REG, val_64, addr_phy, SEC_REG_WR_32);
 110 }
 111
 112 static u32 efuse_readl(u32 offset)
 113 {
 114         return secure_regs_rd_32(efuse_phys + offset);
 115 }
 116
 117 static void efuse_writel(u32 val, u32 offset)
 118 {
 119         secure_regs_wr_32(efuse_phys + offset, val);
 120 }
 121
 122 #define RKTF_VER_MAJOR(ver) (((ver) >> 16) & 0xffff)
 123 #define RKTF_VER_MINOR(ver) ((ver) & 0xffff)
 124 /* valid ver */
 125 #define RKTF_VLDVER_MAJOR (1)
 126 #define RKTF_VLDVER_MINOR (3)
 127
 128
 129 static void rockchip_tf_ver_check(void)
 130 {
 131         u64 val;
 132         u32 ver_val;
 133
 134         ver_val = reg_rd_fn(PSCI_SIP_RKTF_VER, 0, 0, 0, &val);
 135         if (ver_val == 0xffffffff)
 136                 goto ver_error;
 137
 138         if ((RKTF_VER_MAJOR(ver_val) >= RKTF_VLDVER_MAJOR) &&
 139                 (RKTF_VER_MINOR(ver_val) >= RKTF_VLDVER_MINOR))
 140                 return;
 141
 142 ver_error:
 143
 144         pr_err("read tf version 0x%x!\n", ver_val);
 145
 146         do {
 147                 mdelay(1000);
 148                 pr_err("trusted firmware need to update to(%d.%d) or is invaild!\n",
 149                         RKTF_VLDVER_MAJOR, RKTF_VLDVER_MINOR);
 150         } while(1);
 151 }
 152
 153 #endif
 154
 155 static int rk3288_efuse_readregs(u32 addr, u32 length, u8 *buf)
 156 {
 157         int ret = length;
 158
 159         if (!length)
 160                 return 0;
 161         if (!buf)
 162                 return 0;
 163
 164         efuse_writel(EFUSE_CSB, REG_EFUSE_CTRL);
 165         efuse_writel(EFUSE_LOAD | EFUSE_PGENB, REG_EFUSE_CTRL);
 166         udelay(2);
 167         do {
 168                 efuse_writel(efuse_readl(REG_EFUSE_CTRL) &
 169                         (~(EFUSE_A_MASK << EFUSE_A_SHIFT)), REG_EFUSE_CTRL);
 170                 efuse_writel(efuse_readl(REG_EFUSE_CTRL) |
 171                         ((addr & EFUSE_A_MASK) << EFUSE_A_SHIFT),
 172                         REG_EFUSE_CTRL);
 173                 udelay(2);
 174                 efuse_writel(efuse_readl(REG_EFUSE_CTRL) |
 175                                 EFUSE_STROBE, REG_EFUSE_CTRL);
 176                 udelay(2);
 177                 *buf = efuse_readl(REG_EFUSE_DOUT);
 178                 efuse_writel(efuse_readl(REG_EFUSE_CTRL) &
 179                                 (~EFUSE_STROBE), REG_EFUSE_CTRL);
 180                 udelay(2);
 181                 buf++;
 182                 addr++;
 183         } while (--length);
 184         udelay(2);
 185         efuse_writel(efuse_readl(REG_EFUSE_CTRL) | EFUSE_CSB, REG_EFUSE_CTRL);
 186         udelay(1);
 187
 188         return ret;
 189 }
 190
 191 static int __init rk3288_get_efuse_version(void)
 192 {
 193         int ret = efuse_buf[4] & (~(0x1 << 3));
 194         return ret;
 195 }
 196
 197 static int __init rk3288_get_process_version(void)
 198 {
 199         int ret = efuse_buf[6]&0x0f;
 200
 201         return ret;
 202 }
 203
 204 static int rk3288_get_leakage(int ch)
 205 {
 206         if ((ch < 0) || (ch > 2))
 207                 return 0;
 208
 209         return efuse_buf[23+ch];
 210 }
 211
 212 #ifdef CONFIG_ARM
 213 static void __init rk3288_set_system_serial(void)
 214 {
 215         int i;
 216         u8 buf[16];
 217
 218         for (i = 0; i < 8; i++) {
 219                 buf[i] = efuse_buf[8 + (i << 1)];
 220                 buf[i + 8] = efuse_buf[7 + (i << 1)];
 221         }
 222
 223         system_serial_low = crc32(0, buf, 8);
 224         system_serial_high = crc32(system_serial_low, buf + 8, 8);
 225 }
 226 #else
 227 static inline void __init rk3288_set_system_serial(void) {}
 228 #endif
 229
 230 int rk312x_efuse_readregs(u32 addr, u32 length, u8 *buf)
 231 {
 232         int ret = length;
 233
 234         if (!length)
 235                 return 0;
 236
 237         efuse_writel(EFUSE_LOAD, REG_EFUSE_CTRL);
 238         udelay(2);
 239         do {
 240                 efuse_writel(efuse_readl(REG_EFUSE_CTRL) &
 241                                 (~(EFUSE_A_MASK << RK312X_EFUSE_A_SHIFT)),
 242                                 REG_EFUSE_CTRL);
 243                 efuse_writel(efuse_readl(REG_EFUSE_CTRL) |
 244                                 ((addr & EFUSE_A_MASK) << RK312X_EFUSE_A_SHIFT),
 245                                 REG_EFUSE_CTRL);
 246                 udelay(2);
 247                 efuse_writel(efuse_readl(REG_EFUSE_CTRL) |
 248                                 EFUSE_STROBE, REG_EFUSE_CTRL);
 249                 udelay(2);
 250                 *buf = efuse_readl(REG_EFUSE_DOUT);
 251                 efuse_writel(efuse_readl(REG_EFUSE_CTRL) &
 252                                 (~EFUSE_STROBE), REG_EFUSE_CTRL);
 253                 udelay(2);
 254                 buf++;
 255                 addr++;
 256         } while (--length);
 257         udelay(2);
 258         efuse_writel(efuse_readl(REG_EFUSE_CTRL) &
 259                         (~EFUSE_LOAD) , REG_EFUSE_CTRL);
 260         udelay(1);
 261
 262         return ret;
 263 }
 264
 265 int rockchip_efuse_version(void)
 266 {
 267         return efuse.efuse_version;
 268 }
 269
 270 int rockchip_process_version(void)
 271 {
 272         return efuse.process_version;
 273 }
 274
 275 int rockchip_get_leakage(int ch)
 276 {
 277         int ret = 0;
 278
 279         if (efuse.get_leakage) {
 280                 return efuse.get_leakage(ch);
 281         } else {
 282                 ret = rk3288_efuse_readregs(0, 32, efuse_buf);
 283                 if (ret == 32)
 284                         return efuse_buf[23+ch];
 285         }
 286         return 0;
 287 }
 288
 289 int rockchip_efuse_get_temp_adjust(int ch)
 290 {
 291         int temp;
 292
 293         if (efuse_buf[31] & 0x80)
 294                 temp = -(efuse_buf[31] & 0x7f);
 295         else
 296                 temp = efuse_buf[31];
 297
 298         return temp;
 299 }
 300
 301 static void __init rk3288_efuse_init(void)
 302 {
 303         int ret;
 304
 305         ret = rk3288_efuse_readregs(0, 32, efuse_buf);
 306         if (ret == 32) {
 307                 efuse.get_leakage = rk3288_get_leakage;
 308                 efuse.efuse_version = rk3288_get_efuse_version();
 309                 efuse.process_version = rk3288_get_process_version();
 310                 rockchip_set_cpu_version((efuse_buf[6] >> 4) & 3);
 311                 rk3288_set_system_serial();
 312         } else {
 313                 pr_err("failed to read eFuse, return %d\n", ret);
 314         }
 315 }
 316
 317 void __init rockchip_efuse_init(void)
 318 {
 319         int ret;
 320
 321         if (cpu_is_rk3288()) {
 322                 rk3288_efuse_init();
 323         } else if (cpu_is_rk312x()) {
 324                 ret = rk312x_efuse_readregs(0, 32, efuse_buf);
 325                 if (ret == 32)
 326                         efuse.get_leakage = rk3288_get_leakage;
 327                 else
 328                         pr_err("failed to read eFuse, return %d\n", ret);
 329         }
 330 }
 331
 332 #ifdef CONFIG_ARM64
 333 static int __init rockchip_efuse_probe(struct platform_device *pdev)
 334 {
 335         struct resource *regs;
 336
 337         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 338         if (!regs) {
 339                 dev_err(&pdev->dev, "failed to get I/O memory\n");
 340                 return -ENODEV;
 341         }
 342         efuse_phys = regs->start;
 343
 344         rockchip_tf_ver_check();
 345
 346         rk3288_efuse_init();
 347         return 0;
 348 }
 349
 350 static const struct of_device_id rockchip_efuse_of_match[] = {
 351         { .compatible = "rockchip,rk3368-efuse-256", .data = NULL, },
 352         {},
 353 };
 354
 355 static struct platform_driver rockchip_efuse_driver = {
 356         .driver         = {
 357                 .name           = "efuse",
 358                 .owner          = THIS_MODULE,
 359                 .of_match_table = of_match_ptr(rockchip_efuse_of_match),
 360         },
 361 };
 362
 363 static int __init rockchip_efuse_module_init(void)
 364 {
 365         return platform_driver_probe(&rockchip_efuse_driver,
 366                                      rockchip_efuse_probe);
 367 }
 368 arch_initcall_sync(rockchip_efuse_module_init);
 369 #endif