arch/arm/mach-rockchip/ddr_rk32.c

   1 /*
   2  * Function Driver for DDR controller
   3  *
   4  * Copyright (C) 2011-2014 Fuzhou Rockchip Electronics Co.,Ltd
   5  * Author:
   6  * hcy@rock-chips.com
   7  * yk@rock-chips.com
   8  *
   9  * v1.00
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/clk.h>
  16
  17 #include <asm/cacheflush.h>
  18 #include <asm/tlbflush.h>
  19 #include <linux/cpu.h>
  20 #include <dt-bindings/clock/ddr.h>
  21 #include <linux/rockchip/cru.h>
  22 #include <linux/rk_fb.h>
  23 #include "cpu_axi.h"
  24
  25 typedef uint32_t uint32;
  26
  27 #ifdef CONFIG_FB_ROCKCHIP
  28 #define DDR_CHANGE_FREQ_IN_LCDC_VSYNC
  29 #endif
  30 /***********************************
  31  * Global Control Macro
  32  ***********************************/
  33 //#define ENABLE_DDR_CLCOK_GPLL_PATH  //for RK3188
  34
  35 #define DDR3_DDR2_ODT_DISABLE_FREQ    (333)
  36 #define DDR3_DDR2_DLL_DISABLE_FREQ    (333)
  37 #define SR_IDLE                       (0x3)   //unit:32*DDR clk cycle, and 0 for disable auto self-refresh
  38 #define PD_IDLE                       (0X40)  //unit:DDR clk cycle, and 0 for disable auto power-down
  39
  40 //#if (DDR3_DDR2_ODT_DISABLE_FREQ > DDR3_DDR2_DLL_DISABLE_FREQ)
  41 //#error
  42 //#endif
  43
  44 #define ddr_print(x...) printk( "DDR DEBUG: " x )
  45
  46 /***********************************
  47  * ARCH Relative Macro and Struction
  48  ***********************************/
  49 #define SRAM_CODE_OFFSET        rockchip_sram_virt
  50 #define SRAM_SIZE               rockchip_sram_size
  51
  52 /*
  53  * PMU
  54  */
  55 //PMU_PWRDN_ST
  56 #define pd_scu_pwr_st       (1<<11)
  57 #define pd_hevc_pwr_st      (1<<10)
  58 #define pd_gpu_pwr_st       (1<<9)
  59 #define pd_video_pwr_st     (1<<8)
  60 #define pd_vio_pwr_st       (1<<7)
  61 #define pd_peri_pwr_st      (1<<6)
  62 #define pd_bus_pwr_st      (1<<5)
  63 //PMU_IDLE_REQ
  64 #define idle_req_hevc_cfg   (1<<9)
  65 #define idle_req_cpup_cfg   (1<<8)
  66 #define idle_req_dma_cfg    (1<<7)
  67 #define idle_req_alive_cfg  (1<<6)
  68 #define idle_req_core_cfg   (1<<5)
  69 #define idle_req_vio_cfg    (1<<4)
  70 #define idle_req_video_cfg  (1<<3)
  71 #define idle_req_gpu_cfg    (1<<2)
  72 #define idle_req_peri_cfg   (1<<1)
  73 #define idle_req_bus_cfg    (1<<0)
  74
  75 //PMU_IDLE_ST
  76 #define idle_ack_hevc     (1<<25)
  77 #define idle_ack_cpup     (1<<24)
  78 #define idle_ack_dma      (1<<23)
  79 #define idle_ack_alive    (1<<22)
  80 #define idle_ack_core     (1<<21)
  81 #define idle_ack_vio      (1<<20)
  82 #define idle_ack_video    (1<<19)
  83 #define idle_ack_gpu      (1<<18)
  84 #define idle_ack_peir     (1<<17)
  85 #define idle_ack_bus      (1<<16)
  86
  87 #define idle_hevc   (1<<9)
  88 #define idle_cpup   (1<<8)
  89 #define idle_dma    (1<<7)
  90 #define idle_alive  (1<<6)
  91 #define idle_core   (1<<5)
  92 #define idle_vio    (1<<4)
  93 #define idle_video  (1<<3)
  94 #define idle_gpu    (1<<2)
  95 #define idle_peri   (1<<1)
  96 #define idle_bus    (1<<0)
  97
  98 //PMU_PWRMODE_CON
  99 /* ch=0, channel a
 100    ch=1, channel b
 101  */
 102 #define ddrio_ret_de_req(ch)  (1<<(21+(ch)))
 103 #define ddrc_gating_en(ch)    (1<<(19+(ch)))
 104 #define ddrio_ret_en(ch)      (1<<(17+(ch)))
 105 #define sref_enter_en(ch)     (1<<(15+(ch)))
 106
 107 //PMU_PWR_STATE
 108 #define SREF_EXIT             (1<<26)
 109 #define DDR_IO_PWRUP          (1<<25)
 110
 111 //PMU registers
 112 typedef volatile struct tagPMU_FILE
 113 {
 114     uint32 PMU_WAKEUP_CFG[2];
 115     uint32 PMU_PWRDN_CON;
 116     uint32 PMU_PWRDN_ST;
 117     uint32 PMU_IDLE_REQ;
 118     uint32 PMU_IDLE_ST;
 119     uint32 PMU_PWRMODE_CON;
 120     uint32 PMU_PWR_STATE;
 121     uint32 PMU_OSC_CNT;
 122     uint32 PMU_PLL_CNT;
 123     uint32 PMU_STABL_CNT;
 124     uint32 PMU_DDR0IO_PWRON_CNT;
 125     uint32 PMU_DDR1IO_PWRON_CNT;
 126     uint32 PMU_CORE_PWRDN_CNT;
 127     uint32 PMU_CORE_PWRUP_CNT;
 128     uint32 PMU_GPU_PWRDWN_CNT;
 129     uint32 PMU_GPU_PWRUP_CNT;
 130     uint32 PMU_WAKEUP_RST_CLR_CNT;
 131     uint32 PMU_SFT_CON;
 132     uint32 PMU_DDR_SREF_ST;
 133     uint32 PMU_INT_CON;
 134     uint32 PMU_INT_ST;
 135     uint32 PMU_BOOT_ADDR_SEL;
 136     uint32 PMU_GRF_CON;
 137     uint32 PMU_GPIO_SR;
 138     uint32 PMU_GPIO0_A_PULL;
 139     uint32 PMU_GPIO0_B_PULL;
 140     uint32 PMU_GPIO0_C_PULL;
 141     uint32 PMU_GPIO0_A_DRV;
 142     uint32 PMU_GPIO0_B_DRV;
 143     uint32 PMU_GPIO0_C_DRV;
 144     uint32 PMU_GPIO_OP;
 145     uint32 PMU_GPIO0_SEL18;
 146     uint32 PMU_GPIO0_A_IOMUX;
 147     uint32 PMU_GPIO0_B_IOMUX;
 148     uint32 PMU_GPIO0_C_IOMUX;
 149     uint32 PMU_GPIO0_D_IOMUX;
 150     uint32 PMU_PMU_SYS_REG[4];
 151 }PMU_FILE, *pPMU_FILE;
 152
 153 /*
 154  * CRU
 155  */
 156 typedef enum PLL_ID_Tag
 157 {
 158     APLL=0,
 159     DPLL,
 160     CPLL,
 161     GPLL,
 162     PLL_MAX
 163 }PLL_ID;
 164
 165 #define PLL_RESET  (((0x1<<5)<<16) | (0x1<<5))
 166 #define PLL_DE_RESET  (((0x1<<5)<<16) | (0x0<<5))
 167 #define NR(n)      ((0x3F<<(8+16)) | (((n)-1)<<8))
 168 #define NO(n)      ((0xF<<16) | ((n)-1))
 169 #define NF(n)      ((0x1FFF<<16) | ((n)-1))
 170 #define NB(n)      ((0xFFF<<16) | ((n)-1))
 171
 172  //CRU Registers
 173 typedef volatile struct tagCRU_STRUCT
 174 {
 175     uint32 CRU_PLL_CON[5][4];
 176     uint32 CRU_MODE_CON;
 177     uint32 reserved1[(0x60-0x54)/4];
 178     uint32 CRU_CLKSEL_CON[43];
 179     uint32 reserved2[(0x160-0x10c)/4];
 180     uint32 CRU_CLKGATE_CON[19];
 181     uint32 reserved3[(0x1b0-0x1ac)/4];
 182     uint32 CRU_GLB_SRST_FST_VALUE;
 183     uint32 CRU_GLB_SRST_SND_VALUE;
 184     uint32 CRU_SOFTRST_CON[12];
 185     uint32 CRU_MISC_CON;
 186     uint32 CRU_GLB_CNT_TH;
 187     uint32 CRU_TSADC_RST_CON;
 188     uint32 reserved4[(0x200-0x1f4)/4];
 189     uint32 CRU_SDMMC_CON[2];
 190     uint32 CRU_SDIO0_CON[2];
 191     uint32 CRU_SDIO1_CON[2];
 192     uint32 CRU_EMMC_CON[2];
 193     // other regigster unused in boot
 194 } CRU_REG, *pCRU_REG;
 195
 196 /*
 197  * GRF
 198  */
 199 //REG FILE registers
 200 typedef volatile struct tagREG_FILE
 201 {
 202     uint32 GRF_GPIO1A_IOMUX;
 203     uint32 GRF_GPIO1B_IOMUX;
 204     uint32 GRF_GPIO1C_IOMUX;
 205     uint32 GRF_GPIO1D_IOMUX;
 206     uint32 GRF_GPIO2A_IOMUX;
 207     uint32 GRF_GPIO2B_IOMUX;
 208     uint32 GRF_GPIO2C_IOMUX;
 209     uint32 GRF_GPIO2D_IOMUX;
 210     uint32 GRF_GPIO3A_IOMUX;
 211     uint32 GRF_GPIO3B_IOMUX;
 212     uint32 GRF_GPIO3C_IOMUX;
 213     uint32 GRF_GPIO3DL_IOMUX;
 214     uint32 GRF_GPIO3DH_IOMUX;
 215     uint32 GRF_GPIO4AL_IOMUX;
 216     uint32 GRF_GPIO4AH_IOMUX;
 217     uint32 GRF_GPIO4BL_IOMUX;
 218     uint32 GRF_GPIO4BH_IOMUX;
 219     uint32 GRF_GPIO4C_IOMUX;
 220     uint32 GRF_GPIO4D_IOMUX;
 221     uint32 GRF_GPIO5A_IOMUX;
 222     uint32 GRF_GPIO5B_IOMUX;
 223     uint32 GRF_GPIO5C_IOMUX;
 224     uint32 GRF_GPIO5D_IOMUX;
 225     uint32 GRF_GPIO6A_IOMUX;
 226     uint32 GRF_GPIO6B_IOMUX;
 227     uint32 GRF_GPIO6C_IOMUX;
 228     uint32 GRF_GPIO6D_IOMUX;
 229     uint32 GRF_GPIO7A_IOMUX;
 230     uint32 GRF_GPIO7B_IOMUX;
 231     uint32 GRF_GPIO7CL_IOMUX;
 232     uint32 GRF_GPIO7CH_IOMUX;
 233     uint32 GRF_GPIO7D_IOMUX;
 234     uint32 GRF_GPIO8A_IOMUX;
 235     uint32 GRF_GPIO8B_IOMUX;
 236     uint32 GRF_GPIO8C_IOMUX;
 237     uint32 GRF_GPIO8D_IOMUX;
 238     uint32 reserved1[(0x100-0x90)/4];
 239     uint32 GRF_GPIO1L_SR;
 240     uint32 GRF_GPIO1H_SR;
 241     uint32 GRF_GPIO2L_SR;
 242     uint32 GRF_GPIO2H_SR;
 243     uint32 GRF_GPIO3L_SR;
 244     uint32 GRF_GPIO3H_SR;
 245     uint32 GRF_GPIO4L_SR;
 246     uint32 GRF_GPIO4H_SR;
 247     uint32 GRF_GPIO5L_SR;
 248     uint32 GRF_GPIO5H_SR;
 249     uint32 GRF_GPIO6L_SR;
 250     uint32 GRF_GPIO6H_SR;
 251     uint32 GRF_GPIO7L_SR;
 252     uint32 GRF_GPIO7H_SR;
 253     uint32 GRF_GPIO8L_SR;
 254     uint32 GRF_GPIO8H_SR;
 255     uint32 GRF_GPIO1A_P;
 256     uint32 GRF_GPIO1B_P;
 257     uint32 GRF_GPIO1C_P;
 258     uint32 GRF_GPIO1D_P;
 259     uint32 GRF_GPIO2A_P;
 260     uint32 GRF_GPIO2B_P;
 261     uint32 GRF_GPIO2C_P;
 262     uint32 GRF_GPIO2D_P;
 263     uint32 GRF_GPIO3A_P;
 264     uint32 GRF_GPIO3B_P;
 265     uint32 GRF_GPIO3C_P;
 266     uint32 GRF_GPIO3D_P;
 267     uint32 GRF_GPIO4A_P;
 268     uint32 GRF_GPIO4B_P;
 269     uint32 GRF_GPIO4C_P;
 270     uint32 GRF_GPIO4D_P;
 271     uint32 GRF_GPIO5A_P;
 272     uint32 GRF_GPIO5B_P;
 273     uint32 GRF_GPIO5C_P;
 274     uint32 GRF_GPIO5D_P;
 275     uint32 GRF_GPIO6A_P;
 276     uint32 GRF_GPIO6B_P;
 277     uint32 GRF_GPIO6C_P;
 278     uint32 GRF_GPIO6D_P;
 279     uint32 GRF_GPIO7A_P;
 280     uint32 GRF_GPIO7B_P;
 281     uint32 GRF_GPIO7C_P;
 282     uint32 GRF_GPIO7D_P;
 283     uint32 GRF_GPIO8A_P;
 284     uint32 GRF_GPIO8B_P;
 285     uint32 GRF_GPIO8C_P;
 286     uint32 GRF_GPIO8D_P;
 287     uint32 GRF_GPIO1A_E;
 288     uint32 GRF_GPIO1B_E;
 289     uint32 GRF_GPIO1C_E;
 290     uint32 GRF_GPIO1D_E;
 291     uint32 GRF_GPIO2A_E;
 292     uint32 GRF_GPIO2B_E;
 293     uint32 GRF_GPIO2C_E;
 294     uint32 GRF_GPIO2D_E;
 295     uint32 GRF_GPIO3A_E;
 296     uint32 GRF_GPIO3B_E;
 297     uint32 GRF_GPIO3C_E;
 298     uint32 GRF_GPIO3D_E;
 299     uint32 GRF_GPIO4A_E;
 300     uint32 GRF_GPIO4B_E;
 301     uint32 GRF_GPIO4C_E;
 302     uint32 GRF_GPIO4D_E;
 303     uint32 GRF_GPIO5A_E;
 304     uint32 GRF_GPIO5B_E;
 305     uint32 GRF_GPIO5C_E;
 306     uint32 GRF_GPIO5D_E;
 307     uint32 GRF_GPIO6A_E;
 308     uint32 GRF_GPIO6B_E;
 309     uint32 GRF_GPIO6C_E;
 310     uint32 GRF_GPIO6D_E;
 311     uint32 GRF_GPIO7A_E;
 312     uint32 GRF_GPIO7B_E;
 313     uint32 GRF_GPIO7C_E;
 314     uint32 GRF_GPIO7D_E;
 315     uint32 GRF_GPIO8A_E;
 316     uint32 GRF_GPIO8B_E;
 317     uint32 GRF_GPIO8C_E;
 318     uint32 GRF_GPIO8D_E;
 319     uint32 GRF_GPIO_SMT;
 320     uint32 GRF_SOC_CON[15];
 321     uint32 GRF_SOC_STATUS[23];
 322     uint32 reserved2[(0x2e0-0x2dc)/4];
 323     uint32 GRF_DMAC2_CON[4];
 324     uint32 GRF_DDRC0_CON0;
 325     uint32 GRF_DDRC1_CON0;
 326     uint32 GRF_CPU_CON[5];
 327     uint32 reserved3[(0x318-0x30c)/4];
 328     uint32 GRF_CPU_STATUS0;
 329     uint32 reserved4[(0x320-0x31c)/4];
 330     uint32 GRF_UOC0_CON[5];
 331     uint32 GRF_UOC1_CON[5];
 332     uint32 GRF_UOC2_CON[4];
 333     uint32 GRF_UOC3_CON[2];
 334     uint32 GRF_UOC4_CON[2];
 335     uint32 GRF_DLL_CON[3];
 336     uint32 GRF_DLL_STATUS[3];
 337     uint32 GRF_IO_VSEL;
 338     uint32 GRF_SARADC_TESTBIT;
 339     uint32 GRF_TSADC_TESTBIT_L;
 340     uint32 GRF_TSADC_TESTBIT_H;
 341     uint32 GRF_OS_REG[4];
 342     uint32 GRF_FAST_BOOT_ADDR;
 343     uint32 GRF_SOC_CON15;
 344     uint32 GRF_SOC_CON16;
 345 } REG_FILE, *pREG_FILE;
 346
 347 /*
 348  * PCTL
 349  */
 350 //SCTL
 351 #define INIT_STATE                     (0)
 352 #define CFG_STATE                      (1)
 353 #define GO_STATE                       (2)
 354 #define SLEEP_STATE                    (3)
 355 #define WAKEUP_STATE                   (4)
 356
 357 //STAT
 358 #define Init_mem                       (0)
 359 #define Config                         (1)
 360 #define Config_req                     (2)
 361 #define Access                         (3)
 362 #define Access_req                     (4)
 363 #define Low_power                      (5)
 364 #define Low_power_entry_req            (6)
 365 #define Low_power_exit_req             (7)
 366
 367 //MCFG
 368 #define mddr_lpddr2_clk_stop_idle(n)   ((n)<<24)
 369 #define pd_idle(n)                     ((n)<<8)
 370 #define mddr_en                        (2<<22)
 371 #define lpddr2_en                      (3<<22)
 372 #define ddr2_en                        (0<<5)
 373 #define ddr3_en                        (1<<5)
 374 #define lpddr2_s2                      (0<<6)
 375 #define lpddr2_s4                      (1<<6)
 376 #define mddr_lpddr2_bl_2               (0<<20)
 377 #define mddr_lpddr2_bl_4               (1<<20)
 378 #define mddr_lpddr2_bl_8               (2<<20)
 379 #define mddr_lpddr2_bl_16              (3<<20)
 380 #define ddr2_ddr3_bl_4                 (0)
 381 #define ddr2_ddr3_bl_8                 (1)
 382 #define tfaw_cfg(n)                    (((n)-4)<<18)
 383 #define pd_exit_slow                   (0<<17)
 384 #define pd_exit_fast                   (1<<17)
 385 #define pd_type(n)                     ((n)<<16)
 386 #define two_t_en(n)                    ((n)<<3)
 387 #define bl8int_en(n)                   ((n)<<2)
 388 #define cke_or_en(n)                   ((n)<<1)
 389
 390 //POWCTL
 391 #define power_up_start                 (1<<0)
 392
 393 //POWSTAT
 394 #define power_up_done                  (1<<0)
 395
 396 //DFISTSTAT0
 397 #define dfi_init_complete              (1<<0)
 398
 399 //CMDTSTAT
 400 #define cmd_tstat                      (1<<0)
 401
 402 //CMDTSTATEN
 403 #define cmd_tstat_en                   (1<<1)
 404
 405 //MCMD
 406 #define Deselect_cmd                   (0)
 407 #define PREA_cmd                       (1)
 408 #define REF_cmd                        (2)
 409 #define MRS_cmd                        (3)
 410 #define ZQCS_cmd                       (4)
 411 #define ZQCL_cmd                       (5)
 412 #define RSTL_cmd                       (6)
 413 #define MRR_cmd                        (8)
 414 #define DPDE_cmd                       (9)
 415
 416 #define lpddr2_op(n)                   ((n)<<12)
 417 #define lpddr2_ma(n)                   ((n)<<4)
 418
 419 #define bank_addr(n)                   ((n)<<17)
 420 #define cmd_addr(n)                    ((n)<<4)
 421
 422 #define start_cmd                      (1u<<31)
 423
 424 typedef union STAT_Tag
 425 {
 426     uint32 d32;
 427     struct
 428     {
 429         unsigned ctl_stat : 3;
 430         unsigned reserved3 : 1;
 431         unsigned lp_trig : 3;
 432         unsigned reserved7_31 : 25;
 433     }b;
 434 }STAT_T;
 435
 436 typedef union SCFG_Tag
 437 {
 438     uint32 d32;
 439     struct
 440     {
 441         unsigned hw_low_power_en : 1;
 442         unsigned reserved1_5 : 5;
 443         unsigned nfifo_nif1_dis : 1;
 444         unsigned reserved7 : 1;
 445         unsigned bbflags_timing : 4;
 446         unsigned reserved12_31 : 20;
 447     } b;
 448 }SCFG_T;
 449
 450 /* DDR Controller register struct */
 451 typedef volatile struct DDR_REG_Tag
 452 {
 453     //Operational State, Control, and Status Registers
 454     SCFG_T SCFG;                   //State Configuration Register
 455     volatile uint32 SCTL;                   //State Control Register
 456     STAT_T STAT;                   //State Status Register
 457     volatile uint32 INTRSTAT;               //Interrupt Status Register
 458     uint32 reserved0[(0x40-0x10)/4];
 459     //Initailization Control and Status Registers
 460     volatile uint32 MCMD;                   //Memory Command Register
 461     volatile uint32 POWCTL;                 //Power Up Control Registers
 462     volatile uint32 POWSTAT;                //Power Up Status Register
 463     volatile uint32 CMDTSTAT;               //Command Timing Status Register
 464     volatile uint32 CMDTSTATEN;             //Command Timing Status Enable Register
 465     uint32 reserved1[(0x60-0x54)/4];
 466     volatile uint32 MRRCFG0;                //MRR Configuration 0 Register
 467     volatile uint32 MRRSTAT0;               //MRR Status 0 Register
 468     volatile uint32 MRRSTAT1;               //MRR Status 1 Register
 469     uint32 reserved2[(0x7c-0x6c)/4];
 470     //Memory Control and Status Registers
 471     volatile uint32 MCFG1;                  //Memory Configuration 1 Register
 472     volatile uint32 MCFG;                   //Memory Configuration Register
 473     volatile uint32 PPCFG;                  //Partially Populated Memories Configuration Register
 474     volatile uint32 MSTAT;                  //Memory Status Register
 475     volatile uint32 LPDDR2ZQCFG;            //LPDDR2 ZQ Configuration Register
 476     uint32 reserved3;
 477     //DTU Control and Status Registers
 478     volatile uint32 DTUPDES;                //DTU Status Register
 479     volatile uint32 DTUNA;                  //DTU Number of Random Addresses Created Register
 480     volatile uint32 DTUNE;                  //DTU Number of Errors Register
 481     volatile uint32 DTUPRD0;                //DTU Parallel Read 0
 482     volatile uint32 DTUPRD1;                //DTU Parallel Read 1
 483     volatile uint32 DTUPRD2;                //DTU Parallel Read 2
 484     volatile uint32 DTUPRD3;                //DTU Parallel Read 3
 485     volatile uint32 DTUAWDT;                //DTU Address Width
 486     uint32 reserved4[(0xc0-0xb4)/4];
 487     //Memory Timing Registers
 488     volatile uint32 TOGCNT1U;               //Toggle Counter 1U Register
 489     volatile uint32 TINIT;                  //t_init Timing Register
 490     volatile uint32 TRSTH;                  //Reset High Time Register
 491     volatile uint32 TOGCNT100N;             //Toggle Counter 100N Register
 492     volatile uint32 TREFI;                  //t_refi Timing Register
 493     volatile uint32 TMRD;                   //t_mrd Timing Register
 494     volatile uint32 TRFC;                   //t_rfc Timing Register
 495     volatile uint32 TRP;                    //t_rp Timing Register
 496     volatile uint32 TRTW;                   //t_rtw Timing Register
 497     volatile uint32 TAL;                    //AL Latency Register
 498     volatile uint32 TCL;                    //CL Timing Register
 499     volatile uint32 TCWL;                   //CWL Register
 500     volatile uint32 TRAS;                   //t_ras Timing Register
 501     volatile uint32 TRC;                    //t_rc Timing Register
 502     volatile uint32 TRCD;                   //t_rcd Timing Register
 503     volatile uint32 TRRD;                   //t_rrd Timing Register
 504     volatile uint32 TRTP;                   //t_rtp Timing Register
 505     volatile uint32 TWR;                    //t_wr Timing Register
 506     volatile uint32 TWTR;                   //t_wtr Timing Register
 507     volatile uint32 TEXSR;                  //t_exsr Timing Register
 508     volatile uint32 TXP;                    //t_xp Timing Register
 509     volatile uint32 TXPDLL;                 //t_xpdll Timing Register
 510     volatile uint32 TZQCS;                  //t_zqcs Timing Register
 511     volatile uint32 TZQCSI;                 //t_zqcsi Timing Register
 512     volatile uint32 TDQS;                   //t_dqs Timing Register
 513     volatile uint32 TCKSRE;                 //t_cksre Timing Register
 514     volatile uint32 TCKSRX;                 //t_cksrx Timing Register
 515     volatile uint32 TCKE;                   //t_cke Timing Register
 516     volatile uint32 TMOD;                   //t_mod Timing Register
 517     volatile uint32 TRSTL;                  //Reset Low Timing Register
 518     volatile uint32 TZQCL;                  //t_zqcl Timing Register
 519     volatile uint32 TMRR;                   //t_mrr Timing Register
 520     volatile uint32 TCKESR;                 //t_ckesr Timing Register
 521     volatile uint32 TDPD;                   //t_dpd Timing Register
 522     uint32 reserved5[(0x180-0x148)/4];
 523     //ECC Configuration, Control, and Status Registers
 524     volatile uint32 ECCCFG;                   //ECC Configuration Register
 525     volatile uint32 ECCTST;                   //ECC Test Register
 526     volatile uint32 ECCCLR;                   //ECC Clear Register
 527     volatile uint32 ECCLOG;                   //ECC Log Register
 528     uint32 reserved6[(0x200-0x190)/4];
 529     //DTU Control and Status Registers
 530     volatile uint32 DTUWACTL;                 //DTU Write Address Control Register
 531     volatile uint32 DTURACTL;                 //DTU Read Address Control Register
 532     volatile uint32 DTUCFG;                   //DTU Configuration Control Register
 533     volatile uint32 DTUECTL;                  //DTU Execute Control Register
 534     volatile uint32 DTUWD0;                   //DTU Write Data 0
 535     volatile uint32 DTUWD1;                   //DTU Write Data 1
 536     volatile uint32 DTUWD2;                   //DTU Write Data 2
 537     volatile uint32 DTUWD3;                   //DTU Write Data 3
 538     volatile uint32 DTUWDM;                   //DTU Write Data Mask
 539     volatile uint32 DTURD0;                   //DTU Read Data 0
 540     volatile uint32 DTURD1;                   //DTU Read Data 1
 541     volatile uint32 DTURD2;                   //DTU Read Data 2
 542     volatile uint32 DTURD3;                   //DTU Read Data 3
 543     volatile uint32 DTULFSRWD;                //DTU LFSR Seed for Write Data Generation
 544     volatile uint32 DTULFSRRD;                //DTU LFSR Seed for Read Data Generation
 545     volatile uint32 DTUEAF;                   //DTU Error Address FIFO
 546     //DFI Control Registers
 547     volatile uint32 DFITCTRLDELAY;            //DFI tctrl_delay Register
 548     volatile uint32 DFIODTCFG;                //DFI ODT Configuration Register
 549     volatile uint32 DFIODTCFG1;               //DFI ODT Configuration 1 Register
 550     volatile uint32 DFIODTRANKMAP;            //DFI ODT Rank Mapping Register
 551     //DFI Write Data Registers
 552     volatile uint32 DFITPHYWRDATA;            //DFI tphy_wrdata Register
 553     volatile uint32 DFITPHYWRLAT;             //DFI tphy_wrlat Register
 554     uint32 reserved7[(0x260-0x258)/4];
 555     volatile uint32 DFITRDDATAEN;             //DFI trddata_en Register
 556     volatile uint32 DFITPHYRDLAT;             //DFI tphy_rddata Register
 557     uint32 reserved8[(0x270-0x268)/4];
 558     //DFI Update Registers
 559     volatile uint32 DFITPHYUPDTYPE0;          //DFI tphyupd_type0 Register
 560     volatile uint32 DFITPHYUPDTYPE1;          //DFI tphyupd_type1 Register
 561     volatile uint32 DFITPHYUPDTYPE2;          //DFI tphyupd_type2 Register
 562     volatile uint32 DFITPHYUPDTYPE3;          //DFI tphyupd_type3 Register
 563     volatile uint32 DFITCTRLUPDMIN;           //DFI tctrlupd_min Register
 564     volatile uint32 DFITCTRLUPDMAX;           //DFI tctrlupd_max Register
 565     volatile uint32 DFITCTRLUPDDLY;           //DFI tctrlupd_dly Register
 566     uint32 reserved9;
 567     volatile uint32 DFIUPDCFG;                //DFI Update Configuration Register
 568     volatile uint32 DFITREFMSKI;              //DFI Masked Refresh Interval Register
 569     volatile uint32 DFITCTRLUPDI;             //DFI tctrlupd_interval Register
 570     uint32 reserved10[(0x2ac-0x29c)/4];
 571     volatile uint32 DFITRCFG0;                //DFI Training Configuration 0 Register
 572     volatile uint32 DFITRSTAT0;               //DFI Training Status 0 Register
 573     volatile uint32 DFITRWRLVLEN;             //DFI Training dfi_wrlvl_en Register
 574     volatile uint32 DFITRRDLVLEN;             //DFI Training dfi_rdlvl_en Register
 575     volatile uint32 DFITRRDLVLGATEEN;         //DFI Training dfi_rdlvl_gate_en Register
 576     //DFI Status Registers
 577     volatile uint32 DFISTSTAT0;               //DFI Status Status 0 Register
 578     volatile uint32 DFISTCFG0;                //DFI Status Configuration 0 Register
 579     volatile uint32 DFISTCFG1;                //DFI Status configuration 1 Register
 580     uint32 reserved11;
 581     volatile uint32 DFITDRAMCLKEN;            //DFI tdram_clk_enalbe Register
 582     volatile uint32 DFITDRAMCLKDIS;           //DFI tdram_clk_disalbe Register
 583     volatile uint32 DFISTCFG2;                //DFI Status configuration 2 Register
 584     volatile uint32 DFISTPARCLR;              //DFI Status Parity Clear Register
 585     volatile uint32 DFISTPARLOG;              //DFI Status Parity Log Register
 586     uint32 reserved12[(0x2f0-0x2e4)/4];
 587     //DFI Low Power Registers
 588     volatile uint32 DFILPCFG0;                //DFI Low Power Configuration 0 Register
 589     uint32 reserved13[(0x300-0x2f4)/4];
 590     //DFI Training 2 Registers
 591     volatile uint32 DFITRWRLVLRESP0;          //DFI Training dif_wrlvl_resp Status 0 Register
 592     volatile uint32 DFITRWRLVLRESP1;          //DFI Training dif_wrlvl_resp Status 1 Register
 593     volatile uint32 DFITRWRLVLRESP2;          //DFI Training dif_wrlvl_resp Status 2 Register
 594     volatile uint32 DFITRRDLVLRESP0;          //DFI Training dif_rdlvl_resp Status 0 Register
 595     volatile uint32 DFITRRDLVLRESP1;          //DFI Training dif_rdlvl_resp Status 1 Register
 596     volatile uint32 DFITRRDLVLRESP2;          //DFI Training dif_rdlvl_resp Status 2 Register
 597     volatile uint32 DFITRWRLVLDELAY0;         //DFI Training dif_wrlvl_delay Configuration 0 Register
 598     volatile uint32 DFITRWRLVLDELAY1;         //DFI Training dif_wrlvl_delay Configuration 1 Register
 599     volatile uint32 DFITRWRLVLDELAY2;         //DFI Training dif_wrlvl_delay Configuration 2 Register
 600     volatile uint32 DFITRRDLVLDELAY0;         //DFI Training dif_rdlvl_delay Configuration 0 Register
 601     volatile uint32 DFITRRDLVLDELAY1;         //DFI Training dif_rdlvl_delay Configuration 1 Register
 602     volatile uint32 DFITRRDLVLDELAY2;         //DFI Training dif_rdlvl_delay Configuration 2 Register
 603     volatile uint32 DFITRRDLVLGATEDELAY0;     //DFI Training dif_rdlvl_gate_delay Configuration 0 Register
 604     volatile uint32 DFITRRDLVLGATEDELAY1;     //DFI Training dif_rdlvl_gate_delay Configuration 1 Register
 605     volatile uint32 DFITRRDLVLGATEDELAY2;     //DFI Training dif_rdlvl_gate_delay Configuration 2 Register
 606     volatile uint32 DFITRCMD;                 //DFI Training Command Register
 607     uint32 reserved14[(0x3f8-0x340)/4];
 608     //IP Status Registers
 609     volatile uint32 IPVR;                     //IP Version Register
 610     volatile uint32 IPTR;                     //IP Type Register
 611 }DDR_REG_T, *pDDR_REG_T;
 612
 613 /*
 614  * PUBL
 615  */
 616 //PIR
 617 #define INIT                 (1<<0)
 618 #define DLLSRST              (1<<1)
 619 #define DLLLOCK              (1<<2)
 620 #define ZCAL                 (1<<3)
 621 #define ITMSRST              (1<<4)
 622 #define DRAMRST              (1<<5)
 623 #define DRAMINIT             (1<<6)
 624 #define QSTRN                (1<<7)
 625 #define EYETRN               (1<<8)
 626 #define ICPC                 (1<<16)
 627 #define DLLBYP               (1<<17)
 628 #define CTLDINIT             (1<<18)
 629 #define CLRSR                (1<<28)
 630 #define LOCKBYP              (1<<29)
 631 #define ZCALBYP              (1<<30)
 632 #define INITBYP              (1u<<31)
 633
 634 //PGCR
 635 #define DFTLMT(n)            ((n)<<3)
 636 #define DFTCMP(n)            ((n)<<2)
 637 #define DQSCFG(n)            ((n)<<1)
 638 #define ITMDMD(n)            ((n)<<0)
 639 #define RANKEN(n)            ((n)<<18)
 640
 641 //PGSR
 642 #define IDONE                (1<<0)
 643 #define DLDONE               (1<<1)
 644 #define ZCDONE               (1<<2)
 645 #define DIDONE               (1<<3)
 646 #define DTDONE               (1<<4)
 647 #define DTERR                (1<<5)
 648 #define DTIERR               (1<<6)
 649 #define DFTERR               (1<<7)
 650 #define TQ                   (1u<<31)
 651
 652 //PTR0
 653 #define tITMSRST(n)          ((n)<<18)
 654 #define tDLLLOCK(n)          ((n)<<6)
 655 #define tDLLSRST(n)          ((n)<<0)
 656
 657 //PTR1
 658 #define tDINIT1(n)           ((n)<<19)
 659 #define tDINIT0(n)           ((n)<<0)
 660
 661 //PTR2
 662 #define tDINIT3(n)           ((n)<<17)
 663 #define tDINIT2(n)           ((n)<<0)
 664
 665 //DSGCR
 666 #define DQSGE(n)             ((n)<<8)
 667 #define DQSGX(n)             ((n)<<5)
 668
 669 typedef union DCR_Tag
 670 {
 671     uint32 d32;
 672     struct
 673     {
 674         unsigned DDRMD : 3;
 675         unsigned DDR8BNK : 1;
 676         unsigned PDQ : 3;
 677         unsigned MPRDQ : 1;
 678         unsigned DDRTYPE : 2;
 679         unsigned reserved10_26 : 17;
 680         unsigned NOSRA : 1;
 681         unsigned DDR2T : 1;
 682         unsigned UDIMM : 1;
 683         unsigned RDIMM : 1;
 684         unsigned TPD : 1;
 685     } b;
 686 }DCR_T;
 687
 688 typedef volatile struct DATX8_REG_Tag
 689 {
 690     volatile uint32 DXGCR;                 //DATX8 General Configuration Register
 691     volatile uint32 DXGSR[2];              //DATX8 General Status Register
 692     volatile uint32 DXDLLCR;               //DATX8 DLL Control Register
 693     volatile uint32 DXDQTR;                //DATX8 DQ Timing Register
 694     volatile uint32 DXDQSTR;               //DATX8 DQS Timing Register
 695     uint32 reserved[0x80-0x76];
 696 }DATX8_REG_T;
 697
 698 /* DDR PHY register struct */
 699 typedef volatile struct DDRPHY_REG_Tag
 700 {
 701     volatile uint32 RIDR;                   //Revision Identification Register
 702     volatile uint32 PIR;                    //PHY Initialization Register
 703     volatile uint32 PGCR;                   //PHY General Configuration Register
 704     volatile uint32 PGSR;                   //PHY General Status Register
 705     volatile uint32 DLLGCR;                 //DLL General Control Register
 706     volatile uint32 ACDLLCR;                //AC DLL Control Register
 707     volatile uint32 PTR[3];                 //PHY Timing Registers 0-2
 708     volatile uint32 ACIOCR;                 //AC I/O Configuration Register
 709     volatile uint32 DXCCR;                  //DATX8 Common Configuration Register
 710     volatile uint32 DSGCR;                  //DDR System General Configuration Register
 711     DCR_T DCR;                    //DRAM Configuration Register
 712     volatile uint32 DTPR[3];                //DRAM Timing Parameters Register 0-2
 713     volatile uint32 MR[4];                    //Mode Register 0-3
 714     volatile uint32 ODTCR;                  //ODT Configuration Register
 715     volatile uint32 DTAR;                   //Data Training Address Register
 716     volatile uint32 DTDR[2];                //Data Training Data Register 0-1
 717
 718     uint32 reserved1[0x30-0x18];
 719     uint32 DCU[0x38-0x30];
 720     uint32 reserved2[0x40-0x38];
 721     uint32 BIST[0x51-0x40];
 722     uint32 reserved3[0x60-0x51];
 723
 724     volatile uint32 ZQ0CR[2];               //ZQ 0 Impedance Control Register 0-1
 725     volatile uint32 ZQ0SR[2];               //ZQ 0 Impedance Status Register 0-1
 726     volatile uint32 ZQ1CR[2];               //ZQ 1 Impedance Control Register 0-1
 727     volatile uint32 ZQ1SR[2];               //ZQ 1 Impedance Status Register 0-1
 728     volatile uint32 ZQ2CR[2];               //ZQ 2 Impedance Control Register 0-1
 729     volatile uint32 ZQ2SR[2];               //ZQ 2 Impedance Status Register 0-1
 730     volatile uint32 ZQ3CR[2];               //ZQ 3 Impedance Control Register 0-1
 731     volatile uint32 ZQ3SR[2];               //ZQ 3 Impedance Status Register 0-1
 732
 733     DATX8_REG_T     DATX8[9];               //DATX8 Register
 734 }DDRPHY_REG_T, *pDDRPHY_REG_T;
 735
 736 typedef union NOC_TIMING_Tag
 737 {
 738     uint32 d32;
 739     struct
 740     {
 741         unsigned ActToAct : 6;
 742         unsigned RdToMiss : 6;
 743         unsigned WrToMiss : 6;
 744         unsigned BurstLen : 3;
 745         unsigned RdToWr : 5;
 746         unsigned WrToRd : 5;
 747         unsigned BwRatio : 1;
 748     } b;
 749 }NOC_TIMING_T;
 750
 751 typedef union NOC_ACTIVATE_Tag
 752 {
 753     uint32 d32;
 754     struct
 755     {
 756         unsigned Rrd : 4;  //bit[0:3]
 757         unsigned Faw : 6;  //bit[4:9]
 758         unsigned Fawbank : 1; //bit 10
 759         unsigned reserved : 21;
 760     } b;
 761 }NOC_ACTIVATE_T;
 762
 763 typedef volatile struct MSCH_REG_Tag
 764 {
 765     volatile uint32 coreid;
 766     volatile uint32 revisionid;
 767     volatile uint32 ddrconf;
 768     volatile NOC_TIMING_T ddrtiming;
 769     volatile uint32 ddrmode;
 770     volatile uint32 readlatency;
 771     uint32 reserved1[(0x38-0x18)/4];
 772     volatile NOC_ACTIVATE_T activate;
 773     volatile uint32 devtodev;
 774 }MSCH_REG, *pMSCH_REG;
 775
 776 #define CH_MAX                 (2)
 777 #define DRAM_PHYS              (0)   //DRAM Channel a physical address start
 778 #define pPMU_Reg               ((pPMU_FILE)RK_PMU_VIRT)
 779 #define pCRU_Reg               ((pCRU_REG)RK_CRU_VIRT)
 780 #define pGRF_Reg               ((pREG_FILE)RK_GRF_VIRT)
 781 #define pDDR_REG(ch)           ((ch) ? ((pDDR_REG_T)(RK_DDR_VIRT + RK3288_DDR_PCTL_SIZE + RK3288_DDR_PUBL_SIZE)):((pDDR_REG_T)RK_DDR_VIRT))
 782 #define pPHY_REG(ch)           ((ch) ? ((pDDRPHY_REG_T)(RK_DDR_VIRT + 2 * RK3288_DDR_PCTL_SIZE + RK3288_DDR_PUBL_SIZE)) : ((pDDRPHY_REG_T)(RK_DDR_VIRT + RK3288_DDR_PCTL_SIZE)))
 783 #define pMSCH_REG(ch)          ((ch)? ((pMSCH_REG)(RK3288_SERVICE_BUS_VIRT+0x80)):((pMSCH_REG)(RK3288_SERVICE_BUS_VIRT)))
 784 #define GET_DDR3_DS_ODT()      ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
 785 #define GET_LPDDR2_DS_ODT()    ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
 786 #define GET_LPDDR3_DS_ODT()    ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
 787 #define DDR_GET_RANK_2_ROW15() (0)
 788 #define DDR_GET_BANK_2_RANK()  (0)
 789 #define DDR_HW_WAKEUP(ch,en)   do{pGRF_Reg->GRF_SOC_CON[0] = (1<<(16+5+ch)) | (en<<(5+ch));}while(0)
 790 #define READ_GRF_REG()         (pGRF_Reg->GRF_SOC_CON[0])
 791 #define GET_DPLL_LOCK_STATUS() (pGRF_Reg->GRF_SOC_STATUS[1] & (1<<5))
 792 #define SET_DDR_PLL_SRC(src, div)   do{pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3|(0x1<<2))<<16)|(src<<2)| div;}while(0)
 793 #define GET_DDR_PLL_SRC()           ((pCRU_Reg->CRU_CLKSEL_CON[26]&(1<<2)) ? GPLL : DPLL)
 794 #define DDR_GPLL_CLK_GATE(en)       do{pCRU_Reg->CRU_CLKGATE_CON[0] = 0x02000000 | (en<<9);}while(0)
 795 #define SET_DDRPHY_CLKGATE(ch,dis)  do{pCRU_Reg->CRU_CLKGATE_CON[4] = ((0x1<<(12+ch))<<16) | (dis<<(12+ch));}while(0)
 796 #define READ_DDR_STRIDE()           (readl_relaxed(RK_SGRF_VIRT+0x8) &0x1F)
 797
 798 #define READ_CH_CNT()         (1+((pPMU_Reg->PMU_PMU_SYS_REG[2]>>12)&0x1))
 799 #define READ_CH_INFO()        ((pPMU_Reg->PMU_PMU_SYS_REG[2]>>28)&0x3)
 800 #define READ_CH_ROW_INFO(ch)  ((pPMU_Reg->PMU_PMU_SYS_REG[2]>>(30+(ch)))&0x1)    //row_3_4:0=normal, 1=6Gb or 12Gb
 801
 802 #define SET_PLL_MODE(pll, mode) do{pCRU_Reg->CRU_MODE_CON = ((mode<<((pll)*4))|(0x3<<(16+(pll)*4)));}while(0)
 803 #define SET_PLL_PD(pll, pd)     do{pCRU_Reg->CRU_PLL_CON[pll][3] = ((0x1<<1)<<16) | (pd<<1);}while(0)
 804
 805 #define READ_DRAMTYPE_INFO()    ((pPMU_Reg->PMU_PMU_SYS_REG[2]>>13)&0x7)
 806 #define READ_CS_INFO(ch)        ((((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(11+(ch)*16))&0x1)+1)
 807 #define READ_BW_INFO(ch)        (2>>(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(2+(ch)*16))&0x3))
 808 #define READ_COL_INFO(ch)       (9+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(9+(ch)*16))&0x3))
 809 #define READ_BK_INFO(ch)        (3-(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(8+(ch)*16))&0x1))
 810 #define READ_ROW_INFO(ch,cs)    (13+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(6-(2*cs)+(ch)*16))&0x3))
 811 #define READ_DIE_BW_INFO(ch)    (2>>((pPMU_Reg->PMU_PMU_SYS_REG[2]>>((ch)*16))&0x3))
 812
 813 static const uint16_t  ddr_cfg_2_rbc[] =
 814 {
 815     /****************************/
 816     // [8:7]  bank(n:n bit bank)
 817     // [6:4]  row(12+n)
 818     // [3:2]  bank(n:n bit bank)
 819     // [1:0]  col(9+n)
 820     /****************************/
 821     //all config have (13col,3bank,16row,1cs)
 822     //bank,  row,   bank, col          col bank row(32bit)
 823     ((3<<7)|(3<<4)|(0<<2)|2),  // 0     11   8   15
 824     ((0<<7)|(1<<4)|(3<<2)|1),  // 1     10   8   13
 825     ((0<<7)|(2<<4)|(3<<2)|1),  // 2     10   8   14
 826     ((0<<7)|(3<<4)|(3<<2)|1),  // 3     10   8   15
 827     ((0<<7)|(4<<4)|(3<<2)|1),  // 4     10   8   16
 828     ((0<<7)|(1<<4)|(3<<2)|2),  // 5     11   8   13  // 32bit not use
 829     ((0<<7)|(2<<4)|(3<<2)|2),  // 6     11   8   14
 830     ((0<<7)|(3<<4)|(3<<2)|2),  // 7     11   8   15
 831     ((0<<7)|(1<<4)|(3<<2)|0),  // 8     9    8   13
 832     ((0<<7)|(2<<4)|(3<<2)|0),  // 9     9    8   14
 833     ((0<<7)|(3<<4)|(3<<2)|0),  // 10    9    8   15
 834     ((0<<7)|(2<<4)|(2<<2)|0),  // 11    9    4   14
 835     ((0<<7)|(1<<4)|(2<<2)|1),  // 12    10   4   13
 836     ((0<<7)|(0<<4)|(2<<2)|2),  // 13    11   4   12
 837     ((3<<7)|(4<<4)|(0<<2)|1),  // 14    10   8   16 / 10, 4,15 / 10, 8, 15
 838     ((0<<7)|(4<<4)|(3<<2)|2),  // 15    11   8   16
 839 };
 840
 841 /***********************************
 842  * LPDDR2 define
 843  ***********************************/
 844 //MR0 (Device Information)
 845 #define  LPDDR2_DAI    (0x1)        // 0:DAI complete, 1:DAI still in progress
 846 #define  LPDDR2_DI     (0x1<<1)     // 0:S2 or S4 SDRAM, 1:NVM
 847 #define  LPDDR2_DNVI   (0x1<<2)     // 0:DNV not supported, 1:DNV supported
 848 #define  LPDDR2_RZQI   (0x3<<3)     // 00:RZQ self test not supported, 01:ZQ-pin may connect to VDDCA or float
 849                                     // 10:ZQ-pin may short to GND.     11:ZQ-pin self test completed, no error condition detected.
 850
 851 //MR1 (Device Feature)
 852 #define LPDDR2_BL4     (0x2)
 853 #define LPDDR2_BL8     (0x3)
 854 #define LPDDR2_BL16    (0x4)
 855 #define LPDDR2_nWR(n)  (((n)-2)<<5)
 856
 857 //MR2 (Device Feature 2)
 858 #define LPDDR2_RL3_WL1  (0x1)
 859 #define LPDDR2_RL4_WL2  (0x2)
 860 #define LPDDR2_RL5_WL2  (0x3)
 861 #define LPDDR2_RL6_WL3  (0x4)
 862 #define LPDDR2_RL7_WL4  (0x5)
 863 #define LPDDR2_RL8_WL4  (0x6)
 864
 865 //MR3 (IO Configuration 1)
 866 #define LPDDR2_DS_34    (0x1)
 867 #define LPDDR2_DS_40    (0x2)
 868 #define LPDDR2_DS_48    (0x3)
 869 #define LPDDR2_DS_60    (0x4)
 870 #define LPDDR2_DS_80    (0x6)
 871 #define LPDDR2_DS_120   (0x7)   //optional
 872
 873 //MR4 (Device Temperature)
 874 #define LPDDR2_tREF_MASK (0x7)
 875 #define LPDDR2_4_tREF    (0x1)
 876 #define LPDDR2_2_tREF    (0x2)
 877 #define LPDDR2_1_tREF    (0x3)
 878 #define LPDDR2_025_tREF  (0x5)
 879 #define LPDDR2_025_tREF_DERATE    (0x6)
 880
 881 #define LPDDR2_TUF       (0x1<<7)
 882
 883 //MR8 (Basic configuration 4)
 884 #define LPDDR2_S4        (0x0)
 885 #define LPDDR2_S2        (0x1)
 886 #define LPDDR2_N         (0x2)
 887 #define LPDDR2_Density(mr8)  (8<<(((mr8)>>2)&0xf))   // Unit:MB
 888 #define LPDDR2_IO_Width(mr8) (32>>(((mr8)>>6)&0x3))
 889
 890 //MR10 (Calibration)
 891 #define LPDDR2_ZQINIT   (0xFF)
 892 #define LPDDR2_ZQCL     (0xAB)
 893 #define LPDDR2_ZQCS     (0x56)
 894 #define LPDDR2_ZQRESET  (0xC3)
 895
 896 //MR16 (PASR Bank Mask)
 897 // S2 SDRAM Only
 898 #define LPDDR2_PASR_Full (0x0)
 899 #define LPDDR2_PASR_1_2  (0x1)
 900 #define LPDDR2_PASR_1_4  (0x2)
 901 #define LPDDR2_PASR_1_8  (0x3)
 902
 903 //MR17 (PASR Segment Mask) 1Gb-8Gb S4 SDRAM only
 904
 905 //MR32 (DQ Calibration Pattern A)
 906
 907 //MR40 (DQ Calibration Pattern B)
 908
 909 /***********************************
 910  * LPDDR3 define
 911  ***********************************/
 912 //MR0 (Device Information)
 913 #define  LPDDR3_DAI    (0x1)        // 0:DAI complete, 1:DAI still in progress
 914 #define  LPDDR3_RZQI   (0x3<<3)     // 00:RZQ self test not supported, 01:ZQ-pin may connect to VDDCA or float
 915                                     // 10:ZQ-pin may short to GND.     11:ZQ-pin self test completed, no error condition detected.
 916 #define  LPDDR3_WL_SUPOT (1<<6)     // 0:DRAM does not support WL(Set B), 1:DRAM support WL(Set B)
 917 #define  LPDDR3_RL3_SUPOT (1<<7)    // 0:DRAM does not support RL=3,nWR=3,WL=1; 1:DRAM supports RL=3,nWR=3,WL=1 for frequencies <=166
 918
 919 //MR1 (Device Feature)
 920 #define LPDDR3_BL8     (0x3)
 921 #define LPDDR3_nWR(n)  ((n)<<5)
 922
 923 //MR2 (Device Feature 2)
 924 //WL Set A,default
 925 #define LPDDR3_RL3_WL1   (0x1)       // <=166MHz,optional
 926 #define LPDDR3_RL6_WL3   (0x4)       // <=400MHz
 927 #define LPDDR3_RL8_WL4   (0x6)       // <=533MHz
 928 #define LPDDR3_RL9_WL5   (0x7)       // <=600MHz
 929 #define LPDDR3_RL10_WL6  (0x8)       // <=667MHz,default
 930 #define LPDDR3_RL11_WL6  (0x9)       // <=733MHz
 931 #define LPDDR3_RL12_WL6  (0xa)       // <=800MHz
 932 #define LPDDR3_RL14_WL8  (0xc)       // <=933MHz
 933 #define LPDDR3_RL16_WL8  (0xe)       // <=1066MHz
 934 //WL Set B, optional
 935 //#define LPDDR3_RL3_WL1   (0x1)       // <=166MHz,optional
 936 //#define LPDDR3_RL6_WL3   (0x4)       // <=400MHz
 937 //#define LPDDR3_RL8_WL4   (0x6)       // <=533MHz
 938 //#define LPDDR3_RL9_WL5   (0x7)       // <=600MHz
 939 #define LPDDR3_RL10_WL8  (0x8)       // <=667MHz,default
 940 #define LPDDR3_RL11_WL9  (0x9)       // <=733MHz
 941 #define LPDDR3_RL12_WL9  (0xa)       // <=800MHz
 942 #define LPDDR3_RL14_WL11 (0xc)       // <=933MHz
 943 #define LPDDR3_RL16_WL13 (0xe)       // <=1066MHz
 944
 945 #define LPDDR3_nWRE      (1<<4)      // 1:enable nWR programming > 9(defualt)
 946 #define LPDDR3_WL_S      (1<<6)      // 1:Select WL Set B
 947 #define LPDDR3_WR_LEVEL  (1<<7)      // 1:enable
 948
 949 //MR3 (IO Configuration 1)
 950 #define LPDDR3_DS_34    (0x1)
 951 #define LPDDR3_DS_40    (0x2)
 952 #define LPDDR3_DS_48    (0x3)
 953 #define LPDDR3_DS_60    (0x4)        //reserved
 954 #define LPDDR3_DS_80    (0x6)        //reserved
 955 #define LPDDR3_DS_34D_40U   (0x9)
 956 #define LPDDR3_DS_40D_48U   (0xa)
 957 #define LPDDR3_DS_34D_48U   (0xb)
 958
 959 //MR4 (Device Temperature)
 960 #define LPDDR3_tREF_MASK (0x7)
 961 #define LPDDR3_LT_EXED   (0x0)       // SDRAM Low temperature operating limit exceeded
 962 #define LPDDR3_4_tREF    (0x1)
 963 #define LPDDR3_2_tREF    (0x2)
 964 #define LPDDR3_1_tREF    (0x3)
 965 #define LPDDR3_05_tREF   (0x4)
 966 #define LPDDR3_025_tREF  (0x5)
 967 #define LPDDR3_025_tREF_DERATE    (0x6)
 968 #define LPDDR3_HT_EXED   (0x7)       // SDRAM High temperature operating limit exceeded
 969
 970 #define LPDDR3_TUF       (0x1<<7)    // 1:value has changed since last read of MR4
 971
 972 //MR8 (Basic configuration 4)
 973 #define LPDDR3_S8        (0x3)
 974 #define LPDDR3_Density(mr8)  (8<<((mr8>>2)&0xf))   // Unit:MB
 975 #define LPDDR3_IO_Width(mr8) (32>>((mr8>>6)&0x3))
 976
 977 //MR10 (Calibration)
 978 #define LPDDR3_ZQINIT   (0xFF)
 979 #define LPDDR3_ZQCL     (0xAB)
 980 #define LPDDR3_ZQCS     (0x56)
 981 #define LPDDR3_ZQRESET  (0xC3)
 982
 983 //MR11 (ODT Control)
 984 #define LPDDR3_ODT_60   (1)           //optional for 1333 and 1600
 985 #define LPDDR3_ODT_120  (2)
 986 #define LPDDR3_ODT_240  (3)
 987 #define LPDDR3_ODT_DIS  (0)
 988
 989 //MR16 (PASR Bank Mask)
 990
 991 //MR17 (PASR Segment Mask) 1Gb-8Gb S4 SDRAM only
 992
 993 //MR32 (DQ Calibration Pattern A)
 994
 995 //MR40 (DQ Calibration Pattern B)
 996
 997 /***********************************
 998  * DDR3 define
 999  ***********************************/
1000 //mr0 for ddr3
1001 #define DDR3_BL8          (0)
1002 #define DDR3_BC4_8        (1)
1003 #define DDR3_BC4          (2)
1004 #define DDR3_CL(n)        (((((n)-4)&0x7)<<4)|((((n)-4)&0x8)>>1))
1005 #define DDR3_WR(n)        (((n)&0x7)<<9)
1006 #define DDR3_DLL_RESET    (1<<8)
1007 #define DDR3_DLL_DeRESET  (0<<8)
1008
1009 //mr1 for ddr3
1010 #define DDR3_DLL_ENABLE    (0)
1011 #define DDR3_DLL_DISABLE   (1)
1012 #define DDR3_MR1_AL(n)  (((n)&0x3)<<3)
1013
1014 #define DDR3_DS_40            (0)
1015 #define DDR3_DS_34            (1<<1)
1016 #define DDR3_Rtt_Nom_DIS      (0)
1017 #define DDR3_Rtt_Nom_60       (1<<2)
1018 #define DDR3_Rtt_Nom_120      (1<<6)
1019 #define DDR3_Rtt_Nom_40       ((1<<2)|(1<<6))
1020
1021     //mr2 for ddr3
1022 #define DDR3_MR2_CWL(n) ((((n)-5)&0x7)<<3)
1023 #define DDR3_Rtt_WR_DIS       (0)
1024 #define DDR3_Rtt_WR_60        (1<<9)
1025 #define DDR3_Rtt_WR_120       (2<<9)
1026
1027 /***********************************
1028  * DDR2 define
1029  ***********************************/
1030 //MR;                     //Mode Register
1031 #define DDR2_BL4           (2)
1032 #define DDR2_BL8           (3)
1033 #define DDR2_CL(n)         (((n)&0x7)<<4)
1034 #define DDR2_WR(n)        ((((n)-1)&0x7)<<9)
1035 #define DDR2_DLL_RESET    (1<<8)
1036 #define DDR2_DLL_DeRESET  (0<<8)
1037
1038 //EMR;                    //Extended Mode Register
1039 #define DDR2_DLL_ENABLE    (0)
1040 #define DDR2_DLL_DISABLE   (1)
1041
1042 #define DDR2_STR_FULL     (0)
1043 #define DDR2_STR_REDUCE   (1<<1)
1044 #define DDR2_AL(n)        (((n)&0x7)<<3)
1045 #define DDR2_Rtt_Nom_DIS      (0)
1046 #define DDR2_Rtt_Nom_150      (0x40)
1047 #define DDR2_Rtt_Nom_75       (0x4)
1048 #define DDR2_Rtt_Nom_50       (0x44)
1049
1050 /***********************************
1051  * LPDDR define
1052  ***********************************/
1053 #define mDDR_BL2           (1)
1054 #define mDDR_BL4           (2)
1055 #define mDDR_BL8           (3)
1056 #define mDDR_CL(n)         (((n)&0x7)<<4)
1057
1058 #define mDDR_DS_Full       (0)
1059 #define mDDR_DS_1_2        (1<<5)
1060 #define mDDR_DS_1_4        (2<<5)
1061 #define mDDR_DS_1_8        (3<<5)
1062 #define mDDR_DS_3_4        (4<<5)
1063
1064 static const uint8_t ddr3_cl_cwl[22][7]={
1065 /*speed   0~330         331~400       401~533        534~666       667~800        801~933      934~1066
1066  * tCK    >3            2.5~3         1.875~2.5      1.5~1.875     1.25~1.5       1.07~1.25    0.938~1.07
1067  *        cl<<4, cwl    cl<<4, cwl    cl<<4, cwl              */
1068          {((5<<4)|5),   ((5<<4)|5),   0         ,    0,            0,             0,            0}, //DDR3_800D (5-5-5)
1069          {((5<<4)|5),   ((6<<4)|5),   0         ,    0,            0,             0,            0}, //DDR3_800E (6-6-6)
1070
1071          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    0,            0,             0,            0}, //DDR3_1066E (6-6-6)
1072          {((5<<4)|5),   ((6<<4)|5),   ((7<<4)|6),    0,            0,             0,            0}, //DDR3_1066F (7-7-7)
1073          {((5<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    0,            0,             0,            0}, //DDR3_1066G (8-8-8)
1074
1075          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((7<<4)|7),   0,             0,            0}, //DDR3_1333F (7-7-7)
1076          {((5<<4)|5),   ((5<<4)|5),   ((7<<4)|6),    ((8<<4)|7),   0,             0,            0}, //DDR3_1333G (8-8-8)
1077          {((5<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((9<<4)|7),   0,             0,            0}, //DDR3_1333H (9-9-9)
1078          {((5<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((10<<4)|7),  0,             0,            0}, //DDR3_1333J (10-10-10)
1079
1080          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((7<<4)|7),   ((8<<4)|8),    0,            0}, //DDR3_1600G (8-8-8)
1081          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((8<<4)|7),   ((9<<4)|8),    0,            0}, //DDR3_1600H (9-9-9)
1082          {((5<<4)|5),   ((5<<4)|5),   ((7<<4)|6),    ((9<<4)|7),   ((10<<4)|8),   0,            0}, //DDR3_1600J (10-10-10)
1083          {((5<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((10<<4)|7),  ((11<<4)|8),   0,            0}, //DDR3_1600K (11-11-11)
1084
1085          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((8<<4)|7),   ((9<<4)|8),    ((11<<4)|9),  0}, //DDR3_1866J (10-10-10)
1086          {((5<<4)|5),   ((5<<4)|5),   ((7<<4)|6),    ((8<<4)|7),   ((10<<4)|8),   ((11<<4)|9),  0}, //DDR3_1866K (11-11-11)
1087          {((6<<4)|5),   ((6<<4)|5),   ((7<<4)|6),    ((9<<4)|7),   ((11<<4)|8),   ((12<<4)|9),  0}, //DDR3_1866L (12-12-12)
1088          {((6<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((10<<4)|7),  ((11<<4)|8),   ((13<<4)|9),  0}, //DDR3_1866M (13-13-13)
1089
1090          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((7<<4)|7),   ((9<<4)|8),    ((10<<4)|9),  ((11<<4)|10)}, //DDR3_2133K (11-11-11)
1091          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((8<<4)|7),   ((9<<4)|8),    ((11<<4)|9),  ((12<<4)|10)}, //DDR3_2133L (12-12-12)
1092          {((5<<4)|5),   ((5<<4)|5),   ((7<<4)|6),    ((9<<4)|7),   ((10<<4)|8),   ((12<<4)|9),  ((13<<4)|10)}, //DDR3_2133M (13-13-13)
1093          {((6<<4)|5),   ((6<<4)|5),   ((7<<4)|6),    ((9<<4)|7),   ((11<<4)|8),   ((13<<4)|9),  ((14<<4)|10)},  //DDR3_2133N (14-14-14)
1094
1095          {((6<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((10<<4)|7),  ((11<<4)|8),   ((13<<4)|9),  ((14<<4)|10)} //DDR3_DEFAULT
1096 };
1097
1098 static const uint16_t ddr3_tRC_tFAW[22]={
1099 /**    tRC    tFAW   */
1100     ((50<<8)|50), //DDR3_800D (5-5-5)
1101     ((53<<8)|50), //DDR3_800E (6-6-6)
1102
1103     ((49<<8)|50), //DDR3_1066E (6-6-6)
1104     ((51<<8)|50), //DDR3_1066F (7-7-7)
1105     ((53<<8)|50), //DDR3_1066G (8-8-8)
1106
1107     ((47<<8)|45), //DDR3_1333F (7-7-7)
1108     ((48<<8)|45), //DDR3_1333G (8-8-8)
1109     ((50<<8)|45), //DDR3_1333H (9-9-9)
1110     ((51<<8)|45), //DDR3_1333J (10-10-10)
1111
1112     ((45<<8)|40), //DDR3_1600G (8-8-8)
1113     ((47<<8)|40), //DDR3_1600H (9-9-9)
1114     ((48<<8)|40), //DDR3_1600J (10-10-10)
1115     ((49<<8)|40), //DDR3_1600K (11-11-11)
1116
1117     ((45<<8)|35), //DDR3_1866J (10-10-10)
1118     ((46<<8)|35), //DDR3_1866K (11-11-11)
1119     ((47<<8)|35), //DDR3_1866L (12-12-12)
1120     ((48<<8)|35), //DDR3_1866M (13-13-13)
1121
1122     ((44<<8)|35), //DDR3_2133K (11-11-11)
1123     ((45<<8)|35), //DDR3_2133L (12-12-12)
1124     ((46<<8)|35), //DDR3_2133M (13-13-13)
1125     ((47<<8)|35), //DDR3_2133N (14-14-14)
1126
1127     ((53<<8)|50)  //DDR3_DEFAULT
1128 };
1129
1130 typedef enum DRAM_TYPE_Tag
1131 {
1132     LPDDR = 0,
1133     DDR,
1134     DDR2,
1135     DDR3,
1136     LPDDR2,
1137     LPDDR3,
1138
1139     DRAM_MAX
1140 }DRAM_TYPE;
1141
1142 typedef struct PCTRL_TIMING_Tag
1143 {
1144     uint32 ddrFreq;
1145     //Memory Timing Registers
1146     uint32 togcnt1u;               //Toggle Counter 1U Register
1147     uint32 tinit;                  //t_init Timing Register
1148     uint32 trsth;                  //Reset High Time Register
1149     uint32 togcnt100n;             //Toggle Counter 100N Register
1150     uint32 trefi;                  //t_refi Timing Register
1151     uint32 tmrd;                   //t_mrd Timing Register
1152     uint32 trfc;                   //t_rfc Timing Register
1153     uint32 trp;                    //t_rp Timing Register
1154     uint32 trtw;                   //t_rtw Timing Register
1155     uint32 tal;                    //AL Latency Register
1156     uint32 tcl;                    //CL Timing Register
1157     uint32 tcwl;                   //CWL Register
1158     uint32 tras;                   //t_ras Timing Register
1159     uint32 trc;                    //t_rc Timing Register
1160     uint32 trcd;                   //t_rcd Timing Register
1161     uint32 trrd;                   //t_rrd Timing Register
1162     uint32 trtp;                   //t_rtp Timing Register
1163     uint32 twr;                    //t_wr Timing Register
1164     uint32 twtr;                   //t_wtr Timing Register
1165     uint32 texsr;                  //t_exsr Timing Register
1166     uint32 txp;                    //t_xp Timing Register
1167     uint32 txpdll;                 //t_xpdll Timing Register
1168     uint32 tzqcs;                  //t_zqcs Timing Register
1169     uint32 tzqcsi;                 //t_zqcsi Timing Register
1170     uint32 tdqs;                   //t_dqs Timing Register
1171     uint32 tcksre;                 //t_cksre Timing Register
1172     uint32 tcksrx;                 //t_cksrx Timing Register
1173     uint32 tcke;                   //t_cke Timing Register
1174     uint32 tmod;                   //t_mod Timing Register
1175     uint32 trstl;                  //Reset Low Timing Register
1176     uint32 tzqcl;                  //t_zqcl Timing Register
1177     uint32 tmrr;                   //t_mrr Timing Register
1178     uint32 tckesr;                 //t_ckesr Timing Register
1179     uint32 tdpd;                   //t_dpd Timing Register
1180 }PCTL_TIMING_T;
1181
1182 typedef union DTPR_0_Tag
1183 {
1184     uint32 d32;
1185     struct
1186     {
1187         unsigned tMRD : 2;
1188         unsigned tRTP : 3;
1189         unsigned tWTR : 3;
1190         unsigned tRP : 4;
1191         unsigned tRCD : 4;
1192         unsigned tRAS : 5;
1193         unsigned tRRD : 4;
1194         unsigned tRC : 6;
1195         unsigned tCCD : 1;
1196     } b;
1197 }DTPR_0_T;
1198
1199 typedef union DTPR_1_Tag
1200 {
1201     uint32 d32;
1202     struct
1203     {
1204         unsigned tAOND : 2;
1205         unsigned tRTW : 1;
1206         unsigned tFAW : 6;
1207         unsigned tMOD : 2;
1208         unsigned tRTODT : 1;
1209         unsigned reserved12_15 : 4;
1210         unsigned tRFC : 8;
1211         unsigned tDQSCK : 3;
1212         unsigned tDQSCKmax : 3;
1213         unsigned reserved30_31 : 2;
1214     } b;
1215 }DTPR_1_T;
1216
1217 typedef union DTPR_2_Tag
1218 {
1219     uint32 d32;
1220     struct
1221     {
1222         unsigned tXS : 10;
1223         unsigned tXP : 5;
1224         unsigned tCKE : 4;
1225         unsigned tDLLK : 10;
1226         unsigned reserved29_31 : 3;
1227     } b;
1228 }DTPR_2_T;
1229
1230 typedef struct PHY_TIMING_Tag
1231 {
1232     DTPR_0_T  dtpr0;
1233     DTPR_1_T  dtpr1;
1234     DTPR_2_T  dtpr2;
1235     uint32    mr[4];   //LPDDR2 no MR0, mr[2] is mDDR MR1
1236     uint32    mr11;    //for LPDDR3 only
1237 }PHY_TIMING_T;
1238
1239 typedef struct PCTL_REG_Tag
1240 {
1241     uint32 SCFG;
1242     uint32 CMDTSTATEN;
1243     uint32 MCFG1;
1244     uint32 MCFG;
1245     PCTL_TIMING_T pctl_timing;
1246     //DFI Control Registers
1247     uint32 DFITCTRLDELAY;
1248     uint32 DFIODTCFG;
1249     uint32 DFIODTCFG1;
1250     uint32 DFIODTRANKMAP;
1251     //DFI Write Data Registers
1252     uint32 DFITPHYWRDATA;
1253     uint32 DFITPHYWRLAT;
1254     //DFI Read Data Registers
1255     uint32 DFITRDDATAEN;
1256     uint32 DFITPHYRDLAT;
1257     //DFI Update Registers
1258     uint32 DFITPHYUPDTYPE0;
1259     uint32 DFITPHYUPDTYPE1;
1260     uint32 DFITPHYUPDTYPE2;
1261     uint32 DFITPHYUPDTYPE3;
1262     uint32 DFITCTRLUPDMIN;
1263     uint32 DFITCTRLUPDMAX;
1264     uint32 DFITCTRLUPDDLY;
1265     uint32 DFIUPDCFG;
1266     uint32 DFITREFMSKI;
1267     uint32 DFITCTRLUPDI;
1268     //DFI Status Registers
1269     uint32 DFISTCFG0;
1270     uint32 DFISTCFG1;
1271     uint32 DFITDRAMCLKEN;
1272     uint32 DFITDRAMCLKDIS;
1273     uint32 DFISTCFG2;
1274     //DFI Low Power Register
1275     uint32 DFILPCFG0;
1276 }PCTL_REG_T;
1277
1278 typedef struct PUBL_DQS_REG_Tag
1279 {
1280     uint32 DX0GCR;
1281     uint32 DX0DLLCR;
1282     uint32 DX0DQTR;
1283     uint32 DX0DQSTR;
1284
1285     uint32 DX1GCR;
1286     uint32 DX1DLLCR;
1287     uint32 DX1DQTR;
1288     uint32 DX1DQSTR;
1289
1290     uint32 DX2GCR;
1291     uint32 DX2DLLCR;
1292     uint32 DX2DQTR;
1293     uint32 DX2DQSTR;
1294
1295     uint32 DX3GCR;
1296     uint32 DX3DLLCR;
1297     uint32 DX3DQTR;
1298     uint32 DX3DQSTR;
1299 }PUBL_DQS_REG;
1300
1301 typedef struct PUBL_REG_Tag
1302 {
1303     uint32 PIR;
1304     uint32 PGCR;
1305     uint32 DLLGCR;
1306     uint32 ACDLLCR;
1307     uint32 PTR[3];
1308     uint32 ACIOCR;
1309     uint32 DXCCR;
1310     uint32 DSGCR;
1311     uint32 DCR;
1312     PHY_TIMING_T phy_timing;
1313     uint32 ODTCR;
1314     uint32 DTAR;
1315     uint32 ZQ0CR0;
1316     uint32 ZQ1CR0;
1317 }PUBL_REG_T;
1318
1319 typedef struct SET_REG_Tag
1320 {
1321     uint32 addr;
1322     uint32 val;
1323 }SET_REG_T;
1324
1325 typedef struct BACKUP_REG_Tag
1326 {
1327     uint32 tag;
1328     /* any addr = 0xFFFFFFFF, indicate invalid */
1329     uint32 pctlAddr[CH_MAX];
1330     PCTL_REG_T pctl;
1331     uint32 publAddr[CH_MAX];
1332     PUBL_REG_T publ;
1333     PUBL_DQS_REG dqs[CH_MAX];
1334     uint32 nocAddr[CH_MAX];
1335     MSCH_REG   noc[CH_MAX];
1336
1337     uint32 pllpdAddr;
1338     uint32 pllpdMask;
1339     uint32 pllpdVal;
1340
1341     uint32 dpllmodeAddr;
1342     uint32 dpllSlowMode;
1343     uint32 dpllNormalMode;
1344     uint32 dpllResetAddr;
1345     uint32 dpllReset;
1346     uint32 dpllDeReset;
1347     uint32 dpllConAddr;
1348     uint32 dpllCon[4];
1349     uint32 dpllLockAddr;
1350     uint32 dpllLockMask;
1351     uint32 dpllLockVal;
1352
1353     uint32 ddrPllSrcDivAddr;
1354     uint32 ddrPllSrcDiv;
1355
1356     uint32 retenDisAddr;
1357     uint32 retenDisVal;
1358     uint32 retenStAddr;
1359     uint32 retenStMask;
1360     uint32 retenStVal;
1361
1362     /* ddr relative grf register */
1363     uint32 grfRegCnt;     //if no grf, set 0
1364     SET_REG_T grf[3];        //SET_REG_T grf[grfRegCnt];
1365
1366     /* other ddr relative register */
1367     //uint32 otherRegCnt; // if = 0xFFFFFFFF, indicate invalid
1368     //SET_REG_T other[grfRegCnt];
1369     uint32 endTag;         //must = 0xFFFFFFFF
1370 }BACKUP_REG_T;
1371
1372 typedef struct CHANNEL_INFO_Tag
1373 {
1374     //inited data
1375     uint32        chNum;  //channel number,0:channel a; 1:channel b;
1376     pDDR_REG_T    pDDR_Reg;
1377     pDDRPHY_REG_T pPHY_Reg;
1378     pMSCH_REG     pMSCH_Reg;
1379     //need init data
1380     DRAM_TYPE     mem_type; // =DRAM_MAX, channel invalid
1381     uint32        ddr_speed_bin;    // used for ddr3 only
1382     uint32        ddr_capability_per_die;  // one chip cs capability
1383 }CH_INFO,*pCH_INFO;
1384
1385 struct ddr_freq_t {
1386     unsigned long screen_ft_us;
1387     unsigned long long t0;
1388     unsigned long long t1;
1389     unsigned long t2;
1390 };
1391
1392 typedef struct STRIDE_INFO_Tag
1393 {
1394     uint32  size;
1395     uint32  halfCap;
1396 }STRIDE_INFO;
1397
1398 static const STRIDE_INFO   gStrideInfo[]={
1399     {0x10000000,0x10000000},  // 256
1400     {0x20000000,0x20000000},  // 512
1401     {0x40000000,0x40000000},  // 1G
1402     {0x80000000,0x80000000},  // 2G
1403
1404     {128,0x20000000},
1405     {256,0x20000000},
1406     {512,0x20000000},
1407     {4096,0x20000000},
1408
1409     {128,0x40000000},
1410     {256,0x40000000},
1411     {512,0x40000000},
1412     {4096,0x40000000},
1413
1414     {128,0x80000000},
1415     {256,0x80000000},
1416     {512,0x80000000},
1417     {4096,0x80000000},
1418
1419     {128,0x60000000},
1420     {256,0x60000000},
1421     {512,0x60000000},
1422     {4096,0x60000000},
1423
1424     {0,0x20000000},
1425     {0,0x40000000},
1426     {0,0x80000000},
1427     {0,0x80000000},  // 4GB
1428
1429     {0,0},  //reserved
1430     {0,0},  //reserved
1431
1432     {0,0},
1433     {128,0},
1434 };
1435
1436 CH_INFO DEFINE_PIE_DATA(ddr_ch[2]);
1437 static pCH_INFO p_ddr_ch[2];    //only used in kern, not pie
1438 BACKUP_REG_T DEFINE_PIE_DATA(ddr_reg);
1439 static BACKUP_REG_T *p_ddr_reg;
1440 static __attribute__((aligned(4096))) uint32 ddr_data_training_buf[32+8192/4];  //data in two channel even use max stride
1441 uint32 DEFINE_PIE_DATA(ddr_freq);
1442 uint32 DEFINE_PIE_DATA(ddr_sr_idle);
1443
1444 /***********************************
1445  * ARCH Relative Data and Function
1446  ***********************************/
1447 static __sramdata uint32 clkr;
1448 static __sramdata uint32 clkf;
1449 static __sramdata uint32 clkod;
1450 uint32 DEFINE_PIE_DATA(ddr_select_gpll_div); // 0-Disable, 1-1:1, 2-2:1, 4-4:1
1451 #if defined(ENABLE_DDR_CLCOK_GPLL_PATH)
1452 static uint32 *p_ddr_select_gpll_div;
1453 #endif
1454
1455 static void __sramfunc ddr_delayus(uint32 us);
1456
1457 static noinline uint32 ddr_get_pll_freq(PLL_ID pll_id)   //APLL-1;CPLL-2;DPLL-3;GPLL-4
1458 {
1459     uint32 ret = 0;
1460
1461      // freq = (Fin/NR)*NF/OD
1462     if(((pCRU_Reg->CRU_MODE_CON>>(pll_id*4))&3) == 1)             // DPLL Normal mode
1463         ret= 24 *((pCRU_Reg->CRU_PLL_CON[pll_id][1]&0x1fff)+1)    // NF = 2*(CLKF+1)
1464                 /((((pCRU_Reg->CRU_PLL_CON[pll_id][0]>>8)&0x3f)+1)           // NR = CLKR+1
1465                 *((pCRU_Reg->CRU_PLL_CON[pll_id][0]&0xF)+1));             // OD = 2^CLKOD
1466     else
1467         ret = 24;
1468
1469     return ret;
1470 }
1471
1472 /*****************************************
1473 NR   NO     NF               Fout                       freq Step     finally use
1474 1    8      12.5 - 62.5      37.5MHz  - 187.5MHz        3MHz          50MHz   <= 150MHz
1475 1    6      12.5 - 62.5      50MHz    - 250MHz          4MHz          150MHz  <= 200MHz
1476 1    4      12.5 - 62.5      75MHz    - 375MHz          6MHz          200MHz  <= 300MHz
1477 1    2      12.5 - 62.5      150MHz   - 750MHz          12MHz         300MHz  <= 600MHz
1478 1    1      12.5 - 62.5      300MHz   - 1500MHz         24MHz         600MHz  <= 1200MHz
1479 ******************************************/
1480 static uint32 __sramfunc ddr_set_pll_rk3188_plus(uint32 nMHz, uint32 set)
1481 {
1482     uint32 ret = 0;
1483     int delay;
1484
1485     if(nMHz == 24)
1486     {
1487         ret = 24;
1488         goto out;
1489     }
1490
1491     if(set==0)
1492     {
1493         if(nMHz <= 150)
1494         {
1495             clkod = 8;
1496         }
1497         else if(nMHz <= 200)
1498         {
1499             clkod = 6;
1500         }
1501         else if(nMHz <= 300)
1502         {
1503             clkod = 4;
1504         }
1505         else if(nMHz <= 600)
1506         {
1507             clkod = 2;
1508         }
1509         else
1510         {
1511             clkod = 1;
1512         }
1513         clkr = 1;
1514         clkf=(nMHz*clkr*clkod)/24;
1515         ret = (24*clkf)/(clkr*clkod);
1516     }
1517     else if(set == 1)
1518     {
1519         SET_DDR_PLL_SRC(1, (DATA(ddr_select_gpll_div)-1));  //clk_ddr_src = GPLL
1520
1521         SET_PLL_MODE(DPLL,0);            //PLL slow-mode
1522         dsb();
1523
1524         pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_RESET;
1525         ddr_delayus(1);
1526         pCRU_Reg->CRU_PLL_CON[DPLL][0] = NR(clkr) | NO(clkod);
1527         pCRU_Reg->CRU_PLL_CON[DPLL][1] = NF(clkf);
1528         pCRU_Reg->CRU_PLL_CON[DPLL][2] = NB(clkf>>1);
1529         ddr_delayus(1);
1530         pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_DE_RESET;
1531         dsb();
1532     }
1533     else
1534     {
1535         delay = 1000;
1536         while (delay > 0)
1537         {
1538             if (GET_DPLL_LOCK_STATUS())
1539                 break;
1540             ddr_delayus(1);
1541             delay--;
1542         }
1543
1544         SET_DDR_PLL_SRC(0, 0);  //clk_ddr_src = DDR PLL,clk_ddr_src:clk_ddrphy = 1:1
1545         SET_PLL_MODE(DPLL,1);            //PLL normal
1546         dsb();
1547     }
1548
1549 out:
1550     return ret;
1551 }
1552
1553 uint32 PIE_FUNC(ddr_set_pll)(uint32 nMHz, uint32 set)
1554 {
1555     return ddr_set_pll_rk3188_plus(nMHz,set);
1556 }
1557 EXPORT_PIE_SYMBOL(FUNC(ddr_set_pll));
1558 static uint32 (*p_ddr_set_pll)(uint32 nMHz, uint32 set);
1559
1560 static void __sramfunc idle_port(void)
1561 {
1562     register int i,j;
1563     uint32 clk_gate[19];
1564
1565     pPMU_Reg->PMU_IDLE_REQ |= idle_req_core_cfg;
1566     dsb();
1567     while( (pPMU_Reg->PMU_IDLE_ST & idle_core) == 0 );
1568
1569     //save clock gate status
1570     for(i=0;i<19;i++)
1571         clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
1572
1573     //enable all clock gate for request idle
1574     for(i=0;i<19;i++)
1575         pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
1576
1577     i = pPMU_Reg->PMU_PWRDN_ST;
1578     j = idle_req_dma_cfg;
1579
1580     if ( (i & pd_peri_pwr_st) == 0 )
1581     {
1582         j |= idle_req_peri_cfg;
1583     }
1584
1585     if ( (i & pd_video_pwr_st) == 0 )
1586     {
1587         j |= idle_req_video_cfg;
1588     }
1589
1590     if ( (i & pd_gpu_pwr_st) == 0 )
1591     {
1592         j |= idle_req_gpu_cfg;
1593     }
1594
1595     if ( (i & pd_hevc_pwr_st) == 0 )
1596     {
1597         j |= idle_req_hevc_cfg;
1598     }
1599
1600     if ( (i & pd_vio_pwr_st) == 0 )
1601     {
1602         j |= idle_req_vio_cfg;
1603     }
1604
1605     pPMU_Reg->PMU_IDLE_REQ |= j;
1606     dsb();
1607     while( (pPMU_Reg->PMU_IDLE_ST & j) != j );
1608
1609     //resume clock gate status
1610     for(i=0;i<19;i++)
1611         pCRU_Reg->CRU_CLKGATE_CON[i]=  (clk_gate[i] | 0xffff0000);
1612 }
1613
1614 static void inline deidle_port(void)
1615 {
1616     register int i,j;
1617     uint32 clk_gate[19];
1618
1619     //save clock gate status
1620     for(i=0;i<19;i++)
1621         clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
1622
1623     //enable all clock gate for request idle
1624     for(i=0;i<19;i++)
1625         pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
1626
1627     i = pPMU_Reg->PMU_PWRDN_ST;
1628     j = idle_req_dma_cfg;
1629
1630     if ( (i & pd_peri_pwr_st) == 0 )
1631     {
1632         j |= idle_req_peri_cfg;
1633     }
1634
1635     if ( (i & pd_video_pwr_st) == 0 )
1636     {
1637         j |= idle_req_video_cfg;
1638     }
1639
1640     if ( (i & pd_gpu_pwr_st) == 0 )
1641     {
1642         j |= idle_req_gpu_cfg;
1643     }
1644
1645     if ( (i & pd_hevc_pwr_st) == 0 )
1646     {
1647         j |= idle_req_hevc_cfg;
1648     }
1649
1650     if ( (i & pd_vio_pwr_st) == 0 )
1651     {
1652         j |= idle_req_vio_cfg;
1653     }
1654
1655     pPMU_Reg->PMU_IDLE_REQ &= ~j;
1656     dsb();
1657     while( (pPMU_Reg->PMU_IDLE_ST & j) != 0 );
1658
1659     pPMU_Reg->PMU_IDLE_REQ &= ~idle_req_core_cfg;
1660     dsb();
1661     while( (pPMU_Reg->PMU_IDLE_ST & idle_core) != 0 );
1662
1663     //resume clock gate status
1664     for(i=0;i<19;i++)
1665         pCRU_Reg->CRU_CLKGATE_CON[i]=  (clk_gate[i] | 0xffff0000);
1666
1667 }
1668
1669 /***********************************
1670  * Only DDR Relative Function
1671  ***********************************/
1672
1673 /****************************************************************************
1674 Internal sram us delay function
1675 Cpu highest frequency is 1.6 GHz
1676 1 cycle = 1/1.6 ns
1677 1 us = 1000 ns = 1000 * 1.6 cycles = 1600 cycles
1678 *****************************************************************************/
1679 __sramdata volatile uint32 loops_per_us;
1680
1681 #define LPJ_100MHZ  999456UL
1682
1683 static void __sramfunc ddr_delayus(uint32 us)
1684 {
1685     do
1686     {
1687         volatile unsigned int i = (loops_per_us*us);
1688         if (i < 7) i = 7;
1689         barrier();
1690         asm volatile(".align 4; 1: subs %0, %0, #1; bne 1b;" : "+r" (i));
1691     } while (0);
1692 }
1693
1694 void PIE_FUNC(ddr_copy)(uint64_t *pDest, uint64_t *pSrc, uint32 wword)
1695 {
1696     uint32 i;
1697
1698     for(i=0; i<wword; i++)
1699     {
1700         pDest[i] = pSrc[i];
1701     }
1702 }
1703 EXPORT_PIE_SYMBOL(FUNC(ddr_copy));
1704
1705 static void ddr_get_datatraing_addr(uint32 *pdtar)
1706 {
1707     uint32          addr;
1708     uint32          stride;
1709     uint32          strideSize;
1710     uint32          halfCap;
1711     uint32          ch,chCnt;
1712     uint32          socAddr[2];
1713     uint32          chAddr[2];
1714     uint32          col;
1715     uint32          row;
1716     uint32          bank;
1717     uint32          bw;
1718     uint32          conf;
1719
1720     for(ch=0,chCnt=0;ch<CH_MAX;ch++)
1721     {
1722         if(p_ddr_ch[ch]->mem_type != DRAM_MAX)
1723         {
1724             chCnt++;
1725         }
1726     }
1727
1728     // caculate aglined physical address
1729     addr =  __pa((unsigned long)ddr_data_training_buf);
1730     ddr_print("addr=0x%x\n",addr);
1731     if(addr&0x3F)
1732     {
1733         addr += (64-(addr&0x3F));  // 64byte align
1734     }
1735     addr -= DRAM_PHYS;
1736     if(chCnt > 1)
1737     {
1738         //find stride info
1739         stride = READ_DDR_STRIDE();
1740         strideSize = gStrideInfo[stride].size;
1741         halfCap = gStrideInfo[stride].halfCap;
1742         ddr_print("stride=%d, size=%d, halfcap=%x\n", stride,strideSize,halfCap);
1743         //get soc addr
1744         if(addr & strideSize)  // odd stride size
1745         {
1746             socAddr[0] = addr + strideSize;
1747             socAddr[1] = addr;
1748         }
1749         else
1750         {
1751             socAddr[0] = addr;
1752             socAddr[1] = addr + strideSize;
1753         }
1754         ddr_print("socAddr[0]=0x%x, socAddr[1]=0x%x\n", socAddr[0], socAddr[1]);
1755         if((stride >= 0x10) && (stride <= 0x13))  // 3GB stride
1756         {
1757             //conver to ch addr
1758             if(addr < 0x40000000)
1759             {
1760                 chAddr[0] = socAddr[0];
1761                 chAddr[1] = socAddr[1] - strideSize;
1762             }
1763             else if(addr < 0x80000000)
1764             {
1765                 chAddr[0] = socAddr[0] - 0x40000000 + strideSize;
1766                 chAddr[1] = socAddr[1] - 0x40000000;
1767             }
1768             else if(addr < 0xA0000000)
1769             {
1770                 chAddr[0] = socAddr[0] - 0x40000000;
1771                 chAddr[1] = socAddr[1] - 0x40000000 - strideSize;
1772             }
1773             else
1774             {
1775                 chAddr[0] = socAddr[0] - 0x60000000 + strideSize;
1776                 chAddr[1] = socAddr[1] - 0x60000000;
1777             }
1778         }
1779         else
1780         {
1781             //conver to ch addr
1782             if(addr <  halfCap)
1783             {
1784                 chAddr[0] = socAddr[0];
1785                 chAddr[1] = socAddr[1] - strideSize;
1786             }
1787             else
1788             {
1789                 chAddr[0] = socAddr[0] - halfCap + strideSize;
1790                 chAddr[1] = socAddr[1] - halfCap;
1791             }
1792         }
1793         ddr_print("chAddr[0]=0x%x, chAddr[1]=0x%x\n", chAddr[0], chAddr[1]);
1794     }
1795     else
1796     {
1797         chAddr[0] = addr;
1798         chAddr[1] = addr;
1799     }
1800
1801     for(ch=0,chCnt=0;ch<CH_MAX;ch++)
1802     {
1803         if(p_ddr_ch[ch]->mem_type != DRAM_MAX)
1804         {
1805             // find out col£¬row£¬bank,config
1806             row = READ_ROW_INFO(ch,0);
1807             bank = READ_BK_INFO(ch);
1808             col = READ_COL_INFO(ch);
1809             bw = READ_BW_INFO(ch);
1810             conf = p_ddr_ch[ch]->pMSCH_Reg->ddrconf;
1811             // according different address mapping, caculate DTAR register value
1812             pdtar[ch] = 0;
1813             pdtar[ch] |= ((chAddr[ch])>>bw) & ((0x1<<col)-1);  // col
1814             pdtar[ch] |= (((chAddr[ch])>>(bw+col+((ddr_cfg_2_rbc[conf]>>2)&0x3))) & ((0x1<<row)-1)) << 12;  // row
1815             if(((ddr_cfg_2_rbc[conf]>>7)&0x3)==3)
1816             {
1817                 pdtar[ch] |= ((((chAddr[ch])>>(bw+col+row)) & ((0x1<<bank)-1))  << 28);  // bank
1818             }
1819             else
1820             {
1821                 pdtar[ch] |= ((((chAddr[ch])>>(bw+col)) & 0x7) << 28);  // bank
1822             }
1823         }
1824     }
1825     ddr_print("dtar[0]=0x%x, dtar[1]=0x%x\n", pdtar[0], pdtar[1]);
1826 }
1827
1828 static __sramfunc void ddr_reset_dll(uint32 ch)
1829 {
1830     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1831     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
1832
1833     pPHY_Reg->ACDLLCR &= ~0x40000000;
1834     pPHY_Reg->DATX8[0].DXDLLCR &= ~0x40000000;
1835     pPHY_Reg->DATX8[1].DXDLLCR &= ~0x40000000;
1836     if(!(pDDR_Reg->PPCFG & 1))
1837     {
1838         pPHY_Reg->DATX8[2].DXDLLCR &= ~0x40000000;
1839         pPHY_Reg->DATX8[3].DXDLLCR &= ~0x40000000;
1840     }
1841     ddr_delayus(1);
1842     pPHY_Reg->ACDLLCR |= 0x40000000;
1843     pPHY_Reg->DATX8[0].DXDLLCR |= 0x40000000;
1844     pPHY_Reg->DATX8[1].DXDLLCR |= 0x40000000;
1845     if(!(pDDR_Reg->PPCFG & 1))
1846     {
1847         pPHY_Reg->DATX8[2].DXDLLCR |= 0x40000000;
1848         pPHY_Reg->DATX8[3].DXDLLCR |= 0x40000000;
1849     }
1850     ddr_delayus(1);
1851 }
1852
1853 static __sramfunc void ddr_move_to_Lowpower_state(uint32 ch)
1854 {
1855     register uint32 value;
1856     register pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1857
1858     while(1)
1859     {
1860         value = pDDR_Reg->STAT.b.ctl_stat;
1861         if(value == Low_power)
1862         {
1863             break;
1864         }
1865         switch(value)
1866         {
1867             case Init_mem:
1868                 pDDR_Reg->SCTL = CFG_STATE;
1869                 dsb();
1870                 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1871             case Config:
1872                 pDDR_Reg->SCTL = GO_STATE;
1873                 dsb();
1874                 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1875             case Access:
1876                 pDDR_Reg->SCTL = SLEEP_STATE;
1877                 dsb();
1878                 while((pDDR_Reg->STAT.b.ctl_stat) != Low_power);
1879                 break;
1880             default:  //Transitional state
1881                 break;
1882         }
1883     }
1884 }
1885
1886 static __sramfunc void ddr_move_to_Access_state(uint32 ch)
1887 {
1888     register uint32 value;
1889     register pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1890     register pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
1891
1892     //set auto self-refresh idle
1893     pDDR_Reg->MCFG1=(pDDR_Reg->MCFG1&0xffffff00) | DATA(ddr_sr_idle) | (1<<31);
1894     dsb();
1895
1896     while(1)
1897     {
1898         value = pDDR_Reg->STAT.b.ctl_stat;
1899         if((value == Access)
1900            || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power)))
1901         {
1902             break;
1903         }
1904         switch(value)
1905         {
1906             case Low_power:
1907                 pDDR_Reg->SCTL = WAKEUP_STATE;
1908                 dsb();
1909                 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1910                 while((pPHY_Reg->PGSR & DLDONE) != DLDONE);  //wait DLL lock
1911                 break;
1912             case Init_mem:
1913                 pDDR_Reg->SCTL = CFG_STATE;
1914                 dsb();
1915                 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1916             case Config:
1917                 pDDR_Reg->SCTL = GO_STATE;
1918                 dsb();
1919                 while(!(((pDDR_Reg->STAT.b.ctl_stat) == Access)
1920                       || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power))));
1921                 break;
1922             default:  //Transitional state
1923                 break;
1924         }
1925     }
1926     /* de_hw_wakeup :enable auto sr if sr_idle != 0 */
1927     DDR_HW_WAKEUP(ch,0);
1928 }
1929
1930 static __sramfunc void ddr_move_to_Config_state(uint32 ch)
1931 {
1932     register uint32 value;
1933     register pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1934     register pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
1935
1936     /* hw_wakeup :disable auto sr */
1937     DDR_HW_WAKEUP(ch,1);
1938         dsb();
1939
1940     while(1)
1941     {
1942         value = pDDR_Reg->STAT.b.ctl_stat;
1943         if(value == Config)
1944         {
1945             break;
1946         }
1947         switch(value)
1948         {
1949             case Low_power:
1950                 pDDR_Reg->SCTL = WAKEUP_STATE;
1951                 dsb();
1952                 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1953                 while((pPHY_Reg->PGSR & DLDONE) != DLDONE);  //wait DLL lock
1954             case Access:
1955             case Init_mem:
1956                 pDDR_Reg->SCTL = CFG_STATE;
1957                 dsb();
1958                 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1959                 break;
1960             default:  //Transitional state
1961                 break;
1962         }
1963     }
1964 }
1965
1966 //arg°üÀ¨bank_addrºÍcmd_addr
1967 static void __sramfunc ddr_send_command(uint32 ch, uint32 rank, uint32 cmd, uint32 arg)
1968 {
1969     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1970
1971     pDDR_Reg->MCMD = (start_cmd | (rank<<20) | arg | cmd);
1972     dsb();
1973     while(pDDR_Reg->MCMD & start_cmd);
1974 }
1975
1976 //¶ÔtypeÀàÐÍµÄDDRµÄ¼¸¸öcs½øÐÐDTT
1977 //0  DTT³É¹¦
1978 //!0 DTTÊ§°Ü
1979 static uint32 __sramfunc ddr_data_training_trigger(uint32 ch)
1980 {
1981     uint32        cs;
1982     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
1983     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
1984
1985     // disable auto refresh
1986     pDDR_Reg->TREFI = 0;
1987     dsb();
1988     if((DATA(ddr_ch[ch]).mem_type != LPDDR2)
1989        && (DATA(ddr_ch[ch]).mem_type != LPDDR3))
1990     {
1991         // passive window
1992         pPHY_Reg->PGCR |= (1<<1);
1993     }
1994     // clear DTDONE status
1995     pPHY_Reg->PIR |= CLRSR;
1996     cs = ((pPHY_Reg->PGCR>>18) & 0xF);
1997     pPHY_Reg->PGCR = (pPHY_Reg->PGCR & (~(0xF<<18))) | (1<<18);  //use cs0 dtt
1998     // trigger DTT
1999     pPHY_Reg->PIR |= INIT | QSTRN | LOCKBYP | ZCALBYP | CLRSR | ICPC;
2000     return cs;
2001 }
2002 //¶ÔtypeÀàÐÍµÄDDRµÄ¼¸¸öcs½øÐÐDTT
2003 //0  DTT³É¹¦
2004 //!0 DTTÊ§°Ü
2005 static uint32 __sramfunc ddr_data_training(uint32 ch, uint32 cs)
2006 {
2007     uint32        i,byte;
2008     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
2009     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
2010
2011     // wait echo byte DTDONE
2012     while((pPHY_Reg->DATX8[0].DXGSR[0] & 1) != 1);
2013     while((pPHY_Reg->DATX8[1].DXGSR[0] & 1) != 1);
2014     if(!(pDDR_Reg->PPCFG & 1))
2015     {
2016         while((pPHY_Reg->DATX8[2].DXGSR[0] & 1) != 1);
2017         while((pPHY_Reg->DATX8[3].DXGSR[0] & 1) != 1);
2018         byte=4;
2019     }
2020     pPHY_Reg->PGCR = (pPHY_Reg->PGCR & (~(0xF<<18))) | (cs<<18);  //restore cs
2021     for(i=0;i<byte;i++)
2022     {
2023         pPHY_Reg->DATX8[i].DXDQSTR = (pPHY_Reg->DATX8[i].DXDQSTR & (~((0x7<<3)|(0x3<<14))))
2024                                       | ((pPHY_Reg->DATX8[i].DXDQSTR & 0x7)<<3)
2025                                       | (((pPHY_Reg->DATX8[i].DXDQSTR>>12) & 0x3)<<14);
2026     }
2027     // send some auto refresh to complement the lost while DTT£¬//²âµ½1¸öCSµÄDTT×î³¤Ê±¼äÊÇ10.7us¡£×î¶à²¹2´ÎË¢ÐÂ
2028     if(cs > 1)
2029     {
2030         ddr_send_command(ch,cs, REF_cmd, 0);
2031         ddr_send_command(ch,cs, REF_cmd, 0);
2032         ddr_send_command(ch,cs, REF_cmd, 0);
2033         ddr_send_command(ch,cs, REF_cmd, 0);
2034     }
2035     else
2036     {
2037         ddr_send_command(ch,cs, REF_cmd, 0);
2038         ddr_send_command(ch,cs, REF_cmd, 0);
2039     }
2040     if((DATA(ddr_ch[ch]).mem_type != LPDDR2)
2041        && (DATA(ddr_ch[ch]).mem_type != LPDDR3))
2042     {
2043         // active window
2044         pPHY_Reg->PGCR &= ~(1<<1);
2045     }
2046     // resume auto refresh
2047     pDDR_Reg->TREFI = DATA(ddr_reg).pctl.pctl_timing.trefi;
2048
2049     if(pPHY_Reg->PGSR & DTERR)
2050     {
2051         return (-1);
2052     }
2053     else
2054     {
2055         return 0;
2056     }
2057 }
2058
2059 static void __sramfunc ddr_set_dll_bypass(uint32 ch, uint32 freq)
2060 {
2061     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
2062     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
2063
2064     if(freq<=150)
2065     {
2066         pPHY_Reg->DLLGCR &= ~(1<<23);
2067         pPHY_Reg->ACDLLCR |= 0x80000000;
2068         pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
2069         pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
2070         pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
2071         pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
2072         pPHY_Reg->PIR |= DLLBYP;
2073     }
2074     else if(freq<=250)
2075     {
2076         pPHY_Reg->DLLGCR |= (1<<23);
2077         pPHY_Reg->ACDLLCR |= 0x80000000;
2078         pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
2079         pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
2080         pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
2081         pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
2082         pPHY_Reg->PIR |= DLLBYP;
2083     }
2084     else
2085     {
2086         pPHY_Reg->DLLGCR &= ~(1<<23);
2087         pPHY_Reg->ACDLLCR &= ~0x80000000;
2088         pPHY_Reg->DATX8[0].DXDLLCR &= ~0x80000000;
2089         pPHY_Reg->DATX8[1].DXDLLCR &= ~0x80000000;
2090         if(!(pDDR_Reg->PPCFG & 1))
2091         {
2092             pPHY_Reg->DATX8[2].DXDLLCR &= ~0x80000000;
2093             pPHY_Reg->DATX8[3].DXDLLCR &= ~0x80000000;
2094         }
2095         pPHY_Reg->PIR &= ~DLLBYP;
2096     }
2097 }
2098
2099 static noinline uint32 ddr_get_parameter(uint32 nMHz)
2100 {
2101     uint32 tmp;
2102     uint32 ret = 0;
2103     uint32 al;
2104     uint32 bl,bl_tmp;
2105     uint32 cl;
2106     uint32 cwl;
2107     PCTL_TIMING_T *p_pctl_timing=&(p_ddr_reg->pctl.pctl_timing);
2108     PHY_TIMING_T  *p_publ_timing=&(p_ddr_reg->publ.phy_timing);
2109     volatile NOC_TIMING_T  *p_noc_timing=&(p_ddr_reg->noc[0].ddrtiming);
2110     volatile NOC_ACTIVATE_T  *p_noc_activate=&(p_ddr_reg->noc[0].activate);
2111     uint32 ch;
2112     uint32 mem_type;
2113     uint32 ddr_speed_bin=DDR3_DEFAULT;
2114     uint32 ddr_capability_per_die=0;
2115
2116     for(ch=0;ch<CH_MAX;ch++)
2117     {
2118         if(p_ddr_ch[ch]->mem_type != DRAM_MAX)
2119         {
2120             mem_type = p_ddr_ch[ch]->mem_type;
2121             if(ddr_speed_bin == DDR3_DEFAULT)
2122             {
2123                 ddr_speed_bin = p_ddr_ch[ch]->ddr_speed_bin;
2124             }
2125             else
2126             {
2127                 ddr_speed_bin = (ddr_speed_bin > p_ddr_ch[ch]->ddr_speed_bin) ? ddr_speed_bin : p_ddr_ch[ch]->ddr_speed_bin;
2128             }
2129             if(ddr_capability_per_die == 0)
2130             {
2131                 ddr_capability_per_die = p_ddr_ch[ch]->ddr_capability_per_die;
2132             }
2133             else
2134             {
2135                 ddr_capability_per_die = (ddr_capability_per_die > p_ddr_ch[ch]->ddr_capability_per_die) ? ddr_capability_per_die : p_ddr_ch[ch]->ddr_capability_per_die;
2136             }
2137             break;
2138         }
2139     }
2140
2141     p_pctl_timing->togcnt1u = nMHz;
2142     p_pctl_timing->togcnt100n = nMHz/10;
2143     p_pctl_timing->tinit = 200;
2144     p_pctl_timing->trsth = 500;
2145
2146     if(mem_type == DDR3)
2147     {
2148         if(ddr_speed_bin > DDR3_DEFAULT){
2149             ret = -1;
2150             goto out;
2151         }
2152
2153         #define DDR3_tREFI_7_8_us    (78)  //unit 100ns
2154         #define DDR3_tMRD            (4)   //tCK
2155         #define DDR3_tRFC_512Mb      (90)  //ns
2156         #define DDR3_tRFC_1Gb        (110) //ns
2157         #define DDR3_tRFC_2Gb        (160) //ns
2158         #define DDR3_tRFC_4Gb        (300) //ns
2159         #define DDR3_tRFC_8Gb        (350) //ns
2160         #define DDR3_tRTW            (2)   //register min valid value
2161         #define DDR3_tRAS            (37)  //ns
2162         #define DDR3_tRRD            (10)  //ns
2163         #define DDR3_tRTP            (7)   //ns
2164         #define DDR3_tWR             (15)  //ns
2165         #define DDR3_tWTR            (7)   //ns
2166         #define DDR3_tXP             (7)   //ns
2167         #define DDR3_tXPDLL          (24)  //ns
2168         #define DDR3_tZQCS           (80)  //ns
2169         #define DDR3_tZQCSI          (0)   //ns
2170         #define DDR3_tDQS            (1)   //tCK
2171         #define DDR3_tCKSRE          (10)  //ns
2172         #define DDR3_tCKE_400MHz     (7)   //ns
2173         #define DDR3_tCKE_533MHz     (6)   //ns
2174         #define DDR3_tMOD            (15)  //ns
2175         #define DDR3_tRSTL           (100) //ns
2176         #define DDR3_tZQCL           (320) //ns
2177         #define DDR3_tDLLK           (512) //tCK
2178
2179         al = 0;
2180         bl = 8;
2181         if(nMHz <= 330)
2182         {
2183             tmp = 0;
2184         }
2185         else if(nMHz<=400)
2186         {
2187             tmp = 1;
2188         }
2189         else if(nMHz<=533)
2190         {
2191             tmp = 2;
2192         }
2193         else if(nMHz<=666)
2194         {
2195             tmp = 3;
2196         }
2197         else if(nMHz<=800)
2198         {
2199             tmp = 4;
2200         }
2201         else if(nMHz<=933)
2202         {
2203             tmp = 5;
2204         }
2205         else
2206         {
2207             tmp = 6;
2208         }
2209
2210         if(nMHz < 300)       //when dll bypss cl = cwl = 6;
2211         {
2212             cl = 6;
2213             cwl = 6;
2214         }
2215         else
2216         {
2217             cl = (ddr3_cl_cwl[ddr_speed_bin][tmp] >> 4)&0xf;
2218             cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf;
2219         }
2220         if(cl == 0)
2221             ret = -4;
2222         if(nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ)
2223         {
2224             p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_DIS;
2225         }
2226         else
2227         {
2228             p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_120;
2229         }
2230         p_publ_timing->mr[2] = DDR3_MR2_CWL(cwl) /* | DDR3_Rtt_WR_60 */;
2231         p_publ_timing->mr[3] = 0;
2232         /**************************************************
2233          * PCTL Timing
2234          **************************************************/
2235         /*
2236          * tREFI, average periodic refresh interval, 7.8us
2237          */
2238         p_pctl_timing->trefi = DDR3_tREFI_7_8_us;
2239         /*
2240          * tMRD, 4 tCK
2241          */
2242         p_pctl_timing->tmrd = DDR3_tMRD & 0x7;
2243         p_publ_timing->dtpr0.b.tMRD = DDR3_tMRD-4;
2244         /*
2245          * tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb)
2246          */
2247         if(ddr_capability_per_die <= 0x4000000)         // 512Mb 90ns
2248         {
2249             tmp = DDR3_tRFC_512Mb;
2250         }
2251         else if(ddr_capability_per_die <= 0x8000000)    // 1Gb 110ns
2252         {
2253             tmp = DDR3_tRFC_1Gb;
2254         }
2255         else if(ddr_capability_per_die <= 0x10000000)   // 2Gb 160ns
2256         {
2257             tmp = DDR3_tRFC_2Gb;
2258         }
2259         else if(ddr_capability_per_die <= 0x20000000)   // 4Gb 300ns
2260         {
2261             tmp = DDR3_tRFC_4Gb;
2262         }
2263         else    // 8Gb  350ns
2264         {
2265             tmp = DDR3_tRFC_8Gb;
2266         }
2267         p_pctl_timing->trfc = (tmp*nMHz+999)/1000;
2268         p_publ_timing->dtpr1.b.tRFC = ((tmp*nMHz+999)/1000);
2269         /*
2270          * tXSR, =tDLLK=512 tCK
2271          */
2272         p_pctl_timing->texsr = DDR3_tDLLK;
2273         p_publ_timing->dtpr2.b.tXS = DDR3_tDLLK;
2274         /*
2275          * tRP=CL
2276          */
2277         p_pctl_timing->trp = cl;
2278         p_publ_timing->dtpr0.b.tRP = cl;
2279         /*
2280          * WrToMiss=WL*tCK + tWR + tRP + tRCD
2281          */
2282         p_noc_timing->b.WrToMiss = (cwl+((DDR3_tWR*nMHz+999)/1000)+cl+cl);
2283         /*
2284          * tRC=tRAS+tRP
2285          */
2286         p_pctl_timing->trc = ((((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000)&0x3F);
2287         p_noc_timing->b.ActToAct = (((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000);
2288         p_publ_timing->dtpr0.b.tRC = (((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000);
2289
2290         p_pctl_timing->trtw = (cl+2-cwl);//DDR3_tRTW;
2291         p_publ_timing->dtpr1.b.tRTW = 0;
2292         p_noc_timing->b.RdToWr = (cl+2-cwl);
2293         p_pctl_timing->tal = al;
2294         p_pctl_timing->tcl = cl;
2295         p_pctl_timing->tcwl = cwl;
2296         /*
2297          * tRAS, 37.5ns(400MHz)     37.5ns(533MHz)
2298          */
2299         p_pctl_timing->tras = (((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000)&0x3F);
2300         p_publ_timing->dtpr0.b.tRAS = ((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000);
2301         /*
2302          * tRCD=CL
2303          */
2304         p_pctl_timing->trcd = cl;
2305         p_publ_timing->dtpr0.b.tRCD = cl;
2306         /*
2307          * tRRD = max(4nCK, 7.5ns), DDR3-1066(1K), DDR3-1333(2K), DDR3-1600(2K)
2308          *        max(4nCK, 10ns), DDR3-800(1K,2K), DDR3-1066(2K)
2309          *        max(4nCK, 6ns), DDR3-1333(1K), DDR3-1600(1K)
2310          *
2311          */
2312         tmp = ((DDR3_tRRD*nMHz+999)/1000);
2313         if(tmp < 4)
2314         {
2315             tmp = 4;
2316         }
2317         p_pctl_timing->trrd = (tmp&0xF);
2318         p_publ_timing->dtpr0.b.tRRD = tmp;
2319         p_noc_activate->b.Rrd = tmp;
2320         /*
2321          * tRTP, max(4 tCK,7.5ns)
2322          */
2323         tmp = ((DDR3_tRTP*nMHz+(nMHz>>1)+999)/1000);
2324         if(tmp < 4)
2325         {
2326             tmp = 4;
2327         }
2328         p_pctl_timing->trtp = tmp&0xF;
2329         p_publ_timing->dtpr0.b.tRTP = tmp;
2330         /*
2331          * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
2332          */
2333         p_noc_timing->b.RdToMiss = (tmp+cl+cl-(bl>>1));
2334         /*
2335          * tWR, 15ns
2336          */
2337         tmp = ((DDR3_tWR*nMHz+999)/1000);
2338         p_pctl_timing->twr = tmp&0x1F;
2339         if(tmp<9)
2340         {
2341             tmp = tmp - 4;
2342         }
2343         else
2344         {
2345             tmp += (tmp&0x1) ? 1:0;
2346             tmp = tmp>>1;
2347         }
2348         bl_tmp = (bl == 8) ? DDR3_BL8 : DDR3_BC4;
2349         p_publ_timing->mr[0] = bl_tmp | DDR3_CL(cl) | DDR3_WR(tmp);
2350
2351         /*
2352          * tWTR, max(4 tCK,7.5ns)
2353          */
2354         tmp = ((DDR3_tWTR*nMHz+(nMHz>>1)+999)/1000);
2355         if(tmp < 4)
2356         {
2357             tmp = 4;
2358         }
2359         p_pctl_timing->twtr = tmp&0xF;
2360         p_publ_timing->dtpr0.b.tWTR = tmp;
2361         /*
2362          * WrToRd=WL+tWTR
2363          */
2364         p_noc_timing->b.WrToRd = (tmp+cwl);
2365         /*
2366          * tXP, max(3 tCK, 7.5ns)(<933MHz)
2367          */
2368         tmp = ((DDR3_tXP*nMHz+(nMHz>>1)+999)/1000);
2369         if(tmp < 3)
2370         {
2371             tmp = 3;
2372         }
2373         p_pctl_timing->txp = tmp&0x7;
2374         /*
2375          * tXPDLL, max(10 tCK,24ns)
2376          */
2377         tmp = ((DDR3_tXPDLL*nMHz+999)/1000);
2378         if(tmp < 10)
2379         {
2380             tmp = 10;
2381         }
2382         p_pctl_timing->txpdll = tmp & 0x3F;
2383         p_publ_timing->dtpr2.b.tXP = tmp;
2384         /*
2385          * tZQCS, max(64 tCK, 80ns)
2386          */
2387         tmp = ((DDR3_tZQCS*nMHz+999)/1000);
2388         if(tmp < 64)
2389         {
2390             tmp = 64;
2391         }
2392         p_pctl_timing->tzqcs = tmp&0x7F;
2393         /*
2394          * tZQCSI,
2395          */
2396         p_pctl_timing->tzqcsi = DDR3_tZQCSI;
2397         /*
2398          * tDQS,
2399          */
2400         p_pctl_timing->tdqs = DDR3_tDQS;
2401         /*
2402          * tCKSRE, max(5 tCK, 10ns)
2403          */
2404         tmp = ((DDR3_tCKSRE*nMHz+999)/1000);
2405         if(tmp < 5)
2406         {
2407             tmp = 5;
2408         }
2409         p_pctl_timing->tcksre = tmp & 0x1F;
2410         /*
2411          * tCKSRX, max(5 tCK, 10ns)
2412          */
2413         p_pctl_timing->tcksrx = tmp & 0x1F;
2414         /*
2415          * tCKE, max(3 tCK,7.5ns)(400MHz) max(3 tCK,5.625ns)(533MHz)
2416          */
2417         if(nMHz>=533)
2418         {
2419             tmp = ((DDR3_tCKE_533MHz*nMHz+999)/1000);
2420         }
2421         else
2422         {
2423             tmp = ((DDR3_tCKE_400MHz*nMHz+(nMHz>>1)+999)/1000);
2424         }
2425         if(tmp < 3)
2426         {
2427             tmp = 3;
2428         }
2429         p_pctl_timing->tcke = tmp & 0x7;
2430         /*
2431          * tCKESR, =tCKE + 1tCK
2432          */
2433         p_pctl_timing->tckesr = (tmp+1)&0xF;
2434         p_publ_timing->dtpr2.b.tCKE = tmp+1;
2435         /*
2436          * tMOD, max(12 tCK,15ns)
2437          */
2438         tmp = ((DDR3_tMOD*nMHz+999)/1000);
2439         if(tmp < 12)
2440         {
2441             tmp = 12;
2442         }
2443         p_pctl_timing->tmod = tmp&0x1F;
2444         p_publ_timing->dtpr1.b.tMOD = (tmp-12);
2445         /*
2446          * tRSTL, 100ns
2447          */
2448         p_pctl_timing->trstl = ((DDR3_tRSTL*nMHz+999)/1000)&0x7F;
2449         /*
2450          * tZQCL, max(256 tCK, 320ns)
2451          */
2452         tmp = ((DDR3_tZQCL*nMHz+999)/1000);
2453         if(tmp < 256)
2454         {
2455             tmp = 256;
2456         }
2457         p_pctl_timing->tzqcl = tmp&0x3FF;
2458         /*
2459          * tMRR, 0 tCK
2460          */
2461         p_pctl_timing->tmrr = 0;
2462         /*
2463          * tDPD, 0
2464          */
2465         p_pctl_timing->tdpd = 0;
2466
2467         /**************************************************
2468          * PHY Timing
2469          **************************************************/
2470         /*
2471          * tCCD, BL/2 for DDR2 and 4 for DDR3
2472          */
2473         p_publ_timing->dtpr0.b.tCCD = 0;
2474         /*
2475          * tDQSCKmax,5.5ns
2476          */
2477         p_publ_timing->dtpr1.b.tDQSCKmax = 0;
2478         /*
2479          * tRTODT, 0:ODT may be turned on immediately after read post-amble
2480          *         1:ODT may not be turned on until one clock after the read post-amble
2481          */
2482         p_publ_timing->dtpr1.b.tRTODT = 1;
2483         /*
2484          * tFAW,40ns(400MHz 1KB page) 37.5ns(533MHz 1KB page) 50ns(400MHz 2KB page)   50ns(533MHz 2KB page)
2485          */
2486         tmp = (((ddr3_tRC_tFAW[ddr_speed_bin]&0x0ff)*nMHz+999)/1000);
2487         p_publ_timing->dtpr1.b.tFAW = tmp;
2488         p_noc_activate->b.Fawbank = 1;
2489         p_noc_activate->b.Faw = tmp;
2490         /*
2491          * tAOND_tAOFD
2492          */
2493         p_publ_timing->dtpr1.b.tAOND = 0;
2494         /*
2495          * tDLLK,512 tCK
2496          */
2497         p_publ_timing->dtpr2.b.tDLLK = DDR3_tDLLK;
2498         /**************************************************
2499          * NOC Timing
2500          **************************************************/
2501         p_noc_timing->b.BurstLen = (bl>>1);
2502     }
2503     else if(mem_type == LPDDR2)
2504     {
2505         #define LPDDR2_tREFI_3_9_us    (39)  //unit 100ns
2506         #define LPDDR2_tREFI_7_8_us    (78)  //unit 100ns
2507         #define LPDDR2_tMRD            (5)   //tCK
2508         #define LPDDR2_tRFC_8Gb        (210)  //ns
2509         #define LPDDR2_tRFC_4Gb        (130)  //ns
2510         #define LPDDR2_tRPpb_4_BANK             (24)  //ns
2511         #define LPDDR2_tRPab_SUB_tRPpb_4_BANK   (0)   //ns
2512         #define LPDDR2_tRPpb_8_BANK             (24)  //ns
2513         #define LPDDR2_tRPab_SUB_tRPpb_8_BANK   (3)   //ns
2514         #define LPDDR2_tRTW          (1)   //tCK register min valid value
2515         #define LPDDR2_tRAS          (42)  //ns
2516         #define LPDDR2_tRCD          (24)  //ns
2517         #define LPDDR2_tRRD          (10)  //ns
2518         #define LPDDR2_tRTP          (7)   //ns
2519         #define LPDDR2_tWR           (15)  //ns
2520         #define LPDDR2_tWTR_GREAT_200MHz         (7)  //ns
2521         #define LPDDR2_tWTR_LITTLE_200MHz        (10) //ns
2522         #define LPDDR2_tXP           (7)  //ns
2523         #define LPDDR2_tXPDLL        (0)
2524         #define LPDDR2_tZQCS         (90) //ns
2525         #define LPDDR2_tZQCSI        (0)
2526         #define LPDDR2_tDQS          (1)
2527         #define LPDDR2_tCKSRE        (1)  //tCK
2528         #define LPDDR2_tCKSRX        (2)  //tCK
2529         #define LPDDR2_tCKE          (3)  //tCK
2530         #define LPDDR2_tMOD          (0)
2531         #define LPDDR2_tRSTL         (0)
2532         #define LPDDR2_tZQCL         (360)  //ns
2533         #define LPDDR2_tMRR          (2)    //tCK
2534         #define LPDDR2_tCKESR        (15)   //ns
2535         #define LPDDR2_tDPD_US       (500)  //us
2536         #define LPDDR2_tFAW_GREAT_200MHz    (50)  //ns
2537         #define LPDDR2_tFAW_LITTLE_200MHz   (60)  //ns
2538         #define LPDDR2_tDLLK         (2)  //tCK
2539         #define LPDDR2_tDQSCK_MAX    (3)  //tCK
2540         #define LPDDR2_tDQSCK_MIN    (0)  //tCK
2541         #define LPDDR2_tDQSS         (1)  //tCK
2542
2543         uint32 trp_tmp;
2544         uint32 trcd_tmp;
2545         uint32 tras_tmp;
2546         uint32 trtp_tmp;
2547         uint32 twr_tmp;
2548
2549         al = 0;
2550         bl = 8;
2551         /*     1066 933 800 667 533 400 333
2552          * RL,   8   7   6   5   4   3   3
2553          * WL,   4   4   3   2   2   1   1
2554          */
2555         if(nMHz<=200)
2556         {
2557             cl = 3;
2558             cwl = 1;
2559             p_publ_timing->mr[2] = LPDDR2_RL3_WL1;
2560         }
2561         else if(nMHz<=266)
2562         {
2563             cl = 4;
2564             cwl = 2;
2565             p_publ_timing->mr[2] = LPDDR2_RL4_WL2;
2566         }
2567         else if(nMHz<=333)
2568         {
2569             cl = 5;
2570             cwl = 2;
2571             p_publ_timing->mr[2] = LPDDR2_RL5_WL2;
2572         }
2573         else if(nMHz<=400)
2574         {
2575             cl = 6;
2576             cwl = 3;
2577             p_publ_timing->mr[2] = LPDDR2_RL6_WL3;
2578         }
2579         else if(nMHz<=466)
2580         {
2581             cl = 7;
2582             cwl = 4;
2583             p_publ_timing->mr[2] = LPDDR2_RL7_WL4;
2584         }
2585         else //(nMHz<=1066)
2586         {
2587             cl = 8;
2588             cwl = 4;
2589             p_publ_timing->mr[2] = LPDDR2_RL8_WL4;
2590         }
2591         p_publ_timing->mr[3] = LPDDR2_DS_34;
2592         p_publ_timing->mr[0] = 0;
2593         /**************************************************
2594          * PCTL Timing
2595          **************************************************/
2596         /*
2597          * tREFI, average periodic refresh interval, 15.6us(<256Mb) 7.8us(256Mb-1Gb) 3.9us(2Gb-8Gb)
2598          */
2599         if(ddr_capability_per_die >= 0x10000000)   // 2Gb
2600         {
2601             p_pctl_timing->trefi = LPDDR2_tREFI_3_9_us;
2602         }
2603         else
2604         {
2605             p_pctl_timing->trefi = LPDDR2_tREFI_7_8_us;
2606         }
2607
2608         /*
2609          * tMRD, (=tMRW), 5 tCK
2610          */
2611         p_pctl_timing->tmrd = LPDDR2_tMRD & 0x7;
2612         p_publ_timing->dtpr0.b.tMRD = 3;
2613         /*
2614          * tRFC, 90ns(<=512Mb) 130ns(1Gb-4Gb) 210ns(8Gb)
2615          */
2616         if(ddr_capability_per_die >= 0x40000000)   // 8Gb
2617         {
2618             p_pctl_timing->trfc = (LPDDR2_tRFC_8Gb*nMHz+999)/1000;
2619             p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_8Gb*nMHz+999)/1000);
2620             /*
2621              * tXSR, max(2tCK,tRFC+10ns)
2622              */
2623             tmp=(((LPDDR2_tRFC_8Gb+10)*nMHz+999)/1000);
2624         }
2625         else
2626         {
2627             p_pctl_timing->trfc = (LPDDR2_tRFC_4Gb*nMHz+999)/1000;
2628             p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_4Gb*nMHz+999)/1000);
2629             tmp=(((LPDDR2_tRFC_4Gb+10)*nMHz+999)/1000);
2630         }
2631         if(tmp<2)
2632         {
2633             tmp=2;
2634         }
2635         p_pctl_timing->texsr = tmp&0x3FF;
2636         p_publ_timing->dtpr2.b.tXS = tmp;
2637
2638         /*
2639          * tRP, max(3tCK, 4-bank:15ns(Fast) 18ns(Typ) 24ns(Slow), 8-bank:18ns(Fast) 21ns(Typ) 27ns(Slow))
2640          */
2641         //if(pPHY_Reg->DCR.b.DDR8BNK)
2642         if(1)
2643         {
2644             trp_tmp = ((LPDDR2_tRPpb_8_BANK*nMHz+999)/1000);
2645             if(trp_tmp<3)
2646             {
2647                 trp_tmp=3;
2648             }
2649             p_pctl_timing->trp = ((((LPDDR2_tRPab_SUB_tRPpb_8_BANK*nMHz+999)/1000) & 0x3)<<16) | (trp_tmp&0xF);
2650         }
2651         else
2652         {
2653             trp_tmp = ((LPDDR2_tRPpb_4_BANK*nMHz+999)/1000);
2654             if(trp_tmp<3)
2655             {
2656                 trp_tmp=3;
2657             }
2658             p_pctl_timing->trp = (LPDDR2_tRPab_SUB_tRPpb_4_BANK<<16) | (trp_tmp&0xF);
2659         }
2660         p_publ_timing->dtpr0.b.tRP = trp_tmp;
2661         /*
2662          * tRAS, max(3tCK,42ns)
2663          */
2664         tras_tmp=((LPDDR2_tRAS*nMHz+999)/1000);
2665         if(tras_tmp<3)
2666         {
2667             tras_tmp=3;
2668         }
2669         p_pctl_timing->tras = (tras_tmp&0x3F);
2670         p_publ_timing->dtpr0.b.tRAS = tras_tmp;
2671
2672         /*
2673          * tRCD, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow))
2674          */
2675         trcd_tmp = ((LPDDR2_tRCD*nMHz+999)/1000);
2676         if(trcd_tmp<3)
2677         {
2678             trcd_tmp=3;
2679         }
2680         p_pctl_timing->trcd = (trcd_tmp&0xF);
2681         p_publ_timing->dtpr0.b.tRCD = trcd_tmp;
2682
2683         /*
2684          * tRTP, max(2tCK, 7.5ns)
2685          */
2686         trtp_tmp = ((LPDDR2_tRTP*nMHz+(nMHz>>1)+999)/1000);
2687         if(trtp_tmp<2)
2688         {
2689             trtp_tmp = 2;
2690         }
2691         p_pctl_timing->trtp = trtp_tmp&0xF;
2692         p_publ_timing->dtpr0.b.tRTP = trtp_tmp;
2693
2694         /*
2695          * tWR, max(3tCK,15ns)
2696          */
2697         twr_tmp=((LPDDR2_tWR*nMHz+999)/1000);
2698         if(twr_tmp<3)
2699         {
2700             twr_tmp=3;
2701         }
2702         p_pctl_timing->twr = twr_tmp&0x1F;
2703         bl_tmp = (bl == 16) ? LPDDR2_BL16 : ((bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4);
2704         p_publ_timing->mr[1] = bl_tmp | LPDDR2_nWR(twr_tmp);
2705
2706         /*
2707          * WrToMiss=WL*tCK + tWR + tRP + tRCD
2708          */
2709         p_noc_timing->b.WrToMiss = (cwl+twr_tmp+trp_tmp+trcd_tmp);
2710         /*
2711          * RdToMiss=tRTP + tRP + tRCD - (BL/2 * tCK)
2712          */
2713         p_noc_timing->b.RdToMiss = (trtp_tmp+trp_tmp+trcd_tmp-(bl>>1));
2714         /*
2715          * tRC=tRAS+tRP
2716          */
2717         p_pctl_timing->trc = ((tras_tmp+trp_tmp)&0x3F);
2718         p_noc_timing->b.ActToAct = (tras_tmp+trp_tmp);
2719         p_publ_timing->dtpr0.b.tRC = (tras_tmp+trp_tmp);
2720
2721         /*
2722          * RdToWr=(cl+2-cwl)
2723          */
2724         p_pctl_timing->trtw = (cl+2-cwl);//LPDDR2_tRTW;
2725         p_publ_timing->dtpr1.b.tRTW = 0;
2726         p_noc_timing->b.RdToWr = (cl+2-cwl);
2727         p_pctl_timing->tal = al;
2728         p_pctl_timing->tcl = cl;
2729         p_pctl_timing->tcwl = cwl;
2730         /*
2731          * tRRD, max(2tCK,10ns)
2732          */
2733         tmp=((LPDDR2_tRRD*nMHz+999)/1000);
2734         if(tmp<2)
2735         {
2736             tmp=2;
2737         }
2738         p_pctl_timing->trrd = (tmp&0xF);
2739         p_publ_timing->dtpr0.b.tRRD = tmp;
2740         p_noc_activate->b.Rrd = tmp;
2741         /*
2742          * tWTR, max(2tCK, 7.5ns(533-266MHz)  10ns(200-166MHz))
2743          */
2744         if(nMHz > 200)
2745         {
2746             tmp=((LPDDR2_tWTR_GREAT_200MHz*nMHz+(nMHz>>1)+999)/1000);
2747         }
2748         else
2749         {
2750             tmp=((LPDDR2_tWTR_LITTLE_200MHz*nMHz+999)/1000);
2751         }
2752         if(tmp<2)
2753         {
2754             tmp=2;
2755         }
2756         p_pctl_timing->twtr = tmp&0xF;
2757         p_publ_timing->dtpr0.b.tWTR = tmp;
2758         /*
2759          * WrToRd=WL+tWTR
2760          */
2761         p_noc_timing->b.WrToRd = (cwl+tmp);
2762         /*
2763          * tXP, max(2tCK,7.5ns)
2764          */
2765         tmp=((LPDDR2_tXP*nMHz+(nMHz>>1)+999)/1000);
2766         if(tmp<2)
2767         {
2768             tmp=2;
2769         }
2770         p_pctl_timing->txp = tmp&0x7;
2771         p_publ_timing->dtpr2.b.tXP = tmp;
2772         /*
2773          * tXPDLL, 0ns
2774          */
2775         p_pctl_timing->txpdll = LPDDR2_tXPDLL;
2776         /*
2777          * tZQCS, 90ns
2778          */
2779         p_pctl_timing->tzqcs = ((LPDDR2_tZQCS*nMHz+999)/1000)&0x7F;
2780         /*
2781          * tZQCSI,
2782          */
2783         //if(pDDR_Reg->MCFG &= lpddr2_s4)
2784         if(1)
2785         {
2786             p_pctl_timing->tzqcsi = LPDDR2_tZQCSI;
2787         }
2788         else
2789         {
2790             p_pctl_timing->tzqcsi = 0;
2791         }
2792         /*
2793          * tDQS,
2794          */
2795         p_pctl_timing->tdqs = LPDDR2_tDQS;
2796         /*
2797          * tCKSRE, 1 tCK
2798          */
2799         p_pctl_timing->tcksre = LPDDR2_tCKSRE;
2800         /*
2801          * tCKSRX, 2 tCK
2802          */
2803         p_pctl_timing->tcksrx = LPDDR2_tCKSRX;
2804         /*
2805          * tCKE, 3 tCK
2806          */
2807         p_pctl_timing->tcke = LPDDR2_tCKE;
2808         p_publ_timing->dtpr2.b.tCKE = LPDDR2_tCKE;
2809         /*
2810          * tMOD, 0 tCK
2811          */
2812         p_pctl_timing->tmod = LPDDR2_tMOD;
2813         p_publ_timing->dtpr1.b.tMOD = LPDDR2_tMOD;
2814         /*
2815          * tRSTL, 0 tCK
2816          */
2817         p_pctl_timing->trstl = LPDDR2_tRSTL;
2818         /*
2819          * tZQCL, 360ns
2820          */
2821         p_pctl_timing->tzqcl = ((LPDDR2_tZQCL*nMHz+999)/1000)&0x3FF;
2822         /*
2823          * tMRR, 2 tCK
2824          */
2825         p_pctl_timing->tmrr = LPDDR2_tMRR;
2826         /*
2827          * tCKESR, max(3tCK,15ns)
2828          */
2829         tmp = ((LPDDR2_tCKESR*nMHz+999)/1000);
2830         if(tmp < 3)
2831         {
2832             tmp = 3;
2833         }
2834         p_pctl_timing->tckesr = tmp&0xF;
2835         /*
2836          * tDPD, 500us
2837          */
2838         p_pctl_timing->tdpd = LPDDR2_tDPD_US;
2839
2840         /**************************************************
2841          * PHY Timing
2842          **************************************************/
2843         /*
2844          * tCCD, BL/2 for DDR2 and 4 for DDR3
2845          */
2846         p_publ_timing->dtpr0.b.tCCD = 0;
2847         /*
2848          * tDQSCKmax,5.5ns
2849          */
2850         p_publ_timing->dtpr1.b.tDQSCKmax = LPDDR2_tDQSCK_MAX;
2851         /*
2852          * tDQSCKmin,2.5ns
2853          */
2854         p_publ_timing->dtpr1.b.tDQSCK = LPDDR2_tDQSCK_MIN;
2855         /*
2856          * tRTODT, 0:ODT may be turned on immediately after read post-amble
2857          *         1:ODT may not be turned on until one clock after the read post-amble
2858          */
2859         p_publ_timing->dtpr1.b.tRTODT = 1;
2860         /*
2861          * tFAW,max(8tCK, 50ns(200-533MHz)  60ns(166MHz))
2862          */
2863         if(nMHz>=200)
2864         {
2865             tmp=((LPDDR2_tFAW_GREAT_200MHz*nMHz+999)/1000);
2866         }
2867         else
2868         {
2869             tmp=((LPDDR2_tFAW_LITTLE_200MHz*nMHz+999)/1000);
2870         }
2871         if(tmp<8)
2872         {
2873             tmp=8;
2874         }
2875         p_publ_timing->dtpr1.b.tFAW = tmp;
2876         p_noc_activate->b.Fawbank = 1;
2877         p_noc_activate->b.Faw = tmp;
2878         /*
2879          * tAOND_tAOFD
2880          */
2881         p_publ_timing->dtpr1.b.tAOND = 0;
2882         /*
2883          * tDLLK,0
2884          */
2885         p_publ_timing->dtpr2.b.tDLLK = LPDDR2_tDLLK;
2886         /**************************************************
2887          * NOC Timing
2888          **************************************************/
2889         p_noc_timing->b.BurstLen = (bl>>1);
2890     }
2891     else if(mem_type == LPDDR3)
2892     {
2893         #define LPDDR3_tREFI_3_9_us    (39)  //unit 100ns
2894         #define LPDDR3_tMRD            (10)   //tCK
2895         #define LPDDR3_tRFC_8Gb        (210)  //ns
2896         #define LPDDR3_tRFC_4Gb        (130)  //ns
2897         #define LPDDR3_tRPpb_8_BANK             (24)  //ns
2898         #define LPDDR3_tRPab_SUB_tRPpb_8_BANK   (3)   //ns
2899         #define LPDDR3_tRTW          (1)   //tCK register min valid value
2900         #define LPDDR3_tRAS          (42)  //ns
2901         #define LPDDR3_tRCD          (24)  //ns
2902         #define LPDDR3_tRRD          (10)  //ns
2903         #define LPDDR3_tRTP          (7)   //ns
2904         #define LPDDR3_tWR           (15)  //ns
2905         #define LPDDR3_tWTR          (7)  //ns
2906         #define LPDDR3_tXP           (7)  //ns
2907         #define LPDDR3_tXPDLL        (0)
2908         #define LPDDR3_tZQCS         (90) //ns
2909         #define LPDDR3_tZQCSI        (0)
2910         #define LPDDR3_tDQS          (1)
2911         #define LPDDR3_tCKSRE        (2)  //tCK
2912         #define LPDDR3_tCKSRX        (2)  //tCK
2913         #define LPDDR3_tCKE          (3)  //tCK
2914         #define LPDDR3_tMOD          (0)
2915         #define LPDDR3_tRSTL         (0)
2916         #define LPDDR3_tZQCL         (360)  //ns
2917         #define LPDDR3_tMRR          (4)    //tCK
2918         #define LPDDR3_tCKESR        (15)   //ns
2919         #define LPDDR3_tDPD_US       (500)   //us
2920         #define LPDDR3_tFAW          (50)  //ns
2921         #define LPDDR3_tDLLK         (2)  //tCK
2922         #define LPDDR3_tDQSCK_MAX    (3)  //tCK
2923         #define LPDDR3_tDQSCK_MIN    (0)  //tCK
2924         #define LPDDR3_tDQSS         (1)  //tCK
2925
2926         uint32 trp_tmp;
2927         uint32 trcd_tmp;
2928         uint32 tras_tmp;
2929         uint32 trtp_tmp;
2930         uint32 twr_tmp;
2931
2932         al = 0;
2933         bl = 8;
2934         /* Only support Write Latency Set A here
2935          *     1066 933 800 733 667 600 533 400 166
2936          * RL,   16  14  12  11  10  9   8   6   3
2937          * WL,   8   8   6   6   6   5   4   3   1
2938          */
2939         if(nMHz<=166)
2940         {
2941             cl = 3;
2942             cwl = 1;
2943             p_publ_timing->mr[2] = LPDDR3_RL3_WL1;
2944         }
2945         else if(nMHz<=400)
2946         {
2947             cl = 6;
2948             cwl = 3;
2949             p_publ_timing->mr[2] = LPDDR3_RL6_WL3;
2950         }
2951         else if(nMHz<=533)
2952         {
2953             cl = 8;
2954             cwl = 4;
2955             p_publ_timing->mr[2] = LPDDR3_RL8_WL4;
2956         }
2957         else if(nMHz<=600)
2958         {
2959             cl = 9;
2960             cwl = 5;
2961             p_publ_timing->mr[2] = LPDDR3_RL9_WL5;
2962         }
2963         else if(nMHz<=667)
2964         {
2965             cl = 10;
2966             cwl = 6;
2967             p_publ_timing->mr[2] = LPDDR3_RL10_WL6;
2968         }
2969         else if(nMHz<=733)
2970         {
2971             cl = 11;
2972             cwl = 6;
2973             p_publ_timing->mr[2] = LPDDR3_RL11_WL6;
2974         }
2975         else if(nMHz<=800)
2976         {
2977             cl = 12;
2978             cwl = 6;
2979             p_publ_timing->mr[2] = LPDDR3_RL12_WL6;
2980         }
2981         else if(nMHz<=933)
2982         {
2983             cl = 14;
2984             cwl = 8;
2985             p_publ_timing->mr[2] = LPDDR3_RL14_WL8;
2986         }
2987         else //(nMHz<=1066)
2988         {
2989             cl = 16;
2990             cwl = 8;
2991             p_publ_timing->mr[2] = LPDDR3_RL16_WL8;
2992         }
2993         p_publ_timing->mr[3] = LPDDR3_DS_34;
2994         if(nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ)
2995         {
2996             p_publ_timing->mr11 = LPDDR3_ODT_DIS;
2997         }
2998         else
2999         {
3000             p_publ_timing->mr11 = LPDDR3_ODT_240;
3001         }
3002         p_publ_timing->mr[0] = 0;
3003         /**************************************************
3004          * PCTL Timing
3005          **************************************************/
3006         /*
3007          * tREFI, average periodic refresh interval, 3.9us(4Gb-16Gb)
3008          */
3009         p_pctl_timing->trefi = LPDDR3_tREFI_3_9_us;
3010
3011         /*
3012          * tMRD, (=tMRW), 10 tCK
3013          */
3014         p_pctl_timing->tmrd = LPDDR3_tMRD & 0x7;
3015         p_publ_timing->dtpr0.b.tMRD = 3;  //max value
3016         /*
3017          * tRFC, 130ns(4Gb) 210ns(>4Gb)
3018          */
3019         if(ddr_capability_per_die > 0x20000000)   // >4Gb
3020         {
3021             p_pctl_timing->trfc = (LPDDR3_tRFC_8Gb*nMHz+999)/1000;
3022             p_publ_timing->dtpr1.b.tRFC = ((LPDDR3_tRFC_8Gb*nMHz+999)/1000);
3023             /*
3024              * tXSR, max(2tCK,tRFC+10ns)
3025              */
3026             tmp=(((LPDDR3_tRFC_8Gb+10)*nMHz+999)/1000);
3027         }
3028         else
3029         {
3030             p_pctl_timing->trfc = (LPDDR3_tRFC_4Gb*nMHz+999)/1000;
3031             p_publ_timing->dtpr1.b.tRFC = ((LPDDR3_tRFC_4Gb*nMHz+999)/1000);
3032             tmp=(((LPDDR3_tRFC_4Gb+10)*nMHz+999)/1000);
3033         }
3034         if(tmp<2)
3035         {
3036             tmp=2;
3037         }
3038         p_pctl_timing->texsr = tmp&0x3FF;
3039         p_publ_timing->dtpr2.b.tXS = tmp;
3040
3041         /*
3042          * tRP, max(3tCK, 18ns(Fast) 21ns(Typ) 27ns(Slow))
3043          */
3044         //if(pPHY_Reg->DCR.b.DDR8BNK)
3045         if(1)
3046         {
3047             trp_tmp = ((LPDDR3_tRPpb_8_BANK*nMHz+999)/1000);
3048             if(trp_tmp<3)
3049             {
3050                 trp_tmp=3;
3051             }
3052             p_pctl_timing->trp = ((((LPDDR3_tRPab_SUB_tRPpb_8_BANK*nMHz+999)/1000) & 0x3)<<16) | (trp_tmp&0xF);
3053         }
3054         p_publ_timing->dtpr0.b.tRP = trp_tmp;
3055         /*
3056          * tRAS, max(3tCK,42ns)
3057          */
3058         tras_tmp=((LPDDR3_tRAS*nMHz+999)/1000);
3059         if(tras_tmp<3)
3060         {
3061             tras_tmp=3;
3062         }
3063         p_pctl_timing->tras = (tras_tmp&0x3F);
3064         p_publ_timing->dtpr0.b.tRAS = tras_tmp;
3065
3066         /*
3067          * tRCD, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow))
3068          */
3069         trcd_tmp = ((LPDDR3_tRCD*nMHz+999)/1000);
3070         if(trcd_tmp<3)
3071         {
3072             trcd_tmp=3;
3073         }
3074         p_pctl_timing->trcd = (trcd_tmp&0xF);
3075         p_publ_timing->dtpr0.b.tRCD = trcd_tmp;
3076
3077         /*
3078          * tRTP, max(4tCK, 7.5ns)
3079          */
3080         trtp_tmp = ((LPDDR3_tRTP*nMHz+(nMHz>>1)+999)/1000);
3081         if(trtp_tmp<4)
3082         {
3083             trtp_tmp = 4;
3084         }
3085         p_pctl_timing->trtp = trtp_tmp&0xF;
3086         p_publ_timing->dtpr0.b.tRTP = trtp_tmp;
3087
3088         /*
3089          * tWR, max(4tCK,15ns)
3090          */
3091         twr_tmp=((LPDDR3_tWR*nMHz+999)/1000);
3092         if(twr_tmp<4)
3093         {
3094             twr_tmp=4;
3095         }
3096         p_pctl_timing->twr = twr_tmp&0x1F;
3097         bl_tmp = LPDDR3_BL8;
3098         p_publ_timing->mr[1] = bl_tmp | LPDDR2_nWR(twr_tmp);
3099
3100         /*
3101          * WrToMiss=WL*tCK + tWR + tRP + tRCD
3102          */
3103         p_noc_timing->b.WrToMiss = (cwl+twr_tmp+trp_tmp+trcd_tmp);
3104         /*
3105          * RdToMiss=tRTP + tRP + tRCD - (BL/2 * tCK)
3106          */
3107         p_noc_timing->b.RdToMiss = (trtp_tmp+trp_tmp+trcd_tmp-(bl>>1));
3108         /*
3109          * tRC=tRAS+tRP
3110          */
3111         p_pctl_timing->trc = ((tras_tmp+trp_tmp)&0x3F);
3112         p_noc_timing->b.ActToAct = (tras_tmp+trp_tmp);
3113         p_publ_timing->dtpr0.b.tRC = (tras_tmp+trp_tmp);
3114
3115         /*
3116          * RdToWr=(cl+2-cwl)
3117          */
3118         p_pctl_timing->trtw = (cl+2-cwl);//LPDDR2_tRTW;
3119         p_publ_timing->dtpr1.b.tRTW = 0;
3120         p_noc_timing->b.RdToWr = (cl+2-cwl);
3121         p_pctl_timing->tal = al;
3122         p_pctl_timing->tcl = cl;
3123         p_pctl_timing->tcwl = cwl;
3124         /*
3125          * tRRD, max(2tCK,10ns)
3126          */
3127         tmp=((LPDDR3_tRRD*nMHz+999)/1000);
3128         if(tmp<2)
3129         {
3130             tmp=2;
3131         }
3132         p_pctl_timing->trrd = (tmp&0xF);
3133         p_publ_timing->dtpr0.b.tRRD = tmp;
3134         p_noc_activate->b.Rrd = tmp;
3135         /*
3136          * tWTR, max(4tCK, 7.5ns)
3137          */
3138         tmp=((LPDDR3_tWTR*nMHz+(nMHz>>1)+999)/1000);
3139         if(tmp<4)
3140         {
3141             tmp=4;
3142         }
3143         p_pctl_timing->twtr = tmp&0xF;
3144         p_publ_timing->dtpr0.b.tWTR = tmp;
3145         /*
3146          * WrToRd=WL+tWTR
3147          */
3148         p_noc_timing->b.WrToRd = (cwl+tmp);
3149         /*
3150          * tXP, max(3tCK,7.5ns)
3151          */
3152         tmp=((LPDDR3_tXP*nMHz+(nMHz>>1)+999)/1000);
3153         if(tmp<3)
3154         {
3155             tmp=3;
3156         }
3157         p_pctl_timing->txp = tmp&0x7;
3158         p_publ_timing->dtpr2.b.tXP = tmp;
3159         /*
3160          * tXPDLL, 0ns
3161          */
3162         p_pctl_timing->txpdll = LPDDR3_tXPDLL;
3163         /*
3164          * tZQCS, 90ns
3165          */
3166         p_pctl_timing->tzqcs = ((LPDDR3_tZQCS*nMHz+999)/1000)&0x7F;
3167         /*
3168          * tZQCSI,
3169          */
3170         p_pctl_timing->tzqcsi = LPDDR3_tZQCSI;
3171         /*
3172          * tDQS,
3173          */
3174         p_pctl_timing->tdqs = LPDDR3_tDQS;
3175         /*
3176          * tCKSRE=tCPDED, 2 tCK
3177          */
3178         p_pctl_timing->tcksre = LPDDR3_tCKSRE;
3179         /*
3180          * tCKSRX, 2 tCK
3181          */
3182         p_pctl_timing->tcksrx = LPDDR3_tCKSRX;
3183         /*
3184          * tCKE, (max 7.5ns,3 tCK)
3185          */
3186         tmp=((7*nMHz+(nMHz>>1)+999)/1000);
3187         if(tmp<LPDDR3_tCKE)
3188         {
3189             tmp=LPDDR3_tCKE;
3190         }
3191         p_pctl_timing->tcke = tmp;
3192         p_publ_timing->dtpr2.b.tCKE = tmp;
3193         /*
3194          * tMOD, 0 tCK
3195          */
3196         p_pctl_timing->tmod = LPDDR3_tMOD;
3197         p_publ_timing->dtpr1.b.tMOD = LPDDR3_tMOD;
3198         /*
3199          * tRSTL, 0 tCK
3200          */
3201         p_pctl_timing->trstl = LPDDR3_tRSTL;
3202         /*
3203          * tZQCL, 360ns
3204          */
3205         p_pctl_timing->tzqcl = ((LPDDR3_tZQCL*nMHz+999)/1000)&0x3FF;
3206         /*
3207          * tMRR, 4 tCK
3208          */
3209         p_pctl_timing->tmrr = LPDDR3_tMRR;
3210         /*
3211          * tCKESR, max(3tCK,15ns)
3212          */
3213         tmp = ((LPDDR3_tCKESR*nMHz+999)/1000);
3214         if(tmp < 3)
3215         {
3216             tmp = 3;
3217         }
3218         p_pctl_timing->tckesr = tmp&0xF;
3219         /*
3220          * tDPD, 500us
3221          */
3222         p_pctl_timing->tdpd = LPDDR3_tDPD_US;
3223
3224         /**************************************************
3225          * PHY Timing
3226          **************************************************/
3227         /*
3228          * tCCD, BL/2 for DDR2 and 4 for DDR3
3229          */
3230         p_publ_timing->dtpr0.b.tCCD = 0;
3231         /*
3232          * tDQSCKmax,5.5ns
3233          */
3234         p_publ_timing->dtpr1.b.tDQSCKmax = LPDDR3_tDQSCK_MAX;
3235         /*
3236          * tDQSCKmin,2.5ns
3237          */
3238         p_publ_timing->dtpr1.b.tDQSCK = LPDDR3_tDQSCK_MIN;
3239         /*
3240          * tRTODT, 0:ODT may be turned on immediately after read post-amble
3241          *         1:ODT may not be turned on until one clock after the read post-amble
3242          */
3243         p_publ_timing->dtpr1.b.tRTODT = 1;
3244         /*
3245          * tFAW,max(8tCK, 50ns)
3246          */
3247         tmp=((LPDDR3_tFAW*nMHz+999)/1000);
3248         if(tmp<8)
3249         {
3250             tmp=8;
3251         }
3252         p_publ_timing->dtpr1.b.tFAW = tmp;
3253         p_noc_activate->b.Fawbank = 1;
3254         p_noc_activate->b.Faw = tmp;
3255         /*
3256          * tAOND_tAOFD
3257          */
3258         p_publ_timing->dtpr1.b.tAOND = 0;
3259         /*
3260          * tDLLK,0
3261          */
3262         p_publ_timing->dtpr2.b.tDLLK = LPDDR3_tDLLK;
3263         /**************************************************
3264          * NOC Timing
3265          **************************************************/
3266         p_noc_timing->b.BurstLen = (bl>>1);
3267     }
3268
3269 out:
3270     return ret;
3271 }
3272
3273 static uint32 __sramfunc ddr_update_timing(uint32 ch)
3274 {
3275     uint32 i,bl_tmp=0;
3276     PCTL_TIMING_T *p_pctl_timing=&(DATA(ddr_reg).pctl.pctl_timing);
3277     PHY_TIMING_T  *p_publ_timing=&(DATA(ddr_reg).publ.phy_timing);
3278     volatile NOC_TIMING_T  *p_noc_timing=&(DATA(ddr_reg).noc[0].ddrtiming);
3279     volatile NOC_ACTIVATE_T  *p_noc_activate=&(DATA(ddr_reg).noc[0].activate);
3280     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
3281     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3282     pMSCH_REG     pMSCH_Reg= DATA(ddr_ch[ch]).pMSCH_Reg;
3283
3284     FUNC(ddr_copy)((uint64_t *)&(pDDR_Reg->TOGCNT1U), (uint64_t*)&(p_pctl_timing->togcnt1u), 17);
3285     pPHY_Reg->DTPR[0] = p_publ_timing->dtpr0.d32;
3286     pPHY_Reg->DTPR[1] = p_publ_timing->dtpr1.d32;
3287     pPHY_Reg->DTPR[2] = p_publ_timing->dtpr2.d32;
3288     pMSCH_Reg->ddrtiming.d32 = (pMSCH_Reg->ddrtiming.b.BwRatio) | p_noc_timing->d32;
3289     pMSCH_Reg->activate.d32 = p_noc_activate->d32;
3290     // Update PCTL BL
3291     if(DATA(ddr_ch[ch]).mem_type == DDR3)
3292     {
3293         bl_tmp = ((p_publ_timing->mr[0] & 0x3) == DDR3_BL8) ? ddr2_ddr3_bl_8 : ddr2_ddr3_bl_4;
3294         pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_slow|pd_type(1);
3295         if(DATA(ddr_freq) <= DDR3_DDR2_DLL_DISABLE_FREQ)
3296         {
3297             pDDR_Reg->DFITRDDATAEN   = pDDR_Reg->TCL-3;
3298         }
3299         else
3300         {
3301             pDDR_Reg->DFITRDDATAEN   = pDDR_Reg->TCL-2;
3302         }
3303         pDDR_Reg->DFITPHYWRLAT   = pDDR_Reg->TCWL-1;
3304     }
3305     else if((DATA(ddr_ch[ch]).mem_type == LPDDR2)||(DATA(ddr_ch[ch]).mem_type == LPDDR3))
3306     {
3307         if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL8)
3308         {
3309             bl_tmp = mddr_lpddr2_bl_8;
3310         }
3311         else if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL4)
3312         {
3313             bl_tmp = mddr_lpddr2_bl_4;
3314         }
3315         else //if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL16)
3316         {
3317             bl_tmp = mddr_lpddr2_bl_16;
3318         }
3319         if((DATA(ddr_freq)>=200)||(DATA(ddr_ch[ch]).mem_type == LPDDR3))
3320         {
3321             pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
3322         }
3323         else
3324         {
3325             pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(6)|pd_exit_fast|pd_type(1);
3326         }
3327         i = ((pPHY_Reg->DTPR[1] >> 27) & 0x7) - ((pPHY_Reg->DTPR[1] >> 24) & 0x7);
3328         pPHY_Reg->DSGCR = (pPHY_Reg->DSGCR & (~(0x3F<<5))) | (i<<5) | (i<<8);  //tDQSCKmax-tDQSCK
3329         pDDR_Reg->DFITRDDATAEN   = pDDR_Reg->TCL-1;
3330         pDDR_Reg->DFITPHYWRLAT   = pDDR_Reg->TCWL;
3331     }
3332
3333     return 0;
3334 }
3335
3336 static uint32 __sramfunc ddr_update_mr(uint32 ch)
3337 {
3338     PHY_TIMING_T  *p_publ_timing=&(DATA(ddr_reg).publ.phy_timing);
3339     uint32         cs,dll_off;
3340     pDDRPHY_REG_T  pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3341
3342     cs = ((pPHY_Reg->PGCR>>18) & 0xF);
3343     dll_off = (pPHY_Reg->MR[1] & DDR3_DLL_DISABLE) ? 1:0;
3344     FUNC(ddr_copy)((uint64_t *)&(pPHY_Reg->MR[0]), (uint64_t*)&(p_publ_timing->mr[0]), 2);
3345     if(DATA(ddr_ch[ch]).mem_type == DDR3)
3346     {
3347         ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x2) | cmd_addr((p_publ_timing->mr[2])));
3348         if(DATA(ddr_freq)>DDR3_DDR2_DLL_DISABLE_FREQ)
3349         {
3350             if(dll_off)  // off -> on
3351             {
3352                 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[1])));  //DLL enable
3353                 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr(((p_publ_timing->mr[0]))| DDR3_DLL_RESET));  //DLL reset
3354                 ddr_delayus(1);  //at least 200 DDR cycle
3355                 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3356             }
3357             else // on -> on
3358             {
3359                 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[1])));
3360                 ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3361             }
3362         }
3363         else
3364         {
3365             pPHY_Reg->MR[1] = (((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE);
3366             ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE));  //DLL disable
3367             ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3368         }
3369     }
3370     else if((DATA(ddr_ch[ch]).mem_type == LPDDR2)||(DATA(ddr_ch[ch]).mem_type == LPDDR3))
3371     {
3372         ddr_send_command(ch,cs, MRS_cmd, lpddr2_ma(0x1) | lpddr2_op((p_publ_timing->mr[1])));
3373         ddr_send_command(ch,cs, MRS_cmd, lpddr2_ma(0x2) | lpddr2_op((p_publ_timing->mr[2])));
3374         ddr_send_command(ch,cs, MRS_cmd, lpddr2_ma(0x3) | lpddr2_op((p_publ_timing->mr[3])));
3375         if(DATA(ddr_ch[ch]).mem_type == LPDDR3)
3376         {
3377             ddr_send_command(ch,cs, MRS_cmd, lpddr2_ma(11) | lpddr2_op((p_publ_timing->mr11)));
3378         }
3379     }
3380     else //mDDR
3381     {
3382         ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3383         ddr_send_command(ch,cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[2]))); //mr[2] is mDDR MR1
3384     }
3385     return 0;
3386 }
3387
3388 static void __sramfunc ddr_update_odt(uint32 ch)
3389 {
3390     uint32        cs,tmp;
3391     pDDR_REG_T    pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
3392     pDDRPHY_REG_T pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3393
3394     //adjust DRV and ODT
3395     if((DATA(ddr_ch[ch]).mem_type == DDR3) || (DATA(ddr_ch[ch]).mem_type == LPDDR3))
3396     {
3397         if(DATA(ddr_freq) <= DDR3_DDR2_ODT_DISABLE_FREQ)
3398         {
3399             pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9);  //dynamic RTT disable
3400             pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
3401             if(!(pDDR_Reg->PPCFG & 1))
3402             {
3403                 pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
3404                 pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
3405             }
3406         }
3407         else
3408         {
3409             pPHY_Reg->DATX8[0].DXGCR |= (0x3<<9);  //dynamic RTT enable
3410             pPHY_Reg->DATX8[1].DXGCR |= (0x3<<9);
3411             if(!(pDDR_Reg->PPCFG & 1))
3412             {
3413                 pPHY_Reg->DATX8[2].DXGCR |= (0x3<<9);
3414                 pPHY_Reg->DATX8[3].DXGCR |= (0x3<<9);
3415             }
3416         }
3417     }
3418     else
3419     {
3420         pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9);  //dynamic RTT disable
3421         pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
3422         if(!(pDDR_Reg->PPCFG & 1))
3423         {
3424             pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
3425             pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
3426         }
3427     }
3428     if(DATA(ddr_ch[ch]).mem_type == LPDDR2)
3429     {
3430         tmp = GET_LPDDR2_DS_ODT();  //DS=34ohm,ODT=171ohm
3431     }
3432     else if(DATA(ddr_ch[ch]).mem_type == LPDDR3)
3433     {
3434         tmp = GET_LPDDR3_DS_ODT();  //DS=34ohm,ODT=171ohm
3435     }
3436     else
3437     {
3438         tmp = GET_DDR3_DS_ODT();  //DS=34ohm,ODT=171ohm
3439     }
3440     cs = ((pPHY_Reg->PGCR>>18) & 0xF);
3441     if(cs > 1)
3442     {
3443         pPHY_Reg->ZQ1CR[0] = tmp;
3444         dsb();
3445     }
3446     pPHY_Reg->ZQ0CR[0] = tmp;
3447     dsb();
3448 }
3449
3450 static void __sramfunc ddr_selfrefresh_enter(uint32 nMHz)
3451 {
3452     uint32 ch;
3453     pDDR_REG_T    pDDR_Reg;
3454     pDDRPHY_REG_T pPHY_Reg;
3455
3456     for(ch=0;ch<CH_MAX;ch++)
3457     {
3458         pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
3459         pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3460
3461         if(DATA(ddr_ch[ch]).mem_type != DRAM_MAX)
3462         {
3463             ddr_move_to_Lowpower_state(ch);
3464             pDDR_Reg->TZQCSI = 0;
3465         }
3466     }
3467 }
3468
3469 #if defined(CONFIG_ARCH_RK3066B)
3470 static __sramdata uint32 data8_dqstr[25][4];
3471 static __sramdata uint32 min_ddr_freq,dqstr_flag=false;
3472
3473 int ddr_get_datatraing_value_3168(bool end_flag,uint32 dqstr_value,uint32 min_freq)
3474 {
3475     if(end_flag == true)
3476     {
3477         dqstr_flag = true;    //complete learn data training value flag
3478         min_ddr_freq = min_freq;
3479         return 0;
3480     }
3481
3482     data8_dqstr[dqstr_value][0]=pPHY_Reg->DATX8[0].DXDQSTR;
3483     data8_dqstr[dqstr_value][1]=pPHY_Reg->DATX8[0].DXDQSTR;
3484     data8_dqstr[dqstr_value][2]=pPHY_Reg->DATX8[0].DXDQSTR;
3485     data8_dqstr[dqstr_value][3]=pPHY_Reg->DATX8[0].DXDQSTR;
3486
3487     ddr_print("training %luMhz[%d]:0x%x-0x%x-0x%x-0x%x\n",
3488         clk_get_rate(clk_get(NULL, "ddr"))/1000000,dqstr_value,data8_dqstr[dqstr_value][0],data8_dqstr[dqstr_value][1],
3489         data8_dqstr[dqstr_value][2],data8_dqstr[dqstr_value][3]);
3490     return 0;
3491 }
3492
3493 static void __sramfunc ddr_set_pll_enter_3168(uint32 freq_slew)
3494 {
3495     uint32 value_1u,value_100n;
3496     ddr_move_to_Config_state();
3497
3498     if(freq_slew == 1)
3499     {
3500         value_100n = DATA(ddr_reg).pctl.pctl_timing.togcnt100n;
3501         value_1u = DATA(ddr_reg).pctl.pctl_timing.togcnt1u;
3502         DATA(ddr_reg).pctl.pctl_timing.togcnt1u = pDDR_Reg->TOGCNT1U;
3503         DATA(ddr_reg).pctl.pctl_timing.togcnt100n = pDDR_Reg->TOGCNT100N;
3504         ddr_update_timing();
3505         ddr_update_mr();
3506         DATA(ddr_reg).pctl.pctl_timing.togcnt100n = value_100n;
3507         DATA(ddr_reg).pctl.pctl_timing.togcnt1u = value_1u;
3508     }
3509     else
3510     {
3511         pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl.pctl_timing.togcnt100n;
3512         pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl.pctl_timing.togcnt1u;
3513     }
3514
3515     pDDR_Reg->TZQCSI = 0;
3516     ddr_move_to_Lowpower_state();
3517
3518     ddr_set_dll_bypass(0);  //dll bypass
3519     SET_DDRPHY_CLKGATE(ch,1);  //disable DDR PHY clock
3520     dsb();
3521 }
3522
3523 void __sramlocalfunc ddr_set_pll_exit_3168(uint32 freq_slew,uint32 dqstr_value)
3524 {
3525     SET_DDRPHY_CLKGATE(ch,0);  //enable DDR PHY clock
3526     dsb();
3527     ddr_set_dll_bypass(DATA(ddr_freq));
3528     ddr_reset_dll();
3529
3530     if(dqstr_flag==true)
3531     {
3532         pPHY_Reg->DATX8[0].DXDQSTR=data8_dqstr[dqstr_value][0];
3533         pPHY_Reg->DATX8[1].DXDQSTR=data8_dqstr[dqstr_value][1];
3534         pPHY_Reg->DATX8[2].DXDQSTR=data8_dqstr[dqstr_value][2];
3535         pPHY_Reg->DATX8[3].DXDQSTR=data8_dqstr[dqstr_value][3];
3536     }
3537
3538     ddr_update_odt();
3539     ddr_move_to_Config_state();
3540     if(freq_slew == 1)
3541     {
3542         pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl.pctl_timing.togcnt100n;
3543         pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl.pctl_timing.togcnt1u;
3544         pDDR_Reg->TZQCSI = DATA(ddr_reg).pctl.pctl_timing.tzqcsi;
3545     }
3546     else
3547     {
3548         ddr_update_timing();
3549         ddr_update_mr();
3550     }
3551     ddr_data_training();
3552     ddr_move_to_Access_state();
3553 }
3554 #endif
3555
3556 static void __sramfunc ddr_chb_update_timing_odt(void)
3557 {
3558     ddr_set_dll_bypass(1,0); //always use dll bypass
3559     ddr_update_timing(1);
3560     ddr_update_odt(1);
3561 }
3562
3563 /* Make sure ddr_SRE_2_SRX paramter less than 4 */
3564 static void __sramfunc ddr_SRE_2_SRX(uint32 freq, uint32 freq_slew,uint32 dqstr_value)
3565 {
3566     uint32 n,ch;
3567     uint32 cs[CH_MAX];
3568
3569     /** 2. ddr enter self-refresh mode or precharge power-down mode */
3570     idle_port();
3571 #if defined(CONFIG_ARCH_RK3066B)
3572     ddr_set_pll_enter_3168(freq_slew);
3573 #else
3574     ddr_selfrefresh_enter(freq);
3575 #endif
3576
3577     /** 3. change frequence  */
3578     FUNC(ddr_set_pll)(freq,1);
3579     DATA(ddr_freq) = freq;
3580
3581     /** 5. Issues a Mode Exit command   */
3582 #if defined(CONFIG_ARCH_RK3066B)
3583     ddr_set_pll_exit_3168(freq_slew,dqstr_value);
3584 #else
3585     //ddr_selfrefresh_exit();
3586     if(DATA(ddr_ch[1]).mem_type != DRAM_MAX)
3587     {
3588         ddr_chb_update_timing_odt();
3589     }
3590     ddr_set_dll_bypass(0,0); //always use dll bypass
3591     ddr_update_timing(0);
3592     ddr_update_odt(0);
3593     FUNC(ddr_set_pll)(freq,2);
3594     for(ch=0;ch<CH_MAX;ch++)
3595     {
3596         if(DATA(ddr_ch[ch]).mem_type != DRAM_MAX)
3597         {
3598             ddr_set_dll_bypass(ch,DATA(ddr_freq));
3599             ddr_reset_dll(ch);
3600             //ddr_delayus(10);   //wait DLL lock
3601
3602             ddr_move_to_Config_state(ch);
3603             ddr_update_mr(ch);
3604             cs[ch] = ddr_data_training_trigger(ch);
3605         }
3606     }
3607     for(ch=0;ch<CH_MAX;ch++)
3608     {
3609         if(DATA(ddr_ch[ch]).mem_type != DRAM_MAX)
3610         {
3611             n = ddr_data_training(ch,cs[ch]);
3612             ddr_move_to_Access_state(ch);
3613             if(n!=0)
3614             {
3615                 sram_printascii("DTT failed!\n");
3616             }
3617         }
3618     }
3619 #endif
3620     deidle_port();
3621     dsb();
3622 }
3623
3624 struct ddr_change_freq_sram_param {
3625     uint32 arm_freq;
3626     uint32 freq;
3627     uint32 freq_slew;
3628     uint32 dqstr_value;
3629 };
3630
3631 void PIE_FUNC(ddr_change_freq_sram)(void *arg)
3632 {
3633     struct ddr_change_freq_sram_param *param = arg;
3634     loops_per_us = LPJ_100MHZ * param->arm_freq / 1000000;
3635     /* Make sure ddr_SRE_2_SRX paramter less than 4 */
3636     ddr_SRE_2_SRX(param->freq, param->freq_slew, param->dqstr_value);
3637 }
3638 EXPORT_PIE_SYMBOL(FUNC(ddr_change_freq_sram));
3639
3640 typedef struct freq_tag{
3641     uint32_t nMHz;
3642     struct ddr_freq_t *p_ddr_freq_t;
3643 }freq_t;
3644
3645 static noinline uint32 ddr_change_freq_sram(void *arg)
3646 {
3647     uint32 freq;
3648     uint32 freq_slew=0;
3649     uint32 dqstr_value=0;
3650     unsigned long flags;
3651     struct ddr_change_freq_sram_param param;
3652     volatile uint32 n;
3653     volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
3654     uint32 i;
3655     uint32 gpllvaluel;
3656     freq_t *p_freq_t=(freq_t *)arg;
3657     uint32 nMHz=p_freq_t->nMHz;
3658         static struct rk_screen screen;
3659         static int dclk_div, down_dclk_div;
3660
3661 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
3662     struct ddr_freq_t *p_ddr_freq_t=p_freq_t->p_ddr_freq_t;
3663 #endif
3664
3665 #if defined(CONFIG_ARCH_RK3066B)
3666     if(dqstr_flag==true)
3667     {
3668         dqstr_value=((nMHz-min_ddr_freq+1)/25 + 1) /2;
3669         freq_slew = (nMHz>ddr_freq)? 1 : 0;
3670     }
3671 #endif
3672         if (!screen.mode.pixclock) {
3673                 rk_fb_get_prmry_screen(&screen);
3674                 if (screen.lcdc_id == 0)
3675                         dclk_div = (cru_readl(RK3288_CRU_CLKSELS_CON(27)) >> 8) & 0xff;
3676                 else if (screen.lcdc_id == 1)
3677                         dclk_div = (cru_readl(RK3288_CRU_CLKSELS_CON(29)) >> 8) & 0xff;
3678                 down_dclk_div = 64*(dclk_div+1)-1;
3679         }
3680     param.arm_freq = ddr_get_pll_freq(APLL);
3681     gpllvaluel = ddr_get_pll_freq(GPLL);
3682     if((200 < gpllvaluel) ||( gpllvaluel <1600))      //GPLL:200MHz~1600MHz
3683     {
3684         if( gpllvaluel > 800)     //800-1600MHz  /4:200MHz-400MHz
3685         {
3686             *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_select_gpll_div)) = 4;
3687         }
3688         else if( gpllvaluel > 400)    //400-800MHz  /2:200MHz-400MHz
3689         {
3690             *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_select_gpll_div)) = 2;
3691         }
3692         else        //200-400MHz  /1:200MHz-400MHz
3693         {
3694             *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_select_gpll_div)) = 1;
3695         }
3696     }
3697     else
3698     {
3699         ddr_print("GPLL frequency = %dMHz,Not suitable for ddr_clock \n",gpllvaluel);
3700     }
3701     freq=p_ddr_set_pll(nMHz,0);
3702
3703     ddr_get_parameter(freq);
3704
3705     /** 1. Make sure there is no host access */
3706     local_irq_save(flags);
3707     local_fiq_disable();
3708     flush_tlb_all();
3709     isb();
3710
3711 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
3712     if(p_ddr_freq_t->screen_ft_us > 0)
3713     {
3714         p_ddr_freq_t->t1 = cpu_clock(0);
3715         p_ddr_freq_t->t2 = (uint32)(p_ddr_freq_t->t1 - p_ddr_freq_t->t0);   //ns
3716
3717         //if test_count exceed maximum test times,ddr_freq_t.screen_ft_us == 0xfefefefe by ddr_freq.c
3718         if( (p_ddr_freq_t->t2 > p_ddr_freq_t->screen_ft_us*1000) && (p_ddr_freq_t->screen_ft_us != 0xfefefefe))
3719         {
3720             freq = 0;
3721             goto end;
3722         }
3723         else
3724         {
3725              rk_fb_poll_wait_frame_complete();
3726         }
3727     }
3728 #endif
3729     for(i=0;i<SRAM_SIZE/4096;i++)
3730     {
3731         n=temp[1024*i];
3732         barrier();
3733     }
3734
3735     for(i=0;i<CH_MAX;i++)
3736     {
3737         if(p_ddr_ch[i]->mem_type != DRAM_MAX)
3738         {
3739             n= p_ddr_ch[i]->pDDR_Reg->SCFG.d32;
3740             n= p_ddr_ch[i]->pPHY_Reg->RIDR;
3741             n= p_ddr_ch[i]->pMSCH_Reg->ddrconf;
3742         }
3743     }
3744     n= pCRU_Reg->CRU_PLL_CON[0][0];
3745     n= pPMU_Reg->PMU_WAKEUP_CFG[0];
3746     n= READ_GRF_REG();
3747     dsb();
3748
3749     param.freq = freq;
3750     param.freq_slew = freq_slew;
3751     param.dqstr_value = dqstr_value;
3752         rk_fb_set_prmry_screen_status(SCREEN_PREPARE_DDR_CHANGE);
3753         if (screen.lcdc_id == 0)
3754                 cru_writel(0 | CRU_W_MSK_SETBITS(down_dclk_div, 8, 0xff),
3755                            RK3288_CRU_CLKSELS_CON(27));
3756         else if (screen.lcdc_id == 1)
3757                 cru_writel(0 | CRU_W_MSK_SETBITS(down_dclk_div, 8, 0xff),
3758                            RK3288_CRU_CLKSELS_CON(29));
3759
3760     call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_change_freq_sram)),
3761                     &param,
3762                     rockchip_sram_stack-(NR_CPUS-1)*PAUSE_CPU_STACK_SIZE);
3763
3764         if (screen.lcdc_id == 0)
3765                 cru_writel(0 | CRU_W_MSK_SETBITS(dclk_div, 8, 0xff),
3766                 RK3288_CRU_CLKSELS_CON(27));
3767         else if (screen.lcdc_id == 1)
3768                 cru_writel(0 | CRU_W_MSK_SETBITS(dclk_div, 8, 0xff),
3769                 RK3288_CRU_CLKSELS_CON(29));
3770         rk_fb_set_prmry_screen_status(SCREEN_UNPREPARE_DDR_CHANGE);
3771
3772 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
3773 end:
3774 #endif
3775     local_fiq_enable();
3776     local_irq_restore(flags);
3777     return freq;
3778 }
3779
3780 #if defined(ENABLE_DDR_CLCOK_GPLL_PATH)
3781 static uint32 ddr_change_freq_gpll_dpll(uint32 nMHz)
3782 {
3783     uint32 gpll_freq,gpll_div;
3784     struct ddr_freq_t ddr_freq_t;
3785     ddr_freq_t.screen_ft_us = 0;
3786
3787     if(true == ddr_rk3188_dpll_is_good)
3788     {
3789         gpllvaluel = ddr_get_pll_freq(GPLL);
3790
3791         if((200 < gpllvaluel) ||( gpllvaluel <1600))      //GPLL:200MHz~1600MHz
3792         {
3793             gpll_div = (gpllvaluel+nMHz-1)/nMHz;
3794             if( gpllvaluel > 800)     //800-1600MHz  /4:200MHz-400MHz
3795             {
3796                 gpll_freq = gpllvaluel/4;
3797                 gpll_div = 4;
3798             }
3799             else if( gpllvaluel > 400)    //400-800MHz  /2:200MHz-400MHz
3800             {
3801                 gpll_freq = gpllvaluel/2;
3802                 gpll_div = 2;
3803             }
3804             else        //200-400MHz  /1:200MHz-400MHz
3805             {
3806                 gpll_freq = gpllvaluel;
3807                 gpll_div = 1;
3808             }
3809
3810             *p_ddr_select_gpll_div=gpll_div;    //select GPLL
3811             ddr_change_freq_sram(gpll_freq,ddr_freq_t);
3812             *p_ddr_select_gpll_div=0;
3813
3814             p_ddr_set_pll(nMHz,0); //count DPLL
3815             p_ddr_set_pll(nMHz,2); //lock DPLL only,but not select DPLL
3816         }
3817         else
3818         {
3819             ddr_print("GPLL frequency = %dMHz,Not suitable for ddr_clock \n",gpllvaluel);
3820         }
3821     }
3822
3823     return ddr_change_freq_sram(nMHz,ddr_freq_t);
3824
3825 }
3826 #endif
3827
3828 bool DEFINE_PIE_DATA(cpu_pause[NR_CPUS]);
3829 volatile bool *DATA(p_cpu_pause);
3830 static inline bool is_cpu0_paused(unsigned int cpu) { smp_rmb(); return DATA(cpu_pause)[0]; }
3831 static inline void set_cpuX_paused(unsigned int cpu, bool pause) { DATA(cpu_pause)[cpu] = pause; smp_wmb(); }
3832 static inline bool is_cpuX_paused(unsigned int cpu) { smp_rmb(); return DATA(p_cpu_pause)[cpu]; }
3833 static inline void set_cpu0_paused(bool pause) { DATA(p_cpu_pause)[0] = pause; smp_wmb();}
3834
3835 #define MAX_TIMEOUT (16000000UL << 6) //>0.64s
3836
3837 /* Do not use stack, safe on SMP */
3838 void PIE_FUNC(_pause_cpu)(void *arg)
3839 {
3840     unsigned int cpu = (unsigned int)arg;
3841
3842     set_cpuX_paused(cpu, true);
3843     while (is_cpu0_paused(cpu));
3844     set_cpuX_paused(cpu, false);
3845 }
3846
3847 static void pause_cpu(void *info)
3848 {
3849     unsigned int cpu = raw_smp_processor_id();
3850
3851     call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(_pause_cpu)),
3852             (void *)cpu,
3853             rockchip_sram_stack-(cpu-1)*PAUSE_CPU_STACK_SIZE);
3854 }
3855
3856 static void wait_cpu(void *info)
3857 {
3858 }
3859
3860 static int call_with_single_cpu(u32 (*fn)(void *arg), void *arg)
3861 {
3862     u32 timeout = MAX_TIMEOUT;
3863     unsigned int cpu;
3864     unsigned int this_cpu = smp_processor_id();
3865     int ret = 0;
3866
3867     cpu_maps_update_begin();
3868     local_bh_disable();
3869     set_cpu0_paused(true);
3870     smp_call_function((smp_call_func_t)pause_cpu, NULL, 0);
3871
3872     for_each_online_cpu(cpu) {
3873         if (cpu == this_cpu)
3874             continue;
3875         while (!is_cpuX_paused(cpu) && --timeout);
3876         if (timeout == 0) {
3877             pr_err("pause cpu %d timeout\n", cpu);
3878             goto out;
3879         }
3880     }
3881
3882     ret = fn(arg);
3883
3884 out:
3885     set_cpu0_paused(false);
3886     local_bh_enable();
3887     smp_call_function(wait_cpu, NULL, true);
3888     cpu_maps_update_done();
3889
3890     return ret;
3891 }
3892
3893 void PIE_FUNC(ddr_adjust_config)(void *arg)
3894 {
3895     uint32 value[CH_MAX];
3896     uint32 ch;
3897     pDDR_REG_T    pDDR_Reg;
3898     pDDRPHY_REG_T pPHY_Reg;
3899
3900     for(ch=0;ch<CH_MAX;ch++)
3901     {
3902         if(DATA(ddr_ch[ch]).mem_type != DRAM_MAX)
3903         {
3904             value[ch] = ((uint32 *)arg)[ch];
3905             pDDR_Reg = DATA(ddr_ch[ch]).pDDR_Reg;
3906             pPHY_Reg = DATA(ddr_ch[ch]).pPHY_Reg;
3907
3908             //enter config state
3909             ddr_move_to_Config_state(ch);
3910
3911             //set data training address
3912             pPHY_Reg->DTAR = value[ch];
3913
3914             //set auto power down idle
3915             pDDR_Reg->MCFG=(pDDR_Reg->MCFG&0xffff00ff)|(PD_IDLE<<8);
3916
3917             //CKDV=00
3918             pPHY_Reg->PGCR &= ~(0x3<<12);
3919
3920             //enable the hardware low-power interface
3921             pDDR_Reg->SCFG.b.hw_low_power_en = 1;
3922
3923             if(pDDR_Reg->PPCFG & 1)
3924             {
3925                 pPHY_Reg->DATX8[2].DXGCR &= ~(1);          //disable byte
3926                 pPHY_Reg->DATX8[3].DXGCR &= ~(1);
3927                 pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;  //disable DLL
3928                 pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
3929             }
3930
3931             ddr_update_odt(ch);
3932
3933             //enter access state
3934             ddr_move_to_Access_state(ch);
3935         }
3936     }
3937 }
3938 EXPORT_PIE_SYMBOL(FUNC(ddr_adjust_config));
3939
3940 static uint32 _ddr_adjust_config(void *dtar)
3941 {
3942     uint32 i;
3943     unsigned long flags;
3944     volatile uint32 n;
3945     volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
3946
3947      /** 1. Make sure there is no host access */
3948     local_irq_save(flags);
3949     local_fiq_disable();
3950     flush_tlb_all();
3951     isb();
3952
3953     for(i=0;i<SRAM_SIZE/4096;i++)
3954     {
3955         n=temp[1024*i];
3956         barrier();
3957     }
3958     for(i=0;i<CH_MAX;i++)
3959     {
3960         if(p_ddr_ch[i]->mem_type != DRAM_MAX)
3961         {
3962             n= p_ddr_ch[i]->pDDR_Reg->SCFG.d32;
3963             n= p_ddr_ch[i]->pPHY_Reg->RIDR;
3964             n= p_ddr_ch[i]->pMSCH_Reg->ddrconf;
3965         }
3966     }
3967     n= pCRU_Reg->CRU_PLL_CON[0][0];
3968     n= pPMU_Reg->PMU_WAKEUP_CFG[0];
3969     n= READ_GRF_REG();
3970     dsb();
3971
3972     call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_adjust_config)),
3973                     (void *)dtar,
3974                     rockchip_sram_stack-(NR_CPUS-1)*PAUSE_CPU_STACK_SIZE);
3975     local_fiq_enable();
3976     local_irq_restore(flags);
3977     return 0;
3978 }
3979
3980 static void ddr_adjust_config(void)
3981 {
3982     uint32 dtar[CH_MAX];
3983     uint32 i;
3984
3985     //get data training address before idle port
3986     ddr_get_datatraing_addr(dtar);
3987
3988     call_with_single_cpu(&_ddr_adjust_config, (void*)dtar);
3989     //_ddr_adjust_config(dtar);
3990     //disable unused channel
3991     for(i=0;i<CH_MAX;i++)
3992     {
3993         if(p_ddr_ch[i]->mem_type != DRAM_MAX)
3994         {
3995             //FIXME
3996         }
3997     }
3998 }
3999
4000 static int __ddr_change_freq(uint32_t nMHz, struct ddr_freq_t ddr_freq_t)
4001 {
4002     freq_t freq;
4003     int ret = 0;
4004
4005     freq.nMHz = nMHz;
4006     freq.p_ddr_freq_t = &ddr_freq_t;
4007     ret = call_with_single_cpu(&ddr_change_freq_sram,
4008                                (void*)&freq);
4009
4010     return ret;
4011 }
4012
4013 static int _ddr_change_freq(uint32 nMHz)
4014 {
4015         struct ddr_freq_t ddr_freq_t;
4016         #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
4017         unsigned long remain_t, vblank_t, pass_t;
4018         static unsigned long reserve_t = 800;//us
4019         unsigned long long tmp;
4020         int test_count=0;
4021         #endif
4022         int ret;
4023
4024         memset(&ddr_freq_t, 0x00, sizeof(ddr_freq_t));
4025
4026 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
4027         do
4028         {
4029                 ddr_freq_t.screen_ft_us = rk_fb_get_prmry_screen_ft();
4030                 ddr_freq_t.t0 = rk_fb_get_prmry_screen_framedone_t();
4031                 if (!ddr_freq_t.screen_ft_us)
4032                         return __ddr_change_freq(nMHz, ddr_freq_t);
4033
4034                 tmp = cpu_clock(0) - ddr_freq_t.t0;
4035                 do_div(tmp, 1000);
4036                 pass_t = tmp;
4037                 //lost frame interrupt
4038                 while (pass_t > ddr_freq_t.screen_ft_us){
4039                         int n = pass_t/ddr_freq_t.screen_ft_us;
4040
4041                         //printk("lost frame int, pass_t:%lu\n", pass_t);
4042                         pass_t -= n*ddr_freq_t.screen_ft_us;
4043                         ddr_freq_t.t0 += n*ddr_freq_t.screen_ft_us*1000;
4044                 }
4045
4046                 remain_t = ddr_freq_t.screen_ft_us - pass_t;
4047                 if (remain_t < reserve_t) {
4048                         //printk("remain_t(%lu) < reserve_t(%lu)\n", remain_t, reserve_t);
4049                         vblank_t = rk_fb_get_prmry_screen_vbt();
4050                         usleep_range(remain_t+vblank_t, remain_t+vblank_t);
4051                         continue;
4052                 }
4053
4054                 //test 10 times
4055                 test_count++;
4056                 if(test_count > 10)
4057                 {
4058                         ddr_freq_t.screen_ft_us = 0xfefefefe;
4059                 }
4060                 //printk("ft:%lu, pass_t:%lu, remaint_t:%lu, reservet_t:%lu\n",
4061                 //      ddr_freq_t.screen_ft_us, (unsigned long)pass_t, remain_t, reserve_t);
4062                 usleep_range(remain_t-reserve_t, remain_t-reserve_t);
4063                 flush_tlb_all();
4064
4065                 ret = __ddr_change_freq(nMHz, ddr_freq_t);
4066                 if (ret) {
4067                         reserve_t = 800;
4068                         return ret;
4069                 } else {
4070                         if (reserve_t < 3000)
4071                                 reserve_t += 200;
4072                 }
4073         }while(1);
4074 #else
4075         ret = __ddr_change_freq(nMHz, ddr_freq_t);
4076 #endif
4077
4078         return ret;
4079 }
4080
4081 static long _ddr_round_rate(uint32 nMHz)
4082 {
4083         return p_ddr_set_pll(nMHz, 0);
4084 }
4085
4086 static void _ddr_set_auto_self_refresh(bool en)
4087 {
4088     //set auto self-refresh idle
4089     *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = en ? SR_IDLE : 0;
4090 }
4091
4092 #define PERI_ACLK_DIV_MASK 0x1f
4093 #define PERI_ACLK_DIV_OFF 0
4094
4095 #define PERI_HCLK_DIV_MASK 0x3
4096 #define PERI_HCLK_DIV_OFF 8
4097
4098 #define PERI_PCLK_DIV_MASK 0x3
4099 #define PERI_PCLK_DIV_OFF 12
4100 #if 0
4101 static __sramdata u32 cru_sel32_sram;
4102 static void __sramfunc ddr_suspend(void)
4103 {
4104     u32 i;
4105     volatile u32 n;
4106     volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
4107     int pll_id;
4108
4109         pll_id=GET_DDR_PLL_SRC();
4110     /** 1. Make sure there is no host access */
4111     flush_cache_all();
4112     outer_flush_all();
4113     //flush_tlb_all();
4114
4115     for(i=0;i<SRAM_SIZE/4096;i++)
4116     {
4117         n=temp[1024*i];
4118         barrier();
4119     }
4120
4121     n= pDDR_Reg->SCFG.d32;
4122     n= pPHY_Reg->RIDR;
4123     n= pCRU_Reg->CRU_PLL_CON[0][0];
4124     n= pPMU_Reg->PMU_WAKEUP_CFG[0];
4125     n= *(volatile uint32_t *)SysSrv_DdrConf;
4126     n= READ_GRF_REG();
4127     dsb();
4128
4129     ddr_selfrefresh_enter(0);
4130
4131     SET_PLL_MODE(pll_id, 0);   //PLL slow-mode
4132     dsb();
4133     ddr_delayus(1);
4134     SET_PLL_PD(pll_id, 1);         //PLL power-down
4135     dsb();
4136     ddr_delayus(1);
4137     if(pll_id==GPLL)
4138     {
4139         cru_sel32_sram=   pCRU_Reg->CRU_CLKSEL_CON[10];
4140
4141         pCRU_Reg->CRU_CLKSEL_CON[10]=CRU_W_MSK_SETBITS(0, PERI_ACLK_DIV_OFF, PERI_ACLK_DIV_MASK)
4142                                    | CRU_W_MSK_SETBITS(0, PERI_HCLK_DIV_OFF, PERI_HCLK_DIV_MASK)
4143                                    |CRU_W_MSK_SETBITS(0, PERI_PCLK_DIV_OFF, PERI_PCLK_DIV_MASK);
4144     }
4145     pPHY_Reg->DSGCR = pPHY_Reg->DSGCR&(~((0x1<<28)|(0x1<<29)));  //CKOE
4146 }
4147
4148 static void __sramfunc ddr_resume(void)
4149 {
4150     int delay=1000;
4151     int pll_id;
4152
4153     pll_id=GET_DDR_PLL_SRC();
4154         pPHY_Reg->DSGCR = pPHY_Reg->DSGCR|((0x1<<28)|(0x1<<29));  //CKOE
4155         dsb();
4156
4157         if(pll_id==GPLL)
4158         pCRU_Reg->CRU_CLKSEL_CON[10]=0xffff0000|cru_sel32_sram;
4159
4160     SET_PLL_PD(pll_id, 0);         //PLL no power-down
4161     dsb();
4162     while (delay > 0)
4163     {
4164         if (GET_DPLL_LOCK_STATUS())
4165             break;
4166         ddr_delayus(1);
4167         delay--;
4168     }
4169
4170     SET_PLL_MODE(pll_id, 1);   //PLL normal
4171     dsb();
4172
4173     ddr_selfrefresh_exit();
4174 }
4175 #endif
4176
4177 //pArg:Ö¸ÕëÄÚÈÝ±íÊ¾pll pd or not¡£
4178 void ddr_reg_save(uint32 *pArg)
4179 {
4180     uint32        ch;
4181     pDDR_REG_T    pDDR_Reg=NULL;
4182     pDDRPHY_REG_T pPHY_Reg=NULL;
4183     pMSCH_REG     pMSCH_Reg;
4184
4185     p_ddr_reg->tag = 0x56313031;
4186     if(p_ddr_ch[0]->mem_type != DRAM_MAX)
4187     {
4188         p_ddr_reg->pctlAddr[0] = RK3288_DDR_PCTL0_PHYS;
4189         p_ddr_reg->publAddr[0] = RK3288_DDR_PUBL0_PHYS;
4190         p_ddr_reg->nocAddr[0] = RK3288_SERVICE_BUS_PHYS;
4191         pDDR_Reg = p_ddr_ch[0]->pDDR_Reg;
4192         pPHY_Reg = p_ddr_ch[0]->pPHY_Reg;
4193     }
4194     else
4195     {
4196         p_ddr_reg->pctlAddr[0] = 0xFFFFFFFF;
4197         p_ddr_reg->publAddr[0] = 0xFFFFFFFF;
4198         p_ddr_reg->nocAddr[0] = 0xFFFFFFFF;
4199     }
4200     if(p_ddr_ch[1]->mem_type != DRAM_MAX)
4201     {
4202         p_ddr_reg->pctlAddr[1] = RK3288_DDR_PCTL1_PHYS;
4203         p_ddr_reg->publAddr[1] = RK3288_DDR_PUBL1_PHYS;
4204         p_ddr_reg->nocAddr[1] = RK3288_SERVICE_BUS_PHYS+0x80;
4205         if((pDDR_Reg == NULL) || (pPHY_Reg == NULL))
4206         {
4207             pDDR_Reg = p_ddr_ch[1]->pDDR_Reg;
4208             pPHY_Reg = p_ddr_ch[1]->pPHY_Reg;
4209         }
4210     }
4211     else
4212     {
4213         p_ddr_reg->pctlAddr[1] = 0xFFFFFFFF;
4214         p_ddr_reg->publAddr[1] = 0xFFFFFFFF;
4215         p_ddr_reg->nocAddr[1] = 0xFFFFFFFF;
4216     }
4217
4218     //PCTLR
4219     (fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_copy)))((uint64_t*)&(p_ddr_reg->pctl.pctl_timing.togcnt1u), (uint64_t *)&(pDDR_Reg->TOGCNT1U), 17);
4220     p_ddr_reg->pctl.SCFG = pDDR_Reg->SCFG.d32;
4221     p_ddr_reg->pctl.CMDTSTATEN = pDDR_Reg->CMDTSTATEN;
4222     p_ddr_reg->pctl.MCFG1 = pDDR_Reg->MCFG1;
4223     p_ddr_reg->pctl.MCFG = pDDR_Reg->MCFG;
4224     p_ddr_reg->pctl.pctl_timing.ddrFreq = *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq));
4225     p_ddr_reg->pctl.DFITCTRLDELAY = pDDR_Reg->DFITCTRLDELAY;
4226     p_ddr_reg->pctl.DFIODTCFG = pDDR_Reg->DFIODTCFG;
4227     p_ddr_reg->pctl.DFIODTCFG1 = pDDR_Reg->DFIODTCFG1;
4228     p_ddr_reg->pctl.DFIODTRANKMAP = pDDR_Reg->DFIODTRANKMAP;
4229     p_ddr_reg->pctl.DFITPHYWRDATA = pDDR_Reg->DFITPHYWRDATA;
4230     p_ddr_reg->pctl.DFITPHYWRLAT = pDDR_Reg->DFITPHYWRLAT;
4231     p_ddr_reg->pctl.DFITRDDATAEN = pDDR_Reg->DFITRDDATAEN;
4232     p_ddr_reg->pctl.DFITPHYRDLAT = pDDR_Reg->DFITPHYRDLAT;
4233     p_ddr_reg->pctl.DFITPHYUPDTYPE0 = pDDR_Reg->DFITPHYUPDTYPE0;
4234     p_ddr_reg->pctl.DFITPHYUPDTYPE1 = pDDR_Reg->DFITPHYUPDTYPE1;
4235     p_ddr_reg->pctl.DFITPHYUPDTYPE2 = pDDR_Reg->DFITPHYUPDTYPE2;
4236     p_ddr_reg->pctl.DFITPHYUPDTYPE3 = pDDR_Reg->DFITPHYUPDTYPE3;
4237     p_ddr_reg->pctl.DFITCTRLUPDMIN = pDDR_Reg->DFITCTRLUPDMIN;
4238     p_ddr_reg->pctl.DFITCTRLUPDMAX = pDDR_Reg->DFITCTRLUPDMAX;
4239     p_ddr_reg->pctl.DFITCTRLUPDDLY = pDDR_Reg->DFITCTRLUPDDLY;
4240
4241     p_ddr_reg->pctl.DFIUPDCFG = pDDR_Reg->DFIUPDCFG;
4242     p_ddr_reg->pctl.DFITREFMSKI = pDDR_Reg->DFITREFMSKI;
4243     p_ddr_reg->pctl.DFITCTRLUPDI = pDDR_Reg->DFITCTRLUPDI;
4244     p_ddr_reg->pctl.DFISTCFG0 = pDDR_Reg->DFISTCFG0;
4245     p_ddr_reg->pctl.DFISTCFG1 = pDDR_Reg->DFISTCFG1;
4246     p_ddr_reg->pctl.DFITDRAMCLKEN = pDDR_Reg->DFITDRAMCLKEN;
4247     p_ddr_reg->pctl.DFITDRAMCLKDIS = pDDR_Reg->DFITDRAMCLKDIS;
4248     p_ddr_reg->pctl.DFISTCFG2 = pDDR_Reg->DFISTCFG2;
4249     p_ddr_reg->pctl.DFILPCFG0 = pDDR_Reg->DFILPCFG0;
4250
4251     //PUBL
4252     p_ddr_reg->publ.phy_timing.dtpr0.d32 = pPHY_Reg->DTPR[0];
4253     (fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_copy)))((uint64_t*)&(p_ddr_reg->publ.phy_timing.dtpr1), (uint64_t *)&(pPHY_Reg->DTPR[1]), 3);
4254     p_ddr_reg->publ.PIR = pPHY_Reg->PIR;
4255     p_ddr_reg->publ.PGCR = pPHY_Reg->PGCR;
4256     p_ddr_reg->publ.DLLGCR = pPHY_Reg->DLLGCR;
4257     p_ddr_reg->publ.ACDLLCR = pPHY_Reg->ACDLLCR;
4258     p_ddr_reg->publ.PTR[0] = pPHY_Reg->PTR[0];
4259     p_ddr_reg->publ.PTR[1] = pPHY_Reg->PTR[1];
4260     p_ddr_reg->publ.PTR[2] = pPHY_Reg->PTR[2];
4261     p_ddr_reg->publ.ACIOCR = pPHY_Reg->ACIOCR;
4262     p_ddr_reg->publ.DXCCR = pPHY_Reg->DXCCR;
4263     p_ddr_reg->publ.DSGCR = pPHY_Reg->DSGCR;
4264     p_ddr_reg->publ.DCR = pPHY_Reg->DCR.d32;
4265     p_ddr_reg->publ.ODTCR = pPHY_Reg->ODTCR;
4266     p_ddr_reg->publ.DTAR = pPHY_Reg->DTAR;
4267     p_ddr_reg->publ.ZQ0CR0 = (pPHY_Reg->ZQ0SR[0] & 0x0FFFFFFF) | (0x1<<28);
4268     p_ddr_reg->publ.ZQ1CR0 = (pPHY_Reg->ZQ1SR[0] & 0x0FFFFFFF) | (0x1<<28);
4269
4270     for(ch=0;ch<CH_MAX;ch++)
4271     {
4272         if(p_ddr_ch[0]->mem_type != DRAM_MAX)
4273         {
4274             pPHY_Reg = p_ddr_ch[ch]->pPHY_Reg;
4275             p_ddr_reg->dqs[ch].DX0GCR = pPHY_Reg->DATX8[0].DXGCR;
4276             p_ddr_reg->dqs[ch].DX0DLLCR = pPHY_Reg->DATX8[0].DXDLLCR;
4277             p_ddr_reg->dqs[ch].DX0DQTR = pPHY_Reg->DATX8[0].DXDQTR;
4278             p_ddr_reg->dqs[ch].DX0DQSTR = pPHY_Reg->DATX8[0].DXDQSTR;
4279
4280             p_ddr_reg->dqs[ch].DX1GCR = pPHY_Reg->DATX8[1].DXGCR;
4281             p_ddr_reg->dqs[ch].DX1DLLCR = pPHY_Reg->DATX8[1].DXDLLCR;
4282             p_ddr_reg->dqs[ch].DX1DQTR = pPHY_Reg->DATX8[1].DXDQTR;
4283             p_ddr_reg->dqs[ch].DX1DQSTR = pPHY_Reg->DATX8[1].DXDQSTR;
4284
4285             p_ddr_reg->dqs[ch].DX2GCR = pPHY_Reg->DATX8[2].DXGCR;
4286             p_ddr_reg->dqs[ch].DX2DLLCR = pPHY_Reg->DATX8[2].DXDLLCR;
4287             p_ddr_reg->dqs[ch].DX2DQTR = pPHY_Reg->DATX8[2].DXDQTR;
4288             p_ddr_reg->dqs[ch].DX2DQSTR = pPHY_Reg->DATX8[2].DXDQSTR;
4289
4290             p_ddr_reg->dqs[ch].DX3GCR = pPHY_Reg->DATX8[3].DXGCR;
4291             p_ddr_reg->dqs[ch].DX3DLLCR = pPHY_Reg->DATX8[3].DXDLLCR;
4292             p_ddr_reg->dqs[ch].DX3DQTR = pPHY_Reg->DATX8[3].DXDQTR;
4293             p_ddr_reg->dqs[ch].DX3DQSTR = pPHY_Reg->DATX8[3].DXDQSTR;
4294
4295             //NOC
4296             pMSCH_Reg= p_ddr_ch[ch]->pMSCH_Reg;
4297             p_ddr_reg->noc[ch].ddrconf = pMSCH_Reg->ddrconf;
4298             p_ddr_reg->noc[ch].ddrtiming.d32 = pMSCH_Reg->ddrtiming.d32;
4299             p_ddr_reg->noc[ch].ddrmode = pMSCH_Reg->ddrmode;
4300             p_ddr_reg->noc[ch].readlatency = pMSCH_Reg->readlatency;
4301             p_ddr_reg->noc[ch].activate.d32 = pMSCH_Reg->activate.d32;
4302             p_ddr_reg->noc[ch].devtodev = pMSCH_Reg->devtodev;
4303         }
4304     }
4305
4306     //PLLPD
4307     p_ddr_reg->pllpdAddr = (uint32_t)pArg;  //pll power-down tag addr
4308     p_ddr_reg->pllpdMask = 1;
4309     p_ddr_reg->pllpdVal = 1;
4310
4311     //DPLL
4312     p_ddr_reg->dpllmodeAddr = RK3288_CRU_PHYS + 0x50;  //APCRU_MODE_CON
4313     p_ddr_reg->dpllSlowMode = ((3<<4)<<16) | (0<<4);
4314     p_ddr_reg->dpllNormalMode = ((3<<4)<<16) | (1<<4);
4315     p_ddr_reg->dpllResetAddr = RK3288_CRU_PHYS + 0x1c; //APCRU_DPLL_CON3
4316     p_ddr_reg->dpllReset = (((0x1<<5)<<16) | (0x1<<5));
4317     p_ddr_reg->dpllDeReset = (((0x1<<5)<<16) | (0x0<<5));
4318     p_ddr_reg->dpllConAddr = RK3288_CRU_PHYS + 0x10;   //APCRU_DPLL_CON0
4319     p_ddr_reg->dpllCon[0] = pCRU_Reg->CRU_PLL_CON[DPLL][0] | (0xFFFF<<16);
4320     p_ddr_reg->dpllCon[1] = pCRU_Reg->CRU_PLL_CON[DPLL][1] | (0xFFFF<<16);
4321     p_ddr_reg->dpllCon[2] = pCRU_Reg->CRU_PLL_CON[DPLL][2] | (0xFFFF<<16);
4322     p_ddr_reg->dpllCon[3] = pCRU_Reg->CRU_PLL_CON[DPLL][3] | (0xFFFF<<16);
4323     p_ddr_reg->dpllLockAddr = RK3288_GRF_PHYS + 0x284;  //GRF_SOC_STATUS1
4324     p_ddr_reg->dpllLockMask = (1<<5);
4325     p_ddr_reg->dpllLockVal = (1<<5);
4326
4327     //SET_DDR_PLL_SRC
4328     p_ddr_reg->ddrPllSrcDivAddr = RK3288_CRU_PHYS + 0xc8;
4329     p_ddr_reg->ddrPllSrcDiv = (pCRU_Reg->CRU_CLKSEL_CON[26] & 0x7) | (0x7<<16);
4330
4331     p_ddr_reg->retenDisAddr = RK3288_PMU_PHYS+0x18;  //pmu_pwrmode_con
4332     p_ddr_reg->retenDisVal = (3<<21);  //OR operation
4333     p_ddr_reg->retenStAddr = RK3288_PMU_PHYS+0x1c;  //pmu_pwrmode_con
4334     p_ddr_reg->retenStMask = (1<<6);
4335     p_ddr_reg->retenStVal = (0<<6);
4336
4337     p_ddr_reg->grfRegCnt = 3;
4338     //DDR_16BIT,DDR_HW_WAKEUP,DDR_TYPE
4339     p_ddr_reg->grf[0].addr = RK3288_GRF_PHYS + 0x244;
4340     p_ddr_reg->grf[0].val = (pGRF_Reg->GRF_SOC_CON[0] & ((0x3<<8)|(0x3<<5)|(0x3<<3))) | (((0x3<<8)|(0x3<<5)|(0x3<<3))<<16);
4341
4342     //LPDDR_TYPE
4343     p_ddr_reg->grf[1].addr = RK3288_GRF_PHYS + 0x24c;
4344     p_ddr_reg->grf[1].val = (pGRF_Reg->GRF_SOC_CON[2] & (0x3f<<8)) | ((0x3f<<8)<<16);
4345
4346     //STRIDE
4347     p_ddr_reg->grf[2].addr = RK3288_SGRF_PHYS + 0x8;
4348     p_ddr_reg->grf[2].val = READ_DDR_STRIDE() | (0x1F<<16);
4349
4350     p_ddr_reg->endTag = 0xFFFFFFFF;
4351 }
4352
4353 __attribute__((aligned(4)))   uint32 ddr_reg_resume[]=
4354 {
4355 #include "ddr_reg_resume.inc"
4356 };
4357
4358 char * ddr_get_resume_code_info(u32 *size)
4359 {
4360     *size=sizeof(ddr_reg_resume);
4361
4362     return (char *)ddr_reg_resume;
4363
4364 }
4365 EXPORT_SYMBOL(ddr_get_resume_code_info);
4366
4367 char * ddr_get_resume_data_info(u32 *size)
4368 {
4369     *size=sizeof(DATA(ddr_reg));
4370     return (char *) kern_to_pie(rockchip_pie_chunk, &DATA(ddr_reg));
4371 }
4372 EXPORT_SYMBOL(ddr_get_resume_data_info);
4373
4374 /**********************ddr bandwidth calc*********************/
4375 enum ddr_bandwidth_id {
4376         ddrbw_wr_num = 0,
4377         ddrbw_rd_num,
4378         ddrbw_act_num,
4379         ddrbw_time_num,
4380         ddrbw_eff,
4381         ddrbw_id_end
4382 };
4383
4384 #define grf_readl(offset)       readl_relaxed(RK_GRF_VIRT + offset)
4385 #define grf_writel(v, offset) \
4386         do { writel_relaxed(v, RK_GRF_VIRT + offset); dsb(); } while (0)
4387
4388 #define noc_readl(offset)       readl_relaxed(RK3288_SERVICE_BUS_VIRT + offset)
4389 #define noc_writel(v, offset) \
4390         do { writel_relaxed(v, RK3288_SERVICE_BUS_VIRT + offset); \
4391                 dsb(); } while (0)
4392
4393 static void ddr_monitor_start(void)
4394 {
4395         int i;
4396
4397         for (i = 1; i < 8; i++) {
4398                 noc_writel(0x8, (0x400*i+0x8));
4399                 noc_writel(0x1, (0x400*i+0xc));
4400                 noc_writel(0x6, (0x400*i+0x138));
4401                 noc_writel(0x10, (0x400*i+0x14c));
4402                 noc_writel(0x8, (0x400*i+0x160));
4403                 noc_writel(0x10, (0x400*i+0x174));
4404         }
4405
4406         grf_writel((((readl_relaxed(RK_PMU_VIRT+0x9c)>>13)&7) == 3) ?
4407                         0xc000c000 : 0xe000e000, RK3288_GRF_SOC_CON4);
4408
4409         for (i = 1; i < 8; i++)
4410                 noc_writel(0x1, (0x400*i+0x28));
4411 }
4412
4413 static void ddr_monitor_stop(void)
4414 {
4415         grf_writel(0xc0000000, RK3288_GRF_SOC_CON4);
4416 }
4417
4418 static void _ddr_bandwidth_get(struct ddr_bw_info *ddr_bw_ch0,
4419                         struct ddr_bw_info *ddr_bw_ch1)
4420 {
4421         u32 ddr_bw_val[2][ddrbw_id_end], ddr_freq;
4422         u64 temp64;
4423         int i, j;
4424
4425         ddr_monitor_stop();
4426         for (j = 0; j < 2; j++) {
4427                 for (i = 0; i < ddrbw_eff; i++)
4428                         ddr_bw_val[j][i] =
4429                                 grf_readl(RK3288_GRF_SOC_STATUS11+i*4+j*16);
4430         }
4431         if (!ddr_bw_val[0][ddrbw_time_num])
4432                 goto end;
4433
4434         if (ddr_bw_ch0) {
4435                 ddr_freq = readl_relaxed(RK_DDR_VIRT + 0xc0);
4436
4437                 temp64 = ((u64)ddr_bw_val[0][0]+ddr_bw_val[0][1])*4*100;
4438                 do_div(temp64, ddr_bw_val[0][ddrbw_time_num]);
4439                 ddr_bw_val[0][ddrbw_eff] = temp64;
4440
4441                 ddr_bw_ch0->ddr_percent = temp64;
4442                 ddr_bw_ch0->ddr_time =
4443                         ddr_bw_val[0][ddrbw_time_num]/(ddr_freq*1000);
4444                 ddr_bw_ch0->ddr_wr =
4445                         (ddr_bw_val[0][ddrbw_wr_num]*8*4)*
4446                                 ddr_freq/ddr_bw_val[0][ddrbw_time_num];
4447                 ddr_bw_ch0->ddr_rd =
4448                         (ddr_bw_val[0][ddrbw_rd_num]*8*4)*
4449                                 ddr_freq/ddr_bw_val[0][ddrbw_time_num];
4450                 ddr_bw_ch0->ddr_act =
4451                         ddr_bw_val[0][ddrbw_act_num];
4452                 ddr_bw_ch0->ddr_total =
4453                         ddr_freq*2*4;
4454
4455                 ddr_bw_ch0->cpum = (noc_readl(0x400+0x178)<<16)
4456                         + (noc_readl(0x400+0x164));
4457                 ddr_bw_ch0->gpu = (noc_readl(0x800+0x178)<<16)
4458                         + (noc_readl(0x800+0x164));
4459                 ddr_bw_ch0->peri = (noc_readl(0xc00+0x178)<<16)
4460                         + (noc_readl(0xc00+0x164));
4461                 ddr_bw_ch0->video = (noc_readl(0x1000+0x178)<<16)
4462                         + (noc_readl(0x1000+0x164));
4463                 ddr_bw_ch0->vio0 = (noc_readl(0x1400+0x178)<<16)
4464                         + (noc_readl(0x1400+0x164));
4465                 ddr_bw_ch0->vio1 = (noc_readl(0x1800+0x178)<<16)
4466                         + (noc_readl(0x1800+0x164));
4467                 ddr_bw_ch0->vio2 = (noc_readl(0x1c00+0x178)<<16)
4468                         + (noc_readl(0x1c00+0x164));
4469
4470                 ddr_bw_ch0->cpum =
4471                         ddr_bw_ch0->cpum*ddr_freq/ddr_bw_val[0][ddrbw_time_num];
4472                 ddr_bw_ch0->gpu =
4473                         ddr_bw_ch0->gpu*ddr_freq/ddr_bw_val[0][ddrbw_time_num];
4474                 ddr_bw_ch0->peri =
4475                         ddr_bw_ch0->peri*ddr_freq/ddr_bw_val[0][ddrbw_time_num];
4476                 ddr_bw_ch0->video =
4477                         ddr_bw_ch0->video*
4478                                 ddr_freq/ddr_bw_val[0][ddrbw_time_num];
4479                 ddr_bw_ch0->vio0 =
4480                         ddr_bw_ch0->vio0*ddr_freq/ddr_bw_val[0][ddrbw_time_num];
4481                 ddr_bw_ch0->vio1 =
4482                         ddr_bw_ch0->vio1*ddr_freq/ddr_bw_val[0][ddrbw_time_num];
4483                 ddr_bw_ch0->vio2 =
4484                         ddr_bw_ch0->vio2*ddr_freq/ddr_bw_val[0][ddrbw_time_num];
4485         }
4486 end:
4487         ddr_monitor_start();
4488 }
4489
4490 /******************************************************************/
4491
4492 static int ddr_init(uint32 dram_speed_bin, uint32 freq)
4493 {
4494     uint32 tmp;
4495     uint32 die=1;
4496     uint32 gsr,dqstr;
4497     struct clk *clk;
4498     uint32 ch,cap=0,cs_cap;
4499
4500     ddr_print("version 1.00 20140603 \n");
4501
4502     p_ddr_reg = kern_to_pie(rockchip_pie_chunk, &DATA(ddr_reg));
4503     p_ddr_set_pll = fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_set_pll));
4504     DATA(p_cpu_pause) = kern_to_pie(rockchip_pie_chunk, &DATA(cpu_pause[0]));
4505
4506     tmp = clk_get_rate(clk_get(NULL, "clk_ddr"))/1000000;
4507     *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq)) = tmp;
4508     *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = 0;
4509
4510     for(ch=0;ch<CH_MAX;ch++)
4511     {
4512         p_ddr_ch[ch] = kern_to_pie(rockchip_pie_chunk, &DATA(ddr_ch[ch]));
4513
4514         p_ddr_ch[ch]->chNum = ch;
4515         p_ddr_ch[ch]->pDDR_Reg = pDDR_REG(ch);
4516         p_ddr_ch[ch]->pPHY_Reg = pPHY_REG(ch);
4517         p_ddr_ch[ch]->pMSCH_Reg = pMSCH_REG(ch);
4518
4519         if(!(READ_CH_INFO()&(1<<ch)))
4520         {
4521             p_ddr_ch[ch]->mem_type = DRAM_MAX;
4522             continue;
4523         }
4524         else
4525         {
4526             if(ch)
4527             {
4528                 ddr_print("Channel b: \n");
4529             }
4530             else
4531             {
4532                 ddr_print("Channel a: \n");
4533             }
4534             tmp = p_ddr_ch[ch]->pPHY_Reg->DCR.b.DDRMD;
4535             if((tmp ==  LPDDR2) && (READ_DRAMTYPE_INFO() == 6))
4536             {
4537                 tmp = LPDDR3;
4538             }
4539             switch(tmp)
4540             {
4541                 case DDR3:
4542                     ddr_print("DDR3 Device\n");
4543                     break;
4544                 case LPDDR3:
4545                     ddr_print("LPDDR3 Device\n");
4546                     break;
4547                 case LPDDR2:
4548                     ddr_print("LPDDR2 Device\n");
4549                     break;
4550                 default:
4551                     ddr_print("Unkown Device\n");
4552                     tmp = DRAM_MAX;
4553                     break;
4554             }
4555             p_ddr_ch[ch]->mem_type = tmp;
4556             if(tmp == DRAM_MAX)
4557             {
4558                 p_ddr_ch[ch]->mem_type = DRAM_MAX;
4559                 continue;
4560             }
4561         }
4562
4563         p_ddr_ch[ch]->ddr_speed_bin = dram_speed_bin;
4564         //get capability per chip, not total size, used for calculate tRFC
4565         die = (8<<READ_BW_INFO(ch))/(8<<READ_DIE_BW_INFO(ch));
4566         cap = (1 << (READ_ROW_INFO(ch,0)+READ_COL_INFO(ch)+READ_BK_INFO(ch)+READ_BW_INFO(ch)));
4567         cs_cap = cap;
4568         if(READ_CS_INFO(ch) > 1)
4569         {
4570             cap += cap >> (READ_ROW_INFO(ch,0)-READ_ROW_INFO(ch,1));
4571         }
4572         if(READ_CH_ROW_INFO(ch))
4573         {
4574             cap = cap*3/4;
4575         }
4576         p_ddr_ch[ch]->ddr_capability_per_die = cs_cap/die;
4577         ddr_print("Bus Width=%d Col=%d Bank=%d Row=%d CS=%d Total Capability=%dMB\n",
4578                                                                         READ_BW_INFO(ch)*16,\
4579                                                                         READ_COL_INFO(ch), \
4580                                                                         (0x1<<(READ_BK_INFO(ch))), \
4581                                                                         READ_ROW_INFO(ch,0), \
4582                                                                         READ_CS_INFO(ch), \
4583                                                                         (cap>>20));
4584     }
4585
4586     ddr_adjust_config();
4587
4588     clk = clk_get(NULL, "clk_ddr");
4589     if (IS_ERR(clk)) {
4590         ddr_print("failed to get ddr clk\n");
4591         clk = NULL;
4592     }
4593     if(freq != 0)
4594         tmp = clk_set_rate(clk, 1000*1000*freq);
4595     else
4596         tmp = clk_set_rate(clk, clk_get_rate(clk));
4597     ddr_print("init success!!! freq=%luMHz\n", clk ? clk_get_rate(clk)/1000000 : freq);
4598
4599     for(ch=0;ch<CH_MAX;ch++)
4600     {
4601         if(p_ddr_ch[ch]->mem_type != DRAM_MAX)
4602         {
4603             if(ch)
4604             {
4605                 ddr_print("Channel b: \n");
4606             }
4607             else
4608             {
4609                 ddr_print("Channel a: \n");
4610             }
4611             for(tmp=0;tmp<4;tmp++)
4612             {
4613                 gsr = p_ddr_ch[ch]->pPHY_Reg->DATX8[tmp].DXGSR[0];
4614                 dqstr = p_ddr_ch[ch]->pPHY_Reg->DATX8[tmp].DXDQSTR;
4615                 ddr_print("DTONE=0x%x, DTERR=0x%x, DTIERR=0x%x, DTPASS=%d,%d, DGSL=%d,%d extra clock, DGPS=%d,%d\n", \
4616                                                                     (gsr&0xF), ((gsr>>4)&0xF), ((gsr>>8)&0xF), \
4617                                                                     ((gsr>>13)&0x7), ((gsr>>16)&0x7),\
4618                                                                     (dqstr&0x7), ((dqstr>>3)&0x7),\
4619                                                                     ((((dqstr>>12)&0x3)+1)*90), ((((dqstr>>14)&0x3)+1)*90));
4620             }
4621             ddr_print("ZERR=%x, ZDONE=%x, ZPD=0x%x, ZPU=0x%x, OPD=0x%x, OPU=0x%x\n", \
4622                                                         (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>30)&0x1, \
4623                                                         (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>31)&0x1, \
4624                                                         p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[1]&0x3,\
4625                                                         (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[1]>>2)&0x3,\
4626                                                         (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[1]>>4)&0x3,\
4627                                                         (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[1]>>6)&0x3);
4628             ddr_print("DRV Pull-Up=0x%x, DRV Pull-Dwn=0x%x\n", p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]&0x1F, (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>5)&0x1F);
4629             ddr_print("ODT Pull-Up=0x%x, ODT Pull-Dwn=0x%x\n", (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>10)&0x1F, (p_ddr_ch[ch]->pPHY_Reg->ZQ0SR[0]>>15)&0x1F);
4630         }
4631     }
4632
4633     return 0;
4634 }
4635