arch/arm/mach-rockchip/common.c

   1 /*
   2  * Copyright (C) 2013-2014 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/clk-provider.h>
  16 #include <linux/genalloc.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/kernel.h>
  20 #include <linux/of_address.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/of_fdt.h>
  23 #include <asm/cputype.h>
  24 #include <asm/hardware/cache-l2x0.h>
  25 #include <linux/rockchip/common.h>
  26 #include <linux/rockchip/pmu.h>
  27 #include "cpu_axi.h"
  28 #include "loader.h"
  29 #include "sram.h"
  30
  31 static int __init rockchip_cpu_axi_init(void)
  32 {
  33         struct device_node *np, *gp, *cp;
  34         void __iomem *base;
  35
  36         np = of_find_compatible_node(NULL, NULL, "rockchip,cpu_axi_bus");
  37         if (!np)
  38                 return -ENODEV;
  39
  40 #define MAP(base) if (!base) base = of_iomap(cp, 0); if (!base) continue;
  41
  42         gp = of_get_child_by_name(np, "qos");
  43         if (gp) {
  44                 for_each_child_of_node(gp, cp) {
  45                         u32 priority[2], mode, bandwidth, saturation, extcontrol;
  46                         base = NULL;
  47 #ifdef DEBUG
  48                         {
  49                                 struct resource r;
  50                                 of_address_to_resource(cp, 0, &r);
  51                                 pr_debug("qos: %s [%x ~ %x]\n", cp->name, r.start, r.end);
  52                         }
  53 #endif
  54                         if (!of_property_read_u32_array(cp, "rockchip,priority", priority, ARRAY_SIZE(priority))) {
  55                                 MAP(base);
  56                                 CPU_AXI_SET_QOS_PRIORITY(priority[0], priority[1], base);
  57                                 pr_debug("qos: %s priority %x %x\n", cp->name, priority[0], priority[1]);
  58                         }
  59                         if (!of_property_read_u32(cp, "rockchip,mode", &mode)) {
  60                                 MAP(base);
  61                                 CPU_AXI_SET_QOS_MODE(mode, base);
  62                                 pr_debug("qos: %s mode %x\n", cp->name, mode);
  63                         }
  64                         if (!of_property_read_u32(cp, "rockchip,bandwidth", &bandwidth)) {
  65                                 MAP(base);
  66                                 CPU_AXI_SET_QOS_BANDWIDTH(bandwidth, base);
  67                                 pr_debug("qos: %s bandwidth %x\n", cp->name, bandwidth);
  68                         }
  69                         if (!of_property_read_u32(cp, "rockchip,saturation", &saturation)) {
  70                                 MAP(base);
  71                                 CPU_AXI_SET_QOS_SATURATION(saturation, base);
  72                                 pr_debug("qos: %s saturation %x\n", cp->name, saturation);
  73                         }
  74                         if (!of_property_read_u32(cp, "rockchip,extcontrol", &extcontrol)) {
  75                                 MAP(base);
  76                                 CPU_AXI_SET_QOS_EXTCONTROL(extcontrol, base);
  77                                 pr_debug("qos: %s extcontrol %x\n", cp->name, extcontrol);
  78                         }
  79                         if (base)
  80                                 iounmap(base);
  81                 }
  82         };
  83
  84         gp = of_get_child_by_name(np, "msch");
  85         if (gp) {
  86                 for_each_child_of_node(gp, cp) {
  87                         u32 val;
  88                         base = NULL;
  89 #ifdef DEBUG
  90                         {
  91                                 struct resource r;
  92                                 of_address_to_resource(cp, 0, &r);
  93                                 pr_debug("msch: %s [%x ~ %x]\n", cp->name, r.start, r.end);
  94                         }
  95 #endif
  96                         if (!of_property_read_u32(cp, "rockchip,read-latency", &val)) {
  97                                 MAP(base);
  98                                 writel_relaxed(val, base + 0x0014);     // memory scheduler read latency
  99                                 pr_debug("msch: %s read latency %x\n", cp->name, val);
 100                         }
 101                         if (base)
 102                                 iounmap(base);
 103                 }
 104         }
 105         dsb(sy);
 106
 107 #undef MAP
 108
 109         return 0;
 110 }
 111 early_initcall(rockchip_cpu_axi_init);
 112
 113 static int __init rockchip_pl330_l2_cache_init(void)
 114 {
 115         struct device_node *np;
 116         void __iomem *base;
 117         u32 aux[2] = { 0, ~0 }, prefetch, power;
 118
 119         if (read_cpuid_part_number() != ARM_CPU_PART_CORTEX_A9)
 120                 return -ENODEV;
 121
 122         np = of_find_compatible_node(NULL, NULL, "rockchip,pl310-cache");
 123         if (!np)
 124                 return -ENODEV;
 125
 126         base = of_iomap(np, 0);
 127         if (!base)
 128                 return -EINVAL;
 129
 130         if (!of_property_read_u32(np, "rockchip,prefetch-ctrl", &prefetch)) {
 131                 /* L2X0 Prefetch Control */
 132                 writel_relaxed(prefetch, base + L2X0_PREFETCH_CTRL);
 133                 pr_debug("l2c: prefetch %x\n", prefetch);
 134         }
 135
 136         if (!of_property_read_u32(np, "rockchip,power-ctrl", &power)) {
 137                 /* L2X0 Power Control */
 138                 writel_relaxed(power, base + L2X0_POWER_CTRL);
 139                 pr_debug("l2c: power %x\n", power);
 140         }
 141
 142         iounmap(base);
 143
 144         of_property_read_u32_array(np, "rockchip,aux-ctrl", aux, ARRAY_SIZE(aux));
 145         pr_debug("l2c: aux %08x mask %08x\n", aux[0], aux[1]);
 146
 147         l2x0_of_init(aux[0], aux[1]);
 148
 149         return 0;
 150 }
 151 early_initcall(rockchip_pl330_l2_cache_init);
 152
 153 struct gen_pool *rockchip_sram_pool = NULL;
 154 struct pie_chunk *rockchip_pie_chunk = NULL;
 155 void *rockchip_sram_virt = NULL;
 156 size_t rockchip_sram_size = 0;
 157 char *rockchip_sram_stack = NULL;
 158
 159 #ifdef CONFIG_PIE
 160 int __init rockchip_pie_init(void)
 161 {
 162         struct device_node *np;
 163
 164         np = of_find_node_by_path("/");
 165         if (!np)
 166                 return -ENODEV;
 167
 168         rockchip_sram_pool = of_get_named_gen_pool(np, "rockchip,sram", 0);
 169         if (!rockchip_sram_pool) {
 170                 pr_err("%s: failed to get sram pool\n", __func__);
 171                 return -ENODEV;
 172         }
 173         rockchip_sram_size = gen_pool_size(rockchip_sram_pool);
 174
 175         return 0;
 176 }
 177 #endif
 178
 179 static bool is_panic = false;
 180 extern void console_disable_suspend(void);
 181
 182 static int panic_event(struct notifier_block *this, unsigned long event, void *ptr)
 183 {
 184 #if CONFIG_RK_DEBUG_UART >= 0
 185         console_disable_suspend();
 186 #endif
 187         is_panic = true;
 188         return NOTIFY_DONE;
 189 }
 190
 191 static struct notifier_block panic_block = {
 192         .notifier_call  = panic_event,
 193 };
 194
 195 static int boot_mode;
 196
 197 int rockchip_boot_mode(void)
 198 {
 199         return boot_mode;
 200 }
 201 EXPORT_SYMBOL(rockchip_boot_mode);
 202
 203 static inline const char *boot_flag_name(u32 flag)
 204 {
 205         flag -= SYS_KERNRL_REBOOT_FLAG;
 206         switch (flag) {
 207         case BOOT_NORMAL: return "NORMAL";
 208         case BOOT_LOADER: return "LOADER";
 209         case BOOT_MASKROM: return "MASKROM";
 210         case BOOT_RECOVER: return "RECOVER";
 211         case BOOT_NORECOVER: return "NORECOVER";
 212         case BOOT_SECONDOS: return "SECONDOS";
 213         case BOOT_WIPEDATA: return "WIPEDATA";
 214         case BOOT_WIPEALL: return "WIPEALL";
 215         case BOOT_CHECKIMG: return "CHECKIMG";
 216         case BOOT_FASTBOOT: return "FASTBOOT";
 217         case BOOT_CHARGING: return "CHARGING";
 218         default: return "";
 219         }
 220 }
 221
 222 static inline const char *boot_mode_name(u32 mode)
 223 {
 224         switch (mode) {
 225         case BOOT_MODE_NORMAL: return "NORMAL";
 226         case BOOT_MODE_FACTORY2: return "FACTORY2";
 227         case BOOT_MODE_RECOVERY: return "RECOVERY";
 228         case BOOT_MODE_CHARGE: return "CHARGE";
 229         case BOOT_MODE_POWER_TEST: return "POWER_TEST";
 230         case BOOT_MODE_OFFMODE_CHARGING: return "OFFMODE_CHARGING";
 231         case BOOT_MODE_REBOOT: return "REBOOT";
 232         case BOOT_MODE_PANIC: return "PANIC";
 233         case BOOT_MODE_WATCHDOG: return "WATCHDOG";
 234         case BOOT_MODE_TSADC: return "TSADC";
 235         default: return "";
 236         }
 237 }
 238
 239 void __init rockchip_boot_mode_init(u32 flag, u32 mode)
 240 {
 241         boot_mode = mode;
 242         if (mode || ((flag & 0xff) && ((flag & 0xffffff00) == SYS_KERNRL_REBOOT_FLAG)))
 243                 printk("Boot mode: %s (%d) flag: %s (0x%08x)\n", boot_mode_name(mode), mode, boot_flag_name(flag), flag);
 244         atomic_notifier_chain_register(&panic_notifier_list, &panic_block);
 245 }
 246
 247 void rockchip_restart_get_boot_mode(const char *cmd, u32 *flag, u32 *mode)
 248 {
 249         *flag = SYS_LOADER_REBOOT_FLAG + BOOT_NORMAL;
 250         *mode = BOOT_MODE_REBOOT;
 251
 252         if (cmd) {
 253                 if (!strcmp(cmd, "loader") || !strcmp(cmd, "bootloader"))
 254                         *flag = SYS_LOADER_REBOOT_FLAG + BOOT_LOADER;
 255                 else if(!strcmp(cmd, "recovery"))
 256                         *flag = SYS_LOADER_REBOOT_FLAG + BOOT_RECOVER;
 257                 else if (!strcmp(cmd, "fastboot"))
 258                         *flag = SYS_LOADER_REBOOT_FLAG + BOOT_FASTBOOT;
 259                 else if (!strcmp(cmd, "charge")) {
 260                         *flag = SYS_LOADER_REBOOT_FLAG + BOOT_CHARGING;
 261                         *mode = BOOT_MODE_CHARGE;
 262                 }
 263         } else {
 264                 if (is_panic)
 265                         *mode = BOOT_MODE_PANIC;
 266         }
 267 }
 268
 269 struct rockchip_pmu_operations rockchip_pmu_ops;
 270 void (*ddr_bandwidth_get)(struct ddr_bw_info *ddr_bw_ch0,
 271                           struct ddr_bw_info *ddr_bw_ch1);
 272 int (*ddr_change_freq)(uint32_t nMHz) = NULL;
 273 long (*ddr_round_rate)(uint32_t nMHz) = NULL;
 274 void (*ddr_set_auto_self_refresh)(bool en) = NULL;
 275
 276 extern struct ion_platform_data ion_pdata;
 277 extern void __init ion_reserve(struct ion_platform_data *data);
 278 extern int __init rockchip_ion_find_heap(unsigned long node,
 279                                 const char *uname, int depth, void *data);
 280 void __init rockchip_ion_reserve(void)
 281 {
 282 #ifdef CONFIG_ION_ROCKCHIP
 283         printk("%s\n", __func__);
 284         of_scan_flat_dt(rockchip_ion_find_heap, (void*)&ion_pdata);
 285         ion_reserve(&ion_pdata);
 286 #endif
 287 }
 288
 289 bool rockchip_jtag_enabled = false;
 290 static int __init rockchip_jtag_enable(char *__unused)
 291 {
 292         rockchip_jtag_enabled = true;
 293         printk("rockchip jtag enabled\n");
 294         return 1;
 295 }
 296 __setup("rockchip_jtag", rockchip_jtag_enable);