arch/arm/mach-omap2/omap_twl.c

   1 /**
   2  * OMAP and TWL PMIC specific intializations.
   3  *
   4  * Copyright (C) 2010 Texas Instruments Incorporated.
   5  * Thara Gopinath
   6  * Copyright (C) 2009 Texas Instruments Incorporated.
   7  * Nishanth Menon
   8  * Copyright (C) 2009 Nokia Corporation
   9  * Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/i2c/twl.h>
  20
  21 #include "soc.h"
  22 #include "voltage.h"
  23
  24 #include "pm.h"
  25
  26 #define OMAP3_SRI2C_SLAVE_ADDR          0x12
  27 #define OMAP3_VDD_MPU_SR_CONTROL_REG    0x00
  28 #define OMAP3_VDD_CORE_SR_CONTROL_REG   0x01
  29 #define OMAP3_VP_CONFIG_ERROROFFSET     0x00
  30 #define OMAP3_VP_VSTEPMIN_VSTEPMIN      0x1
  31 #define OMAP3_VP_VSTEPMAX_VSTEPMAX      0x04
  32 #define OMAP3_VP_VLIMITTO_TIMEOUT_US    200
  33
  34 #define OMAP4_SRI2C_SLAVE_ADDR          0x12
  35 #define OMAP4_VDD_MPU_SR_VOLT_REG       0x55
  36 #define OMAP4_VDD_MPU_SR_CMD_REG        0x56
  37 #define OMAP4_VDD_IVA_SR_VOLT_REG       0x5B
  38 #define OMAP4_VDD_IVA_SR_CMD_REG        0x5C
  39 #define OMAP4_VDD_CORE_SR_VOLT_REG      0x61
  40 #define OMAP4_VDD_CORE_SR_CMD_REG       0x62
  41
  42 #define OMAP4_VP_CONFIG_ERROROFFSET     0x00
  43 #define OMAP4_VP_VSTEPMIN_VSTEPMIN      0x01
  44 #define OMAP4_VP_VSTEPMAX_VSTEPMAX      0x04
  45 #define OMAP4_VP_VLIMITTO_TIMEOUT_US    200
  46
  47 static bool is_offset_valid;
  48 static u8 smps_offset;
  49 /*
  50  * Flag to ensure Smartreflex bit in TWL
  51  * being cleared in board file is not overwritten.
  52  */
  53 static bool __initdata twl_sr_enable_autoinit;
  54
  55 #define TWL4030_DCDC_GLOBAL_CFG        0x06
  56 #define REG_SMPS_OFFSET         0xE0
  57 #define SMARTREFLEX_ENABLE     BIT(3)
  58
  59 static unsigned long twl4030_vsel_to_uv(const u8 vsel)
  60 {
  61         return (((vsel * 125) + 6000)) * 100;
  62 }
  63
  64 static u8 twl4030_uv_to_vsel(unsigned long uv)
  65 {
  66         return DIV_ROUND_UP(uv - 600000, 12500);
  67 }
  68
  69 static unsigned long twl6030_vsel_to_uv(const u8 vsel)
  70 {
  71         /*
  72          * In TWL6030 depending on the value of SMPS_OFFSET
  73          * efuse register the voltage range supported in
  74          * standard mode can be either between 0.6V - 1.3V or
  75          * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
  76          * is programmed to all 0's where as starting from
  77          * TWL6030 ES1.1 the efuse is programmed to 1
  78          */
  79         if (!is_offset_valid) {
  80                 twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
  81                                 REG_SMPS_OFFSET);
  82                 is_offset_valid = true;
  83         }
  84
  85         if (!vsel)
  86                 return 0;
  87         /*
  88          * There is no specific formula for voltage to vsel
  89          * conversion above 1.3V. There are special hardcoded
  90          * values for voltages above 1.3V. Currently we are
  91          * hardcoding only for 1.35 V which is used for 1GH OPP for
  92          * OMAP4430.
  93          */
  94         if (vsel == 0x3A)
  95                 return 1350000;
  96
  97         if (smps_offset & 0x8)
  98                 return ((((vsel - 1) * 1266) + 70900)) * 10;
  99         else
 100                 return ((((vsel - 1) * 1266) + 60770)) * 10;
 101 }
 102
 103 static u8 twl6030_uv_to_vsel(unsigned long uv)
 104 {
 105         /*
 106          * In TWL6030 depending on the value of SMPS_OFFSET
 107          * efuse register the voltage range supported in
 108          * standard mode can be either between 0.6V - 1.3V or
 109          * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
 110          * is programmed to all 0's where as starting from
 111          * TWL6030 ES1.1 the efuse is programmed to 1
 112          */
 113         if (!is_offset_valid) {
 114                 twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
 115                                 REG_SMPS_OFFSET);
 116                 is_offset_valid = true;
 117         }
 118
 119         if (!uv)
 120                 return 0x00;
 121         /*
 122          * There is no specific formula for voltage to vsel
 123          * conversion above 1.3V. There are special hardcoded
 124          * values for voltages above 1.3V. Currently we are
 125          * hardcoding only for 1.35 V which is used for 1GH OPP for
 126          * OMAP4430.
 127          */
 128         if (uv > twl6030_vsel_to_uv(0x39)) {
 129                 if (uv == 1350000)
 130                         return 0x3A;
 131                 pr_err("%s:OUT OF RANGE! non mapped vsel for %ld Vs max %ld\n",
 132                         __func__, uv, twl6030_vsel_to_uv(0x39));
 133                 return 0x3A;
 134         }
 135
 136         if (smps_offset & 0x8)
 137                 return DIV_ROUND_UP(uv - 709000, 12660) + 1;
 138         else
 139                 return DIV_ROUND_UP(uv - 607700, 12660) + 1;
 140 }
 141
 142 static struct omap_voltdm_pmic omap3_mpu_pmic = {
 143         .slew_rate              = 4000,
 144         .step_size              = 12500,
 145         .vp_erroroffset         = OMAP3_VP_CONFIG_ERROROFFSET,
 146         .vp_vstepmin            = OMAP3_VP_VSTEPMIN_VSTEPMIN,
 147         .vp_vstepmax            = OMAP3_VP_VSTEPMAX_VSTEPMAX,
 148         .vddmin                 = 600000,
 149         .vddmax                 = 1450000,
 150         .vp_timeout_us          = OMAP3_VP_VLIMITTO_TIMEOUT_US,
 151         .i2c_slave_addr         = OMAP3_SRI2C_SLAVE_ADDR,
 152         .volt_reg_addr          = OMAP3_VDD_MPU_SR_CONTROL_REG,
 153         .i2c_high_speed         = true,
 154         .vsel_to_uv             = twl4030_vsel_to_uv,
 155         .uv_to_vsel             = twl4030_uv_to_vsel,
 156 };
 157
 158 static struct omap_voltdm_pmic omap3_core_pmic = {
 159         .slew_rate              = 4000,
 160         .step_size              = 12500,
 161         .vp_erroroffset         = OMAP3_VP_CONFIG_ERROROFFSET,
 162         .vp_vstepmin            = OMAP3_VP_VSTEPMIN_VSTEPMIN,
 163         .vp_vstepmax            = OMAP3_VP_VSTEPMAX_VSTEPMAX,
 164         .vddmin                 = 600000,
 165         .vddmax                 = 1450000,
 166         .vp_timeout_us          = OMAP3_VP_VLIMITTO_TIMEOUT_US,
 167         .i2c_slave_addr         = OMAP3_SRI2C_SLAVE_ADDR,
 168         .volt_reg_addr          = OMAP3_VDD_CORE_SR_CONTROL_REG,
 169         .i2c_high_speed         = true,
 170         .vsel_to_uv             = twl4030_vsel_to_uv,
 171         .uv_to_vsel             = twl4030_uv_to_vsel,
 172 };
 173
 174 static struct omap_voltdm_pmic omap4_mpu_pmic = {
 175         .slew_rate              = 4000,
 176         .step_size              = 12660,
 177         .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
 178         .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
 179         .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
 180         .vddmin                 = 0,
 181         .vddmax                 = 2100000,
 182         .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
 183         .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
 184         .volt_reg_addr          = OMAP4_VDD_MPU_SR_VOLT_REG,
 185         .cmd_reg_addr           = OMAP4_VDD_MPU_SR_CMD_REG,
 186         .i2c_high_speed         = true,
 187         .i2c_pad_load           = 3,
 188         .vsel_to_uv             = twl6030_vsel_to_uv,
 189         .uv_to_vsel             = twl6030_uv_to_vsel,
 190 };
 191
 192 static struct omap_voltdm_pmic omap4_iva_pmic = {
 193         .slew_rate              = 4000,
 194         .step_size              = 12660,
 195         .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
 196         .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
 197         .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
 198         .vddmin                 = 0,
 199         .vddmax                 = 2100000,
 200         .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
 201         .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
 202         .volt_reg_addr          = OMAP4_VDD_IVA_SR_VOLT_REG,
 203         .cmd_reg_addr           = OMAP4_VDD_IVA_SR_CMD_REG,
 204         .i2c_high_speed         = true,
 205         .i2c_pad_load           = 3,
 206         .vsel_to_uv             = twl6030_vsel_to_uv,
 207         .uv_to_vsel             = twl6030_uv_to_vsel,
 208 };
 209
 210 static struct omap_voltdm_pmic omap4_core_pmic = {
 211         .slew_rate              = 4000,
 212         .step_size              = 12660,
 213         .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
 214         .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
 215         .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
 216         .vddmin                 = 0,
 217         .vddmax                 = 2100000,
 218         .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
 219         .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
 220         .volt_reg_addr          = OMAP4_VDD_CORE_SR_VOLT_REG,
 221         .cmd_reg_addr           = OMAP4_VDD_CORE_SR_CMD_REG,
 222         .i2c_high_speed         = true,
 223         .i2c_pad_load           = 3,
 224         .vsel_to_uv             = twl6030_vsel_to_uv,
 225         .uv_to_vsel             = twl6030_uv_to_vsel,
 226 };
 227
 228 int __init omap4_twl_init(void)
 229 {
 230         struct voltagedomain *voltdm;
 231
 232         if (!cpu_is_omap44xx())
 233                 return -ENODEV;
 234
 235         voltdm = voltdm_lookup("mpu");
 236         omap_voltage_register_pmic(voltdm, &omap4_mpu_pmic);
 237
 238         voltdm = voltdm_lookup("iva");
 239         omap_voltage_register_pmic(voltdm, &omap4_iva_pmic);
 240
 241         voltdm = voltdm_lookup("core");
 242         omap_voltage_register_pmic(voltdm, &omap4_core_pmic);
 243
 244         return 0;
 245 }
 246
 247 int __init omap3_twl_init(void)
 248 {
 249         struct voltagedomain *voltdm;
 250
 251         if (!cpu_is_omap34xx())
 252                 return -ENODEV;
 253
 254         /*
 255          * The smartreflex bit on twl4030 specifies if the setting of voltage
 256          * is done over the I2C_SR path. Since this setting is independent of
 257          * the actual usage of smartreflex AVS module, we enable TWL SR bit
 258          * by default irrespective of whether smartreflex AVS module is enabled
 259          * on the OMAP side or not. This is because without this bit enabled,
 260          * the voltage scaling through vp forceupdate/bypass mechanism of
 261          * voltage scaling will not function on TWL over I2C_SR.
 262          */
 263         if (!twl_sr_enable_autoinit)
 264                 omap3_twl_set_sr_bit(true);
 265
 266         voltdm = voltdm_lookup("mpu_iva");
 267         omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic);
 268
 269         voltdm = voltdm_lookup("core");
 270         omap_voltage_register_pmic(voltdm, &omap3_core_pmic);
 271
 272         return 0;
 273 }
 274
 275 /**
 276  * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
 277  * @enable: enable SR mode in twl or not
 278  *
 279  * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
 280  * voltage scaling through OMAP SR works. Else, the smartreflex bit
 281  * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
 282  * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
 283  * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
 284  * in those scenarios this bit is to be cleared (enable = false).
 285  *
 286  * Returns 0 on success, error is returned if I2C read/write fails.
 287  */
 288 int __init omap3_twl_set_sr_bit(bool enable)
 289 {
 290         u8 temp;
 291         int ret;
 292         if (twl_sr_enable_autoinit)
 293                 pr_warning("%s: unexpected multiple calls\n", __func__);
 294
 295         ret = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp,
 296                               TWL4030_DCDC_GLOBAL_CFG);
 297         if (ret)
 298                 goto err;
 299
 300         if (enable)
 301                 temp |= SMARTREFLEX_ENABLE;
 302         else
 303                 temp &= ~SMARTREFLEX_ENABLE;
 304
 305         ret = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp,
 306                                TWL4030_DCDC_GLOBAL_CFG);
 307         if (!ret) {
 308                 twl_sr_enable_autoinit = true;
 309                 return 0;
 310         }
 311 err:
 312         pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret);
 313         return ret;
 314 }