arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22 #include <linux/platform_data/gpio-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/platform_data/omap_ocp2scp.h>
  25 #include <linux/i2c-omap.h>
  26
  27 #include <linux/omap-dma.h>
  28
  29 #include <linux/platform_data/spi-omap2-mcspi.h>
  30 #include <linux/platform_data/asoc-ti-mcbsp.h>
  31 #include <linux/platform_data/iommu-omap.h>
  32 #include <plat/dmtimer.h>
  33
  34 #include "omap_hwmod.h"
  35 #include "omap_hwmod_common_data.h"
  36 #include "cm1_44xx.h"
  37 #include "cm2_44xx.h"
  38 #include "prm44xx.h"
  39 #include "prm-regbits-44xx.h"
  40 #include "i2c.h"
  41 #include "mmc.h"
  42 #include "wd_timer.h"
  43
  44 /* Base offset for all OMAP4 interrupts external to MPUSS */
  45 #define OMAP44XX_IRQ_GIC_START  32
  46
  47 /* Base offset for all OMAP4 dma requests */
  48 #define OMAP44XX_DMA_REQ_START  1
  49
  50 /*
  51  * IP blocks
  52  */
  53
  54 /*
  55  * 'c2c_target_fw' class
  56  * instance(s): c2c_target_fw
  57  */
  58 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  59         .name   = "c2c_target_fw",
  60 };
  61
  62 /* c2c_target_fw */
  63 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  64         .name           = "c2c_target_fw",
  65         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  66         .clkdm_name     = "d2d_clkdm",
  67         .prcm = {
  68                 .omap4 = {
  69                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  70                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  71                 },
  72         },
  73 };
  74
  75 /*
  76  * 'dmm' class
  77  * instance(s): dmm
  78  */
  79 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  80         .name   = "dmm",
  81 };
  82
  83 /* dmm */
  84 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  85         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  86         { .irq = -1 }
  87 };
  88
  89 static struct omap_hwmod omap44xx_dmm_hwmod = {
  90         .name           = "dmm",
  91         .class          = &omap44xx_dmm_hwmod_class,
  92         .clkdm_name     = "l3_emif_clkdm",
  93         .mpu_irqs       = omap44xx_dmm_irqs,
  94         .prcm = {
  95                 .omap4 = {
  96                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  97                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  98                 },
  99         },
 100 };
 101
 102 /*
 103  * 'emif_fw' class
 104  * instance(s): emif_fw
 105  */
 106 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 107         .name   = "emif_fw",
 108 };
 109
 110 /* emif_fw */
 111 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 112         .name           = "emif_fw",
 113         .class          = &omap44xx_emif_fw_hwmod_class,
 114         .clkdm_name     = "l3_emif_clkdm",
 115         .prcm = {
 116                 .omap4 = {
 117                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 118                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 119                 },
 120         },
 121 };
 122
 123 /*
 124  * 'l3' class
 125  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 126  */
 127 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 128         .name   = "l3",
 129 };
 130
 131 /* l3_instr */
 132 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 133         .name           = "l3_instr",
 134         .class          = &omap44xx_l3_hwmod_class,
 135         .clkdm_name     = "l3_instr_clkdm",
 136         .prcm = {
 137                 .omap4 = {
 138                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 139                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 140                         .modulemode   = MODULEMODE_HWCTRL,
 141                 },
 142         },
 143 };
 144
 145 /* l3_main_1 */
 146 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 147         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 148         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 149         { .irq = -1 }
 150 };
 151
 152 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 153         .name           = "l3_main_1",
 154         .class          = &omap44xx_l3_hwmod_class,
 155         .clkdm_name     = "l3_1_clkdm",
 156         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 157         .prcm = {
 158                 .omap4 = {
 159                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 160                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 161                 },
 162         },
 163 };
 164
 165 /* l3_main_2 */
 166 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 167         .name           = "l3_main_2",
 168         .class          = &omap44xx_l3_hwmod_class,
 169         .clkdm_name     = "l3_2_clkdm",
 170         .prcm = {
 171                 .omap4 = {
 172                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 173                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 174                 },
 175         },
 176 };
 177
 178 /* l3_main_3 */
 179 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 180         .name           = "l3_main_3",
 181         .class          = &omap44xx_l3_hwmod_class,
 182         .clkdm_name     = "l3_instr_clkdm",
 183         .prcm = {
 184                 .omap4 = {
 185                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 186                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 187                         .modulemode   = MODULEMODE_HWCTRL,
 188                 },
 189         },
 190 };
 191
 192 /*
 193  * 'l4' class
 194  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 195  */
 196 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 197         .name   = "l4",
 198 };
 199
 200 /* l4_abe */
 201 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 202         .name           = "l4_abe",
 203         .class          = &omap44xx_l4_hwmod_class,
 204         .clkdm_name     = "abe_clkdm",
 205         .prcm = {
 206                 .omap4 = {
 207                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 208                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 209                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 210                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 211                 },
 212         },
 213 };
 214
 215 /* l4_cfg */
 216 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 217         .name           = "l4_cfg",
 218         .class          = &omap44xx_l4_hwmod_class,
 219         .clkdm_name     = "l4_cfg_clkdm",
 220         .prcm = {
 221                 .omap4 = {
 222                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 223                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 224                 },
 225         },
 226 };
 227
 228 /* l4_per */
 229 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 230         .name           = "l4_per",
 231         .class          = &omap44xx_l4_hwmod_class,
 232         .clkdm_name     = "l4_per_clkdm",
 233         .prcm = {
 234                 .omap4 = {
 235                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 236                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 237                 },
 238         },
 239 };
 240
 241 /* l4_wkup */
 242 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 243         .name           = "l4_wkup",
 244         .class          = &omap44xx_l4_hwmod_class,
 245         .clkdm_name     = "l4_wkup_clkdm",
 246         .prcm = {
 247                 .omap4 = {
 248                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 249                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 250                 },
 251         },
 252 };
 253
 254 /*
 255  * 'mpu_bus' class
 256  * instance(s): mpu_private
 257  */
 258 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 259         .name   = "mpu_bus",
 260 };
 261
 262 /* mpu_private */
 263 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 264         .name           = "mpu_private",
 265         .class          = &omap44xx_mpu_bus_hwmod_class,
 266         .clkdm_name     = "mpuss_clkdm",
 267         .prcm = {
 268                 .omap4 = {
 269                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 270                 },
 271         },
 272 };
 273
 274 /*
 275  * 'ocp_wp_noc' class
 276  * instance(s): ocp_wp_noc
 277  */
 278 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 279         .name   = "ocp_wp_noc",
 280 };
 281
 282 /* ocp_wp_noc */
 283 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 284         .name           = "ocp_wp_noc",
 285         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 286         .clkdm_name     = "l3_instr_clkdm",
 287         .prcm = {
 288                 .omap4 = {
 289                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 290                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 291                         .modulemode   = MODULEMODE_HWCTRL,
 292                 },
 293         },
 294 };
 295
 296 /*
 297  * Modules omap_hwmod structures
 298  *
 299  * The following IPs are excluded for the moment because:
 300  * - They do not need an explicit SW control using omap_hwmod API.
 301  * - They still need to be validated with the driver
 302  *   properly adapted to omap_hwmod / omap_device
 303  *
 304  * usim
 305  */
 306
 307 /*
 308  * 'aess' class
 309  * audio engine sub system
 310  */
 311
 312 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 313         .rev_offs       = 0x0000,
 314         .sysc_offs      = 0x0010,
 315         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 316         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 317                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 318                            MSTANDBY_SMART_WKUP),
 319         .sysc_fields    = &omap_hwmod_sysc_type2,
 320 };
 321
 322 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 323         .name   = "aess",
 324         .sysc   = &omap44xx_aess_sysc,
 325         .enable_preprogram = omap_hwmod_aess_preprogram,
 326 };
 327
 328 /* aess */
 329 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 330         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 331         { .irq = -1 }
 332 };
 333
 334 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 335         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 336         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 337         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 338         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 339         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 340         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 341         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 342         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 343         { .dma_req = -1 }
 344 };
 345
 346 static struct omap_hwmod omap44xx_aess_hwmod = {
 347         .name           = "aess",
 348         .class          = &omap44xx_aess_hwmod_class,
 349         .clkdm_name     = "abe_clkdm",
 350         .mpu_irqs       = omap44xx_aess_irqs,
 351         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 352         .main_clk       = "aess_fclk",
 353         .prcm = {
 354                 .omap4 = {
 355                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 356                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 357                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 358                         .modulemode   = MODULEMODE_SWCTRL,
 359                 },
 360         },
 361 };
 362
 363 /*
 364  * 'c2c' class
 365  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 366  * soc
 367  */
 368
 369 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 370         .name   = "c2c",
 371 };
 372
 373 /* c2c */
 374 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 375         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 376         { .irq = -1 }
 377 };
 378
 379 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 380         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 381         { .dma_req = -1 }
 382 };
 383
 384 static struct omap_hwmod omap44xx_c2c_hwmod = {
 385         .name           = "c2c",
 386         .class          = &omap44xx_c2c_hwmod_class,
 387         .clkdm_name     = "d2d_clkdm",
 388         .mpu_irqs       = omap44xx_c2c_irqs,
 389         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 390         .prcm = {
 391                 .omap4 = {
 392                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 393                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 394                 },
 395         },
 396 };
 397
 398 /*
 399  * 'counter' class
 400  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 401  */
 402
 403 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 404         .rev_offs       = 0x0000,
 405         .sysc_offs      = 0x0004,
 406         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 407         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 408         .sysc_fields    = &omap_hwmod_sysc_type1,
 409 };
 410
 411 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 412         .name   = "counter",
 413         .sysc   = &omap44xx_counter_sysc,
 414 };
 415
 416 /* counter_32k */
 417 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 418         .name           = "counter_32k",
 419         .class          = &omap44xx_counter_hwmod_class,
 420         .clkdm_name     = "l4_wkup_clkdm",
 421         .flags          = HWMOD_SWSUP_SIDLE,
 422         .main_clk       = "sys_32k_ck",
 423         .prcm = {
 424                 .omap4 = {
 425                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 426                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 427                 },
 428         },
 429 };
 430
 431 /*
 432  * 'ctrl_module' class
 433  * attila core control module + core pad control module + wkup pad control
 434  * module + attila wkup control module
 435  */
 436
 437 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 438         .rev_offs       = 0x0000,
 439         .sysc_offs      = 0x0010,
 440         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 441         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 442                            SIDLE_SMART_WKUP),
 443         .sysc_fields    = &omap_hwmod_sysc_type2,
 444 };
 445
 446 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 447         .name   = "ctrl_module",
 448         .sysc   = &omap44xx_ctrl_module_sysc,
 449 };
 450
 451 /* ctrl_module_core */
 452 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 453         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 454         { .irq = -1 }
 455 };
 456
 457 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 458         .name           = "ctrl_module_core",
 459         .class          = &omap44xx_ctrl_module_hwmod_class,
 460         .clkdm_name     = "l4_cfg_clkdm",
 461         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 462         .prcm = {
 463                 .omap4 = {
 464                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 465                 },
 466         },
 467 };
 468
 469 /* ctrl_module_pad_core */
 470 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 471         .name           = "ctrl_module_pad_core",
 472         .class          = &omap44xx_ctrl_module_hwmod_class,
 473         .clkdm_name     = "l4_cfg_clkdm",
 474         .prcm = {
 475                 .omap4 = {
 476                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 477                 },
 478         },
 479 };
 480
 481 /* ctrl_module_wkup */
 482 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 483         .name           = "ctrl_module_wkup",
 484         .class          = &omap44xx_ctrl_module_hwmod_class,
 485         .clkdm_name     = "l4_wkup_clkdm",
 486         .prcm = {
 487                 .omap4 = {
 488                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 489                 },
 490         },
 491 };
 492
 493 /* ctrl_module_pad_wkup */
 494 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 495         .name           = "ctrl_module_pad_wkup",
 496         .class          = &omap44xx_ctrl_module_hwmod_class,
 497         .clkdm_name     = "l4_wkup_clkdm",
 498         .prcm = {
 499                 .omap4 = {
 500                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 501                 },
 502         },
 503 };
 504
 505 /*
 506  * 'debugss' class
 507  * debug and emulation sub system
 508  */
 509
 510 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 511         .name   = "debugss",
 512 };
 513
 514 /* debugss */
 515 static struct omap_hwmod omap44xx_debugss_hwmod = {
 516         .name           = "debugss",
 517         .class          = &omap44xx_debugss_hwmod_class,
 518         .clkdm_name     = "emu_sys_clkdm",
 519         .main_clk       = "trace_clk_div_ck",
 520         .prcm = {
 521                 .omap4 = {
 522                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 523                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 524                 },
 525         },
 526 };
 527
 528 /*
 529  * 'dma' class
 530  * dma controller for data exchange between memory to memory (i.e. internal or
 531  * external memory) and gp peripherals to memory or memory to gp peripherals
 532  */
 533
 534 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 535         .rev_offs       = 0x0000,
 536         .sysc_offs      = 0x002c,
 537         .syss_offs      = 0x0028,
 538         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 539                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 540                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 541                            SYSS_HAS_RESET_STATUS),
 542         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 543                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 544         .sysc_fields    = &omap_hwmod_sysc_type1,
 545 };
 546
 547 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 548         .name   = "dma",
 549         .sysc   = &omap44xx_dma_sysc,
 550 };
 551
 552 /* dma dev_attr */
 553 static struct omap_dma_dev_attr dma_dev_attr = {
 554         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 555                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 556         .lch_count      = 32,
 557 };
 558
 559 /* dma_system */
 560 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 561         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 562         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 563         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 564         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 565         { .irq = -1 }
 566 };
 567
 568 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 569         .name           = "dma_system",
 570         .class          = &omap44xx_dma_hwmod_class,
 571         .clkdm_name     = "l3_dma_clkdm",
 572         .mpu_irqs       = omap44xx_dma_system_irqs,
 573         .main_clk       = "l3_div_ck",
 574         .prcm = {
 575                 .omap4 = {
 576                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 577                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 578                 },
 579         },
 580         .dev_attr       = &dma_dev_attr,
 581 };
 582
 583 /*
 584  * 'dmic' class
 585  * digital microphone controller
 586  */
 587
 588 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 589         .rev_offs       = 0x0000,
 590         .sysc_offs      = 0x0010,
 591         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 592                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 593         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 594                            SIDLE_SMART_WKUP),
 595         .sysc_fields    = &omap_hwmod_sysc_type2,
 596 };
 597
 598 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 599         .name   = "dmic",
 600         .sysc   = &omap44xx_dmic_sysc,
 601 };
 602
 603 /* dmic */
 604 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 605         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 606         { .irq = -1 }
 607 };
 608
 609 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 610         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 611         { .dma_req = -1 }
 612 };
 613
 614 static struct omap_hwmod omap44xx_dmic_hwmod = {
 615         .name           = "dmic",
 616         .class          = &omap44xx_dmic_hwmod_class,
 617         .clkdm_name     = "abe_clkdm",
 618         .mpu_irqs       = omap44xx_dmic_irqs,
 619         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 620         .main_clk       = "func_dmic_abe_gfclk",
 621         .prcm = {
 622                 .omap4 = {
 623                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 624                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 625                         .modulemode   = MODULEMODE_SWCTRL,
 626                 },
 627         },
 628 };
 629
 630 /*
 631  * 'dsp' class
 632  * dsp sub-system
 633  */
 634
 635 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 636         .name   = "dsp",
 637 };
 638
 639 /* dsp */
 640 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 641         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 642         { .irq = -1 }
 643 };
 644
 645 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 646         { .name = "dsp", .rst_shift = 0 },
 647 };
 648
 649 static struct omap_hwmod omap44xx_dsp_hwmod = {
 650         .name           = "dsp",
 651         .class          = &omap44xx_dsp_hwmod_class,
 652         .clkdm_name     = "tesla_clkdm",
 653         .mpu_irqs       = omap44xx_dsp_irqs,
 654         .rst_lines      = omap44xx_dsp_resets,
 655         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 656         .main_clk       = "dpll_iva_m4x2_ck",
 657         .prcm = {
 658                 .omap4 = {
 659                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 660                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 661                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 662                         .modulemode   = MODULEMODE_HWCTRL,
 663                 },
 664         },
 665 };
 666
 667 /*
 668  * 'dss' class
 669  * display sub-system
 670  */
 671
 672 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 673         .rev_offs       = 0x0000,
 674         .syss_offs      = 0x0014,
 675         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 676 };
 677
 678 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 679         .name   = "dss",
 680         .sysc   = &omap44xx_dss_sysc,
 681         .reset  = omap_dss_reset,
 682 };
 683
 684 /* dss */
 685 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 686         { .role = "sys_clk", .clk = "dss_sys_clk" },
 687         { .role = "tv_clk", .clk = "dss_tv_clk" },
 688         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 689 };
 690
 691 static struct omap_hwmod omap44xx_dss_hwmod = {
 692         .name           = "dss_core",
 693         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 694         .class          = &omap44xx_dss_hwmod_class,
 695         .clkdm_name     = "l3_dss_clkdm",
 696         .main_clk       = "dss_dss_clk",
 697         .prcm = {
 698                 .omap4 = {
 699                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 700                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 701                 },
 702         },
 703         .opt_clks       = dss_opt_clks,
 704         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 705 };
 706
 707 /*
 708  * 'dispc' class
 709  * display controller
 710  */
 711
 712 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 713         .rev_offs       = 0x0000,
 714         .sysc_offs      = 0x0010,
 715         .syss_offs      = 0x0014,
 716         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 717                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 718                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 719                            SYSS_HAS_RESET_STATUS),
 720         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 721                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 722         .sysc_fields    = &omap_hwmod_sysc_type1,
 723 };
 724
 725 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 726         .name   = "dispc",
 727         .sysc   = &omap44xx_dispc_sysc,
 728 };
 729
 730 /* dss_dispc */
 731 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 732         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 733         { .irq = -1 }
 734 };
 735
 736 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 737         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 738         { .dma_req = -1 }
 739 };
 740
 741 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 742         .manager_count          = 3,
 743         .has_framedonetv_irq    = 1
 744 };
 745
 746 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 747         .name           = "dss_dispc",
 748         .class          = &omap44xx_dispc_hwmod_class,
 749         .clkdm_name     = "l3_dss_clkdm",
 750         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 751         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 752         .main_clk       = "dss_dss_clk",
 753         .prcm = {
 754                 .omap4 = {
 755                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 756                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 757                 },
 758         },
 759         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 760 };
 761
 762 /*
 763  * 'dsi' class
 764  * display serial interface controller
 765  */
 766
 767 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 768         .rev_offs       = 0x0000,
 769         .sysc_offs      = 0x0010,
 770         .syss_offs      = 0x0014,
 771         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 772                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 773                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 774         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 775         .sysc_fields    = &omap_hwmod_sysc_type1,
 776 };
 777
 778 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 779         .name   = "dsi",
 780         .sysc   = &omap44xx_dsi_sysc,
 781 };
 782
 783 /* dss_dsi1 */
 784 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 785         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 786         { .irq = -1 }
 787 };
 788
 789 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 790         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 791         { .dma_req = -1 }
 792 };
 793
 794 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 795         { .role = "sys_clk", .clk = "dss_sys_clk" },
 796 };
 797
 798 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 799         .name           = "dss_dsi1",
 800         .class          = &omap44xx_dsi_hwmod_class,
 801         .clkdm_name     = "l3_dss_clkdm",
 802         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 803         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 804         .main_clk       = "dss_dss_clk",
 805         .prcm = {
 806                 .omap4 = {
 807                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 808                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 809                 },
 810         },
 811         .opt_clks       = dss_dsi1_opt_clks,
 812         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 813 };
 814
 815 /* dss_dsi2 */
 816 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 817         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 818         { .irq = -1 }
 819 };
 820
 821 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 822         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 823         { .dma_req = -1 }
 824 };
 825
 826 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 827         { .role = "sys_clk", .clk = "dss_sys_clk" },
 828 };
 829
 830 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 831         .name           = "dss_dsi2",
 832         .class          = &omap44xx_dsi_hwmod_class,
 833         .clkdm_name     = "l3_dss_clkdm",
 834         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 835         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 836         .main_clk       = "dss_dss_clk",
 837         .prcm = {
 838                 .omap4 = {
 839                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 840                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 841                 },
 842         },
 843         .opt_clks       = dss_dsi2_opt_clks,
 844         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 845 };
 846
 847 /*
 848  * 'hdmi' class
 849  * hdmi controller
 850  */
 851
 852 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 853         .rev_offs       = 0x0000,
 854         .sysc_offs      = 0x0010,
 855         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 856                            SYSC_HAS_SOFTRESET),
 857         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 858                            SIDLE_SMART_WKUP),
 859         .sysc_fields    = &omap_hwmod_sysc_type2,
 860 };
 861
 862 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 863         .name   = "hdmi",
 864         .sysc   = &omap44xx_hdmi_sysc,
 865 };
 866
 867 /* dss_hdmi */
 868 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 869         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 870         { .irq = -1 }
 871 };
 872
 873 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 874         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 875         { .dma_req = -1 }
 876 };
 877
 878 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 879         { .role = "sys_clk", .clk = "dss_sys_clk" },
 880 };
 881
 882 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 883         .name           = "dss_hdmi",
 884         .class          = &omap44xx_hdmi_hwmod_class,
 885         .clkdm_name     = "l3_dss_clkdm",
 886         /*
 887          * HDMI audio requires to use no-idle mode. Hence,
 888          * set idle mode by software.
 889          */
 890         .flags          = HWMOD_SWSUP_SIDLE,
 891         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 892         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 893         .main_clk       = "dss_48mhz_clk",
 894         .prcm = {
 895                 .omap4 = {
 896                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 897                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 898                 },
 899         },
 900         .opt_clks       = dss_hdmi_opt_clks,
 901         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 902 };
 903
 904 /*
 905  * 'rfbi' class
 906  * remote frame buffer interface
 907  */
 908
 909 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 910         .rev_offs       = 0x0000,
 911         .sysc_offs      = 0x0010,
 912         .syss_offs      = 0x0014,
 913         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 914                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 915         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 916         .sysc_fields    = &omap_hwmod_sysc_type1,
 917 };
 918
 919 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 920         .name   = "rfbi",
 921         .sysc   = &omap44xx_rfbi_sysc,
 922 };
 923
 924 /* dss_rfbi */
 925 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 926         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 927         { .dma_req = -1 }
 928 };
 929
 930 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 931         { .role = "ick", .clk = "dss_fck" },
 932 };
 933
 934 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 935         .name           = "dss_rfbi",
 936         .class          = &omap44xx_rfbi_hwmod_class,
 937         .clkdm_name     = "l3_dss_clkdm",
 938         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 939         .main_clk       = "dss_dss_clk",
 940         .prcm = {
 941                 .omap4 = {
 942                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 943                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 944                 },
 945         },
 946         .opt_clks       = dss_rfbi_opt_clks,
 947         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 948 };
 949
 950 /*
 951  * 'venc' class
 952  * video encoder
 953  */
 954
 955 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 956         .name   = "venc",
 957 };
 958
 959 /* dss_venc */
 960 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 961         .name           = "dss_venc",
 962         .class          = &omap44xx_venc_hwmod_class,
 963         .clkdm_name     = "l3_dss_clkdm",
 964         .main_clk       = "dss_tv_clk",
 965         .prcm = {
 966                 .omap4 = {
 967                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 968                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 969                 },
 970         },
 971 };
 972
 973 /*
 974  * 'elm' class
 975  * bch error location module
 976  */
 977
 978 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 979         .rev_offs       = 0x0000,
 980         .sysc_offs      = 0x0010,
 981         .syss_offs      = 0x0014,
 982         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 983                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 984                            SYSS_HAS_RESET_STATUS),
 985         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 986         .sysc_fields    = &omap_hwmod_sysc_type1,
 987 };
 988
 989 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 990         .name   = "elm",
 991         .sysc   = &omap44xx_elm_sysc,
 992 };
 993
 994 /* elm */
 995 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 996         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 997         { .irq = -1 }
 998 };
 999
1000 static struct omap_hwmod omap44xx_elm_hwmod = {
1001         .name           = "elm",
1002         .class          = &omap44xx_elm_hwmod_class,
1003         .clkdm_name     = "l4_per_clkdm",
1004         .mpu_irqs       = omap44xx_elm_irqs,
1005         .prcm = {
1006                 .omap4 = {
1007                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1008                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1009                 },
1010         },
1011 };
1012
1013 /*
1014  * 'emif' class
1015  * external memory interface no1
1016  */
1017
1018 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1019         .rev_offs       = 0x0000,
1020 };
1021
1022 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1023         .name   = "emif",
1024         .sysc   = &omap44xx_emif_sysc,
1025 };
1026
1027 /* emif1 */
1028 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1029         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1030         { .irq = -1 }
1031 };
1032
1033 static struct omap_hwmod omap44xx_emif1_hwmod = {
1034         .name           = "emif1",
1035         .class          = &omap44xx_emif_hwmod_class,
1036         .clkdm_name     = "l3_emif_clkdm",
1037         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1038         .mpu_irqs       = omap44xx_emif1_irqs,
1039         .main_clk       = "ddrphy_ck",
1040         .prcm = {
1041                 .omap4 = {
1042                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1043                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1044                         .modulemode   = MODULEMODE_HWCTRL,
1045                 },
1046         },
1047 };
1048
1049 /* emif2 */
1050 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1051         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1052         { .irq = -1 }
1053 };
1054
1055 static struct omap_hwmod omap44xx_emif2_hwmod = {
1056         .name           = "emif2",
1057         .class          = &omap44xx_emif_hwmod_class,
1058         .clkdm_name     = "l3_emif_clkdm",
1059         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1060         .mpu_irqs       = omap44xx_emif2_irqs,
1061         .main_clk       = "ddrphy_ck",
1062         .prcm = {
1063                 .omap4 = {
1064                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1065                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1066                         .modulemode   = MODULEMODE_HWCTRL,
1067                 },
1068         },
1069 };
1070
1071 /*
1072  * 'fdif' class
1073  * face detection hw accelerator module
1074  */
1075
1076 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1077         .rev_offs       = 0x0000,
1078         .sysc_offs      = 0x0010,
1079         /*
1080          * FDIF needs 100 OCP clk cycles delay after a softreset before
1081          * accessing sysconfig again.
1082          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1083          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1084          *
1085          * TODO: Indicate errata when available.
1086          */
1087         .srst_udelay    = 2,
1088         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1089                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1090         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1091                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1092         .sysc_fields    = &omap_hwmod_sysc_type2,
1093 };
1094
1095 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1096         .name   = "fdif",
1097         .sysc   = &omap44xx_fdif_sysc,
1098 };
1099
1100 /* fdif */
1101 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1102         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1103         { .irq = -1 }
1104 };
1105
1106 static struct omap_hwmod omap44xx_fdif_hwmod = {
1107         .name           = "fdif",
1108         .class          = &omap44xx_fdif_hwmod_class,
1109         .clkdm_name     = "iss_clkdm",
1110         .mpu_irqs       = omap44xx_fdif_irqs,
1111         .main_clk       = "fdif_fck",
1112         .prcm = {
1113                 .omap4 = {
1114                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1115                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1116                         .modulemode   = MODULEMODE_SWCTRL,
1117                 },
1118         },
1119 };
1120
1121 /*
1122  * 'gpio' class
1123  * general purpose io module
1124  */
1125
1126 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1127         .rev_offs       = 0x0000,
1128         .sysc_offs      = 0x0010,
1129         .syss_offs      = 0x0114,
1130         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1131                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1132                            SYSS_HAS_RESET_STATUS),
1133         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1134                            SIDLE_SMART_WKUP),
1135         .sysc_fields    = &omap_hwmod_sysc_type1,
1136 };
1137
1138 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1139         .name   = "gpio",
1140         .sysc   = &omap44xx_gpio_sysc,
1141         .rev    = 2,
1142 };
1143
1144 /* gpio dev_attr */
1145 static struct omap_gpio_dev_attr gpio_dev_attr = {
1146         .bank_width     = 32,
1147         .dbck_flag      = true,
1148 };
1149
1150 /* gpio1 */
1151 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1152         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1153         { .irq = -1 }
1154 };
1155
1156 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1157         { .role = "dbclk", .clk = "gpio1_dbclk" },
1158 };
1159
1160 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1161         .name           = "gpio1",
1162         .class          = &omap44xx_gpio_hwmod_class,
1163         .clkdm_name     = "l4_wkup_clkdm",
1164         .mpu_irqs       = omap44xx_gpio1_irqs,
1165         .main_clk       = "l4_wkup_clk_mux_ck",
1166         .prcm = {
1167                 .omap4 = {
1168                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1169                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1170                         .modulemode   = MODULEMODE_HWCTRL,
1171                 },
1172         },
1173         .opt_clks       = gpio1_opt_clks,
1174         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1175         .dev_attr       = &gpio_dev_attr,
1176 };
1177
1178 /* gpio2 */
1179 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1180         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1181         { .irq = -1 }
1182 };
1183
1184 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1185         { .role = "dbclk", .clk = "gpio2_dbclk" },
1186 };
1187
1188 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1189         .name           = "gpio2",
1190         .class          = &omap44xx_gpio_hwmod_class,
1191         .clkdm_name     = "l4_per_clkdm",
1192         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1193         .mpu_irqs       = omap44xx_gpio2_irqs,
1194         .main_clk       = "l4_div_ck",
1195         .prcm = {
1196                 .omap4 = {
1197                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1198                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1199                         .modulemode   = MODULEMODE_HWCTRL,
1200                 },
1201         },
1202         .opt_clks       = gpio2_opt_clks,
1203         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1204         .dev_attr       = &gpio_dev_attr,
1205 };
1206
1207 /* gpio3 */
1208 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1209         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1210         { .irq = -1 }
1211 };
1212
1213 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1214         { .role = "dbclk", .clk = "gpio3_dbclk" },
1215 };
1216
1217 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1218         .name           = "gpio3",
1219         .class          = &omap44xx_gpio_hwmod_class,
1220         .clkdm_name     = "l4_per_clkdm",
1221         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1222         .mpu_irqs       = omap44xx_gpio3_irqs,
1223         .main_clk       = "l4_div_ck",
1224         .prcm = {
1225                 .omap4 = {
1226                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1227                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1228                         .modulemode   = MODULEMODE_HWCTRL,
1229                 },
1230         },
1231         .opt_clks       = gpio3_opt_clks,
1232         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1233         .dev_attr       = &gpio_dev_attr,
1234 };
1235
1236 /* gpio4 */
1237 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1238         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1239         { .irq = -1 }
1240 };
1241
1242 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1243         { .role = "dbclk", .clk = "gpio4_dbclk" },
1244 };
1245
1246 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1247         .name           = "gpio4",
1248         .class          = &omap44xx_gpio_hwmod_class,
1249         .clkdm_name     = "l4_per_clkdm",
1250         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1251         .mpu_irqs       = omap44xx_gpio4_irqs,
1252         .main_clk       = "l4_div_ck",
1253         .prcm = {
1254                 .omap4 = {
1255                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1256                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1257                         .modulemode   = MODULEMODE_HWCTRL,
1258                 },
1259         },
1260         .opt_clks       = gpio4_opt_clks,
1261         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1262         .dev_attr       = &gpio_dev_attr,
1263 };
1264
1265 /* gpio5 */
1266 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1267         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1268         { .irq = -1 }
1269 };
1270
1271 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1272         { .role = "dbclk", .clk = "gpio5_dbclk" },
1273 };
1274
1275 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1276         .name           = "gpio5",
1277         .class          = &omap44xx_gpio_hwmod_class,
1278         .clkdm_name     = "l4_per_clkdm",
1279         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1280         .mpu_irqs       = omap44xx_gpio5_irqs,
1281         .main_clk       = "l4_div_ck",
1282         .prcm = {
1283                 .omap4 = {
1284                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1285                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1286                         .modulemode   = MODULEMODE_HWCTRL,
1287                 },
1288         },
1289         .opt_clks       = gpio5_opt_clks,
1290         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1291         .dev_attr       = &gpio_dev_attr,
1292 };
1293
1294 /* gpio6 */
1295 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1296         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1297         { .irq = -1 }
1298 };
1299
1300 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1301         { .role = "dbclk", .clk = "gpio6_dbclk" },
1302 };
1303
1304 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1305         .name           = "gpio6",
1306         .class          = &omap44xx_gpio_hwmod_class,
1307         .clkdm_name     = "l4_per_clkdm",
1308         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1309         .mpu_irqs       = omap44xx_gpio6_irqs,
1310         .main_clk       = "l4_div_ck",
1311         .prcm = {
1312                 .omap4 = {
1313                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1314                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1315                         .modulemode   = MODULEMODE_HWCTRL,
1316                 },
1317         },
1318         .opt_clks       = gpio6_opt_clks,
1319         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1320         .dev_attr       = &gpio_dev_attr,
1321 };
1322
1323 /*
1324  * 'gpmc' class
1325  * general purpose memory controller
1326  */
1327
1328 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1329         .rev_offs       = 0x0000,
1330         .sysc_offs      = 0x0010,
1331         .syss_offs      = 0x0014,
1332         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1333                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1334         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1335         .sysc_fields    = &omap_hwmod_sysc_type1,
1336 };
1337
1338 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1339         .name   = "gpmc",
1340         .sysc   = &omap44xx_gpmc_sysc,
1341 };
1342
1343 /* gpmc */
1344 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1345         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1346         { .irq = -1 }
1347 };
1348
1349 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1350         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1351         { .dma_req = -1 }
1352 };
1353
1354 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1355         .name           = "gpmc",
1356         .class          = &omap44xx_gpmc_hwmod_class,
1357         .clkdm_name     = "l3_2_clkdm",
1358         /*
1359          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1360          * block.  It is not being added due to any known bugs with
1361          * resetting the GPMC IP block, but rather because any timings
1362          * set by the bootloader are not being correctly programmed by
1363          * the kernel from the board file or DT data.
1364          * HWMOD_INIT_NO_RESET should be removed ASAP.
1365          */
1366         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1367         .mpu_irqs       = omap44xx_gpmc_irqs,
1368         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1369         .prcm = {
1370                 .omap4 = {
1371                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1372                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1373                         .modulemode   = MODULEMODE_HWCTRL,
1374                 },
1375         },
1376 };
1377
1378 /*
1379  * 'gpu' class
1380  * 2d/3d graphics accelerator
1381  */
1382
1383 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1384         .rev_offs       = 0x1fc00,
1385         .sysc_offs      = 0x1fc10,
1386         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1387         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1388                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1389                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1390         .sysc_fields    = &omap_hwmod_sysc_type2,
1391 };
1392
1393 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1394         .name   = "gpu",
1395         .sysc   = &omap44xx_gpu_sysc,
1396 };
1397
1398 /* gpu */
1399 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1400         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1401         { .irq = -1 }
1402 };
1403
1404 static struct omap_hwmod omap44xx_gpu_hwmod = {
1405         .name           = "gpu",
1406         .class          = &omap44xx_gpu_hwmod_class,
1407         .clkdm_name     = "l3_gfx_clkdm",
1408         .mpu_irqs       = omap44xx_gpu_irqs,
1409         .main_clk       = "sgx_clk_mux",
1410         .prcm = {
1411                 .omap4 = {
1412                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1413                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1414                         .modulemode   = MODULEMODE_SWCTRL,
1415                 },
1416         },
1417 };
1418
1419 /*
1420  * 'hdq1w' class
1421  * hdq / 1-wire serial interface controller
1422  */
1423
1424 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1425         .rev_offs       = 0x0000,
1426         .sysc_offs      = 0x0014,
1427         .syss_offs      = 0x0018,
1428         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1429                            SYSS_HAS_RESET_STATUS),
1430         .sysc_fields    = &omap_hwmod_sysc_type1,
1431 };
1432
1433 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1434         .name   = "hdq1w",
1435         .sysc   = &omap44xx_hdq1w_sysc,
1436 };
1437
1438 /* hdq1w */
1439 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1440         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1441         { .irq = -1 }
1442 };
1443
1444 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1445         .name           = "hdq1w",
1446         .class          = &omap44xx_hdq1w_hwmod_class,
1447         .clkdm_name     = "l4_per_clkdm",
1448         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1449         .mpu_irqs       = omap44xx_hdq1w_irqs,
1450         .main_clk       = "func_12m_fclk",
1451         .prcm = {
1452                 .omap4 = {
1453                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1454                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1455                         .modulemode   = MODULEMODE_SWCTRL,
1456                 },
1457         },
1458 };
1459
1460 /*
1461  * 'hsi' class
1462  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1463  * serial if)
1464  */
1465
1466 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1467         .rev_offs       = 0x0000,
1468         .sysc_offs      = 0x0010,
1469         .syss_offs      = 0x0014,
1470         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1471                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1472                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1473         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1474                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1475                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1476         .sysc_fields    = &omap_hwmod_sysc_type1,
1477 };
1478
1479 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1480         .name   = "hsi",
1481         .sysc   = &omap44xx_hsi_sysc,
1482 };
1483
1484 /* hsi */
1485 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1486         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1487         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1488         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1489         { .irq = -1 }
1490 };
1491
1492 static struct omap_hwmod omap44xx_hsi_hwmod = {
1493         .name           = "hsi",
1494         .class          = &omap44xx_hsi_hwmod_class,
1495         .clkdm_name     = "l3_init_clkdm",
1496         .mpu_irqs       = omap44xx_hsi_irqs,
1497         .main_clk       = "hsi_fck",
1498         .prcm = {
1499                 .omap4 = {
1500                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1501                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1502                         .modulemode   = MODULEMODE_HWCTRL,
1503                 },
1504         },
1505 };
1506
1507 /*
1508  * 'i2c' class
1509  * multimaster high-speed i2c controller
1510  */
1511
1512 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1513         .sysc_offs      = 0x0010,
1514         .syss_offs      = 0x0090,
1515         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1516                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1517                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1518         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1519                            SIDLE_SMART_WKUP),
1520         .clockact       = CLOCKACT_TEST_ICLK,
1521         .sysc_fields    = &omap_hwmod_sysc_type1,
1522 };
1523
1524 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1525         .name   = "i2c",
1526         .sysc   = &omap44xx_i2c_sysc,
1527         .rev    = OMAP_I2C_IP_VERSION_2,
1528         .reset  = &omap_i2c_reset,
1529 };
1530
1531 static struct omap_i2c_dev_attr i2c_dev_attr = {
1532         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1533 };
1534
1535 /* i2c1 */
1536 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1537         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1538         { .irq = -1 }
1539 };
1540
1541 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1542         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1543         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1544         { .dma_req = -1 }
1545 };
1546
1547 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1548         .name           = "i2c1",
1549         .class          = &omap44xx_i2c_hwmod_class,
1550         .clkdm_name     = "l4_per_clkdm",
1551         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1552         .mpu_irqs       = omap44xx_i2c1_irqs,
1553         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1554         .main_clk       = "func_96m_fclk",
1555         .prcm = {
1556                 .omap4 = {
1557                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1558                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1559                         .modulemode   = MODULEMODE_SWCTRL,
1560                 },
1561         },
1562         .dev_attr       = &i2c_dev_attr,
1563 };
1564
1565 /* i2c2 */
1566 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1567         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1568         { .irq = -1 }
1569 };
1570
1571 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1572         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1573         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1574         { .dma_req = -1 }
1575 };
1576
1577 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1578         .name           = "i2c2",
1579         .class          = &omap44xx_i2c_hwmod_class,
1580         .clkdm_name     = "l4_per_clkdm",
1581         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1582         .mpu_irqs       = omap44xx_i2c2_irqs,
1583         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1584         .main_clk       = "func_96m_fclk",
1585         .prcm = {
1586                 .omap4 = {
1587                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1588                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1589                         .modulemode   = MODULEMODE_SWCTRL,
1590                 },
1591         },
1592         .dev_attr       = &i2c_dev_attr,
1593 };
1594
1595 /* i2c3 */
1596 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1597         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1598         { .irq = -1 }
1599 };
1600
1601 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1602         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1603         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1604         { .dma_req = -1 }
1605 };
1606
1607 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1608         .name           = "i2c3",
1609         .class          = &omap44xx_i2c_hwmod_class,
1610         .clkdm_name     = "l4_per_clkdm",
1611         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1612         .mpu_irqs       = omap44xx_i2c3_irqs,
1613         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1614         .main_clk       = "func_96m_fclk",
1615         .prcm = {
1616                 .omap4 = {
1617                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1618                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1619                         .modulemode   = MODULEMODE_SWCTRL,
1620                 },
1621         },
1622         .dev_attr       = &i2c_dev_attr,
1623 };
1624
1625 /* i2c4 */
1626 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1627         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1628         { .irq = -1 }
1629 };
1630
1631 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1632         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1633         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1634         { .dma_req = -1 }
1635 };
1636
1637 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1638         .name           = "i2c4",
1639         .class          = &omap44xx_i2c_hwmod_class,
1640         .clkdm_name     = "l4_per_clkdm",
1641         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1642         .mpu_irqs       = omap44xx_i2c4_irqs,
1643         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1644         .main_clk       = "func_96m_fclk",
1645         .prcm = {
1646                 .omap4 = {
1647                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1648                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1649                         .modulemode   = MODULEMODE_SWCTRL,
1650                 },
1651         },
1652         .dev_attr       = &i2c_dev_attr,
1653 };
1654
1655 /*
1656  * 'ipu' class
1657  * imaging processor unit
1658  */
1659
1660 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1661         .name   = "ipu",
1662 };
1663
1664 /* ipu */
1665 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1666         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1667         { .irq = -1 }
1668 };
1669
1670 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1671         { .name = "cpu0", .rst_shift = 0 },
1672         { .name = "cpu1", .rst_shift = 1 },
1673 };
1674
1675 static struct omap_hwmod omap44xx_ipu_hwmod = {
1676         .name           = "ipu",
1677         .class          = &omap44xx_ipu_hwmod_class,
1678         .clkdm_name     = "ducati_clkdm",
1679         .mpu_irqs       = omap44xx_ipu_irqs,
1680         .rst_lines      = omap44xx_ipu_resets,
1681         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1682         .main_clk       = "ducati_clk_mux_ck",
1683         .prcm = {
1684                 .omap4 = {
1685                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1686                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1687                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1688                         .modulemode   = MODULEMODE_HWCTRL,
1689                 },
1690         },
1691 };
1692
1693 /*
1694  * 'iss' class
1695  * external images sensor pixel data processor
1696  */
1697
1698 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1699         .rev_offs       = 0x0000,
1700         .sysc_offs      = 0x0010,
1701         /*
1702          * ISS needs 100 OCP clk cycles delay after a softreset before
1703          * accessing sysconfig again.
1704          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1705          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1706          *
1707          * TODO: Indicate errata when available.
1708          */
1709         .srst_udelay    = 2,
1710         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1711                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1712         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1713                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1714                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1715         .sysc_fields    = &omap_hwmod_sysc_type2,
1716 };
1717
1718 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1719         .name   = "iss",
1720         .sysc   = &omap44xx_iss_sysc,
1721 };
1722
1723 /* iss */
1724 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1725         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1726         { .irq = -1 }
1727 };
1728
1729 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1730         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1731         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1732         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1733         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1734         { .dma_req = -1 }
1735 };
1736
1737 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1738         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1739 };
1740
1741 static struct omap_hwmod omap44xx_iss_hwmod = {
1742         .name           = "iss",
1743         .class          = &omap44xx_iss_hwmod_class,
1744         .clkdm_name     = "iss_clkdm",
1745         .mpu_irqs       = omap44xx_iss_irqs,
1746         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1747         .main_clk       = "ducati_clk_mux_ck",
1748         .prcm = {
1749                 .omap4 = {
1750                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1751                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1752                         .modulemode   = MODULEMODE_SWCTRL,
1753                 },
1754         },
1755         .opt_clks       = iss_opt_clks,
1756         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1757 };
1758
1759 /*
1760  * 'iva' class
1761  * multi-standard video encoder/decoder hardware accelerator
1762  */
1763
1764 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1765         .name   = "iva",
1766 };
1767
1768 /* iva */
1769 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1770         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1771         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1772         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1773         { .irq = -1 }
1774 };
1775
1776 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1777         { .name = "seq0", .rst_shift = 0 },
1778         { .name = "seq1", .rst_shift = 1 },
1779         { .name = "logic", .rst_shift = 2 },
1780 };
1781
1782 static struct omap_hwmod omap44xx_iva_hwmod = {
1783         .name           = "iva",
1784         .class          = &omap44xx_iva_hwmod_class,
1785         .clkdm_name     = "ivahd_clkdm",
1786         .mpu_irqs       = omap44xx_iva_irqs,
1787         .rst_lines      = omap44xx_iva_resets,
1788         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1789         .main_clk       = "dpll_iva_m5x2_ck",
1790         .prcm = {
1791                 .omap4 = {
1792                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1793                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1794                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1795                         .modulemode   = MODULEMODE_HWCTRL,
1796                 },
1797         },
1798 };
1799
1800 /*
1801  * 'kbd' class
1802  * keyboard controller
1803  */
1804
1805 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1806         .rev_offs       = 0x0000,
1807         .sysc_offs      = 0x0010,
1808         .syss_offs      = 0x0014,
1809         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1810                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1811                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1812                            SYSS_HAS_RESET_STATUS),
1813         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1814         .sysc_fields    = &omap_hwmod_sysc_type1,
1815 };
1816
1817 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1818         .name   = "kbd",
1819         .sysc   = &omap44xx_kbd_sysc,
1820 };
1821
1822 /* kbd */
1823 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1824         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1825         { .irq = -1 }
1826 };
1827
1828 static struct omap_hwmod omap44xx_kbd_hwmod = {
1829         .name           = "kbd",
1830         .class          = &omap44xx_kbd_hwmod_class,
1831         .clkdm_name     = "l4_wkup_clkdm",
1832         .mpu_irqs       = omap44xx_kbd_irqs,
1833         .main_clk       = "sys_32k_ck",
1834         .prcm = {
1835                 .omap4 = {
1836                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1837                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1838                         .modulemode   = MODULEMODE_SWCTRL,
1839                 },
1840         },
1841 };
1842
1843 /*
1844  * 'mailbox' class
1845  * mailbox module allowing communication between the on-chip processors using a
1846  * queued mailbox-interrupt mechanism.
1847  */
1848
1849 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1850         .rev_offs       = 0x0000,
1851         .sysc_offs      = 0x0010,
1852         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1853                            SYSC_HAS_SOFTRESET),
1854         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1855         .sysc_fields    = &omap_hwmod_sysc_type2,
1856 };
1857
1858 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1859         .name   = "mailbox",
1860         .sysc   = &omap44xx_mailbox_sysc,
1861 };
1862
1863 /* mailbox */
1864 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1865         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1866         { .irq = -1 }
1867 };
1868
1869 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1870         .name           = "mailbox",
1871         .class          = &omap44xx_mailbox_hwmod_class,
1872         .clkdm_name     = "l4_cfg_clkdm",
1873         .mpu_irqs       = omap44xx_mailbox_irqs,
1874         .prcm = {
1875                 .omap4 = {
1876                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1877                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1878                 },
1879         },
1880 };
1881
1882 /*
1883  * 'mcasp' class
1884  * multi-channel audio serial port controller
1885  */
1886
1887 /* The IP is not compliant to type1 / type2 scheme */
1888 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1889         .sidle_shift    = 0,
1890 };
1891
1892 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1893         .sysc_offs      = 0x0004,
1894         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1895         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1896                            SIDLE_SMART_WKUP),
1897         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1898 };
1899
1900 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1901         .name   = "mcasp",
1902         .sysc   = &omap44xx_mcasp_sysc,
1903 };
1904
1905 /* mcasp */
1906 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1907         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1908         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1909         { .irq = -1 }
1910 };
1911
1912 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1913         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1914         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1915         { .dma_req = -1 }
1916 };
1917
1918 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1919         .name           = "mcasp",
1920         .class          = &omap44xx_mcasp_hwmod_class,
1921         .clkdm_name     = "abe_clkdm",
1922         .mpu_irqs       = omap44xx_mcasp_irqs,
1923         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1924         .main_clk       = "func_mcasp_abe_gfclk",
1925         .prcm = {
1926                 .omap4 = {
1927                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1928                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1929                         .modulemode   = MODULEMODE_SWCTRL,
1930                 },
1931         },
1932 };
1933
1934 /*
1935  * 'mcbsp' class
1936  * multi channel buffered serial port controller
1937  */
1938
1939 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1940         .sysc_offs      = 0x008c,
1941         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1942                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1943         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1944         .sysc_fields    = &omap_hwmod_sysc_type1,
1945 };
1946
1947 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1948         .name   = "mcbsp",
1949         .sysc   = &omap44xx_mcbsp_sysc,
1950         .rev    = MCBSP_CONFIG_TYPE4,
1951 };
1952
1953 /* mcbsp1 */
1954 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1955         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1956         { .irq = -1 }
1957 };
1958
1959 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1960         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1961         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1962         { .dma_req = -1 }
1963 };
1964
1965 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1966         { .role = "pad_fck", .clk = "pad_clks_ck" },
1967         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1968 };
1969
1970 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1971         .name           = "mcbsp1",
1972         .class          = &omap44xx_mcbsp_hwmod_class,
1973         .clkdm_name     = "abe_clkdm",
1974         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1975         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1976         .main_clk       = "func_mcbsp1_gfclk",
1977         .prcm = {
1978                 .omap4 = {
1979                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1980                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1981                         .modulemode   = MODULEMODE_SWCTRL,
1982                 },
1983         },
1984         .opt_clks       = mcbsp1_opt_clks,
1985         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1986 };
1987
1988 /* mcbsp2 */
1989 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1990         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1991         { .irq = -1 }
1992 };
1993
1994 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1995         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1996         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1997         { .dma_req = -1 }
1998 };
1999
2000 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2001         { .role = "pad_fck", .clk = "pad_clks_ck" },
2002         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2003 };
2004
2005 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2006         .name           = "mcbsp2",
2007         .class          = &omap44xx_mcbsp_hwmod_class,
2008         .clkdm_name     = "abe_clkdm",
2009         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2010         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2011         .main_clk       = "func_mcbsp2_gfclk",
2012         .prcm = {
2013                 .omap4 = {
2014                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2015                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2016                         .modulemode   = MODULEMODE_SWCTRL,
2017                 },
2018         },
2019         .opt_clks       = mcbsp2_opt_clks,
2020         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2021 };
2022
2023 /* mcbsp3 */
2024 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2025         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2026         { .irq = -1 }
2027 };
2028
2029 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2030         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2031         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2032         { .dma_req = -1 }
2033 };
2034
2035 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2036         { .role = "pad_fck", .clk = "pad_clks_ck" },
2037         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2038 };
2039
2040 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2041         .name           = "mcbsp3",
2042         .class          = &omap44xx_mcbsp_hwmod_class,
2043         .clkdm_name     = "abe_clkdm",
2044         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2045         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2046         .main_clk       = "func_mcbsp3_gfclk",
2047         .prcm = {
2048                 .omap4 = {
2049                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2050                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2051                         .modulemode   = MODULEMODE_SWCTRL,
2052                 },
2053         },
2054         .opt_clks       = mcbsp3_opt_clks,
2055         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2056 };
2057
2058 /* mcbsp4 */
2059 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2060         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2061         { .irq = -1 }
2062 };
2063
2064 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2065         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2066         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2067         { .dma_req = -1 }
2068 };
2069
2070 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2071         { .role = "pad_fck", .clk = "pad_clks_ck" },
2072         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2073 };
2074
2075 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2076         .name           = "mcbsp4",
2077         .class          = &omap44xx_mcbsp_hwmod_class,
2078         .clkdm_name     = "l4_per_clkdm",
2079         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2080         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2081         .main_clk       = "per_mcbsp4_gfclk",
2082         .prcm = {
2083                 .omap4 = {
2084                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2085                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2086                         .modulemode   = MODULEMODE_SWCTRL,
2087                 },
2088         },
2089         .opt_clks       = mcbsp4_opt_clks,
2090         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2091 };
2092
2093 /*
2094  * 'mcpdm' class
2095  * multi channel pdm controller (proprietary interface with phoenix power
2096  * ic)
2097  */
2098
2099 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2100         .rev_offs       = 0x0000,
2101         .sysc_offs      = 0x0010,
2102         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2103                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2104         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2105                            SIDLE_SMART_WKUP),
2106         .sysc_fields    = &omap_hwmod_sysc_type2,
2107 };
2108
2109 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2110         .name   = "mcpdm",
2111         .sysc   = &omap44xx_mcpdm_sysc,
2112 };
2113
2114 /* mcpdm */
2115 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2116         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2117         { .irq = -1 }
2118 };
2119
2120 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2121         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2122         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2123         { .dma_req = -1 }
2124 };
2125
2126 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2127         .name           = "mcpdm",
2128         .class          = &omap44xx_mcpdm_hwmod_class,
2129         .clkdm_name     = "abe_clkdm",
2130         /*
2131          * It's suspected that the McPDM requires an off-chip main
2132          * functional clock, controlled via I2C.  This IP block is
2133          * currently reset very early during boot, before I2C is
2134          * available, so it doesn't seem that we have any choice in
2135          * the kernel other than to avoid resetting it.
2136          *
2137          * Also, McPDM needs to be configured to NO_IDLE mode when it
2138          * is in used otherwise vital clocks will be gated which
2139          * results 'slow motion' audio playback.
2140          */
2141         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
2142         .mpu_irqs       = omap44xx_mcpdm_irqs,
2143         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2144         .main_clk       = "pad_clks_ck",
2145         .prcm = {
2146                 .omap4 = {
2147                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2148                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2149                         .modulemode   = MODULEMODE_SWCTRL,
2150                 },
2151         },
2152 };
2153
2154 /*
2155  * 'mcspi' class
2156  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2157  * bus
2158  */
2159
2160 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2161         .rev_offs       = 0x0000,
2162         .sysc_offs      = 0x0010,
2163         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2164                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2165         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2166                            SIDLE_SMART_WKUP),
2167         .sysc_fields    = &omap_hwmod_sysc_type2,
2168 };
2169
2170 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2171         .name   = "mcspi",
2172         .sysc   = &omap44xx_mcspi_sysc,
2173         .rev    = OMAP4_MCSPI_REV,
2174 };
2175
2176 /* mcspi1 */
2177 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2178         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2179         { .irq = -1 }
2180 };
2181
2182 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2183         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2184         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2185         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2186         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2187         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2188         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2189         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2190         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2191         { .dma_req = -1 }
2192 };
2193
2194 /* mcspi1 dev_attr */
2195 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2196         .num_chipselect = 4,
2197 };
2198
2199 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2200         .name           = "mcspi1",
2201         .class          = &omap44xx_mcspi_hwmod_class,
2202         .clkdm_name     = "l4_per_clkdm",
2203         .mpu_irqs       = omap44xx_mcspi1_irqs,
2204         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2205         .main_clk       = "func_48m_fclk",
2206         .prcm = {
2207                 .omap4 = {
2208                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2209                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2210                         .modulemode   = MODULEMODE_SWCTRL,
2211                 },
2212         },
2213         .dev_attr       = &mcspi1_dev_attr,
2214 };
2215
2216 /* mcspi2 */
2217 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2218         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2219         { .irq = -1 }
2220 };
2221
2222 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2223         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2224         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2225         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2226         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2227         { .dma_req = -1 }
2228 };
2229
2230 /* mcspi2 dev_attr */
2231 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2232         .num_chipselect = 2,
2233 };
2234
2235 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2236         .name           = "mcspi2",
2237         .class          = &omap44xx_mcspi_hwmod_class,
2238         .clkdm_name     = "l4_per_clkdm",
2239         .mpu_irqs       = omap44xx_mcspi2_irqs,
2240         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2241         .main_clk       = "func_48m_fclk",
2242         .prcm = {
2243                 .omap4 = {
2244                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2245                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2246                         .modulemode   = MODULEMODE_SWCTRL,
2247                 },
2248         },
2249         .dev_attr       = &mcspi2_dev_attr,
2250 };
2251
2252 /* mcspi3 */
2253 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2254         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2255         { .irq = -1 }
2256 };
2257
2258 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2259         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2260         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2261         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2262         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2263         { .dma_req = -1 }
2264 };
2265
2266 /* mcspi3 dev_attr */
2267 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2268         .num_chipselect = 2,
2269 };
2270
2271 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2272         .name           = "mcspi3",
2273         .class          = &omap44xx_mcspi_hwmod_class,
2274         .clkdm_name     = "l4_per_clkdm",
2275         .mpu_irqs       = omap44xx_mcspi3_irqs,
2276         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2277         .main_clk       = "func_48m_fclk",
2278         .prcm = {
2279                 .omap4 = {
2280                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2281                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2282                         .modulemode   = MODULEMODE_SWCTRL,
2283                 },
2284         },
2285         .dev_attr       = &mcspi3_dev_attr,
2286 };
2287
2288 /* mcspi4 */
2289 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2290         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2291         { .irq = -1 }
2292 };
2293
2294 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2295         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2296         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2297         { .dma_req = -1 }
2298 };
2299
2300 /* mcspi4 dev_attr */
2301 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2302         .num_chipselect = 1,
2303 };
2304
2305 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2306         .name           = "mcspi4",
2307         .class          = &omap44xx_mcspi_hwmod_class,
2308         .clkdm_name     = "l4_per_clkdm",
2309         .mpu_irqs       = omap44xx_mcspi4_irqs,
2310         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2311         .main_clk       = "func_48m_fclk",
2312         .prcm = {
2313                 .omap4 = {
2314                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2315                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2316                         .modulemode   = MODULEMODE_SWCTRL,
2317                 },
2318         },
2319         .dev_attr       = &mcspi4_dev_attr,
2320 };
2321
2322 /*
2323  * 'mmc' class
2324  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2325  */
2326
2327 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2328         .rev_offs       = 0x0000,
2329         .sysc_offs      = 0x0010,
2330         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2331                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2332                            SYSC_HAS_SOFTRESET),
2333         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2334                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2335                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2336         .sysc_fields    = &omap_hwmod_sysc_type2,
2337 };
2338
2339 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2340         .name   = "mmc",
2341         .sysc   = &omap44xx_mmc_sysc,
2342 };
2343
2344 /* mmc1 */
2345 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2346         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2347         { .irq = -1 }
2348 };
2349
2350 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2351         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2352         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2353         { .dma_req = -1 }
2354 };
2355
2356 /* mmc1 dev_attr */
2357 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2358         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2359 };
2360
2361 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2362         .name           = "mmc1",
2363         .class          = &omap44xx_mmc_hwmod_class,
2364         .clkdm_name     = "l3_init_clkdm",
2365         .mpu_irqs       = omap44xx_mmc1_irqs,
2366         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2367         .main_clk       = "hsmmc1_fclk",
2368         .prcm = {
2369                 .omap4 = {
2370                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2371                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2372                         .modulemode   = MODULEMODE_SWCTRL,
2373                 },
2374         },
2375         .dev_attr       = &mmc1_dev_attr,
2376 };
2377
2378 /* mmc2 */
2379 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2380         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2381         { .irq = -1 }
2382 };
2383
2384 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2385         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2386         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2387         { .dma_req = -1 }
2388 };
2389
2390 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2391         .name           = "mmc2",
2392         .class          = &omap44xx_mmc_hwmod_class,
2393         .clkdm_name     = "l3_init_clkdm",
2394         .mpu_irqs       = omap44xx_mmc2_irqs,
2395         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2396         .main_clk       = "hsmmc2_fclk",
2397         .prcm = {
2398                 .omap4 = {
2399                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2400                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2401                         .modulemode   = MODULEMODE_SWCTRL,
2402                 },
2403         },
2404 };
2405
2406 /* mmc3 */
2407 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2408         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2409         { .irq = -1 }
2410 };
2411
2412 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2413         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2414         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2415         { .dma_req = -1 }
2416 };
2417
2418 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2419         .name           = "mmc3",
2420         .class          = &omap44xx_mmc_hwmod_class,
2421         .clkdm_name     = "l4_per_clkdm",
2422         .mpu_irqs       = omap44xx_mmc3_irqs,
2423         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2424         .main_clk       = "func_48m_fclk",
2425         .prcm = {
2426                 .omap4 = {
2427                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2428                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2429                         .modulemode   = MODULEMODE_SWCTRL,
2430                 },
2431         },
2432 };
2433
2434 /* mmc4 */
2435 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2436         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2437         { .irq = -1 }
2438 };
2439
2440 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2441         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2442         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2443         { .dma_req = -1 }
2444 };
2445
2446 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2447         .name           = "mmc4",
2448         .class          = &omap44xx_mmc_hwmod_class,
2449         .clkdm_name     = "l4_per_clkdm",
2450         .mpu_irqs       = omap44xx_mmc4_irqs,
2451         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2452         .main_clk       = "func_48m_fclk",
2453         .prcm = {
2454                 .omap4 = {
2455                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2456                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2457                         .modulemode   = MODULEMODE_SWCTRL,
2458                 },
2459         },
2460 };
2461
2462 /* mmc5 */
2463 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2464         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2465         { .irq = -1 }
2466 };
2467
2468 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2469         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2470         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2471         { .dma_req = -1 }
2472 };
2473
2474 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2475         .name           = "mmc5",
2476         .class          = &omap44xx_mmc_hwmod_class,
2477         .clkdm_name     = "l4_per_clkdm",
2478         .mpu_irqs       = omap44xx_mmc5_irqs,
2479         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2480         .main_clk       = "func_48m_fclk",
2481         .prcm = {
2482                 .omap4 = {
2483                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2484                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2485                         .modulemode   = MODULEMODE_SWCTRL,
2486                 },
2487         },
2488 };
2489
2490 /*
2491  * 'mmu' class
2492  * The memory management unit performs virtual to physical address translation
2493  * for its requestors.
2494  */
2495
2496 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2497         .rev_offs       = 0x000,
2498         .sysc_offs      = 0x010,
2499         .syss_offs      = 0x014,
2500         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2501                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2502         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2503         .sysc_fields    = &omap_hwmod_sysc_type1,
2504 };
2505
2506 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2507         .name = "mmu",
2508         .sysc = &mmu_sysc,
2509 };
2510
2511 /* mmu ipu */
2512
2513 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2514         .da_start       = 0x0,
2515         .da_end         = 0xfffff000,
2516         .nr_tlb_entries = 32,
2517 };
2518
2519 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2520 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2521         { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2522         { .irq = -1 }
2523 };
2524
2525 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2526         { .name = "mmu_cache", .rst_shift = 2 },
2527 };
2528
2529 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2530         {
2531                 .pa_start       = 0x55082000,
2532                 .pa_end         = 0x550820ff,
2533                 .flags          = ADDR_TYPE_RT,
2534         },
2535         { }
2536 };
2537
2538 /* l3_main_2 -> mmu_ipu */
2539 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2540         .master         = &omap44xx_l3_main_2_hwmod,
2541         .slave          = &omap44xx_mmu_ipu_hwmod,
2542         .clk            = "l3_div_ck",
2543         .addr           = omap44xx_mmu_ipu_addrs,
2544         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2545 };
2546
2547 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2548         .name           = "mmu_ipu",
2549         .class          = &omap44xx_mmu_hwmod_class,
2550         .clkdm_name     = "ducati_clkdm",
2551         .mpu_irqs       = omap44xx_mmu_ipu_irqs,
2552         .rst_lines      = omap44xx_mmu_ipu_resets,
2553         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2554         .main_clk       = "ducati_clk_mux_ck",
2555         .prcm = {
2556                 .omap4 = {
2557                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2558                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2559                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2560                         .modulemode   = MODULEMODE_HWCTRL,
2561                 },
2562         },
2563         .dev_attr       = &mmu_ipu_dev_attr,
2564 };
2565
2566 /* mmu dsp */
2567
2568 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2569         .da_start       = 0x0,
2570         .da_end         = 0xfffff000,
2571         .nr_tlb_entries = 32,
2572 };
2573
2574 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2575 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2576         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2577         { .irq = -1 }
2578 };
2579
2580 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2581         { .name = "mmu_cache", .rst_shift = 1 },
2582 };
2583
2584 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2585         {
2586                 .pa_start       = 0x4a066000,
2587                 .pa_end         = 0x4a0660ff,
2588                 .flags          = ADDR_TYPE_RT,
2589         },
2590         { }
2591 };
2592
2593 /* l4_cfg -> dsp */
2594 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2595         .master         = &omap44xx_l4_cfg_hwmod,
2596         .slave          = &omap44xx_mmu_dsp_hwmod,
2597         .clk            = "l4_div_ck",
2598         .addr           = omap44xx_mmu_dsp_addrs,
2599         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2600 };
2601
2602 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2603         .name           = "mmu_dsp",
2604         .class          = &omap44xx_mmu_hwmod_class,
2605         .clkdm_name     = "tesla_clkdm",
2606         .mpu_irqs       = omap44xx_mmu_dsp_irqs,
2607         .rst_lines      = omap44xx_mmu_dsp_resets,
2608         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2609         .main_clk       = "dpll_iva_m4x2_ck",
2610         .prcm = {
2611                 .omap4 = {
2612                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2613                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2614                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2615                         .modulemode   = MODULEMODE_HWCTRL,
2616                 },
2617         },
2618         .dev_attr       = &mmu_dsp_dev_attr,
2619 };
2620
2621 /*
2622  * 'mpu' class
2623  * mpu sub-system
2624  */
2625
2626 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2627         .name   = "mpu",
2628 };
2629
2630 /* mpu */
2631 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2632         { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2633         { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2634         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2635         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2636         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2637         { .irq = -1 }
2638 };
2639
2640 static struct omap_hwmod omap44xx_mpu_hwmod = {
2641         .name           = "mpu",
2642         .class          = &omap44xx_mpu_hwmod_class,
2643         .clkdm_name     = "mpuss_clkdm",
2644         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2645         .mpu_irqs       = omap44xx_mpu_irqs,
2646         .main_clk       = "dpll_mpu_m2_ck",
2647         .prcm = {
2648                 .omap4 = {
2649                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2650                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2651                 },
2652         },
2653 };
2654
2655 /*
2656  * 'ocmc_ram' class
2657  * top-level core on-chip ram
2658  */
2659
2660 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2661         .name   = "ocmc_ram",
2662 };
2663
2664 /* ocmc_ram */
2665 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2666         .name           = "ocmc_ram",
2667         .class          = &omap44xx_ocmc_ram_hwmod_class,
2668         .clkdm_name     = "l3_2_clkdm",
2669         .prcm = {
2670                 .omap4 = {
2671                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2672                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2673                 },
2674         },
2675 };
2676
2677 /*
2678  * 'ocp2scp' class
2679  * bridge to transform ocp interface protocol to scp (serial control port)
2680  * protocol
2681  */
2682
2683 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2684         .rev_offs       = 0x0000,
2685         .sysc_offs      = 0x0010,
2686         .syss_offs      = 0x0014,
2687         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2688                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2689         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2690         .sysc_fields    = &omap_hwmod_sysc_type1,
2691 };
2692
2693 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2694         .name   = "ocp2scp",
2695         .sysc   = &omap44xx_ocp2scp_sysc,
2696 };
2697
2698 /* ocp2scp dev_attr */
2699 static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
2700         {
2701                 .name           = "usb_phy",
2702                 .start          = 0x4a0ad080,
2703                 .end            = 0x4a0ae000,
2704                 .flags          = IORESOURCE_MEM,
2705         },
2706         { }
2707 };
2708
2709 static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
2710         {
2711                 .drv_name       = "omap-usb2",
2712                 .res            = omap44xx_usb_phy_and_pll_addrs,
2713         },
2714         { }
2715 };
2716
2717 /* ocp2scp_usb_phy */
2718 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2719         .name           = "ocp2scp_usb_phy",
2720         .class          = &omap44xx_ocp2scp_hwmod_class,
2721         .clkdm_name     = "l3_init_clkdm",
2722         /*
2723          * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
2724          * block as an "optional clock," and normally should never be
2725          * specified as the main_clk for an OMAP IP block.  However it
2726          * turns out that this clock is actually the main clock for
2727          * the ocp2scp_usb_phy IP block:
2728          * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
2729          * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
2730          * to be the best workaround.
2731          */
2732         .main_clk       = "ocp2scp_usb_phy_phy_48m",
2733         .prcm = {
2734                 .omap4 = {
2735                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2736                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2737                         .modulemode   = MODULEMODE_HWCTRL,
2738                 },
2739         },
2740         .dev_attr       = ocp2scp_dev_attr,
2741 };
2742
2743 /*
2744  * 'prcm' class
2745  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2746  * + clock manager 1 (in always on power domain) + local prm in mpu
2747  */
2748
2749 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2750         .name   = "prcm",
2751 };
2752
2753 /* prcm_mpu */
2754 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2755         .name           = "prcm_mpu",
2756         .class          = &omap44xx_prcm_hwmod_class,
2757         .clkdm_name     = "l4_wkup_clkdm",
2758         .flags          = HWMOD_NO_IDLEST,
2759         .prcm = {
2760                 .omap4 = {
2761                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2762                 },
2763         },
2764 };
2765
2766 /* cm_core_aon */
2767 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2768         .name           = "cm_core_aon",
2769         .class          = &omap44xx_prcm_hwmod_class,
2770         .flags          = HWMOD_NO_IDLEST,
2771         .prcm = {
2772                 .omap4 = {
2773                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2774                 },
2775         },
2776 };
2777
2778 /* cm_core */
2779 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2780         .name           = "cm_core",
2781         .class          = &omap44xx_prcm_hwmod_class,
2782         .flags          = HWMOD_NO_IDLEST,
2783         .prcm = {
2784                 .omap4 = {
2785                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2786                 },
2787         },
2788 };
2789
2790 /* prm */
2791 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2792         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2793         { .irq = -1 }
2794 };
2795
2796 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2797         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2798         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2799 };
2800
2801 static struct omap_hwmod omap44xx_prm_hwmod = {
2802         .name           = "prm",
2803         .class          = &omap44xx_prcm_hwmod_class,
2804         .mpu_irqs       = omap44xx_prm_irqs,
2805         .rst_lines      = omap44xx_prm_resets,
2806         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2807 };
2808
2809 /*
2810  * 'scrm' class
2811  * system clock and reset manager
2812  */
2813
2814 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2815         .name   = "scrm",
2816 };
2817
2818 /* scrm */
2819 static struct omap_hwmod omap44xx_scrm_hwmod = {
2820         .name           = "scrm",
2821         .class          = &omap44xx_scrm_hwmod_class,
2822         .clkdm_name     = "l4_wkup_clkdm",
2823         .prcm = {
2824                 .omap4 = {
2825                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2826                 },
2827         },
2828 };
2829
2830 /*
2831  * 'sl2if' class
2832  * shared level 2 memory interface
2833  */
2834
2835 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2836         .name   = "sl2if",
2837 };
2838
2839 /* sl2if */
2840 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2841         .name           = "sl2if",
2842         .class          = &omap44xx_sl2if_hwmod_class,
2843         .clkdm_name     = "ivahd_clkdm",
2844         .prcm = {
2845                 .omap4 = {
2846                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2847                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2848                         .modulemode   = MODULEMODE_HWCTRL,
2849                 },
2850         },
2851 };
2852
2853 /*
2854  * 'slimbus' class
2855  * bidirectional, multi-drop, multi-channel two-line serial interface between
2856  * the device and external components
2857  */
2858
2859 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2860         .rev_offs       = 0x0000,
2861         .sysc_offs      = 0x0010,
2862         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2863                            SYSC_HAS_SOFTRESET),
2864         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2865                            SIDLE_SMART_WKUP),
2866         .sysc_fields    = &omap_hwmod_sysc_type2,
2867 };
2868
2869 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2870         .name   = "slimbus",
2871         .sysc   = &omap44xx_slimbus_sysc,
2872 };
2873
2874 /* slimbus1 */
2875 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2876         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2877         { .irq = -1 }
2878 };
2879
2880 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2881         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2882         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2883         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2884         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2885         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2886         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2887         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2888         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2889         { .dma_req = -1 }
2890 };
2891
2892 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2893         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2894         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2895         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2896         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2897 };
2898
2899 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2900         .name           = "slimbus1",
2901         .class          = &omap44xx_slimbus_hwmod_class,
2902         .clkdm_name     = "abe_clkdm",
2903         .mpu_irqs       = omap44xx_slimbus1_irqs,
2904         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2905         .prcm = {
2906                 .omap4 = {
2907                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2908                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2909                         .modulemode   = MODULEMODE_SWCTRL,
2910                 },
2911         },
2912         .opt_clks       = slimbus1_opt_clks,
2913         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2914 };
2915
2916 /* slimbus2 */
2917 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2918         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2919         { .irq = -1 }
2920 };
2921
2922 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2923         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2924         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2925         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2926         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2927         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2928         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2929         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2930         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2931         { .dma_req = -1 }
2932 };
2933
2934 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2935         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2936         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2937         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2938 };
2939
2940 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2941         .name           = "slimbus2",
2942         .class          = &omap44xx_slimbus_hwmod_class,
2943         .clkdm_name     = "l4_per_clkdm",
2944         .mpu_irqs       = omap44xx_slimbus2_irqs,
2945         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2946         .prcm = {
2947                 .omap4 = {
2948                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2949                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2950                         .modulemode   = MODULEMODE_SWCTRL,
2951                 },
2952         },
2953         .opt_clks       = slimbus2_opt_clks,
2954         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2955 };
2956
2957 /*
2958  * 'smartreflex' class
2959  * smartreflex module (monitor silicon performance and outputs a measure of
2960  * performance error)
2961  */
2962
2963 /* The IP is not compliant to type1 / type2 scheme */
2964 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2965         .sidle_shift    = 24,
2966         .enwkup_shift   = 26,
2967 };
2968
2969 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2970         .sysc_offs      = 0x0038,
2971         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2972         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2973                            SIDLE_SMART_WKUP),
2974         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2975 };
2976
2977 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2978         .name   = "smartreflex",
2979         .sysc   = &omap44xx_smartreflex_sysc,
2980         .rev    = 2,
2981 };
2982
2983 /* smartreflex_core */
2984 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2985         .sensor_voltdm_name   = "core",
2986 };
2987
2988 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2989         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2990         { .irq = -1 }
2991 };
2992
2993 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2994         .name           = "smartreflex_core",
2995         .class          = &omap44xx_smartreflex_hwmod_class,
2996         .clkdm_name     = "l4_ao_clkdm",
2997         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2998
2999         .main_clk       = "smartreflex_core_fck",
3000         .prcm = {
3001                 .omap4 = {
3002                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
3003                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
3004                         .modulemode   = MODULEMODE_SWCTRL,
3005                 },
3006         },
3007         .dev_attr       = &smartreflex_core_dev_attr,
3008 };
3009
3010 /* smartreflex_iva */
3011 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
3012         .sensor_voltdm_name     = "iva",
3013 };
3014
3015 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3016         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3017         { .irq = -1 }
3018 };
3019
3020 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3021         .name           = "smartreflex_iva",
3022         .class          = &omap44xx_smartreflex_hwmod_class,
3023         .clkdm_name     = "l4_ao_clkdm",
3024         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3025         .main_clk       = "smartreflex_iva_fck",
3026         .prcm = {
3027                 .omap4 = {
3028                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
3029                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
3030                         .modulemode   = MODULEMODE_SWCTRL,
3031                 },
3032         },
3033         .dev_attr       = &smartreflex_iva_dev_attr,
3034 };
3035
3036 /* smartreflex_mpu */
3037 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
3038         .sensor_voltdm_name     = "mpu",
3039 };
3040
3041 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3042         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3043         { .irq = -1 }
3044 };
3045
3046 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3047         .name           = "smartreflex_mpu",
3048         .class          = &omap44xx_smartreflex_hwmod_class,
3049         .clkdm_name     = "l4_ao_clkdm",
3050         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3051         .main_clk       = "smartreflex_mpu_fck",
3052         .prcm = {
3053                 .omap4 = {
3054                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3055                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3056                         .modulemode   = MODULEMODE_SWCTRL,
3057                 },
3058         },
3059         .dev_attr       = &smartreflex_mpu_dev_attr,
3060 };
3061
3062 /*
3063  * 'spinlock' class
3064  * spinlock provides hardware assistance for synchronizing the processes
3065  * running on multiple processors
3066  */
3067
3068 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3069         .rev_offs       = 0x0000,
3070         .sysc_offs      = 0x0010,
3071         .syss_offs      = 0x0014,
3072         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3073                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3074                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3075         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3076                            SIDLE_SMART_WKUP),
3077         .sysc_fields    = &omap_hwmod_sysc_type1,
3078 };
3079
3080 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3081         .name   = "spinlock",
3082         .sysc   = &omap44xx_spinlock_sysc,
3083 };
3084
3085 /* spinlock */
3086 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3087         .name           = "spinlock",
3088         .class          = &omap44xx_spinlock_hwmod_class,
3089         .clkdm_name     = "l4_cfg_clkdm",
3090         .prcm = {
3091                 .omap4 = {
3092                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3093                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3094                 },
3095         },
3096 };
3097
3098 /*
3099  * 'timer' class
3100  * general purpose timer module with accurate 1ms tick
3101  * This class contains several variants: ['timer_1ms', 'timer']
3102  */
3103
3104 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3105         .rev_offs       = 0x0000,
3106         .sysc_offs      = 0x0010,
3107         .syss_offs      = 0x0014,
3108         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3109                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3110                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3111                            SYSS_HAS_RESET_STATUS),
3112         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3113         .clockact       = CLOCKACT_TEST_ICLK,
3114         .sysc_fields    = &omap_hwmod_sysc_type1,
3115 };
3116
3117 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3118         .name   = "timer",
3119         .sysc   = &omap44xx_timer_1ms_sysc,
3120 };
3121
3122 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3123         .rev_offs       = 0x0000,
3124         .sysc_offs      = 0x0010,
3125         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3126                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3127         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3128                            SIDLE_SMART_WKUP),
3129         .sysc_fields    = &omap_hwmod_sysc_type2,
3130 };
3131
3132 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3133         .name   = "timer",
3134         .sysc   = &omap44xx_timer_sysc,
3135 };
3136
3137 /* always-on timers dev attribute */
3138 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3139         .timer_capability       = OMAP_TIMER_ALWON,
3140 };
3141
3142 /* pwm timers dev attribute */
3143 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3144         .timer_capability       = OMAP_TIMER_HAS_PWM,
3145 };
3146
3147 /* timers with DSP interrupt dev attribute */
3148 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3149         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
3150 };
3151
3152 /* pwm timers with DSP interrupt dev attribute */
3153 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3154         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3155 };
3156
3157 /* timer1 */
3158 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3159         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3160         { .irq = -1 }
3161 };
3162
3163 static struct omap_hwmod omap44xx_timer1_hwmod = {
3164         .name           = "timer1",
3165         .class          = &omap44xx_timer_1ms_hwmod_class,
3166         .clkdm_name     = "l4_wkup_clkdm",
3167         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3168         .mpu_irqs       = omap44xx_timer1_irqs,
3169         .main_clk       = "dmt1_clk_mux",
3170         .prcm = {
3171                 .omap4 = {
3172                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3173                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3174                         .modulemode   = MODULEMODE_SWCTRL,
3175                 },
3176         },
3177         .dev_attr       = &capability_alwon_dev_attr,
3178 };
3179
3180 /* timer2 */
3181 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3182         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3183         { .irq = -1 }
3184 };
3185
3186 static struct omap_hwmod omap44xx_timer2_hwmod = {
3187         .name           = "timer2",
3188         .class          = &omap44xx_timer_1ms_hwmod_class,
3189         .clkdm_name     = "l4_per_clkdm",
3190         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3191         .mpu_irqs       = omap44xx_timer2_irqs,
3192         .main_clk       = "cm2_dm2_mux",
3193         .prcm = {
3194                 .omap4 = {
3195                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3196                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3197                         .modulemode   = MODULEMODE_SWCTRL,
3198                 },
3199         },
3200 };
3201
3202 /* timer3 */
3203 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3204         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3205         { .irq = -1 }
3206 };
3207
3208 static struct omap_hwmod omap44xx_timer3_hwmod = {
3209         .name           = "timer3",
3210         .class          = &omap44xx_timer_hwmod_class,
3211         .clkdm_name     = "l4_per_clkdm",
3212         .mpu_irqs       = omap44xx_timer3_irqs,
3213         .main_clk       = "cm2_dm3_mux",
3214         .prcm = {
3215                 .omap4 = {
3216                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3217                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3218                         .modulemode   = MODULEMODE_SWCTRL,
3219                 },
3220         },
3221 };
3222
3223 /* timer4 */
3224 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3225         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3226         { .irq = -1 }
3227 };
3228
3229 static struct omap_hwmod omap44xx_timer4_hwmod = {
3230         .name           = "timer4",
3231         .class          = &omap44xx_timer_hwmod_class,
3232         .clkdm_name     = "l4_per_clkdm",
3233         .mpu_irqs       = omap44xx_timer4_irqs,
3234         .main_clk       = "cm2_dm4_mux",
3235         .prcm = {
3236                 .omap4 = {
3237                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3238                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3239                         .modulemode   = MODULEMODE_SWCTRL,
3240                 },
3241         },
3242 };
3243
3244 /* timer5 */
3245 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3246         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3247         { .irq = -1 }
3248 };
3249
3250 static struct omap_hwmod omap44xx_timer5_hwmod = {
3251         .name           = "timer5",
3252         .class          = &omap44xx_timer_hwmod_class,
3253         .clkdm_name     = "abe_clkdm",
3254         .mpu_irqs       = omap44xx_timer5_irqs,
3255         .main_clk       = "timer5_sync_mux",
3256         .prcm = {
3257                 .omap4 = {
3258                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3259                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3260                         .modulemode   = MODULEMODE_SWCTRL,
3261                 },
3262         },
3263         .dev_attr       = &capability_dsp_dev_attr,
3264 };
3265
3266 /* timer6 */
3267 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3268         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3269         { .irq = -1 }
3270 };
3271
3272 static struct omap_hwmod omap44xx_timer6_hwmod = {
3273         .name           = "timer6",
3274         .class          = &omap44xx_timer_hwmod_class,
3275         .clkdm_name     = "abe_clkdm",
3276         .mpu_irqs       = omap44xx_timer6_irqs,
3277         .main_clk       = "timer6_sync_mux",
3278         .prcm = {
3279                 .omap4 = {
3280                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3281                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3282                         .modulemode   = MODULEMODE_SWCTRL,
3283                 },
3284         },
3285         .dev_attr       = &capability_dsp_dev_attr,
3286 };
3287
3288 /* timer7 */
3289 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3290         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3291         { .irq = -1 }
3292 };
3293
3294 static struct omap_hwmod omap44xx_timer7_hwmod = {
3295         .name           = "timer7",
3296         .class          = &omap44xx_timer_hwmod_class,
3297         .clkdm_name     = "abe_clkdm",
3298         .mpu_irqs       = omap44xx_timer7_irqs,
3299         .main_clk       = "timer7_sync_mux",
3300         .prcm = {
3301                 .omap4 = {
3302                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3303                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3304                         .modulemode   = MODULEMODE_SWCTRL,
3305                 },
3306         },
3307         .dev_attr       = &capability_dsp_dev_attr,
3308 };
3309
3310 /* timer8 */
3311 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3312         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3313         { .irq = -1 }
3314 };
3315
3316 static struct omap_hwmod omap44xx_timer8_hwmod = {
3317         .name           = "timer8",
3318         .class          = &omap44xx_timer_hwmod_class,
3319         .clkdm_name     = "abe_clkdm",
3320         .mpu_irqs       = omap44xx_timer8_irqs,
3321         .main_clk       = "timer8_sync_mux",
3322         .prcm = {
3323                 .omap4 = {
3324                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3325                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3326                         .modulemode   = MODULEMODE_SWCTRL,
3327                 },
3328         },
3329         .dev_attr       = &capability_dsp_pwm_dev_attr,
3330 };
3331
3332 /* timer9 */
3333 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3334         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3335         { .irq = -1 }
3336 };
3337
3338 static struct omap_hwmod omap44xx_timer9_hwmod = {
3339         .name           = "timer9",
3340         .class          = &omap44xx_timer_hwmod_class,
3341         .clkdm_name     = "l4_per_clkdm",
3342         .mpu_irqs       = omap44xx_timer9_irqs,
3343         .main_clk       = "cm2_dm9_mux",
3344         .prcm = {
3345                 .omap4 = {
3346                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3347                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3348                         .modulemode   = MODULEMODE_SWCTRL,
3349                 },
3350         },
3351         .dev_attr       = &capability_pwm_dev_attr,
3352 };
3353
3354 /* timer10 */
3355 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3356         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3357         { .irq = -1 }
3358 };
3359
3360 static struct omap_hwmod omap44xx_timer10_hwmod = {
3361         .name           = "timer10",
3362         .class          = &omap44xx_timer_1ms_hwmod_class,
3363         .clkdm_name     = "l4_per_clkdm",
3364         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3365         .mpu_irqs       = omap44xx_timer10_irqs,
3366         .main_clk       = "cm2_dm10_mux",
3367         .prcm = {
3368                 .omap4 = {
3369                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3370                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3371                         .modulemode   = MODULEMODE_SWCTRL,
3372                 },
3373         },
3374         .dev_attr       = &capability_pwm_dev_attr,
3375 };
3376
3377 /* timer11 */
3378 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3379         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3380         { .irq = -1 }
3381 };
3382
3383 static struct omap_hwmod omap44xx_timer11_hwmod = {
3384         .name           = "timer11",
3385         .class          = &omap44xx_timer_hwmod_class,
3386         .clkdm_name     = "l4_per_clkdm",
3387         .mpu_irqs       = omap44xx_timer11_irqs,
3388         .main_clk       = "cm2_dm11_mux",
3389         .prcm = {
3390                 .omap4 = {
3391                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3392                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3393                         .modulemode   = MODULEMODE_SWCTRL,
3394                 },
3395         },
3396         .dev_attr       = &capability_pwm_dev_attr,
3397 };
3398
3399 /*
3400  * 'uart' class
3401  * universal asynchronous receiver/transmitter (uart)
3402  */
3403
3404 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3405         .rev_offs       = 0x0050,
3406         .sysc_offs      = 0x0054,
3407         .syss_offs      = 0x0058,
3408         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3409                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3410                            SYSS_HAS_RESET_STATUS),
3411         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3412                            SIDLE_SMART_WKUP),
3413         .sysc_fields    = &omap_hwmod_sysc_type1,
3414 };
3415
3416 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3417         .name   = "uart",
3418         .sysc   = &omap44xx_uart_sysc,
3419 };
3420
3421 /* uart1 */
3422 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3423         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3424         { .irq = -1 }
3425 };
3426
3427 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3428         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3429         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3430         { .dma_req = -1 }
3431 };
3432
3433 static struct omap_hwmod omap44xx_uart1_hwmod = {
3434         .name           = "uart1",
3435         .class          = &omap44xx_uart_hwmod_class,
3436         .clkdm_name     = "l4_per_clkdm",
3437         .flags          = HWMOD_SWSUP_SIDLE_ACT,
3438         .mpu_irqs       = omap44xx_uart1_irqs,
3439         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3440         .main_clk       = "func_48m_fclk",
3441         .prcm = {
3442                 .omap4 = {
3443                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3444                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3445                         .modulemode   = MODULEMODE_SWCTRL,
3446                 },
3447         },
3448 };
3449
3450 /* uart2 */
3451 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3452         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3453         { .irq = -1 }
3454 };
3455
3456 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3457         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3458         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3459         { .dma_req = -1 }
3460 };
3461
3462 static struct omap_hwmod omap44xx_uart2_hwmod = {
3463         .name           = "uart2",
3464         .class          = &omap44xx_uart_hwmod_class,
3465         .clkdm_name     = "l4_per_clkdm",
3466         .flags          = HWMOD_SWSUP_SIDLE_ACT,
3467         .mpu_irqs       = omap44xx_uart2_irqs,
3468         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3469         .main_clk       = "func_48m_fclk",
3470         .prcm = {
3471                 .omap4 = {
3472                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3473                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3474                         .modulemode   = MODULEMODE_SWCTRL,
3475                 },
3476         },
3477 };
3478
3479 /* uart3 */
3480 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3481         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3482         { .irq = -1 }
3483 };
3484
3485 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3486         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3487         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3488         { .dma_req = -1 }
3489 };
3490
3491 static struct omap_hwmod omap44xx_uart3_hwmod = {
3492         .name           = "uart3",
3493         .class          = &omap44xx_uart_hwmod_class,
3494         .clkdm_name     = "l4_per_clkdm",
3495         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
3496                                 HWMOD_SWSUP_SIDLE_ACT,
3497         .mpu_irqs       = omap44xx_uart3_irqs,
3498         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3499         .main_clk       = "func_48m_fclk",
3500         .prcm = {
3501                 .omap4 = {
3502                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3503                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3504                         .modulemode   = MODULEMODE_SWCTRL,
3505                 },
3506         },
3507 };
3508
3509 /* uart4 */
3510 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3511         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3512         { .irq = -1 }
3513 };
3514
3515 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3516         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3517         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3518         { .dma_req = -1 }
3519 };
3520
3521 static struct omap_hwmod omap44xx_uart4_hwmod = {
3522         .name           = "uart4",
3523         .class          = &omap44xx_uart_hwmod_class,
3524         .clkdm_name     = "l4_per_clkdm",
3525         .flags          = HWMOD_SWSUP_SIDLE_ACT,
3526         .mpu_irqs       = omap44xx_uart4_irqs,
3527         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3528         .main_clk       = "func_48m_fclk",
3529         .prcm = {
3530                 .omap4 = {
3531                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3532                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3533                         .modulemode   = MODULEMODE_SWCTRL,
3534                 },
3535         },
3536 };
3537
3538 /*
3539  * 'usb_host_fs' class
3540  * full-speed usb host controller
3541  */
3542
3543 /* The IP is not compliant to type1 / type2 scheme */
3544 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3545         .midle_shift    = 4,
3546         .sidle_shift    = 2,
3547         .srst_shift     = 1,
3548 };
3549
3550 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3551         .rev_offs       = 0x0000,
3552         .sysc_offs      = 0x0210,
3553         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3554                            SYSC_HAS_SOFTRESET),
3555         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3556                            SIDLE_SMART_WKUP),
3557         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3558 };
3559
3560 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3561         .name   = "usb_host_fs",
3562         .sysc   = &omap44xx_usb_host_fs_sysc,
3563 };
3564
3565 /* usb_host_fs */
3566 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3567         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3568         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3569         { .irq = -1 }
3570 };
3571
3572 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3573         .name           = "usb_host_fs",
3574         .class          = &omap44xx_usb_host_fs_hwmod_class,
3575         .clkdm_name     = "l3_init_clkdm",
3576         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3577         .main_clk       = "usb_host_fs_fck",
3578         .prcm = {
3579                 .omap4 = {
3580                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3581                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3582                         .modulemode   = MODULEMODE_SWCTRL,
3583                 },
3584         },
3585 };
3586
3587 /*
3588  * 'usb_host_hs' class
3589  * high-speed multi-port usb host controller
3590  */
3591
3592 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3593         .rev_offs       = 0x0000,
3594         .sysc_offs      = 0x0010,
3595         .syss_offs      = 0x0014,
3596         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3597                            SYSC_HAS_SOFTRESET),
3598         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3599                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3600                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3601         .sysc_fields    = &omap_hwmod_sysc_type2,
3602 };
3603
3604 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3605         .name   = "usb_host_hs",
3606         .sysc   = &omap44xx_usb_host_hs_sysc,
3607 };
3608
3609 /* usb_host_hs */
3610 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3611         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3612         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3613         { .irq = -1 }
3614 };
3615
3616 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3617         .name           = "usb_host_hs",
3618         .class          = &omap44xx_usb_host_hs_hwmod_class,
3619         .clkdm_name     = "l3_init_clkdm",
3620         .main_clk       = "usb_host_hs_fck",
3621         .prcm = {
3622                 .omap4 = {
3623                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3624                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3625                         .modulemode   = MODULEMODE_SWCTRL,
3626                 },
3627         },
3628         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3629
3630         /*
3631          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3632          * id: i660
3633          *
3634          * Description:
3635          * In the following configuration :
3636          * - USBHOST module is set to smart-idle mode
3637          * - PRCM asserts idle_req to the USBHOST module ( This typically
3638          *   happens when the system is going to a low power mode : all ports
3639          *   have been suspended, the master part of the USBHOST module has
3640          *   entered the standby state, and SW has cut the functional clocks)
3641          * - an USBHOST interrupt occurs before the module is able to answer
3642          *   idle_ack, typically a remote wakeup IRQ.
3643          * Then the USB HOST module will enter a deadlock situation where it
3644          * is no more accessible nor functional.
3645          *
3646          * Workaround:
3647          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3648          */
3649
3650         /*
3651          * Errata: USB host EHCI may stall when entering smart-standby mode
3652          * Id: i571
3653          *
3654          * Description:
3655          * When the USBHOST module is set to smart-standby mode, and when it is
3656          * ready to enter the standby state (i.e. all ports are suspended and
3657          * all attached devices are in suspend mode), then it can wrongly assert
3658          * the Mstandby signal too early while there are still some residual OCP
3659          * transactions ongoing. If this condition occurs, the internal state
3660          * machine may go to an undefined state and the USB link may be stuck
3661          * upon the next resume.
3662          *
3663          * Workaround:
3664          * Don't use smart standby; use only force standby,
3665          * hence HWMOD_SWSUP_MSTANDBY
3666          */
3667
3668         /*
3669          * During system boot; If the hwmod framework resets the module
3670          * the module will have smart idle settings; which can lead to deadlock
3671          * (above Errata Id:i660); so, dont reset the module during boot;
3672          * Use HWMOD_INIT_NO_RESET.
3673          */
3674
3675         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3676                           HWMOD_INIT_NO_RESET,
3677 };
3678
3679 /*
3680  * 'usb_otg_hs' class
3681  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3682  */
3683
3684 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3685         .rev_offs       = 0x0400,
3686         .sysc_offs      = 0x0404,
3687         .syss_offs      = 0x0408,
3688         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3689                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3690                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3691         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3692                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3693                            MSTANDBY_SMART),
3694         .sysc_fields    = &omap_hwmod_sysc_type1,
3695 };
3696
3697 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3698         .name   = "usb_otg_hs",
3699         .sysc   = &omap44xx_usb_otg_hs_sysc,
3700 };
3701
3702 /* usb_otg_hs */
3703 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3704         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3705         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3706         { .irq = -1 }
3707 };
3708
3709 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3710         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3711 };
3712
3713 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3714         .name           = "usb_otg_hs",
3715         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3716         .clkdm_name     = "l3_init_clkdm",
3717         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3718         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3719         .main_clk       = "usb_otg_hs_ick",
3720         .prcm = {
3721                 .omap4 = {
3722                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3723                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3724                         .modulemode   = MODULEMODE_HWCTRL,
3725                 },
3726         },
3727         .opt_clks       = usb_otg_hs_opt_clks,
3728         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3729 };
3730
3731 /*
3732  * 'usb_tll_hs' class
3733  * usb_tll_hs module is the adapter on the usb_host_hs ports
3734  */
3735
3736 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3737         .rev_offs       = 0x0000,
3738         .sysc_offs      = 0x0010,
3739         .syss_offs      = 0x0014,
3740         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3741                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3742                            SYSC_HAS_AUTOIDLE),
3743         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3744         .sysc_fields    = &omap_hwmod_sysc_type1,
3745 };
3746
3747 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3748         .name   = "usb_tll_hs",
3749         .sysc   = &omap44xx_usb_tll_hs_sysc,
3750 };
3751
3752 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3753         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3754         { .irq = -1 }
3755 };
3756
3757 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3758         .name           = "usb_tll_hs",
3759         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3760         .clkdm_name     = "l3_init_clkdm",
3761         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3762         .main_clk       = "usb_tll_hs_ick",
3763         .prcm = {
3764                 .omap4 = {
3765                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3766                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3767                         .modulemode   = MODULEMODE_HWCTRL,
3768                 },
3769         },
3770 };
3771
3772 /*
3773  * 'wd_timer' class
3774  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3775  * overflow condition
3776  */
3777
3778 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3779         .rev_offs       = 0x0000,
3780         .sysc_offs      = 0x0010,
3781         .syss_offs      = 0x0014,
3782         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3783                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3784         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3785                            SIDLE_SMART_WKUP),
3786         .sysc_fields    = &omap_hwmod_sysc_type1,
3787 };
3788
3789 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3790         .name           = "wd_timer",
3791         .sysc           = &omap44xx_wd_timer_sysc,
3792         .pre_shutdown   = &omap2_wd_timer_disable,
3793         .reset          = &omap2_wd_timer_reset,
3794 };
3795
3796 /* wd_timer2 */
3797 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3798         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3799         { .irq = -1 }
3800 };
3801
3802 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3803         .name           = "wd_timer2",
3804         .class          = &omap44xx_wd_timer_hwmod_class,
3805         .clkdm_name     = "l4_wkup_clkdm",
3806         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3807         .main_clk       = "sys_32k_ck",
3808         .prcm = {
3809                 .omap4 = {
3810                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3811                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3812                         .modulemode   = MODULEMODE_SWCTRL,
3813                 },
3814         },
3815 };
3816
3817 /* wd_timer3 */
3818 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3819         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3820         { .irq = -1 }
3821 };
3822
3823 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3824         .name           = "wd_timer3",
3825         .class          = &omap44xx_wd_timer_hwmod_class,
3826         .clkdm_name     = "abe_clkdm",
3827         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3828         .main_clk       = "sys_32k_ck",
3829         .prcm = {
3830                 .omap4 = {
3831                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3832                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3833                         .modulemode   = MODULEMODE_SWCTRL,
3834                 },
3835         },
3836 };
3837
3838
3839 /*
3840  * interfaces
3841  */
3842
3843 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3844         {
3845                 .pa_start       = 0x4a204000,
3846                 .pa_end         = 0x4a2040ff,
3847                 .flags          = ADDR_TYPE_RT
3848         },
3849         { }
3850 };
3851
3852 /* c2c -> c2c_target_fw */
3853 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3854         .master         = &omap44xx_c2c_hwmod,
3855         .slave          = &omap44xx_c2c_target_fw_hwmod,
3856         .clk            = "div_core_ck",
3857         .addr           = omap44xx_c2c_target_fw_addrs,
3858         .user           = OCP_USER_MPU,
3859 };
3860
3861 /* l4_cfg -> c2c_target_fw */
3862 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3863         .master         = &omap44xx_l4_cfg_hwmod,
3864         .slave          = &omap44xx_c2c_target_fw_hwmod,
3865         .clk            = "l4_div_ck",
3866         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3867 };
3868
3869 /* l3_main_1 -> dmm */
3870 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3871         .master         = &omap44xx_l3_main_1_hwmod,
3872         .slave          = &omap44xx_dmm_hwmod,
3873         .clk            = "l3_div_ck",
3874         .user           = OCP_USER_SDMA,
3875 };
3876
3877 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3878         {
3879                 .pa_start       = 0x4e000000,
3880                 .pa_end         = 0x4e0007ff,
3881                 .flags          = ADDR_TYPE_RT
3882         },
3883         { }
3884 };
3885
3886 /* mpu -> dmm */
3887 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3888         .master         = &omap44xx_mpu_hwmod,
3889         .slave          = &omap44xx_dmm_hwmod,
3890         .clk            = "l3_div_ck",
3891         .addr           = omap44xx_dmm_addrs,
3892         .user           = OCP_USER_MPU,
3893 };
3894
3895 /* c2c -> emif_fw */
3896 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3897         .master         = &omap44xx_c2c_hwmod,
3898         .slave          = &omap44xx_emif_fw_hwmod,
3899         .clk            = "div_core_ck",
3900         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3901 };
3902
3903 /* dmm -> emif_fw */
3904 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3905         .master         = &omap44xx_dmm_hwmod,
3906         .slave          = &omap44xx_emif_fw_hwmod,
3907         .clk            = "l3_div_ck",
3908         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3909 };
3910
3911 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3912         {
3913                 .pa_start       = 0x4a20c000,
3914                 .pa_end         = 0x4a20c0ff,
3915                 .flags          = ADDR_TYPE_RT
3916         },
3917         { }
3918 };
3919
3920 /* l4_cfg -> emif_fw */
3921 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3922         .master         = &omap44xx_l4_cfg_hwmod,
3923         .slave          = &omap44xx_emif_fw_hwmod,
3924         .clk            = "l4_div_ck",
3925         .addr           = omap44xx_emif_fw_addrs,
3926         .user           = OCP_USER_MPU,
3927 };
3928
3929 /* iva -> l3_instr */
3930 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3931         .master         = &omap44xx_iva_hwmod,
3932         .slave          = &omap44xx_l3_instr_hwmod,
3933         .clk            = "l3_div_ck",
3934         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3935 };
3936
3937 /* l3_main_3 -> l3_instr */
3938 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3939         .master         = &omap44xx_l3_main_3_hwmod,
3940         .slave          = &omap44xx_l3_instr_hwmod,
3941         .clk            = "l3_div_ck",
3942         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3943 };
3944
3945 /* ocp_wp_noc -> l3_instr */
3946 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3947         .master         = &omap44xx_ocp_wp_noc_hwmod,
3948         .slave          = &omap44xx_l3_instr_hwmod,
3949         .clk            = "l3_div_ck",
3950         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3951 };
3952
3953 /* dsp -> l3_main_1 */
3954 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3955         .master         = &omap44xx_dsp_hwmod,
3956         .slave          = &omap44xx_l3_main_1_hwmod,
3957         .clk            = "l3_div_ck",
3958         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3959 };
3960
3961 /* dss -> l3_main_1 */
3962 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3963         .master         = &omap44xx_dss_hwmod,
3964         .slave          = &omap44xx_l3_main_1_hwmod,
3965         .clk            = "l3_div_ck",
3966         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3967 };
3968
3969 /* l3_main_2 -> l3_main_1 */
3970 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3971         .master         = &omap44xx_l3_main_2_hwmod,
3972         .slave          = &omap44xx_l3_main_1_hwmod,
3973         .clk            = "l3_div_ck",
3974         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3975 };
3976
3977 /* l4_cfg -> l3_main_1 */
3978 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3979         .master         = &omap44xx_l4_cfg_hwmod,
3980         .slave          = &omap44xx_l3_main_1_hwmod,
3981         .clk            = "l4_div_ck",
3982         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3983 };
3984
3985 /* mmc1 -> l3_main_1 */
3986 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3987         .master         = &omap44xx_mmc1_hwmod,
3988         .slave          = &omap44xx_l3_main_1_hwmod,
3989         .clk            = "l3_div_ck",
3990         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3991 };
3992
3993 /* mmc2 -> l3_main_1 */
3994 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3995         .master         = &omap44xx_mmc2_hwmod,
3996         .slave          = &omap44xx_l3_main_1_hwmod,
3997         .clk            = "l3_div_ck",
3998         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3999 };
4000
4001 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
4002         {
4003                 .pa_start       = 0x44000000,
4004                 .pa_end         = 0x44000fff,
4005                 .flags          = ADDR_TYPE_RT
4006         },
4007         { }
4008 };
4009
4010 /* mpu -> l3_main_1 */
4011 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
4012         .master         = &omap44xx_mpu_hwmod,
4013         .slave          = &omap44xx_l3_main_1_hwmod,
4014         .clk            = "l3_div_ck",
4015         .addr           = omap44xx_l3_main_1_addrs,
4016         .user           = OCP_USER_MPU,
4017 };
4018
4019 /* c2c_target_fw -> l3_main_2 */
4020 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
4021         .master         = &omap44xx_c2c_target_fw_hwmod,
4022         .slave          = &omap44xx_l3_main_2_hwmod,
4023         .clk            = "l3_div_ck",
4024         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4025 };
4026
4027 /* debugss -> l3_main_2 */
4028 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
4029         .master         = &omap44xx_debugss_hwmod,
4030         .slave          = &omap44xx_l3_main_2_hwmod,
4031         .clk            = "dbgclk_mux_ck",
4032         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4033 };
4034
4035 /* dma_system -> l3_main_2 */
4036 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
4037         .master         = &omap44xx_dma_system_hwmod,
4038         .slave          = &omap44xx_l3_main_2_hwmod,
4039         .clk            = "l3_div_ck",
4040         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4041 };
4042
4043 /* fdif -> l3_main_2 */
4044 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
4045         .master         = &omap44xx_fdif_hwmod,
4046         .slave          = &omap44xx_l3_main_2_hwmod,
4047         .clk            = "l3_div_ck",
4048         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4049 };
4050
4051 /* gpu -> l3_main_2 */
4052 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
4053         .master         = &omap44xx_gpu_hwmod,
4054         .slave          = &omap44xx_l3_main_2_hwmod,
4055         .clk            = "l3_div_ck",
4056         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4057 };
4058
4059 /* hsi -> l3_main_2 */
4060 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
4061         .master         = &omap44xx_hsi_hwmod,
4062         .slave          = &omap44xx_l3_main_2_hwmod,
4063         .clk            = "l3_div_ck",
4064         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4065 };
4066
4067 /* ipu -> l3_main_2 */
4068 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
4069         .master         = &omap44xx_ipu_hwmod,
4070         .slave          = &omap44xx_l3_main_2_hwmod,
4071         .clk            = "l3_div_ck",
4072         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4073 };
4074
4075 /* iss -> l3_main_2 */
4076 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
4077         .master         = &omap44xx_iss_hwmod,
4078         .slave          = &omap44xx_l3_main_2_hwmod,
4079         .clk            = "l3_div_ck",
4080         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4081 };
4082
4083 /* iva -> l3_main_2 */
4084 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
4085         .master         = &omap44xx_iva_hwmod,
4086         .slave          = &omap44xx_l3_main_2_hwmod,
4087         .clk            = "l3_div_ck",
4088         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4089 };
4090
4091 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
4092         {
4093                 .pa_start       = 0x44800000,
4094                 .pa_end         = 0x44801fff,
4095                 .flags          = ADDR_TYPE_RT
4096         },
4097         { }
4098 };
4099
4100 /* l3_main_1 -> l3_main_2 */
4101 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
4102         .master         = &omap44xx_l3_main_1_hwmod,
4103         .slave          = &omap44xx_l3_main_2_hwmod,
4104         .clk            = "l3_div_ck",
4105         .addr           = omap44xx_l3_main_2_addrs,
4106         .user           = OCP_USER_MPU,
4107 };
4108
4109 /* l4_cfg -> l3_main_2 */
4110 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
4111         .master         = &omap44xx_l4_cfg_hwmod,
4112         .slave          = &omap44xx_l3_main_2_hwmod,
4113         .clk            = "l4_div_ck",
4114         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4115 };
4116
4117 /* usb_host_fs -> l3_main_2 */
4118 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
4119         .master         = &omap44xx_usb_host_fs_hwmod,
4120         .slave          = &omap44xx_l3_main_2_hwmod,
4121         .clk            = "l3_div_ck",
4122         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4123 };
4124
4125 /* usb_host_hs -> l3_main_2 */
4126 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
4127         .master         = &omap44xx_usb_host_hs_hwmod,
4128         .slave          = &omap44xx_l3_main_2_hwmod,
4129         .clk            = "l3_div_ck",
4130         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4131 };
4132
4133 /* usb_otg_hs -> l3_main_2 */
4134 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
4135         .master         = &omap44xx_usb_otg_hs_hwmod,
4136         .slave          = &omap44xx_l3_main_2_hwmod,
4137         .clk            = "l3_div_ck",
4138         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4139 };
4140
4141 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
4142         {
4143                 .pa_start       = 0x45000000,
4144                 .pa_end         = 0x45000fff,
4145                 .flags          = ADDR_TYPE_RT
4146         },
4147         { }
4148 };
4149
4150 /* l3_main_1 -> l3_main_3 */
4151 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
4152         .master         = &omap44xx_l3_main_1_hwmod,
4153         .slave          = &omap44xx_l3_main_3_hwmod,
4154         .clk            = "l3_div_ck",
4155         .addr           = omap44xx_l3_main_3_addrs,
4156         .user           = OCP_USER_MPU,
4157 };
4158
4159 /* l3_main_2 -> l3_main_3 */
4160 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
4161         .master         = &omap44xx_l3_main_2_hwmod,
4162         .slave          = &omap44xx_l3_main_3_hwmod,
4163         .clk            = "l3_div_ck",
4164         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4165 };
4166
4167 /* l4_cfg -> l3_main_3 */
4168 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
4169         .master         = &omap44xx_l4_cfg_hwmod,
4170         .slave          = &omap44xx_l3_main_3_hwmod,
4171         .clk            = "l4_div_ck",
4172         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4173 };
4174
4175 /* aess -> l4_abe */
4176 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
4177         .master         = &omap44xx_aess_hwmod,
4178         .slave          = &omap44xx_l4_abe_hwmod,
4179         .clk            = "ocp_abe_iclk",
4180         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4181 };
4182
4183 /* dsp -> l4_abe */
4184 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
4185         .master         = &omap44xx_dsp_hwmod,
4186         .slave          = &omap44xx_l4_abe_hwmod,
4187         .clk            = "ocp_abe_iclk",
4188         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4189 };
4190
4191 /* l3_main_1 -> l4_abe */
4192 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
4193         .master         = &omap44xx_l3_main_1_hwmod,
4194         .slave          = &omap44xx_l4_abe_hwmod,
4195         .clk            = "l3_div_ck",
4196         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4197 };
4198
4199 /* mpu -> l4_abe */
4200 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
4201         .master         = &omap44xx_mpu_hwmod,
4202         .slave          = &omap44xx_l4_abe_hwmod,
4203         .clk            = "ocp_abe_iclk",
4204         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4205 };
4206
4207 /* l3_main_1 -> l4_cfg */
4208 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
4209         .master         = &omap44xx_l3_main_1_hwmod,
4210         .slave          = &omap44xx_l4_cfg_hwmod,
4211         .clk            = "l3_div_ck",
4212         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4213 };
4214
4215 /* l3_main_2 -> l4_per */
4216 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
4217         .master         = &omap44xx_l3_main_2_hwmod,
4218         .slave          = &omap44xx_l4_per_hwmod,
4219         .clk            = "l3_div_ck",
4220         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4221 };
4222
4223 /* l4_cfg -> l4_wkup */
4224 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
4225         .master         = &omap44xx_l4_cfg_hwmod,
4226         .slave          = &omap44xx_l4_wkup_hwmod,
4227         .clk            = "l4_div_ck",
4228         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4229 };
4230
4231 /* mpu -> mpu_private */
4232 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4233         .master         = &omap44xx_mpu_hwmod,
4234         .slave          = &omap44xx_mpu_private_hwmod,
4235         .clk            = "l3_div_ck",
4236         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4237 };
4238
4239 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4240         {
4241                 .pa_start       = 0x4a102000,
4242                 .pa_end         = 0x4a10207f,
4243                 .flags          = ADDR_TYPE_RT
4244         },
4245         { }
4246 };
4247
4248 /* l4_cfg -> ocp_wp_noc */
4249 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4250         .master         = &omap44xx_l4_cfg_hwmod,
4251         .slave          = &omap44xx_ocp_wp_noc_hwmod,
4252         .clk            = "l4_div_ck",
4253         .addr           = omap44xx_ocp_wp_noc_addrs,
4254         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4255 };
4256
4257 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4258         {
4259                 .name           = "dmem",
4260                 .pa_start       = 0x40180000,
4261                 .pa_end         = 0x4018ffff
4262         },
4263         {
4264                 .name           = "cmem",
4265                 .pa_start       = 0x401a0000,
4266                 .pa_end         = 0x401a1fff
4267         },
4268         {
4269                 .name           = "smem",
4270                 .pa_start       = 0x401c0000,
4271                 .pa_end         = 0x401c5fff
4272         },
4273         {
4274                 .name           = "pmem",
4275                 .pa_start       = 0x401e0000,
4276                 .pa_end         = 0x401e1fff
4277         },
4278         {
4279                 .name           = "mpu",
4280                 .pa_start       = 0x401f1000,
4281                 .pa_end         = 0x401f13ff,
4282                 .flags          = ADDR_TYPE_RT
4283         },
4284         { }
4285 };
4286
4287 /* l4_abe -> aess */
4288 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4289         .master         = &omap44xx_l4_abe_hwmod,
4290         .slave          = &omap44xx_aess_hwmod,
4291         .clk            = "ocp_abe_iclk",
4292         .addr           = omap44xx_aess_addrs,
4293         .user           = OCP_USER_MPU,
4294 };
4295
4296 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4297         {
4298                 .name           = "dmem_dma",
4299                 .pa_start       = 0x49080000,
4300                 .pa_end         = 0x4908ffff
4301         },
4302         {
4303                 .name           = "cmem_dma",
4304                 .pa_start       = 0x490a0000,
4305                 .pa_end         = 0x490a1fff
4306         },
4307         {
4308                 .name           = "smem_dma",
4309                 .pa_start       = 0x490c0000,
4310                 .pa_end         = 0x490c5fff
4311         },
4312         {
4313                 .name           = "pmem_dma",
4314                 .pa_start       = 0x490e0000,
4315                 .pa_end         = 0x490e1fff
4316         },
4317         {
4318                 .name           = "dma",
4319                 .pa_start       = 0x490f1000,
4320                 .pa_end         = 0x490f13ff,
4321                 .flags          = ADDR_TYPE_RT
4322         },
4323         { }
4324 };
4325
4326 /* l4_abe -> aess (dma) */
4327 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4328         .master         = &omap44xx_l4_abe_hwmod,
4329         .slave          = &omap44xx_aess_hwmod,
4330         .clk            = "ocp_abe_iclk",
4331         .addr           = omap44xx_aess_dma_addrs,
4332         .user           = OCP_USER_SDMA,
4333 };
4334
4335 /* l3_main_2 -> c2c */
4336 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4337         .master         = &omap44xx_l3_main_2_hwmod,
4338         .slave          = &omap44xx_c2c_hwmod,
4339         .clk            = "l3_div_ck",
4340         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4341 };
4342
4343 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4344         {
4345                 .pa_start       = 0x4a304000,
4346                 .pa_end         = 0x4a30401f,
4347                 .flags          = ADDR_TYPE_RT
4348         },
4349         { }
4350 };
4351
4352 /* l4_wkup -> counter_32k */
4353 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4354         .master         = &omap44xx_l4_wkup_hwmod,
4355         .slave          = &omap44xx_counter_32k_hwmod,
4356         .clk            = "l4_wkup_clk_mux_ck",
4357         .addr           = omap44xx_counter_32k_addrs,
4358         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4359 };
4360
4361 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4362         {
4363                 .pa_start       = 0x4a002000,
4364                 .pa_end         = 0x4a0027ff,
4365                 .flags          = ADDR_TYPE_RT
4366         },
4367         { }
4368 };
4369
4370 /* l4_cfg -> ctrl_module_core */
4371 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4372         .master         = &omap44xx_l4_cfg_hwmod,
4373         .slave          = &omap44xx_ctrl_module_core_hwmod,
4374         .clk            = "l4_div_ck",
4375         .addr           = omap44xx_ctrl_module_core_addrs,
4376         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4377 };
4378
4379 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4380         {
4381                 .pa_start       = 0x4a100000,
4382                 .pa_end         = 0x4a1007ff,
4383                 .flags          = ADDR_TYPE_RT
4384         },
4385         { }
4386 };
4387
4388 /* l4_cfg -> ctrl_module_pad_core */
4389 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4390         .master         = &omap44xx_l4_cfg_hwmod,
4391         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4392         .clk            = "l4_div_ck",
4393         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4394         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4395 };
4396
4397 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4398         {
4399                 .pa_start       = 0x4a30c000,
4400                 .pa_end         = 0x4a30c7ff,
4401                 .flags          = ADDR_TYPE_RT
4402         },
4403         { }
4404 };
4405
4406 /* l4_wkup -> ctrl_module_wkup */
4407 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4408         .master         = &omap44xx_l4_wkup_hwmod,
4409         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4410         .clk            = "l4_wkup_clk_mux_ck",
4411         .addr           = omap44xx_ctrl_module_wkup_addrs,
4412         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4413 };
4414
4415 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4416         {
4417                 .pa_start       = 0x4a31e000,
4418                 .pa_end         = 0x4a31e7ff,
4419                 .flags          = ADDR_TYPE_RT
4420         },
4421         { }
4422 };
4423
4424 /* l4_wkup -> ctrl_module_pad_wkup */
4425 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4426         .master         = &omap44xx_l4_wkup_hwmod,
4427         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4428         .clk            = "l4_wkup_clk_mux_ck",
4429         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4430         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4431 };
4432
4433 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4434         {
4435                 .pa_start       = 0x54160000,
4436                 .pa_end         = 0x54167fff,
4437                 .flags          = ADDR_TYPE_RT
4438         },
4439         { }
4440 };
4441
4442 /* l3_instr -> debugss */
4443 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4444         .master         = &omap44xx_l3_instr_hwmod,
4445         .slave          = &omap44xx_debugss_hwmod,
4446         .clk            = "l3_div_ck",
4447         .addr           = omap44xx_debugss_addrs,
4448         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4449 };
4450
4451 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4452         {
4453                 .pa_start       = 0x4a056000,
4454                 .pa_end         = 0x4a056fff,
4455                 .flags          = ADDR_TYPE_RT
4456         },
4457         { }
4458 };
4459
4460 /* l4_cfg -> dma_system */
4461 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4462         .master         = &omap44xx_l4_cfg_hwmod,
4463         .slave          = &omap44xx_dma_system_hwmod,
4464         .clk            = "l4_div_ck",
4465         .addr           = omap44xx_dma_system_addrs,
4466         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4467 };
4468
4469 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4470         {
4471                 .name           = "mpu",
4472                 .pa_start       = 0x4012e000,
4473                 .pa_end         = 0x4012e07f,
4474                 .flags          = ADDR_TYPE_RT
4475         },
4476         { }
4477 };
4478
4479 /* l4_abe -> dmic */
4480 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4481         .master         = &omap44xx_l4_abe_hwmod,
4482         .slave          = &omap44xx_dmic_hwmod,
4483         .clk            = "ocp_abe_iclk",
4484         .addr           = omap44xx_dmic_addrs,
4485         .user           = OCP_USER_MPU,
4486 };
4487
4488 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4489         {
4490                 .name           = "dma",
4491                 .pa_start       = 0x4902e000,
4492                 .pa_end         = 0x4902e07f,
4493                 .flags          = ADDR_TYPE_RT
4494         },
4495         { }
4496 };
4497
4498 /* l4_abe -> dmic (dma) */
4499 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4500         .master         = &omap44xx_l4_abe_hwmod,
4501         .slave          = &omap44xx_dmic_hwmod,
4502         .clk            = "ocp_abe_iclk",
4503         .addr           = omap44xx_dmic_dma_addrs,
4504         .user           = OCP_USER_SDMA,
4505 };
4506
4507 /* dsp -> iva */
4508 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4509         .master         = &omap44xx_dsp_hwmod,
4510         .slave          = &omap44xx_iva_hwmod,
4511         .clk            = "dpll_iva_m5x2_ck",
4512         .user           = OCP_USER_DSP,
4513 };
4514
4515 /* dsp -> sl2if */
4516 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4517         .master         = &omap44xx_dsp_hwmod,
4518         .slave          = &omap44xx_sl2if_hwmod,
4519         .clk            = "dpll_iva_m5x2_ck",
4520         .user           = OCP_USER_DSP,
4521 };
4522
4523 /* l4_cfg -> dsp */
4524 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4525         .master         = &omap44xx_l4_cfg_hwmod,
4526         .slave          = &omap44xx_dsp_hwmod,
4527         .clk            = "l4_div_ck",
4528         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4529 };
4530
4531 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4532         {
4533                 .pa_start       = 0x58000000,
4534                 .pa_end         = 0x5800007f,
4535                 .flags          = ADDR_TYPE_RT
4536         },
4537         { }
4538 };
4539
4540 /* l3_main_2 -> dss */
4541 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4542         .master         = &omap44xx_l3_main_2_hwmod,
4543         .slave          = &omap44xx_dss_hwmod,
4544         .clk            = "dss_fck",
4545         .addr           = omap44xx_dss_dma_addrs,
4546         .user           = OCP_USER_SDMA,
4547 };
4548
4549 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4550         {
4551                 .pa_start       = 0x48040000,
4552                 .pa_end         = 0x4804007f,
4553                 .flags          = ADDR_TYPE_RT
4554         },
4555         { }
4556 };
4557
4558 /* l4_per -> dss */
4559 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4560         .master         = &omap44xx_l4_per_hwmod,
4561         .slave          = &omap44xx_dss_hwmod,
4562         .clk            = "l4_div_ck",
4563         .addr           = omap44xx_dss_addrs,
4564         .user           = OCP_USER_MPU,
4565 };
4566
4567 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4568         {
4569                 .pa_start       = 0x58001000,
4570                 .pa_end         = 0x58001fff,
4571                 .flags          = ADDR_TYPE_RT
4572         },
4573         { }
4574 };
4575
4576 /* l3_main_2 -> dss_dispc */
4577 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4578         .master         = &omap44xx_l3_main_2_hwmod,
4579         .slave          = &omap44xx_dss_dispc_hwmod,
4580         .clk            = "dss_fck",
4581         .addr           = omap44xx_dss_dispc_dma_addrs,
4582         .user           = OCP_USER_SDMA,
4583 };
4584
4585 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4586         {
4587                 .pa_start       = 0x48041000,
4588                 .pa_end         = 0x48041fff,
4589                 .flags          = ADDR_TYPE_RT
4590         },
4591         { }
4592 };
4593
4594 /* l4_per -> dss_dispc */
4595 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4596         .master         = &omap44xx_l4_per_hwmod,
4597         .slave          = &omap44xx_dss_dispc_hwmod,
4598         .clk            = "l4_div_ck",
4599         .addr           = omap44xx_dss_dispc_addrs,
4600         .user           = OCP_USER_MPU,
4601 };
4602
4603 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4604         {
4605                 .pa_start       = 0x58004000,
4606                 .pa_end         = 0x580041ff,
4607                 .flags          = ADDR_TYPE_RT
4608         },
4609         { }
4610 };
4611
4612 /* l3_main_2 -> dss_dsi1 */
4613 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4614         .master         = &omap44xx_l3_main_2_hwmod,
4615         .slave          = &omap44xx_dss_dsi1_hwmod,
4616         .clk            = "dss_fck",
4617         .addr           = omap44xx_dss_dsi1_dma_addrs,
4618         .user           = OCP_USER_SDMA,
4619 };
4620
4621 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4622         {
4623                 .pa_start       = 0x48044000,
4624                 .pa_end         = 0x480441ff,
4625                 .flags          = ADDR_TYPE_RT
4626         },
4627         { }
4628 };
4629
4630 /* l4_per -> dss_dsi1 */
4631 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4632         .master         = &omap44xx_l4_per_hwmod,
4633         .slave          = &omap44xx_dss_dsi1_hwmod,
4634         .clk            = "l4_div_ck",
4635         .addr           = omap44xx_dss_dsi1_addrs,
4636         .user           = OCP_USER_MPU,
4637 };
4638
4639 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4640         {
4641                 .pa_start       = 0x58005000,
4642                 .pa_end         = 0x580051ff,
4643                 .flags          = ADDR_TYPE_RT
4644         },
4645         { }
4646 };
4647
4648 /* l3_main_2 -> dss_dsi2 */
4649 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4650         .master         = &omap44xx_l3_main_2_hwmod,
4651         .slave          = &omap44xx_dss_dsi2_hwmod,
4652         .clk            = "dss_fck",
4653         .addr           = omap44xx_dss_dsi2_dma_addrs,
4654         .user           = OCP_USER_SDMA,
4655 };
4656
4657 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4658         {
4659                 .pa_start       = 0x48045000,
4660                 .pa_end         = 0x480451ff,
4661                 .flags          = ADDR_TYPE_RT
4662         },
4663         { }
4664 };
4665
4666 /* l4_per -> dss_dsi2 */
4667 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4668         .master         = &omap44xx_l4_per_hwmod,
4669         .slave          = &omap44xx_dss_dsi2_hwmod,
4670         .clk            = "l4_div_ck",
4671         .addr           = omap44xx_dss_dsi2_addrs,
4672         .user           = OCP_USER_MPU,
4673 };
4674
4675 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4676         {
4677                 .pa_start       = 0x58006000,
4678                 .pa_end         = 0x58006fff,
4679                 .flags          = ADDR_TYPE_RT
4680         },
4681         { }
4682 };
4683
4684 /* l3_main_2 -> dss_hdmi */
4685 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4686         .master         = &omap44xx_l3_main_2_hwmod,
4687         .slave          = &omap44xx_dss_hdmi_hwmod,
4688         .clk            = "dss_fck",
4689         .addr           = omap44xx_dss_hdmi_dma_addrs,
4690         .user           = OCP_USER_SDMA,
4691 };
4692
4693 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4694         {
4695                 .pa_start       = 0x48046000,
4696                 .pa_end         = 0x48046fff,
4697                 .flags          = ADDR_TYPE_RT
4698         },
4699         { }
4700 };
4701
4702 /* l4_per -> dss_hdmi */
4703 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4704         .master         = &omap44xx_l4_per_hwmod,
4705         .slave          = &omap44xx_dss_hdmi_hwmod,
4706         .clk            = "l4_div_ck",
4707         .addr           = omap44xx_dss_hdmi_addrs,
4708         .user           = OCP_USER_MPU,
4709 };
4710
4711 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4712         {
4713                 .pa_start       = 0x58002000,
4714                 .pa_end         = 0x580020ff,
4715                 .flags          = ADDR_TYPE_RT
4716         },
4717         { }
4718 };
4719
4720 /* l3_main_2 -> dss_rfbi */
4721 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4722         .master         = &omap44xx_l3_main_2_hwmod,
4723         .slave          = &omap44xx_dss_rfbi_hwmod,
4724         .clk            = "dss_fck",
4725         .addr           = omap44xx_dss_rfbi_dma_addrs,
4726         .user           = OCP_USER_SDMA,
4727 };
4728
4729 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4730         {
4731                 .pa_start       = 0x48042000,
4732                 .pa_end         = 0x480420ff,
4733                 .flags          = ADDR_TYPE_RT
4734         },
4735         { }
4736 };
4737
4738 /* l4_per -> dss_rfbi */
4739 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4740         .master         = &omap44xx_l4_per_hwmod,
4741         .slave          = &omap44xx_dss_rfbi_hwmod,
4742         .clk            = "l4_div_ck",
4743         .addr           = omap44xx_dss_rfbi_addrs,
4744         .user           = OCP_USER_MPU,
4745 };
4746
4747 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4748         {
4749                 .pa_start       = 0x58003000,
4750                 .pa_end         = 0x580030ff,
4751                 .flags          = ADDR_TYPE_RT
4752         },
4753         { }
4754 };
4755
4756 /* l3_main_2 -> dss_venc */
4757 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4758         .master         = &omap44xx_l3_main_2_hwmod,
4759         .slave          = &omap44xx_dss_venc_hwmod,
4760         .clk            = "dss_fck",
4761         .addr           = omap44xx_dss_venc_dma_addrs,
4762         .user           = OCP_USER_SDMA,
4763 };
4764
4765 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4766         {
4767                 .pa_start       = 0x48043000,
4768                 .pa_end         = 0x480430ff,
4769                 .flags          = ADDR_TYPE_RT
4770         },
4771         { }
4772 };
4773
4774 /* l4_per -> dss_venc */
4775 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4776         .master         = &omap44xx_l4_per_hwmod,
4777         .slave          = &omap44xx_dss_venc_hwmod,
4778         .clk            = "l4_div_ck",
4779         .addr           = omap44xx_dss_venc_addrs,
4780         .user           = OCP_USER_MPU,
4781 };
4782
4783 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4784         {
4785                 .pa_start       = 0x48078000,
4786                 .pa_end         = 0x48078fff,
4787                 .flags          = ADDR_TYPE_RT
4788         },
4789         { }
4790 };
4791
4792 /* l4_per -> elm */
4793 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4794         .master         = &omap44xx_l4_per_hwmod,
4795         .slave          = &omap44xx_elm_hwmod,
4796         .clk            = "l4_div_ck",
4797         .addr           = omap44xx_elm_addrs,
4798         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4799 };
4800
4801 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4802         {
4803                 .pa_start       = 0x4c000000,
4804                 .pa_end         = 0x4c0000ff,
4805                 .flags          = ADDR_TYPE_RT
4806         },
4807         { }
4808 };
4809
4810 /* emif_fw -> emif1 */
4811 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4812         .master         = &omap44xx_emif_fw_hwmod,
4813         .slave          = &omap44xx_emif1_hwmod,
4814         .clk            = "l3_div_ck",
4815         .addr           = omap44xx_emif1_addrs,
4816         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4817 };
4818
4819 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4820         {
4821                 .pa_start       = 0x4d000000,
4822                 .pa_end         = 0x4d0000ff,
4823                 .flags          = ADDR_TYPE_RT
4824         },
4825         { }
4826 };
4827
4828 /* emif_fw -> emif2 */
4829 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4830         .master         = &omap44xx_emif_fw_hwmod,
4831         .slave          = &omap44xx_emif2_hwmod,
4832         .clk            = "l3_div_ck",
4833         .addr           = omap44xx_emif2_addrs,
4834         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4835 };
4836
4837 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4838         {
4839                 .pa_start       = 0x4a10a000,
4840                 .pa_end         = 0x4a10a1ff,
4841                 .flags          = ADDR_TYPE_RT
4842         },
4843         { }
4844 };
4845
4846 /* l4_cfg -> fdif */
4847 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4848         .master         = &omap44xx_l4_cfg_hwmod,
4849         .slave          = &omap44xx_fdif_hwmod,
4850         .clk            = "l4_div_ck",
4851         .addr           = omap44xx_fdif_addrs,
4852         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4853 };
4854
4855 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4856         {
4857                 .pa_start       = 0x4a310000,
4858                 .pa_end         = 0x4a3101ff,
4859                 .flags          = ADDR_TYPE_RT
4860         },
4861         { }
4862 };
4863
4864 /* l4_wkup -> gpio1 */
4865 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4866         .master         = &omap44xx_l4_wkup_hwmod,
4867         .slave          = &omap44xx_gpio1_hwmod,
4868         .clk            = "l4_wkup_clk_mux_ck",
4869         .addr           = omap44xx_gpio1_addrs,
4870         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4871 };
4872
4873 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4874         {
4875                 .pa_start       = 0x48055000,
4876                 .pa_end         = 0x480551ff,
4877                 .flags          = ADDR_TYPE_RT
4878         },
4879         { }
4880 };
4881
4882 /* l4_per -> gpio2 */
4883 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4884         .master         = &omap44xx_l4_per_hwmod,
4885         .slave          = &omap44xx_gpio2_hwmod,
4886         .clk            = "l4_div_ck",
4887         .addr           = omap44xx_gpio2_addrs,
4888         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4889 };
4890
4891 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4892         {
4893                 .pa_start       = 0x48057000,
4894                 .pa_end         = 0x480571ff,
4895                 .flags          = ADDR_TYPE_RT
4896         },
4897         { }
4898 };
4899
4900 /* l4_per -> gpio3 */
4901 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4902         .master         = &omap44xx_l4_per_hwmod,
4903         .slave          = &omap44xx_gpio3_hwmod,
4904         .clk            = "l4_div_ck",
4905         .addr           = omap44xx_gpio3_addrs,
4906         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4907 };
4908
4909 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4910         {
4911                 .pa_start       = 0x48059000,
4912                 .pa_end         = 0x480591ff,
4913                 .flags          = ADDR_TYPE_RT
4914         },
4915         { }
4916 };
4917
4918 /* l4_per -> gpio4 */
4919 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4920         .master         = &omap44xx_l4_per_hwmod,
4921         .slave          = &omap44xx_gpio4_hwmod,
4922         .clk            = "l4_div_ck",
4923         .addr           = omap44xx_gpio4_addrs,
4924         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4925 };
4926
4927 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4928         {
4929                 .pa_start       = 0x4805b000,
4930                 .pa_end         = 0x4805b1ff,
4931                 .flags          = ADDR_TYPE_RT
4932         },
4933         { }
4934 };
4935
4936 /* l4_per -> gpio5 */
4937 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4938         .master         = &omap44xx_l4_per_hwmod,
4939         .slave          = &omap44xx_gpio5_hwmod,
4940         .clk            = "l4_div_ck",
4941         .addr           = omap44xx_gpio5_addrs,
4942         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4943 };
4944
4945 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4946         {
4947                 .pa_start       = 0x4805d000,
4948                 .pa_end         = 0x4805d1ff,
4949                 .flags          = ADDR_TYPE_RT
4950         },
4951         { }
4952 };
4953
4954 /* l4_per -> gpio6 */
4955 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4956         .master         = &omap44xx_l4_per_hwmod,
4957         .slave          = &omap44xx_gpio6_hwmod,
4958         .clk            = "l4_div_ck",
4959         .addr           = omap44xx_gpio6_addrs,
4960         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4961 };
4962
4963 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4964         {
4965                 .pa_start       = 0x50000000,
4966                 .pa_end         = 0x500003ff,
4967                 .flags          = ADDR_TYPE_RT
4968         },
4969         { }
4970 };
4971
4972 /* l3_main_2 -> gpmc */
4973 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4974         .master         = &omap44xx_l3_main_2_hwmod,
4975         .slave          = &omap44xx_gpmc_hwmod,
4976         .clk            = "l3_div_ck",
4977         .addr           = omap44xx_gpmc_addrs,
4978         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4979 };
4980
4981 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4982         {
4983                 .pa_start       = 0x56000000,
4984                 .pa_end         = 0x5600ffff,
4985                 .flags          = ADDR_TYPE_RT
4986         },
4987         { }
4988 };
4989
4990 /* l3_main_2 -> gpu */
4991 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4992         .master         = &omap44xx_l3_main_2_hwmod,
4993         .slave          = &omap44xx_gpu_hwmod,
4994         .clk            = "l3_div_ck",
4995         .addr           = omap44xx_gpu_addrs,
4996         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4997 };
4998
4999 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
5000         {
5001                 .pa_start       = 0x480b2000,
5002                 .pa_end         = 0x480b201f,
5003                 .flags          = ADDR_TYPE_RT
5004         },
5005         { }
5006 };
5007
5008 /* l4_per -> hdq1w */
5009 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
5010         .master         = &omap44xx_l4_per_hwmod,
5011         .slave          = &omap44xx_hdq1w_hwmod,
5012         .clk            = "l4_div_ck",
5013         .addr           = omap44xx_hdq1w_addrs,
5014         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5015 };
5016
5017 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
5018         {
5019                 .pa_start       = 0x4a058000,
5020                 .pa_end         = 0x4a05bfff,
5021                 .flags          = ADDR_TYPE_RT
5022         },
5023         { }
5024 };
5025
5026 /* l4_cfg -> hsi */
5027 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
5028         .master         = &omap44xx_l4_cfg_hwmod,
5029         .slave          = &omap44xx_hsi_hwmod,
5030         .clk            = "l4_div_ck",
5031         .addr           = omap44xx_hsi_addrs,
5032         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5033 };
5034
5035 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
5036         {
5037                 .pa_start       = 0x48070000,
5038                 .pa_end         = 0x480700ff,
5039                 .flags          = ADDR_TYPE_RT
5040         },
5041         { }
5042 };
5043
5044 /* l4_per -> i2c1 */
5045 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
5046         .master         = &omap44xx_l4_per_hwmod,
5047         .slave          = &omap44xx_i2c1_hwmod,
5048         .clk            = "l4_div_ck",
5049         .addr           = omap44xx_i2c1_addrs,
5050         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5051 };
5052
5053 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
5054         {
5055                 .pa_start       = 0x48072000,
5056                 .pa_end         = 0x480720ff,
5057                 .flags          = ADDR_TYPE_RT
5058         },
5059         { }
5060 };
5061
5062 /* l4_per -> i2c2 */
5063 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
5064         .master         = &omap44xx_l4_per_hwmod,
5065         .slave          = &omap44xx_i2c2_hwmod,
5066         .clk            = "l4_div_ck",
5067         .addr           = omap44xx_i2c2_addrs,
5068         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5069 };
5070
5071 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
5072         {
5073                 .pa_start       = 0x48060000,
5074                 .pa_end         = 0x480600ff,
5075                 .flags          = ADDR_TYPE_RT
5076         },
5077         { }
5078 };
5079
5080 /* l4_per -> i2c3 */
5081 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
5082         .master         = &omap44xx_l4_per_hwmod,
5083         .slave          = &omap44xx_i2c3_hwmod,
5084         .clk            = "l4_div_ck",
5085         .addr           = omap44xx_i2c3_addrs,
5086         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5087 };
5088
5089 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
5090         {
5091                 .pa_start       = 0x48350000,
5092                 .pa_end         = 0x483500ff,
5093                 .flags          = ADDR_TYPE_RT
5094         },
5095         { }
5096 };
5097
5098 /* l4_per -> i2c4 */
5099 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
5100         .master         = &omap44xx_l4_per_hwmod,
5101         .slave          = &omap44xx_i2c4_hwmod,
5102         .clk            = "l4_div_ck",
5103         .addr           = omap44xx_i2c4_addrs,
5104         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5105 };
5106
5107 /* l3_main_2 -> ipu */
5108 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
5109         .master         = &omap44xx_l3_main_2_hwmod,
5110         .slave          = &omap44xx_ipu_hwmod,
5111         .clk            = "l3_div_ck",
5112         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5113 };
5114
5115 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
5116         {
5117                 .pa_start       = 0x52000000,
5118                 .pa_end         = 0x520000ff,
5119                 .flags          = ADDR_TYPE_RT
5120         },
5121         { }
5122 };
5123
5124 /* l3_main_2 -> iss */
5125 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
5126         .master         = &omap44xx_l3_main_2_hwmod,
5127         .slave          = &omap44xx_iss_hwmod,
5128         .clk            = "l3_div_ck",
5129         .addr           = omap44xx_iss_addrs,
5130         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5131 };
5132
5133 /* iva -> sl2if */
5134 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
5135         .master         = &omap44xx_iva_hwmod,
5136         .slave          = &omap44xx_sl2if_hwmod,
5137         .clk            = "dpll_iva_m5x2_ck",
5138         .user           = OCP_USER_IVA,
5139 };
5140
5141 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
5142         {
5143                 .pa_start       = 0x5a000000,
5144                 .pa_end         = 0x5a07ffff,
5145                 .flags          = ADDR_TYPE_RT
5146         },
5147         { }
5148 };
5149
5150 /* l3_main_2 -> iva */
5151 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
5152         .master         = &omap44xx_l3_main_2_hwmod,
5153         .slave          = &omap44xx_iva_hwmod,
5154         .clk            = "l3_div_ck",
5155         .addr           = omap44xx_iva_addrs,
5156         .user           = OCP_USER_MPU,
5157 };
5158
5159 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
5160         {
5161                 .pa_start       = 0x4a31c000,
5162                 .pa_end         = 0x4a31c07f,
5163                 .flags          = ADDR_TYPE_RT
5164         },
5165         { }
5166 };
5167
5168 /* l4_wkup -> kbd */
5169 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
5170         .master         = &omap44xx_l4_wkup_hwmod,
5171         .slave          = &omap44xx_kbd_hwmod,
5172         .clk            = "l4_wkup_clk_mux_ck",
5173         .addr           = omap44xx_kbd_addrs,
5174         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5175 };
5176
5177 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
5178         {
5179                 .pa_start       = 0x4a0f4000,
5180                 .pa_end         = 0x4a0f41ff,
5181                 .flags          = ADDR_TYPE_RT
5182         },
5183         { }
5184 };
5185
5186 /* l4_cfg -> mailbox */
5187 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
5188         .master         = &omap44xx_l4_cfg_hwmod,
5189         .slave          = &omap44xx_mailbox_hwmod,
5190         .clk            = "l4_div_ck",
5191         .addr           = omap44xx_mailbox_addrs,
5192         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5193 };
5194
5195 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
5196         {
5197                 .pa_start       = 0x40128000,
5198                 .pa_end         = 0x401283ff,
5199                 .flags          = ADDR_TYPE_RT
5200         },
5201         { }
5202 };
5203
5204 /* l4_abe -> mcasp */
5205 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
5206         .master         = &omap44xx_l4_abe_hwmod,
5207         .slave          = &omap44xx_mcasp_hwmod,
5208         .clk            = "ocp_abe_iclk",
5209         .addr           = omap44xx_mcasp_addrs,
5210         .user           = OCP_USER_MPU,
5211 };
5212
5213 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
5214         {
5215                 .pa_start       = 0x49028000,
5216                 .pa_end         = 0x490283ff,
5217                 .flags          = ADDR_TYPE_RT
5218         },
5219         { }
5220 };
5221
5222 /* l4_abe -> mcasp (dma) */
5223 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
5224         .master         = &omap44xx_l4_abe_hwmod,
5225         .slave          = &omap44xx_mcasp_hwmod,
5226         .clk            = "ocp_abe_iclk",
5227         .addr           = omap44xx_mcasp_dma_addrs,
5228         .user           = OCP_USER_SDMA,
5229 };
5230
5231 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
5232         {
5233                 .name           = "mpu",
5234                 .pa_start       = 0x40122000,
5235                 .pa_end         = 0x401220ff,
5236                 .flags          = ADDR_TYPE_RT
5237         },
5238         { }
5239 };
5240
5241 /* l4_abe -> mcbsp1 */
5242 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
5243         .master         = &omap44xx_l4_abe_hwmod,
5244         .slave          = &omap44xx_mcbsp1_hwmod,
5245         .clk            = "ocp_abe_iclk",
5246         .addr           = omap44xx_mcbsp1_addrs,
5247         .user           = OCP_USER_MPU,
5248 };
5249
5250 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
5251         {
5252                 .name           = "dma",
5253                 .pa_start       = 0x49022000,
5254                 .pa_end         = 0x490220ff,
5255                 .flags          = ADDR_TYPE_RT
5256         },
5257         { }
5258 };
5259
5260 /* l4_abe -> mcbsp1 (dma) */
5261 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5262         .master         = &omap44xx_l4_abe_hwmod,
5263         .slave          = &omap44xx_mcbsp1_hwmod,
5264         .clk            = "ocp_abe_iclk",
5265         .addr           = omap44xx_mcbsp1_dma_addrs,
5266         .user           = OCP_USER_SDMA,
5267 };
5268
5269 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5270         {
5271                 .name           = "mpu",
5272                 .pa_start       = 0x40124000,
5273                 .pa_end         = 0x401240ff,
5274                 .flags          = ADDR_TYPE_RT
5275         },
5276         { }
5277 };
5278
5279 /* l4_abe -> mcbsp2 */
5280 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5281         .master         = &omap44xx_l4_abe_hwmod,
5282         .slave          = &omap44xx_mcbsp2_hwmod,
5283         .clk            = "ocp_abe_iclk",
5284         .addr           = omap44xx_mcbsp2_addrs,
5285         .user           = OCP_USER_MPU,
5286 };
5287
5288 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5289         {
5290                 .name           = "dma",
5291                 .pa_start       = 0x49024000,
5292                 .pa_end         = 0x490240ff,
5293                 .flags          = ADDR_TYPE_RT
5294         },
5295         { }
5296 };
5297
5298 /* l4_abe -> mcbsp2 (dma) */
5299 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5300         .master         = &omap44xx_l4_abe_hwmod,
5301         .slave          = &omap44xx_mcbsp2_hwmod,
5302         .clk            = "ocp_abe_iclk",
5303         .addr           = omap44xx_mcbsp2_dma_addrs,
5304         .user           = OCP_USER_SDMA,
5305 };
5306
5307 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5308         {
5309                 .name           = "mpu",
5310                 .pa_start       = 0x40126000,
5311                 .pa_end         = 0x401260ff,
5312                 .flags          = ADDR_TYPE_RT
5313         },
5314         { }
5315 };
5316
5317 /* l4_abe -> mcbsp3 */
5318 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5319         .master         = &omap44xx_l4_abe_hwmod,
5320         .slave          = &omap44xx_mcbsp3_hwmod,
5321         .clk            = "ocp_abe_iclk",
5322         .addr           = omap44xx_mcbsp3_addrs,
5323         .user           = OCP_USER_MPU,
5324 };
5325
5326 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5327         {
5328                 .name           = "dma",
5329                 .pa_start       = 0x49026000,
5330                 .pa_end         = 0x490260ff,
5331                 .flags          = ADDR_TYPE_RT
5332         },
5333         { }
5334 };
5335
5336 /* l4_abe -> mcbsp3 (dma) */
5337 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5338         .master         = &omap44xx_l4_abe_hwmod,
5339         .slave          = &omap44xx_mcbsp3_hwmod,
5340         .clk            = "ocp_abe_iclk",
5341         .addr           = omap44xx_mcbsp3_dma_addrs,
5342         .user           = OCP_USER_SDMA,
5343 };
5344
5345 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5346         {
5347                 .pa_start       = 0x48096000,
5348                 .pa_end         = 0x480960ff,
5349                 .flags          = ADDR_TYPE_RT
5350         },
5351         { }
5352 };
5353
5354 /* l4_per -> mcbsp4 */
5355 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5356         .master         = &omap44xx_l4_per_hwmod,
5357         .slave          = &omap44xx_mcbsp4_hwmod,
5358         .clk            = "l4_div_ck",
5359         .addr           = omap44xx_mcbsp4_addrs,
5360         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5361 };
5362
5363 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5364         {
5365                 .name           = "mpu",
5366                 .pa_start       = 0x40132000,
5367                 .pa_end         = 0x4013207f,
5368                 .flags          = ADDR_TYPE_RT
5369         },
5370         { }
5371 };
5372
5373 /* l4_abe -> mcpdm */
5374 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5375         .master         = &omap44xx_l4_abe_hwmod,
5376         .slave          = &omap44xx_mcpdm_hwmod,
5377         .clk            = "ocp_abe_iclk",
5378         .addr           = omap44xx_mcpdm_addrs,
5379         .user           = OCP_USER_MPU,
5380 };
5381
5382 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5383         {
5384                 .name           = "dma",
5385                 .pa_start       = 0x49032000,
5386                 .pa_end         = 0x4903207f,
5387                 .flags          = ADDR_TYPE_RT
5388         },
5389         { }
5390 };
5391
5392 /* l4_abe -> mcpdm (dma) */
5393 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5394         .master         = &omap44xx_l4_abe_hwmod,
5395         .slave          = &omap44xx_mcpdm_hwmod,
5396         .clk            = "ocp_abe_iclk",
5397         .addr           = omap44xx_mcpdm_dma_addrs,
5398         .user           = OCP_USER_SDMA,
5399 };
5400
5401 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5402         {
5403                 .pa_start       = 0x48098000,
5404                 .pa_end         = 0x480981ff,
5405                 .flags          = ADDR_TYPE_RT
5406         },
5407         { }
5408 };
5409
5410 /* l4_per -> mcspi1 */
5411 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5412         .master         = &omap44xx_l4_per_hwmod,
5413         .slave          = &omap44xx_mcspi1_hwmod,
5414         .clk            = "l4_div_ck",
5415         .addr           = omap44xx_mcspi1_addrs,
5416         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5417 };
5418
5419 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5420         {
5421                 .pa_start       = 0x4809a000,
5422                 .pa_end         = 0x4809a1ff,
5423                 .flags          = ADDR_TYPE_RT
5424         },
5425         { }
5426 };
5427
5428 /* l4_per -> mcspi2 */
5429 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5430         .master         = &omap44xx_l4_per_hwmod,
5431         .slave          = &omap44xx_mcspi2_hwmod,
5432         .clk            = "l4_div_ck",
5433         .addr           = omap44xx_mcspi2_addrs,
5434         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5435 };
5436
5437 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5438         {
5439                 .pa_start       = 0x480b8000,
5440                 .pa_end         = 0x480b81ff,
5441                 .flags          = ADDR_TYPE_RT
5442         },
5443         { }
5444 };
5445
5446 /* l4_per -> mcspi3 */
5447 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5448         .master         = &omap44xx_l4_per_hwmod,
5449         .slave          = &omap44xx_mcspi3_hwmod,
5450         .clk            = "l4_div_ck",
5451         .addr           = omap44xx_mcspi3_addrs,
5452         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5453 };
5454
5455 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5456         {
5457                 .pa_start       = 0x480ba000,
5458                 .pa_end         = 0x480ba1ff,
5459                 .flags          = ADDR_TYPE_RT
5460         },
5461         { }
5462 };
5463
5464 /* l4_per -> mcspi4 */
5465 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5466         .master         = &omap44xx_l4_per_hwmod,
5467         .slave          = &omap44xx_mcspi4_hwmod,
5468         .clk            = "l4_div_ck",
5469         .addr           = omap44xx_mcspi4_addrs,
5470         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5471 };
5472
5473 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5474         {
5475                 .pa_start       = 0x4809c000,
5476                 .pa_end         = 0x4809c3ff,
5477                 .flags          = ADDR_TYPE_RT
5478         },
5479         { }
5480 };
5481
5482 /* l4_per -> mmc1 */
5483 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5484         .master         = &omap44xx_l4_per_hwmod,
5485         .slave          = &omap44xx_mmc1_hwmod,
5486         .clk            = "l4_div_ck",
5487         .addr           = omap44xx_mmc1_addrs,
5488         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5489 };
5490
5491 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5492         {
5493                 .pa_start       = 0x480b4000,
5494                 .pa_end         = 0x480b43ff,
5495                 .flags          = ADDR_TYPE_RT
5496         },
5497         { }
5498 };
5499
5500 /* l4_per -> mmc2 */
5501 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5502         .master         = &omap44xx_l4_per_hwmod,
5503         .slave          = &omap44xx_mmc2_hwmod,
5504         .clk            = "l4_div_ck",
5505         .addr           = omap44xx_mmc2_addrs,
5506         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5507 };
5508
5509 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5510         {
5511                 .pa_start       = 0x480ad000,
5512                 .pa_end         = 0x480ad3ff,
5513                 .flags          = ADDR_TYPE_RT
5514         },
5515         { }
5516 };
5517
5518 /* l4_per -> mmc3 */
5519 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5520         .master         = &omap44xx_l4_per_hwmod,
5521         .slave          = &omap44xx_mmc3_hwmod,
5522         .clk            = "l4_div_ck",
5523         .addr           = omap44xx_mmc3_addrs,
5524         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5525 };
5526
5527 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5528         {
5529                 .pa_start       = 0x480d1000,
5530                 .pa_end         = 0x480d13ff,
5531                 .flags          = ADDR_TYPE_RT
5532         },
5533         { }
5534 };
5535
5536 /* l4_per -> mmc4 */
5537 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5538         .master         = &omap44xx_l4_per_hwmod,
5539         .slave          = &omap44xx_mmc4_hwmod,
5540         .clk            = "l4_div_ck",
5541         .addr           = omap44xx_mmc4_addrs,
5542         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5543 };
5544
5545 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5546         {
5547                 .pa_start       = 0x480d5000,
5548                 .pa_end         = 0x480d53ff,
5549                 .flags          = ADDR_TYPE_RT
5550         },
5551         { }
5552 };
5553
5554 /* l4_per -> mmc5 */
5555 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5556         .master         = &omap44xx_l4_per_hwmod,
5557         .slave          = &omap44xx_mmc5_hwmod,
5558         .clk            = "l4_div_ck",
5559         .addr           = omap44xx_mmc5_addrs,
5560         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5561 };
5562
5563 /* l3_main_2 -> ocmc_ram */
5564 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5565         .master         = &omap44xx_l3_main_2_hwmod,
5566         .slave          = &omap44xx_ocmc_ram_hwmod,
5567         .clk            = "l3_div_ck",
5568         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5569 };
5570
5571 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
5572         {
5573                 .pa_start       = 0x4a0ad000,
5574                 .pa_end         = 0x4a0ad01f,
5575                 .flags          = ADDR_TYPE_RT
5576         },
5577         { }
5578 };
5579
5580 /* l4_cfg -> ocp2scp_usb_phy */
5581 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5582         .master         = &omap44xx_l4_cfg_hwmod,
5583         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5584         .clk            = "l4_div_ck",
5585         .addr           = omap44xx_ocp2scp_usb_phy_addrs,
5586         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5587 };
5588
5589 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5590         {
5591                 .pa_start       = 0x48243000,
5592                 .pa_end         = 0x48243fff,
5593                 .flags          = ADDR_TYPE_RT
5594         },
5595         { }
5596 };
5597
5598 /* mpu_private -> prcm_mpu */
5599 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5600         .master         = &omap44xx_mpu_private_hwmod,
5601         .slave          = &omap44xx_prcm_mpu_hwmod,
5602         .clk            = "l3_div_ck",
5603         .addr           = omap44xx_prcm_mpu_addrs,
5604         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5605 };
5606
5607 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5608         {
5609                 .pa_start       = 0x4a004000,
5610                 .pa_end         = 0x4a004fff,
5611                 .flags          = ADDR_TYPE_RT
5612         },
5613         { }
5614 };
5615
5616 /* l4_wkup -> cm_core_aon */
5617 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5618         .master         = &omap44xx_l4_wkup_hwmod,
5619         .slave          = &omap44xx_cm_core_aon_hwmod,
5620         .clk            = "l4_wkup_clk_mux_ck",
5621         .addr           = omap44xx_cm_core_aon_addrs,
5622         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5623 };
5624
5625 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5626         {
5627                 .pa_start       = 0x4a008000,
5628                 .pa_end         = 0x4a009fff,
5629                 .flags          = ADDR_TYPE_RT
5630         },
5631         { }
5632 };
5633
5634 /* l4_cfg -> cm_core */
5635 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5636         .master         = &omap44xx_l4_cfg_hwmod,
5637         .slave          = &omap44xx_cm_core_hwmod,
5638         .clk            = "l4_div_ck",
5639         .addr           = omap44xx_cm_core_addrs,
5640         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5641 };
5642
5643 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5644         {
5645                 .pa_start       = 0x4a306000,
5646                 .pa_end         = 0x4a307fff,
5647                 .flags          = ADDR_TYPE_RT
5648         },
5649         { }
5650 };
5651
5652 /* l4_wkup -> prm */
5653 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5654         .master         = &omap44xx_l4_wkup_hwmod,
5655         .slave          = &omap44xx_prm_hwmod,
5656         .clk            = "l4_wkup_clk_mux_ck",
5657         .addr           = omap44xx_prm_addrs,
5658         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5659 };
5660
5661 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5662         {
5663                 .pa_start       = 0x4a30a000,
5664                 .pa_end         = 0x4a30a7ff,
5665                 .flags          = ADDR_TYPE_RT
5666         },
5667         { }
5668 };
5669
5670 /* l4_wkup -> scrm */
5671 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5672         .master         = &omap44xx_l4_wkup_hwmod,
5673         .slave          = &omap44xx_scrm_hwmod,
5674         .clk            = "l4_wkup_clk_mux_ck",
5675         .addr           = omap44xx_scrm_addrs,
5676         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5677 };
5678
5679 /* l3_main_2 -> sl2if */
5680 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5681         .master         = &omap44xx_l3_main_2_hwmod,
5682         .slave          = &omap44xx_sl2if_hwmod,
5683         .clk            = "l3_div_ck",
5684         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5685 };
5686
5687 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5688         {
5689                 .pa_start       = 0x4012c000,
5690                 .pa_end         = 0x4012c3ff,
5691                 .flags          = ADDR_TYPE_RT
5692         },
5693         { }
5694 };
5695
5696 /* l4_abe -> slimbus1 */
5697 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5698         .master         = &omap44xx_l4_abe_hwmod,
5699         .slave          = &omap44xx_slimbus1_hwmod,
5700         .clk            = "ocp_abe_iclk",
5701         .addr           = omap44xx_slimbus1_addrs,
5702         .user           = OCP_USER_MPU,
5703 };
5704
5705 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5706         {
5707                 .pa_start       = 0x4902c000,
5708                 .pa_end         = 0x4902c3ff,
5709                 .flags          = ADDR_TYPE_RT
5710         },
5711         { }
5712 };
5713
5714 /* l4_abe -> slimbus1 (dma) */
5715 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5716         .master         = &omap44xx_l4_abe_hwmod,
5717         .slave          = &omap44xx_slimbus1_hwmod,
5718         .clk            = "ocp_abe_iclk",
5719         .addr           = omap44xx_slimbus1_dma_addrs,
5720         .user           = OCP_USER_SDMA,
5721 };
5722
5723 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5724         {
5725                 .pa_start       = 0x48076000,
5726                 .pa_end         = 0x480763ff,
5727                 .flags          = ADDR_TYPE_RT
5728         },
5729         { }
5730 };
5731
5732 /* l4_per -> slimbus2 */
5733 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5734         .master         = &omap44xx_l4_per_hwmod,
5735         .slave          = &omap44xx_slimbus2_hwmod,
5736         .clk            = "l4_div_ck",
5737         .addr           = omap44xx_slimbus2_addrs,
5738         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5739 };
5740
5741 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5742         {
5743                 .pa_start       = 0x4a0dd000,
5744                 .pa_end         = 0x4a0dd03f,
5745                 .flags          = ADDR_TYPE_RT
5746         },
5747         { }
5748 };
5749
5750 /* l4_cfg -> smartreflex_core */
5751 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5752         .master         = &omap44xx_l4_cfg_hwmod,
5753         .slave          = &omap44xx_smartreflex_core_hwmod,
5754         .clk            = "l4_div_ck",
5755         .addr           = omap44xx_smartreflex_core_addrs,
5756         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5757 };
5758
5759 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5760         {
5761                 .pa_start       = 0x4a0db000,
5762                 .pa_end         = 0x4a0db03f,
5763                 .flags          = ADDR_TYPE_RT
5764         },
5765         { }
5766 };
5767
5768 /* l4_cfg -> smartreflex_iva */
5769 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5770         .master         = &omap44xx_l4_cfg_hwmod,
5771         .slave          = &omap44xx_smartreflex_iva_hwmod,
5772         .clk            = "l4_div_ck",
5773         .addr           = omap44xx_smartreflex_iva_addrs,
5774         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5775 };
5776
5777 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5778         {
5779                 .pa_start       = 0x4a0d9000,
5780                 .pa_end         = 0x4a0d903f,
5781                 .flags          = ADDR_TYPE_RT
5782         },
5783         { }
5784 };
5785
5786 /* l4_cfg -> smartreflex_mpu */
5787 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5788         .master         = &omap44xx_l4_cfg_hwmod,
5789         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5790         .clk            = "l4_div_ck",
5791         .addr           = omap44xx_smartreflex_mpu_addrs,
5792         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5793 };
5794
5795 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5796         {
5797                 .pa_start       = 0x4a0f6000,
5798                 .pa_end         = 0x4a0f6fff,
5799                 .flags          = ADDR_TYPE_RT
5800         },
5801         { }
5802 };
5803
5804 /* l4_cfg -> spinlock */
5805 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5806         .master         = &omap44xx_l4_cfg_hwmod,
5807         .slave          = &omap44xx_spinlock_hwmod,
5808         .clk            = "l4_div_ck",
5809         .addr           = omap44xx_spinlock_addrs,
5810         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5811 };
5812
5813 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5814         {
5815                 .pa_start       = 0x4a318000,
5816                 .pa_end         = 0x4a31807f,
5817                 .flags          = ADDR_TYPE_RT
5818         },
5819         { }
5820 };
5821
5822 /* l4_wkup -> timer1 */
5823 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5824         .master         = &omap44xx_l4_wkup_hwmod,
5825         .slave          = &omap44xx_timer1_hwmod,
5826         .clk            = "l4_wkup_clk_mux_ck",
5827         .addr           = omap44xx_timer1_addrs,
5828         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5829 };
5830
5831 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5832         {
5833                 .pa_start       = 0x48032000,
5834                 .pa_end         = 0x4803207f,
5835                 .flags          = ADDR_TYPE_RT
5836         },
5837         { }
5838 };
5839
5840 /* l4_per -> timer2 */
5841 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5842         .master         = &omap44xx_l4_per_hwmod,
5843         .slave          = &omap44xx_timer2_hwmod,
5844         .clk            = "l4_div_ck",
5845         .addr           = omap44xx_timer2_addrs,
5846         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5847 };
5848
5849 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5850         {
5851                 .pa_start       = 0x48034000,
5852                 .pa_end         = 0x4803407f,
5853                 .flags          = ADDR_TYPE_RT
5854         },
5855         { }
5856 };
5857
5858 /* l4_per -> timer3 */
5859 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5860         .master         = &omap44xx_l4_per_hwmod,
5861         .slave          = &omap44xx_timer3_hwmod,
5862         .clk            = "l4_div_ck",
5863         .addr           = omap44xx_timer3_addrs,
5864         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5865 };
5866
5867 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5868         {
5869                 .pa_start       = 0x48036000,
5870                 .pa_end         = 0x4803607f,
5871                 .flags          = ADDR_TYPE_RT
5872         },
5873         { }
5874 };
5875
5876 /* l4_per -> timer4 */
5877 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5878         .master         = &omap44xx_l4_per_hwmod,
5879         .slave          = &omap44xx_timer4_hwmod,
5880         .clk            = "l4_div_ck",
5881         .addr           = omap44xx_timer4_addrs,
5882         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5883 };
5884
5885 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5886         {
5887                 .pa_start       = 0x40138000,
5888                 .pa_end         = 0x4013807f,
5889                 .flags          = ADDR_TYPE_RT
5890         },
5891         { }
5892 };
5893
5894 /* l4_abe -> timer5 */
5895 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5896         .master         = &omap44xx_l4_abe_hwmod,
5897         .slave          = &omap44xx_timer5_hwmod,
5898         .clk            = "ocp_abe_iclk",
5899         .addr           = omap44xx_timer5_addrs,
5900         .user           = OCP_USER_MPU,
5901 };
5902
5903 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5904         {
5905                 .pa_start       = 0x49038000,
5906                 .pa_end         = 0x4903807f,
5907                 .flags          = ADDR_TYPE_RT
5908         },
5909         { }
5910 };
5911
5912 /* l4_abe -> timer5 (dma) */
5913 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5914         .master         = &omap44xx_l4_abe_hwmod,
5915         .slave          = &omap44xx_timer5_hwmod,
5916         .clk            = "ocp_abe_iclk",
5917         .addr           = omap44xx_timer5_dma_addrs,
5918         .user           = OCP_USER_SDMA,
5919 };
5920
5921 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5922         {
5923                 .pa_start       = 0x4013a000,
5924                 .pa_end         = 0x4013a07f,
5925                 .flags          = ADDR_TYPE_RT
5926         },
5927         { }
5928 };
5929
5930 /* l4_abe -> timer6 */
5931 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5932         .master         = &omap44xx_l4_abe_hwmod,
5933         .slave          = &omap44xx_timer6_hwmod,
5934         .clk            = "ocp_abe_iclk",
5935         .addr           = omap44xx_timer6_addrs,
5936         .user           = OCP_USER_MPU,
5937 };
5938
5939 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5940         {
5941                 .pa_start       = 0x4903a000,
5942                 .pa_end         = 0x4903a07f,
5943                 .flags          = ADDR_TYPE_RT
5944         },
5945         { }
5946 };
5947
5948 /* l4_abe -> timer6 (dma) */
5949 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5950         .master         = &omap44xx_l4_abe_hwmod,
5951         .slave          = &omap44xx_timer6_hwmod,
5952         .clk            = "ocp_abe_iclk",
5953         .addr           = omap44xx_timer6_dma_addrs,
5954         .user           = OCP_USER_SDMA,
5955 };
5956
5957 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5958         {
5959                 .pa_start       = 0x4013c000,
5960                 .pa_end         = 0x4013c07f,
5961                 .flags          = ADDR_TYPE_RT
5962         },
5963         { }
5964 };
5965
5966 /* l4_abe -> timer7 */
5967 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5968         .master         = &omap44xx_l4_abe_hwmod,
5969         .slave          = &omap44xx_timer7_hwmod,
5970         .clk            = "ocp_abe_iclk",
5971         .addr           = omap44xx_timer7_addrs,
5972         .user           = OCP_USER_MPU,
5973 };
5974
5975 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5976         {
5977                 .pa_start       = 0x4903c000,
5978                 .pa_end         = 0x4903c07f,
5979                 .flags          = ADDR_TYPE_RT
5980         },
5981         { }
5982 };
5983
5984 /* l4_abe -> timer7 (dma) */
5985 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5986         .master         = &omap44xx_l4_abe_hwmod,
5987         .slave          = &omap44xx_timer7_hwmod,
5988         .clk            = "ocp_abe_iclk",
5989         .addr           = omap44xx_timer7_dma_addrs,
5990         .user           = OCP_USER_SDMA,
5991 };
5992
5993 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5994         {
5995                 .pa_start       = 0x4013e000,
5996                 .pa_end         = 0x4013e07f,
5997                 .flags          = ADDR_TYPE_RT
5998         },
5999         { }
6000 };
6001
6002 /* l4_abe -> timer8 */
6003 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
6004         .master         = &omap44xx_l4_abe_hwmod,
6005         .slave          = &omap44xx_timer8_hwmod,
6006         .clk            = "ocp_abe_iclk",
6007         .addr           = omap44xx_timer8_addrs,
6008         .user           = OCP_USER_MPU,
6009 };
6010
6011 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
6012         {
6013                 .pa_start       = 0x4903e000,
6014                 .pa_end         = 0x4903e07f,
6015                 .flags          = ADDR_TYPE_RT
6016         },
6017         { }
6018 };
6019
6020 /* l4_abe -> timer8 (dma) */
6021 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
6022         .master         = &omap44xx_l4_abe_hwmod,
6023         .slave          = &omap44xx_timer8_hwmod,
6024         .clk            = "ocp_abe_iclk",
6025         .addr           = omap44xx_timer8_dma_addrs,
6026         .user           = OCP_USER_SDMA,
6027 };
6028
6029 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
6030         {
6031                 .pa_start       = 0x4803e000,
6032                 .pa_end         = 0x4803e07f,
6033                 .flags          = ADDR_TYPE_RT
6034         },
6035         { }
6036 };
6037
6038 /* l4_per -> timer9 */
6039 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
6040         .master         = &omap44xx_l4_per_hwmod,
6041         .slave          = &omap44xx_timer9_hwmod,
6042         .clk            = "l4_div_ck",
6043         .addr           = omap44xx_timer9_addrs,
6044         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6045 };
6046
6047 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
6048         {
6049                 .pa_start       = 0x48086000,
6050                 .pa_end         = 0x4808607f,
6051                 .flags          = ADDR_TYPE_RT
6052         },
6053         { }
6054 };
6055
6056 /* l4_per -> timer10 */
6057 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
6058         .master         = &omap44xx_l4_per_hwmod,
6059         .slave          = &omap44xx_timer10_hwmod,
6060         .clk            = "l4_div_ck",
6061         .addr           = omap44xx_timer10_addrs,
6062         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6063 };
6064
6065 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
6066         {
6067                 .pa_start       = 0x48088000,
6068                 .pa_end         = 0x4808807f,
6069                 .flags          = ADDR_TYPE_RT
6070         },
6071         { }
6072 };
6073
6074 /* l4_per -> timer11 */
6075 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
6076         .master         = &omap44xx_l4_per_hwmod,
6077         .slave          = &omap44xx_timer11_hwmod,
6078         .clk            = "l4_div_ck",
6079         .addr           = omap44xx_timer11_addrs,
6080         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6081 };
6082
6083 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
6084         {
6085                 .pa_start       = 0x4806a000,
6086                 .pa_end         = 0x4806a0ff,
6087                 .flags          = ADDR_TYPE_RT
6088         },
6089         { }
6090 };
6091
6092 /* l4_per -> uart1 */
6093 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
6094         .master         = &omap44xx_l4_per_hwmod,
6095         .slave          = &omap44xx_uart1_hwmod,
6096         .clk            = "l4_div_ck",
6097         .addr           = omap44xx_uart1_addrs,
6098         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6099 };
6100
6101 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
6102         {
6103                 .pa_start       = 0x4806c000,
6104                 .pa_end         = 0x4806c0ff,
6105                 .flags          = ADDR_TYPE_RT
6106         },
6107         { }
6108 };
6109
6110 /* l4_per -> uart2 */
6111 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
6112         .master         = &omap44xx_l4_per_hwmod,
6113         .slave          = &omap44xx_uart2_hwmod,
6114         .clk            = "l4_div_ck",
6115         .addr           = omap44xx_uart2_addrs,
6116         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6117 };
6118
6119 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
6120         {
6121                 .pa_start       = 0x48020000,
6122                 .pa_end         = 0x480200ff,
6123                 .flags          = ADDR_TYPE_RT
6124         },
6125         { }
6126 };
6127
6128 /* l4_per -> uart3 */
6129 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
6130         .master         = &omap44xx_l4_per_hwmod,
6131         .slave          = &omap44xx_uart3_hwmod,
6132         .clk            = "l4_div_ck",
6133         .addr           = omap44xx_uart3_addrs,
6134         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6135 };
6136
6137 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
6138         {
6139                 .pa_start       = 0x4806e000,
6140                 .pa_end         = 0x4806e0ff,
6141                 .flags          = ADDR_TYPE_RT
6142         },
6143         { }
6144 };
6145
6146 /* l4_per -> uart4 */
6147 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
6148         .master         = &omap44xx_l4_per_hwmod,
6149         .slave          = &omap44xx_uart4_hwmod,
6150         .clk            = "l4_div_ck",
6151         .addr           = omap44xx_uart4_addrs,
6152         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6153 };
6154
6155 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
6156         {
6157                 .pa_start       = 0x4a0a9000,
6158                 .pa_end         = 0x4a0a93ff,
6159                 .flags          = ADDR_TYPE_RT
6160         },
6161         { }
6162 };
6163
6164 /* l4_cfg -> usb_host_fs */
6165 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
6166         .master         = &omap44xx_l4_cfg_hwmod,
6167         .slave          = &omap44xx_usb_host_fs_hwmod,
6168         .clk            = "l4_div_ck",
6169         .addr           = omap44xx_usb_host_fs_addrs,
6170         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6171 };
6172
6173 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
6174         {
6175                 .name           = "uhh",
6176                 .pa_start       = 0x4a064000,
6177                 .pa_end         = 0x4a0647ff,
6178                 .flags          = ADDR_TYPE_RT
6179         },
6180         {
6181                 .name           = "ohci",
6182                 .pa_start       = 0x4a064800,
6183                 .pa_end         = 0x4a064bff,
6184         },
6185         {
6186                 .name           = "ehci",
6187                 .pa_start       = 0x4a064c00,
6188                 .pa_end         = 0x4a064fff,
6189         },
6190         {}
6191 };
6192
6193 /* l4_cfg -> usb_host_hs */
6194 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
6195         .master         = &omap44xx_l4_cfg_hwmod,
6196         .slave          = &omap44xx_usb_host_hs_hwmod,
6197         .clk            = "l4_div_ck",
6198         .addr           = omap44xx_usb_host_hs_addrs,
6199         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6200 };
6201
6202 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
6203         {
6204                 .pa_start       = 0x4a0ab000,
6205                 .pa_end         = 0x4a0ab7ff,
6206                 .flags          = ADDR_TYPE_RT
6207         },
6208         { }
6209 };
6210
6211 /* l4_cfg -> usb_otg_hs */
6212 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
6213         .master         = &omap44xx_l4_cfg_hwmod,
6214         .slave          = &omap44xx_usb_otg_hs_hwmod,
6215         .clk            = "l4_div_ck",
6216         .addr           = omap44xx_usb_otg_hs_addrs,
6217         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6218 };
6219
6220 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
6221         {
6222                 .name           = "tll",
6223                 .pa_start       = 0x4a062000,
6224                 .pa_end         = 0x4a063fff,
6225                 .flags          = ADDR_TYPE_RT
6226         },
6227         {}
6228 };
6229
6230 /* l4_cfg -> usb_tll_hs */
6231 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
6232         .master         = &omap44xx_l4_cfg_hwmod,
6233         .slave          = &omap44xx_usb_tll_hs_hwmod,
6234         .clk            = "l4_div_ck",
6235         .addr           = omap44xx_usb_tll_hs_addrs,
6236         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6237 };
6238
6239 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
6240         {
6241                 .pa_start       = 0x4a314000,
6242                 .pa_end         = 0x4a31407f,
6243                 .flags          = ADDR_TYPE_RT
6244         },
6245         { }
6246 };
6247
6248 /* l4_wkup -> wd_timer2 */
6249 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
6250         .master         = &omap44xx_l4_wkup_hwmod,
6251         .slave          = &omap44xx_wd_timer2_hwmod,
6252         .clk            = "l4_wkup_clk_mux_ck",
6253         .addr           = omap44xx_wd_timer2_addrs,
6254         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6255 };
6256
6257 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
6258         {
6259                 .pa_start       = 0x40130000,
6260                 .pa_end         = 0x4013007f,
6261                 .flags          = ADDR_TYPE_RT
6262         },
6263         { }
6264 };
6265
6266 /* l4_abe -> wd_timer3 */
6267 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
6268         .master         = &omap44xx_l4_abe_hwmod,
6269         .slave          = &omap44xx_wd_timer3_hwmod,
6270         .clk            = "ocp_abe_iclk",
6271         .addr           = omap44xx_wd_timer3_addrs,
6272         .user           = OCP_USER_MPU,
6273 };
6274
6275 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
6276         {
6277                 .pa_start       = 0x49030000,
6278                 .pa_end         = 0x4903007f,
6279                 .flags          = ADDR_TYPE_RT
6280         },
6281         { }
6282 };
6283
6284 /* l4_abe -> wd_timer3 (dma) */
6285 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6286         .master         = &omap44xx_l4_abe_hwmod,
6287         .slave          = &omap44xx_wd_timer3_hwmod,
6288         .clk            = "ocp_abe_iclk",
6289         .addr           = omap44xx_wd_timer3_dma_addrs,
6290         .user           = OCP_USER_SDMA,
6291 };
6292
6293 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6294         &omap44xx_c2c__c2c_target_fw,
6295         &omap44xx_l4_cfg__c2c_target_fw,
6296         &omap44xx_l3_main_1__dmm,
6297         &omap44xx_mpu__dmm,
6298         &omap44xx_c2c__emif_fw,
6299         &omap44xx_dmm__emif_fw,
6300         &omap44xx_l4_cfg__emif_fw,
6301         &omap44xx_iva__l3_instr,
6302         &omap44xx_l3_main_3__l3_instr,
6303         &omap44xx_ocp_wp_noc__l3_instr,
6304         &omap44xx_dsp__l3_main_1,
6305         &omap44xx_dss__l3_main_1,
6306         &omap44xx_l3_main_2__l3_main_1,
6307         &omap44xx_l4_cfg__l3_main_1,
6308         &omap44xx_mmc1__l3_main_1,
6309         &omap44xx_mmc2__l3_main_1,
6310         &omap44xx_mpu__l3_main_1,
6311         &omap44xx_c2c_target_fw__l3_main_2,
6312         &omap44xx_debugss__l3_main_2,
6313         &omap44xx_dma_system__l3_main_2,
6314         &omap44xx_fdif__l3_main_2,
6315         &omap44xx_gpu__l3_main_2,
6316         &omap44xx_hsi__l3_main_2,
6317         &omap44xx_ipu__l3_main_2,
6318         &omap44xx_iss__l3_main_2,
6319         &omap44xx_iva__l3_main_2,
6320         &omap44xx_l3_main_1__l3_main_2,
6321         &omap44xx_l4_cfg__l3_main_2,
6322         /* &omap44xx_usb_host_fs__l3_main_2, */
6323         &omap44xx_usb_host_hs__l3_main_2,
6324         &omap44xx_usb_otg_hs__l3_main_2,
6325         &omap44xx_l3_main_1__l3_main_3,
6326         &omap44xx_l3_main_2__l3_main_3,
6327         &omap44xx_l4_cfg__l3_main_3,
6328         &omap44xx_aess__l4_abe,
6329         &omap44xx_dsp__l4_abe,
6330         &omap44xx_l3_main_1__l4_abe,
6331         &omap44xx_mpu__l4_abe,
6332         &omap44xx_l3_main_1__l4_cfg,
6333         &omap44xx_l3_main_2__l4_per,
6334         &omap44xx_l4_cfg__l4_wkup,
6335         &omap44xx_mpu__mpu_private,
6336         &omap44xx_l4_cfg__ocp_wp_noc,
6337         &omap44xx_l4_abe__aess,
6338         &omap44xx_l4_abe__aess_dma,
6339         &omap44xx_l3_main_2__c2c,
6340         &omap44xx_l4_wkup__counter_32k,
6341         &omap44xx_l4_cfg__ctrl_module_core,
6342         &omap44xx_l4_cfg__ctrl_module_pad_core,
6343         &omap44xx_l4_wkup__ctrl_module_wkup,
6344         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6345         &omap44xx_l3_instr__debugss,
6346         &omap44xx_l4_cfg__dma_system,
6347         &omap44xx_l4_abe__dmic,
6348         &omap44xx_l4_abe__dmic_dma,
6349         &omap44xx_dsp__iva,
6350         /* &omap44xx_dsp__sl2if, */
6351         &omap44xx_l4_cfg__dsp,
6352         &omap44xx_l3_main_2__dss,
6353         &omap44xx_l4_per__dss,
6354         &omap44xx_l3_main_2__dss_dispc,
6355         &omap44xx_l4_per__dss_dispc,
6356         &omap44xx_l3_main_2__dss_dsi1,
6357         &omap44xx_l4_per__dss_dsi1,
6358         &omap44xx_l3_main_2__dss_dsi2,
6359         &omap44xx_l4_per__dss_dsi2,
6360         &omap44xx_l3_main_2__dss_hdmi,
6361         &omap44xx_l4_per__dss_hdmi,
6362         &omap44xx_l3_main_2__dss_rfbi,
6363         &omap44xx_l4_per__dss_rfbi,
6364         &omap44xx_l3_main_2__dss_venc,
6365         &omap44xx_l4_per__dss_venc,
6366         &omap44xx_l4_per__elm,
6367         &omap44xx_emif_fw__emif1,
6368         &omap44xx_emif_fw__emif2,
6369         &omap44xx_l4_cfg__fdif,
6370         &omap44xx_l4_wkup__gpio1,
6371         &omap44xx_l4_per__gpio2,
6372         &omap44xx_l4_per__gpio3,
6373         &omap44xx_l4_per__gpio4,
6374         &omap44xx_l4_per__gpio5,
6375         &omap44xx_l4_per__gpio6,
6376         &omap44xx_l3_main_2__gpmc,
6377         &omap44xx_l3_main_2__gpu,
6378         &omap44xx_l4_per__hdq1w,
6379         &omap44xx_l4_cfg__hsi,
6380         &omap44xx_l4_per__i2c1,
6381         &omap44xx_l4_per__i2c2,
6382         &omap44xx_l4_per__i2c3,
6383         &omap44xx_l4_per__i2c4,
6384         &omap44xx_l3_main_2__ipu,
6385         &omap44xx_l3_main_2__iss,
6386         /* &omap44xx_iva__sl2if, */
6387         &omap44xx_l3_main_2__iva,
6388         &omap44xx_l4_wkup__kbd,
6389         &omap44xx_l4_cfg__mailbox,
6390         &omap44xx_l4_abe__mcasp,
6391         &omap44xx_l4_abe__mcasp_dma,
6392         &omap44xx_l4_abe__mcbsp1,
6393         &omap44xx_l4_abe__mcbsp1_dma,
6394         &omap44xx_l4_abe__mcbsp2,
6395         &omap44xx_l4_abe__mcbsp2_dma,
6396         &omap44xx_l4_abe__mcbsp3,
6397         &omap44xx_l4_abe__mcbsp3_dma,
6398         &omap44xx_l4_per__mcbsp4,
6399         &omap44xx_l4_abe__mcpdm,
6400         &omap44xx_l4_abe__mcpdm_dma,
6401         &omap44xx_l4_per__mcspi1,
6402         &omap44xx_l4_per__mcspi2,
6403         &omap44xx_l4_per__mcspi3,
6404         &omap44xx_l4_per__mcspi4,
6405         &omap44xx_l4_per__mmc1,
6406         &omap44xx_l4_per__mmc2,
6407         &omap44xx_l4_per__mmc3,
6408         &omap44xx_l4_per__mmc4,
6409         &omap44xx_l4_per__mmc5,
6410         &omap44xx_l3_main_2__mmu_ipu,
6411         &omap44xx_l4_cfg__mmu_dsp,
6412         &omap44xx_l3_main_2__ocmc_ram,
6413         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6414         &omap44xx_mpu_private__prcm_mpu,
6415         &omap44xx_l4_wkup__cm_core_aon,
6416         &omap44xx_l4_cfg__cm_core,
6417         &omap44xx_l4_wkup__prm,
6418         &omap44xx_l4_wkup__scrm,
6419         /* &omap44xx_l3_main_2__sl2if, */
6420         &omap44xx_l4_abe__slimbus1,
6421         &omap44xx_l4_abe__slimbus1_dma,
6422         &omap44xx_l4_per__slimbus2,
6423         &omap44xx_l4_cfg__smartreflex_core,
6424         &omap44xx_l4_cfg__smartreflex_iva,
6425         &omap44xx_l4_cfg__smartreflex_mpu,
6426         &omap44xx_l4_cfg__spinlock,
6427         &omap44xx_l4_wkup__timer1,
6428         &omap44xx_l4_per__timer2,
6429         &omap44xx_l4_per__timer3,
6430         &omap44xx_l4_per__timer4,
6431         &omap44xx_l4_abe__timer5,
6432         &omap44xx_l4_abe__timer5_dma,
6433         &omap44xx_l4_abe__timer6,
6434         &omap44xx_l4_abe__timer6_dma,
6435         &omap44xx_l4_abe__timer7,
6436         &omap44xx_l4_abe__timer7_dma,
6437         &omap44xx_l4_abe__timer8,
6438         &omap44xx_l4_abe__timer8_dma,
6439         &omap44xx_l4_per__timer9,
6440         &omap44xx_l4_per__timer10,
6441         &omap44xx_l4_per__timer11,
6442         &omap44xx_l4_per__uart1,
6443         &omap44xx_l4_per__uart2,
6444         &omap44xx_l4_per__uart3,
6445         &omap44xx_l4_per__uart4,
6446         /* &omap44xx_l4_cfg__usb_host_fs, */
6447         &omap44xx_l4_cfg__usb_host_hs,
6448         &omap44xx_l4_cfg__usb_otg_hs,
6449         &omap44xx_l4_cfg__usb_tll_hs,
6450         &omap44xx_l4_wkup__wd_timer2,
6451         &omap44xx_l4_abe__wd_timer3,
6452         &omap44xx_l4_abe__wd_timer3_dma,
6453         NULL,
6454 };
6455
6456 int __init omap44xx_hwmod_init(void)
6457 {
6458         omap_hwmod_init();
6459         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6460 }
6461