arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22 #include <linux/platform_data/gpio-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/platform_data/omap_ocp2scp.h>
  25 #include <linux/i2c-omap.h>
  26
  27 #include <linux/omap-dma.h>
  28
  29 #include <linux/platform_data/spi-omap2-mcspi.h>
  30 #include <linux/platform_data/asoc-ti-mcbsp.h>
  31 #include <linux/platform_data/iommu-omap.h>
  32 #include <plat/dmtimer.h>
  33
  34 #include "omap_hwmod.h"
  35 #include "omap_hwmod_common_data.h"
  36 #include "cm1_44xx.h"
  37 #include "cm2_44xx.h"
  38 #include "prm44xx.h"
  39 #include "prm-regbits-44xx.h"
  40 #include "i2c.h"
  41 #include "mmc.h"
  42 #include "wd_timer.h"
  43
  44 /* Base offset for all OMAP4 interrupts external to MPUSS */
  45 #define OMAP44XX_IRQ_GIC_START  32
  46
  47 /* Base offset for all OMAP4 dma requests */
  48 #define OMAP44XX_DMA_REQ_START  1
  49
  50 /*
  51  * IP blocks
  52  */
  53
  54 /*
  55  * 'c2c_target_fw' class
  56  * instance(s): c2c_target_fw
  57  */
  58 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  59         .name   = "c2c_target_fw",
  60 };
  61
  62 /* c2c_target_fw */
  63 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  64         .name           = "c2c_target_fw",
  65         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  66         .clkdm_name     = "d2d_clkdm",
  67         .prcm = {
  68                 .omap4 = {
  69                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  70                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  71                 },
  72         },
  73 };
  74
  75 /*
  76  * 'dmm' class
  77  * instance(s): dmm
  78  */
  79 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  80         .name   = "dmm",
  81 };
  82
  83 /* dmm */
  84 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  85         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  86         { .irq = -1 }
  87 };
  88
  89 static struct omap_hwmod omap44xx_dmm_hwmod = {
  90         .name           = "dmm",
  91         .class          = &omap44xx_dmm_hwmod_class,
  92         .clkdm_name     = "l3_emif_clkdm",
  93         .mpu_irqs       = omap44xx_dmm_irqs,
  94         .prcm = {
  95                 .omap4 = {
  96                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  97                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  98                 },
  99         },
 100 };
 101
 102 /*
 103  * 'emif_fw' class
 104  * instance(s): emif_fw
 105  */
 106 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 107         .name   = "emif_fw",
 108 };
 109
 110 /* emif_fw */
 111 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 112         .name           = "emif_fw",
 113         .class          = &omap44xx_emif_fw_hwmod_class,
 114         .clkdm_name     = "l3_emif_clkdm",
 115         .prcm = {
 116                 .omap4 = {
 117                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 118                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 119                 },
 120         },
 121 };
 122
 123 /*
 124  * 'l3' class
 125  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 126  */
 127 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 128         .name   = "l3",
 129 };
 130
 131 /* l3_instr */
 132 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 133         .name           = "l3_instr",
 134         .class          = &omap44xx_l3_hwmod_class,
 135         .clkdm_name     = "l3_instr_clkdm",
 136         .prcm = {
 137                 .omap4 = {
 138                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 139                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 140                         .modulemode   = MODULEMODE_HWCTRL,
 141                 },
 142         },
 143 };
 144
 145 /* l3_main_1 */
 146 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 147         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 148         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 149         { .irq = -1 }
 150 };
 151
 152 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 153         .name           = "l3_main_1",
 154         .class          = &omap44xx_l3_hwmod_class,
 155         .clkdm_name     = "l3_1_clkdm",
 156         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 157         .prcm = {
 158                 .omap4 = {
 159                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 160                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 161                 },
 162         },
 163 };
 164
 165 /* l3_main_2 */
 166 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 167         .name           = "l3_main_2",
 168         .class          = &omap44xx_l3_hwmod_class,
 169         .clkdm_name     = "l3_2_clkdm",
 170         .prcm = {
 171                 .omap4 = {
 172                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 173                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 174                 },
 175         },
 176 };
 177
 178 /* l3_main_3 */
 179 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 180         .name           = "l3_main_3",
 181         .class          = &omap44xx_l3_hwmod_class,
 182         .clkdm_name     = "l3_instr_clkdm",
 183         .prcm = {
 184                 .omap4 = {
 185                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 186                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 187                         .modulemode   = MODULEMODE_HWCTRL,
 188                 },
 189         },
 190 };
 191
 192 /*
 193  * 'l4' class
 194  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 195  */
 196 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 197         .name   = "l4",
 198 };
 199
 200 /* l4_abe */
 201 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 202         .name           = "l4_abe",
 203         .class          = &omap44xx_l4_hwmod_class,
 204         .clkdm_name     = "abe_clkdm",
 205         .prcm = {
 206                 .omap4 = {
 207                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 208                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 209                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 210                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 211                 },
 212         },
 213 };
 214
 215 /* l4_cfg */
 216 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 217         .name           = "l4_cfg",
 218         .class          = &omap44xx_l4_hwmod_class,
 219         .clkdm_name     = "l4_cfg_clkdm",
 220         .prcm = {
 221                 .omap4 = {
 222                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 223                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 224                 },
 225         },
 226 };
 227
 228 /* l4_per */
 229 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 230         .name           = "l4_per",
 231         .class          = &omap44xx_l4_hwmod_class,
 232         .clkdm_name     = "l4_per_clkdm",
 233         .prcm = {
 234                 .omap4 = {
 235                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 236                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 237                 },
 238         },
 239 };
 240
 241 /* l4_wkup */
 242 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 243         .name           = "l4_wkup",
 244         .class          = &omap44xx_l4_hwmod_class,
 245         .clkdm_name     = "l4_wkup_clkdm",
 246         .prcm = {
 247                 .omap4 = {
 248                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 249                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 250                 },
 251         },
 252 };
 253
 254 /*
 255  * 'mpu_bus' class
 256  * instance(s): mpu_private
 257  */
 258 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 259         .name   = "mpu_bus",
 260 };
 261
 262 /* mpu_private */
 263 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 264         .name           = "mpu_private",
 265         .class          = &omap44xx_mpu_bus_hwmod_class,
 266         .clkdm_name     = "mpuss_clkdm",
 267         .prcm = {
 268                 .omap4 = {
 269                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 270                 },
 271         },
 272 };
 273
 274 /*
 275  * 'ocp_wp_noc' class
 276  * instance(s): ocp_wp_noc
 277  */
 278 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 279         .name   = "ocp_wp_noc",
 280 };
 281
 282 /* ocp_wp_noc */
 283 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 284         .name           = "ocp_wp_noc",
 285         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 286         .clkdm_name     = "l3_instr_clkdm",
 287         .prcm = {
 288                 .omap4 = {
 289                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 290                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 291                         .modulemode   = MODULEMODE_HWCTRL,
 292                 },
 293         },
 294 };
 295
 296 /*
 297  * Modules omap_hwmod structures
 298  *
 299  * The following IPs are excluded for the moment because:
 300  * - They do not need an explicit SW control using omap_hwmod API.
 301  * - They still need to be validated with the driver
 302  *   properly adapted to omap_hwmod / omap_device
 303  *
 304  * usim
 305  */
 306
 307 /*
 308  * 'aess' class
 309  * audio engine sub system
 310  */
 311
 312 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 313         .rev_offs       = 0x0000,
 314         .sysc_offs      = 0x0010,
 315         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 316         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 317                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 318                            MSTANDBY_SMART_WKUP),
 319         .sysc_fields    = &omap_hwmod_sysc_type2,
 320 };
 321
 322 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 323         .name   = "aess",
 324         .sysc   = &omap44xx_aess_sysc,
 325         .enable_preprogram = omap_hwmod_aess_preprogram,
 326 };
 327
 328 /* aess */
 329 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 330         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 331         { .irq = -1 }
 332 };
 333
 334 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 335         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 336         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 337         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 338         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 339         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 340         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 341         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 342         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 343         { .dma_req = -1 }
 344 };
 345
 346 static struct omap_hwmod omap44xx_aess_hwmod = {
 347         .name           = "aess",
 348         .class          = &omap44xx_aess_hwmod_class,
 349         .clkdm_name     = "abe_clkdm",
 350         .mpu_irqs       = omap44xx_aess_irqs,
 351         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 352         .main_clk       = "aess_fclk",
 353         .prcm = {
 354                 .omap4 = {
 355                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 356                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 357                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 358                         .modulemode   = MODULEMODE_SWCTRL,
 359                 },
 360         },
 361 };
 362
 363 /*
 364  * 'c2c' class
 365  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 366  * soc
 367  */
 368
 369 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 370         .name   = "c2c",
 371 };
 372
 373 /* c2c */
 374 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 375         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 376         { .irq = -1 }
 377 };
 378
 379 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 380         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 381         { .dma_req = -1 }
 382 };
 383
 384 static struct omap_hwmod omap44xx_c2c_hwmod = {
 385         .name           = "c2c",
 386         .class          = &omap44xx_c2c_hwmod_class,
 387         .clkdm_name     = "d2d_clkdm",
 388         .mpu_irqs       = omap44xx_c2c_irqs,
 389         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 390         .prcm = {
 391                 .omap4 = {
 392                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 393                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 394                 },
 395         },
 396 };
 397
 398 /*
 399  * 'counter' class
 400  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 401  */
 402
 403 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 404         .rev_offs       = 0x0000,
 405         .sysc_offs      = 0x0004,
 406         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 407         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 408         .sysc_fields    = &omap_hwmod_sysc_type1,
 409 };
 410
 411 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 412         .name   = "counter",
 413         .sysc   = &omap44xx_counter_sysc,
 414 };
 415
 416 /* counter_32k */
 417 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 418         .name           = "counter_32k",
 419         .class          = &omap44xx_counter_hwmod_class,
 420         .clkdm_name     = "l4_wkup_clkdm",
 421         .flags          = HWMOD_SWSUP_SIDLE,
 422         .main_clk       = "sys_32k_ck",
 423         .prcm = {
 424                 .omap4 = {
 425                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 426                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 427                 },
 428         },
 429 };
 430
 431 /*
 432  * 'ctrl_module' class
 433  * attila core control module + core pad control module + wkup pad control
 434  * module + attila wkup control module
 435  */
 436
 437 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 438         .rev_offs       = 0x0000,
 439         .sysc_offs      = 0x0010,
 440         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 441         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 442                            SIDLE_SMART_WKUP),
 443         .sysc_fields    = &omap_hwmod_sysc_type2,
 444 };
 445
 446 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 447         .name   = "ctrl_module",
 448         .sysc   = &omap44xx_ctrl_module_sysc,
 449 };
 450
 451 /* ctrl_module_core */
 452 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 453         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 454         { .irq = -1 }
 455 };
 456
 457 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 458         .name           = "ctrl_module_core",
 459         .class          = &omap44xx_ctrl_module_hwmod_class,
 460         .clkdm_name     = "l4_cfg_clkdm",
 461         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 462         .prcm = {
 463                 .omap4 = {
 464                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 465                 },
 466         },
 467 };
 468
 469 /* ctrl_module_pad_core */
 470 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 471         .name           = "ctrl_module_pad_core",
 472         .class          = &omap44xx_ctrl_module_hwmod_class,
 473         .clkdm_name     = "l4_cfg_clkdm",
 474         .prcm = {
 475                 .omap4 = {
 476                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 477                 },
 478         },
 479 };
 480
 481 /* ctrl_module_wkup */
 482 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 483         .name           = "ctrl_module_wkup",
 484         .class          = &omap44xx_ctrl_module_hwmod_class,
 485         .clkdm_name     = "l4_wkup_clkdm",
 486         .prcm = {
 487                 .omap4 = {
 488                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 489                 },
 490         },
 491 };
 492
 493 /* ctrl_module_pad_wkup */
 494 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 495         .name           = "ctrl_module_pad_wkup",
 496         .class          = &omap44xx_ctrl_module_hwmod_class,
 497         .clkdm_name     = "l4_wkup_clkdm",
 498         .prcm = {
 499                 .omap4 = {
 500                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 501                 },
 502         },
 503 };
 504
 505 /*
 506  * 'debugss' class
 507  * debug and emulation sub system
 508  */
 509
 510 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 511         .name   = "debugss",
 512 };
 513
 514 /* debugss */
 515 static struct omap_hwmod omap44xx_debugss_hwmod = {
 516         .name           = "debugss",
 517         .class          = &omap44xx_debugss_hwmod_class,
 518         .clkdm_name     = "emu_sys_clkdm",
 519         .main_clk       = "trace_clk_div_ck",
 520         .prcm = {
 521                 .omap4 = {
 522                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 523                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 524                 },
 525         },
 526 };
 527
 528 /*
 529  * 'dma' class
 530  * dma controller for data exchange between memory to memory (i.e. internal or
 531  * external memory) and gp peripherals to memory or memory to gp peripherals
 532  */
 533
 534 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 535         .rev_offs       = 0x0000,
 536         .sysc_offs      = 0x002c,
 537         .syss_offs      = 0x0028,
 538         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 539                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 540                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 541                            SYSS_HAS_RESET_STATUS),
 542         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 543                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 544         .sysc_fields    = &omap_hwmod_sysc_type1,
 545 };
 546
 547 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 548         .name   = "dma",
 549         .sysc   = &omap44xx_dma_sysc,
 550 };
 551
 552 /* dma dev_attr */
 553 static struct omap_dma_dev_attr dma_dev_attr = {
 554         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 555                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 556         .lch_count      = 32,
 557 };
 558
 559 /* dma_system */
 560 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 561         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 562         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 563         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 564         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 565         { .irq = -1 }
 566 };
 567
 568 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 569         .name           = "dma_system",
 570         .class          = &omap44xx_dma_hwmod_class,
 571         .clkdm_name     = "l3_dma_clkdm",
 572         .mpu_irqs       = omap44xx_dma_system_irqs,
 573         .main_clk       = "l3_div_ck",
 574         .prcm = {
 575                 .omap4 = {
 576                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 577                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 578                 },
 579         },
 580         .dev_attr       = &dma_dev_attr,
 581 };
 582
 583 /*
 584  * 'dmic' class
 585  * digital microphone controller
 586  */
 587
 588 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 589         .rev_offs       = 0x0000,
 590         .sysc_offs      = 0x0010,
 591         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 592                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 593         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 594                            SIDLE_SMART_WKUP),
 595         .sysc_fields    = &omap_hwmod_sysc_type2,
 596 };
 597
 598 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 599         .name   = "dmic",
 600         .sysc   = &omap44xx_dmic_sysc,
 601 };
 602
 603 /* dmic */
 604 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 605         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 606         { .irq = -1 }
 607 };
 608
 609 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 610         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 611         { .dma_req = -1 }
 612 };
 613
 614 static struct omap_hwmod omap44xx_dmic_hwmod = {
 615         .name           = "dmic",
 616         .class          = &omap44xx_dmic_hwmod_class,
 617         .clkdm_name     = "abe_clkdm",
 618         .mpu_irqs       = omap44xx_dmic_irqs,
 619         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 620         .main_clk       = "func_dmic_abe_gfclk",
 621         .prcm = {
 622                 .omap4 = {
 623                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 624                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 625                         .modulemode   = MODULEMODE_SWCTRL,
 626                 },
 627         },
 628 };
 629
 630 /*
 631  * 'dsp' class
 632  * dsp sub-system
 633  */
 634
 635 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 636         .name   = "dsp",
 637 };
 638
 639 /* dsp */
 640 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 641         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 642         { .irq = -1 }
 643 };
 644
 645 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 646         { .name = "dsp", .rst_shift = 0 },
 647 };
 648
 649 static struct omap_hwmod omap44xx_dsp_hwmod = {
 650         .name           = "dsp",
 651         .class          = &omap44xx_dsp_hwmod_class,
 652         .clkdm_name     = "tesla_clkdm",
 653         .mpu_irqs       = omap44xx_dsp_irqs,
 654         .rst_lines      = omap44xx_dsp_resets,
 655         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 656         .main_clk       = "dpll_iva_m4x2_ck",
 657         .prcm = {
 658                 .omap4 = {
 659                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 660                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 661                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 662                         .modulemode   = MODULEMODE_HWCTRL,
 663                 },
 664         },
 665 };
 666
 667 /*
 668  * 'dss' class
 669  * display sub-system
 670  */
 671
 672 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 673         .rev_offs       = 0x0000,
 674         .syss_offs      = 0x0014,
 675         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 676 };
 677
 678 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 679         .name   = "dss",
 680         .sysc   = &omap44xx_dss_sysc,
 681         .reset  = omap_dss_reset,
 682 };
 683
 684 /* dss */
 685 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 686         { .role = "sys_clk", .clk = "dss_sys_clk" },
 687         { .role = "tv_clk", .clk = "dss_tv_clk" },
 688         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 689 };
 690
 691 static struct omap_hwmod omap44xx_dss_hwmod = {
 692         .name           = "dss_core",
 693         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 694         .class          = &omap44xx_dss_hwmod_class,
 695         .clkdm_name     = "l3_dss_clkdm",
 696         .main_clk       = "dss_dss_clk",
 697         .prcm = {
 698                 .omap4 = {
 699                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 700                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 701                 },
 702         },
 703         .opt_clks       = dss_opt_clks,
 704         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 705 };
 706
 707 /*
 708  * 'dispc' class
 709  * display controller
 710  */
 711
 712 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 713         .rev_offs       = 0x0000,
 714         .sysc_offs      = 0x0010,
 715         .syss_offs      = 0x0014,
 716         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 717                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 718                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 719                            SYSS_HAS_RESET_STATUS),
 720         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 721                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 722         .sysc_fields    = &omap_hwmod_sysc_type1,
 723 };
 724
 725 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 726         .name   = "dispc",
 727         .sysc   = &omap44xx_dispc_sysc,
 728 };
 729
 730 /* dss_dispc */
 731 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 732         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 733         { .irq = -1 }
 734 };
 735
 736 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 737         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 738         { .dma_req = -1 }
 739 };
 740
 741 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 742         .manager_count          = 3,
 743         .has_framedonetv_irq    = 1
 744 };
 745
 746 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 747         .name           = "dss_dispc",
 748         .class          = &omap44xx_dispc_hwmod_class,
 749         .clkdm_name     = "l3_dss_clkdm",
 750         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 751         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 752         .main_clk       = "dss_dss_clk",
 753         .prcm = {
 754                 .omap4 = {
 755                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 756                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 757                 },
 758         },
 759         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 760 };
 761
 762 /*
 763  * 'dsi' class
 764  * display serial interface controller
 765  */
 766
 767 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 768         .rev_offs       = 0x0000,
 769         .sysc_offs      = 0x0010,
 770         .syss_offs      = 0x0014,
 771         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 772                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 773                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 774         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 775         .sysc_fields    = &omap_hwmod_sysc_type1,
 776 };
 777
 778 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 779         .name   = "dsi",
 780         .sysc   = &omap44xx_dsi_sysc,
 781 };
 782
 783 /* dss_dsi1 */
 784 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 785         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 786         { .irq = -1 }
 787 };
 788
 789 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 790         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 791         { .dma_req = -1 }
 792 };
 793
 794 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 795         { .role = "sys_clk", .clk = "dss_sys_clk" },
 796 };
 797
 798 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 799         .name           = "dss_dsi1",
 800         .class          = &omap44xx_dsi_hwmod_class,
 801         .clkdm_name     = "l3_dss_clkdm",
 802         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 803         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 804         .main_clk       = "dss_dss_clk",
 805         .prcm = {
 806                 .omap4 = {
 807                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 808                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 809                 },
 810         },
 811         .opt_clks       = dss_dsi1_opt_clks,
 812         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 813 };
 814
 815 /* dss_dsi2 */
 816 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 817         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 818         { .irq = -1 }
 819 };
 820
 821 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 822         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 823         { .dma_req = -1 }
 824 };
 825
 826 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 827         { .role = "sys_clk", .clk = "dss_sys_clk" },
 828 };
 829
 830 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 831         .name           = "dss_dsi2",
 832         .class          = &omap44xx_dsi_hwmod_class,
 833         .clkdm_name     = "l3_dss_clkdm",
 834         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 835         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 836         .main_clk       = "dss_dss_clk",
 837         .prcm = {
 838                 .omap4 = {
 839                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 840                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 841                 },
 842         },
 843         .opt_clks       = dss_dsi2_opt_clks,
 844         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 845 };
 846
 847 /*
 848  * 'hdmi' class
 849  * hdmi controller
 850  */
 851
 852 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 853         .rev_offs       = 0x0000,
 854         .sysc_offs      = 0x0010,
 855         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 856                            SYSC_HAS_SOFTRESET),
 857         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 858                            SIDLE_SMART_WKUP),
 859         .sysc_fields    = &omap_hwmod_sysc_type2,
 860 };
 861
 862 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 863         .name   = "hdmi",
 864         .sysc   = &omap44xx_hdmi_sysc,
 865 };
 866
 867 /* dss_hdmi */
 868 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 869         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 870         { .irq = -1 }
 871 };
 872
 873 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 874         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 875         { .dma_req = -1 }
 876 };
 877
 878 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 879         { .role = "sys_clk", .clk = "dss_sys_clk" },
 880 };
 881
 882 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 883         .name           = "dss_hdmi",
 884         .class          = &omap44xx_hdmi_hwmod_class,
 885         .clkdm_name     = "l3_dss_clkdm",
 886         /*
 887          * HDMI audio requires to use no-idle mode. Hence,
 888          * set idle mode by software.
 889          */
 890         .flags          = HWMOD_SWSUP_SIDLE,
 891         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 892         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 893         .main_clk       = "dss_48mhz_clk",
 894         .prcm = {
 895                 .omap4 = {
 896                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 897                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 898                 },
 899         },
 900         .opt_clks       = dss_hdmi_opt_clks,
 901         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 902 };
 903
 904 /*
 905  * 'rfbi' class
 906  * remote frame buffer interface
 907  */
 908
 909 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 910         .rev_offs       = 0x0000,
 911         .sysc_offs      = 0x0010,
 912         .syss_offs      = 0x0014,
 913         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 914                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 915         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 916         .sysc_fields    = &omap_hwmod_sysc_type1,
 917 };
 918
 919 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 920         .name   = "rfbi",
 921         .sysc   = &omap44xx_rfbi_sysc,
 922 };
 923
 924 /* dss_rfbi */
 925 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 926         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 927         { .dma_req = -1 }
 928 };
 929
 930 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 931         { .role = "ick", .clk = "dss_fck" },
 932 };
 933
 934 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 935         .name           = "dss_rfbi",
 936         .class          = &omap44xx_rfbi_hwmod_class,
 937         .clkdm_name     = "l3_dss_clkdm",
 938         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 939         .main_clk       = "dss_dss_clk",
 940         .prcm = {
 941                 .omap4 = {
 942                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 943                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 944                 },
 945         },
 946         .opt_clks       = dss_rfbi_opt_clks,
 947         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 948 };
 949
 950 /*
 951  * 'venc' class
 952  * video encoder
 953  */
 954
 955 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 956         .name   = "venc",
 957 };
 958
 959 /* dss_venc */
 960 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 961         .name           = "dss_venc",
 962         .class          = &omap44xx_venc_hwmod_class,
 963         .clkdm_name     = "l3_dss_clkdm",
 964         .main_clk       = "dss_tv_clk",
 965         .prcm = {
 966                 .omap4 = {
 967                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 968                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 969                 },
 970         },
 971 };
 972
 973 /*
 974  * 'elm' class
 975  * bch error location module
 976  */
 977
 978 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 979         .rev_offs       = 0x0000,
 980         .sysc_offs      = 0x0010,
 981         .syss_offs      = 0x0014,
 982         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 983                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 984                            SYSS_HAS_RESET_STATUS),
 985         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 986         .sysc_fields    = &omap_hwmod_sysc_type1,
 987 };
 988
 989 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 990         .name   = "elm",
 991         .sysc   = &omap44xx_elm_sysc,
 992 };
 993
 994 /* elm */
 995 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 996         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 997         { .irq = -1 }
 998 };
 999
1000 static struct omap_hwmod omap44xx_elm_hwmod = {
1001         .name           = "elm",
1002         .class          = &omap44xx_elm_hwmod_class,
1003         .clkdm_name     = "l4_per_clkdm",
1004         .mpu_irqs       = omap44xx_elm_irqs,
1005         .prcm = {
1006                 .omap4 = {
1007                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1008                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1009                 },
1010         },
1011 };
1012
1013 /*
1014  * 'emif' class
1015  * external memory interface no1
1016  */
1017
1018 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1019         .rev_offs       = 0x0000,
1020 };
1021
1022 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1023         .name   = "emif",
1024         .sysc   = &omap44xx_emif_sysc,
1025 };
1026
1027 /* emif1 */
1028 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1029         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1030         { .irq = -1 }
1031 };
1032
1033 static struct omap_hwmod omap44xx_emif1_hwmod = {
1034         .name           = "emif1",
1035         .class          = &omap44xx_emif_hwmod_class,
1036         .clkdm_name     = "l3_emif_clkdm",
1037         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1038         .mpu_irqs       = omap44xx_emif1_irqs,
1039         .main_clk       = "ddrphy_ck",
1040         .prcm = {
1041                 .omap4 = {
1042                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1043                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1044                         .modulemode   = MODULEMODE_HWCTRL,
1045                 },
1046         },
1047 };
1048
1049 /* emif2 */
1050 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1051         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1052         { .irq = -1 }
1053 };
1054
1055 static struct omap_hwmod omap44xx_emif2_hwmod = {
1056         .name           = "emif2",
1057         .class          = &omap44xx_emif_hwmod_class,
1058         .clkdm_name     = "l3_emif_clkdm",
1059         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1060         .mpu_irqs       = omap44xx_emif2_irqs,
1061         .main_clk       = "ddrphy_ck",
1062         .prcm = {
1063                 .omap4 = {
1064                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1065                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1066                         .modulemode   = MODULEMODE_HWCTRL,
1067                 },
1068         },
1069 };
1070
1071 /*
1072  * 'fdif' class
1073  * face detection hw accelerator module
1074  */
1075
1076 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1077         .rev_offs       = 0x0000,
1078         .sysc_offs      = 0x0010,
1079         /*
1080          * FDIF needs 100 OCP clk cycles delay after a softreset before
1081          * accessing sysconfig again.
1082          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1083          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1084          *
1085          * TODO: Indicate errata when available.
1086          */
1087         .srst_udelay    = 2,
1088         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1089                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1090         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1091                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1092         .sysc_fields    = &omap_hwmod_sysc_type2,
1093 };
1094
1095 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1096         .name   = "fdif",
1097         .sysc   = &omap44xx_fdif_sysc,
1098 };
1099
1100 /* fdif */
1101 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1102         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1103         { .irq = -1 }
1104 };
1105
1106 static struct omap_hwmod omap44xx_fdif_hwmod = {
1107         .name           = "fdif",
1108         .class          = &omap44xx_fdif_hwmod_class,
1109         .clkdm_name     = "iss_clkdm",
1110         .mpu_irqs       = omap44xx_fdif_irqs,
1111         .main_clk       = "fdif_fck",
1112         .prcm = {
1113                 .omap4 = {
1114                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1115                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1116                         .modulemode   = MODULEMODE_SWCTRL,
1117                 },
1118         },
1119 };
1120
1121 /*
1122  * 'gpio' class
1123  * general purpose io module
1124  */
1125
1126 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1127         .rev_offs       = 0x0000,
1128         .sysc_offs      = 0x0010,
1129         .syss_offs      = 0x0114,
1130         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1131                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1132                            SYSS_HAS_RESET_STATUS),
1133         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1134                            SIDLE_SMART_WKUP),
1135         .sysc_fields    = &omap_hwmod_sysc_type1,
1136 };
1137
1138 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1139         .name   = "gpio",
1140         .sysc   = &omap44xx_gpio_sysc,
1141         .rev    = 2,
1142 };
1143
1144 /* gpio dev_attr */
1145 static struct omap_gpio_dev_attr gpio_dev_attr = {
1146         .bank_width     = 32,
1147         .dbck_flag      = true,
1148 };
1149
1150 /* gpio1 */
1151 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1152         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1153         { .irq = -1 }
1154 };
1155
1156 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1157         { .role = "dbclk", .clk = "gpio1_dbclk" },
1158 };
1159
1160 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1161         .name           = "gpio1",
1162         .class          = &omap44xx_gpio_hwmod_class,
1163         .clkdm_name     = "l4_wkup_clkdm",
1164         .mpu_irqs       = omap44xx_gpio1_irqs,
1165         .main_clk       = "l4_wkup_clk_mux_ck",
1166         .prcm = {
1167                 .omap4 = {
1168                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1169                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1170                         .modulemode   = MODULEMODE_HWCTRL,
1171                 },
1172         },
1173         .opt_clks       = gpio1_opt_clks,
1174         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1175         .dev_attr       = &gpio_dev_attr,
1176 };
1177
1178 /* gpio2 */
1179 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1180         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1181         { .irq = -1 }
1182 };
1183
1184 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1185         { .role = "dbclk", .clk = "gpio2_dbclk" },
1186 };
1187
1188 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1189         .name           = "gpio2",
1190         .class          = &omap44xx_gpio_hwmod_class,
1191         .clkdm_name     = "l4_per_clkdm",
1192         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1193         .mpu_irqs       = omap44xx_gpio2_irqs,
1194         .main_clk       = "l4_div_ck",
1195         .prcm = {
1196                 .omap4 = {
1197                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1198                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1199                         .modulemode   = MODULEMODE_HWCTRL,
1200                 },
1201         },
1202         .opt_clks       = gpio2_opt_clks,
1203         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1204         .dev_attr       = &gpio_dev_attr,
1205 };
1206
1207 /* gpio3 */
1208 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1209         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1210         { .irq = -1 }
1211 };
1212
1213 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1214         { .role = "dbclk", .clk = "gpio3_dbclk" },
1215 };
1216
1217 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1218         .name           = "gpio3",
1219         .class          = &omap44xx_gpio_hwmod_class,
1220         .clkdm_name     = "l4_per_clkdm",
1221         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1222         .mpu_irqs       = omap44xx_gpio3_irqs,
1223         .main_clk       = "l4_div_ck",
1224         .prcm = {
1225                 .omap4 = {
1226                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1227                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1228                         .modulemode   = MODULEMODE_HWCTRL,
1229                 },
1230         },
1231         .opt_clks       = gpio3_opt_clks,
1232         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1233         .dev_attr       = &gpio_dev_attr,
1234 };
1235
1236 /* gpio4 */
1237 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1238         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1239         { .irq = -1 }
1240 };
1241
1242 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1243         { .role = "dbclk", .clk = "gpio4_dbclk" },
1244 };
1245
1246 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1247         .name           = "gpio4",
1248         .class          = &omap44xx_gpio_hwmod_class,
1249         .clkdm_name     = "l4_per_clkdm",
1250         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1251         .mpu_irqs       = omap44xx_gpio4_irqs,
1252         .main_clk       = "l4_div_ck",
1253         .prcm = {
1254                 .omap4 = {
1255                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1256                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1257                         .modulemode   = MODULEMODE_HWCTRL,
1258                 },
1259         },
1260         .opt_clks       = gpio4_opt_clks,
1261         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1262         .dev_attr       = &gpio_dev_attr,
1263 };
1264
1265 /* gpio5 */
1266 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1267         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1268         { .irq = -1 }
1269 };
1270
1271 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1272         { .role = "dbclk", .clk = "gpio5_dbclk" },
1273 };
1274
1275 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1276         .name           = "gpio5",
1277         .class          = &omap44xx_gpio_hwmod_class,
1278         .clkdm_name     = "l4_per_clkdm",
1279         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1280         .mpu_irqs       = omap44xx_gpio5_irqs,
1281         .main_clk       = "l4_div_ck",
1282         .prcm = {
1283                 .omap4 = {
1284                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1285                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1286                         .modulemode   = MODULEMODE_HWCTRL,
1287                 },
1288         },
1289         .opt_clks       = gpio5_opt_clks,
1290         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1291         .dev_attr       = &gpio_dev_attr,
1292 };
1293
1294 /* gpio6 */
1295 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1296         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1297         { .irq = -1 }
1298 };
1299
1300 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1301         { .role = "dbclk", .clk = "gpio6_dbclk" },
1302 };
1303
1304 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1305         .name           = "gpio6",
1306         .class          = &omap44xx_gpio_hwmod_class,
1307         .clkdm_name     = "l4_per_clkdm",
1308         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1309         .mpu_irqs       = omap44xx_gpio6_irqs,
1310         .main_clk       = "l4_div_ck",
1311         .prcm = {
1312                 .omap4 = {
1313                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1314                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1315                         .modulemode   = MODULEMODE_HWCTRL,
1316                 },
1317         },
1318         .opt_clks       = gpio6_opt_clks,
1319         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1320         .dev_attr       = &gpio_dev_attr,
1321 };
1322
1323 /*
1324  * 'gpmc' class
1325  * general purpose memory controller
1326  */
1327
1328 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1329         .rev_offs       = 0x0000,
1330         .sysc_offs      = 0x0010,
1331         .syss_offs      = 0x0014,
1332         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1333                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1334         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1335         .sysc_fields    = &omap_hwmod_sysc_type1,
1336 };
1337
1338 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1339         .name   = "gpmc",
1340         .sysc   = &omap44xx_gpmc_sysc,
1341 };
1342
1343 /* gpmc */
1344 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1345         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1346         { .irq = -1 }
1347 };
1348
1349 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1350         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1351         { .dma_req = -1 }
1352 };
1353
1354 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1355         .name           = "gpmc",
1356         .class          = &omap44xx_gpmc_hwmod_class,
1357         .clkdm_name     = "l3_2_clkdm",
1358         /*
1359          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1360          * block.  It is not being added due to any known bugs with
1361          * resetting the GPMC IP block, but rather because any timings
1362          * set by the bootloader are not being correctly programmed by
1363          * the kernel from the board file or DT data.
1364          * HWMOD_INIT_NO_RESET should be removed ASAP.
1365          */
1366         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1367         .mpu_irqs       = omap44xx_gpmc_irqs,
1368         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1369         .prcm = {
1370                 .omap4 = {
1371                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1372                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1373                         .modulemode   = MODULEMODE_HWCTRL,
1374                 },
1375         },
1376 };
1377
1378 /*
1379  * 'gpu' class
1380  * 2d/3d graphics accelerator
1381  */
1382
1383 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1384         .rev_offs       = 0x1fc00,
1385         .sysc_offs      = 0x1fc10,
1386         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1387         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1388                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1389                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1390         .sysc_fields    = &omap_hwmod_sysc_type2,
1391 };
1392
1393 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1394         .name   = "gpu",
1395         .sysc   = &omap44xx_gpu_sysc,
1396 };
1397
1398 /* gpu */
1399 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1400         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1401         { .irq = -1 }
1402 };
1403
1404 static struct omap_hwmod omap44xx_gpu_hwmod = {
1405         .name           = "gpu",
1406         .class          = &omap44xx_gpu_hwmod_class,
1407         .clkdm_name     = "l3_gfx_clkdm",
1408         .mpu_irqs       = omap44xx_gpu_irqs,
1409         .main_clk       = "sgx_clk_mux",
1410         .prcm = {
1411                 .omap4 = {
1412                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1413                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1414                         .modulemode   = MODULEMODE_SWCTRL,
1415                 },
1416         },
1417 };
1418
1419 /*
1420  * 'hdq1w' class
1421  * hdq / 1-wire serial interface controller
1422  */
1423
1424 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1425         .rev_offs       = 0x0000,
1426         .sysc_offs      = 0x0014,
1427         .syss_offs      = 0x0018,
1428         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1429                            SYSS_HAS_RESET_STATUS),
1430         .sysc_fields    = &omap_hwmod_sysc_type1,
1431 };
1432
1433 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1434         .name   = "hdq1w",
1435         .sysc   = &omap44xx_hdq1w_sysc,
1436 };
1437
1438 /* hdq1w */
1439 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1440         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1441         { .irq = -1 }
1442 };
1443
1444 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1445         .name           = "hdq1w",
1446         .class          = &omap44xx_hdq1w_hwmod_class,
1447         .clkdm_name     = "l4_per_clkdm",
1448         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1449         .mpu_irqs       = omap44xx_hdq1w_irqs,
1450         .main_clk       = "func_12m_fclk",
1451         .prcm = {
1452                 .omap4 = {
1453                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1454                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1455                         .modulemode   = MODULEMODE_SWCTRL,
1456                 },
1457         },
1458 };
1459
1460 /*
1461  * 'hsi' class
1462  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1463  * serial if)
1464  */
1465
1466 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1467         .rev_offs       = 0x0000,
1468         .sysc_offs      = 0x0010,
1469         .syss_offs      = 0x0014,
1470         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1471                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1472                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1473         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1474                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1475                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1476         .sysc_fields    = &omap_hwmod_sysc_type1,
1477 };
1478
1479 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1480         .name   = "hsi",
1481         .sysc   = &omap44xx_hsi_sysc,
1482 };
1483
1484 /* hsi */
1485 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1486         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1487         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1488         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1489         { .irq = -1 }
1490 };
1491
1492 static struct omap_hwmod omap44xx_hsi_hwmod = {
1493         .name           = "hsi",
1494         .class          = &omap44xx_hsi_hwmod_class,
1495         .clkdm_name     = "l3_init_clkdm",
1496         .mpu_irqs       = omap44xx_hsi_irqs,
1497         .main_clk       = "hsi_fck",
1498         .prcm = {
1499                 .omap4 = {
1500                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1501                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1502                         .modulemode   = MODULEMODE_HWCTRL,
1503                 },
1504         },
1505 };
1506
1507 /*
1508  * 'i2c' class
1509  * multimaster high-speed i2c controller
1510  */
1511
1512 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1513         .sysc_offs      = 0x0010,
1514         .syss_offs      = 0x0090,
1515         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1516                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1517                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1518         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1519                            SIDLE_SMART_WKUP),
1520         .clockact       = CLOCKACT_TEST_ICLK,
1521         .sysc_fields    = &omap_hwmod_sysc_type1,
1522 };
1523
1524 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1525         .name   = "i2c",
1526         .sysc   = &omap44xx_i2c_sysc,
1527         .rev    = OMAP_I2C_IP_VERSION_2,
1528         .reset  = &omap_i2c_reset,
1529 };
1530
1531 static struct omap_i2c_dev_attr i2c_dev_attr = {
1532         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1533 };
1534
1535 /* i2c1 */
1536 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1537         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1538         { .irq = -1 }
1539 };
1540
1541 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1542         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1543         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1544         { .dma_req = -1 }
1545 };
1546
1547 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1548         .name           = "i2c1",
1549         .class          = &omap44xx_i2c_hwmod_class,
1550         .clkdm_name     = "l4_per_clkdm",
1551         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1552         .mpu_irqs       = omap44xx_i2c1_irqs,
1553         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1554         .main_clk       = "func_96m_fclk",
1555         .prcm = {
1556                 .omap4 = {
1557                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1558                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1559                         .modulemode   = MODULEMODE_SWCTRL,
1560                 },
1561         },
1562         .dev_attr       = &i2c_dev_attr,
1563 };
1564
1565 /* i2c2 */
1566 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1567         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1568         { .irq = -1 }
1569 };
1570
1571 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1572         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1573         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1574         { .dma_req = -1 }
1575 };
1576
1577 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1578         .name           = "i2c2",
1579         .class          = &omap44xx_i2c_hwmod_class,
1580         .clkdm_name     = "l4_per_clkdm",
1581         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1582         .mpu_irqs       = omap44xx_i2c2_irqs,
1583         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1584         .main_clk       = "func_96m_fclk",
1585         .prcm = {
1586                 .omap4 = {
1587                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1588                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1589                         .modulemode   = MODULEMODE_SWCTRL,
1590                 },
1591         },
1592         .dev_attr       = &i2c_dev_attr,
1593 };
1594
1595 /* i2c3 */
1596 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1597         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1598         { .irq = -1 }
1599 };
1600
1601 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1602         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1603         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1604         { .dma_req = -1 }
1605 };
1606
1607 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1608         .name           = "i2c3",
1609         .class          = &omap44xx_i2c_hwmod_class,
1610         .clkdm_name     = "l4_per_clkdm",
1611         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1612         .mpu_irqs       = omap44xx_i2c3_irqs,
1613         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1614         .main_clk       = "func_96m_fclk",
1615         .prcm = {
1616                 .omap4 = {
1617                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1618                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1619                         .modulemode   = MODULEMODE_SWCTRL,
1620                 },
1621         },
1622         .dev_attr       = &i2c_dev_attr,
1623 };
1624
1625 /* i2c4 */
1626 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1627         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1628         { .irq = -1 }
1629 };
1630
1631 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1632         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1633         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1634         { .dma_req = -1 }
1635 };
1636
1637 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1638         .name           = "i2c4",
1639         .class          = &omap44xx_i2c_hwmod_class,
1640         .clkdm_name     = "l4_per_clkdm",
1641         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1642         .mpu_irqs       = omap44xx_i2c4_irqs,
1643         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1644         .main_clk       = "func_96m_fclk",
1645         .prcm = {
1646                 .omap4 = {
1647                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1648                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1649                         .modulemode   = MODULEMODE_SWCTRL,
1650                 },
1651         },
1652         .dev_attr       = &i2c_dev_attr,
1653 };
1654
1655 /*
1656  * 'ipu' class
1657  * imaging processor unit
1658  */
1659
1660 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1661         .name   = "ipu",
1662 };
1663
1664 /* ipu */
1665 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1666         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1667         { .irq = -1 }
1668 };
1669
1670 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1671         { .name = "cpu0", .rst_shift = 0 },
1672         { .name = "cpu1", .rst_shift = 1 },
1673 };
1674
1675 static struct omap_hwmod omap44xx_ipu_hwmod = {
1676         .name           = "ipu",
1677         .class          = &omap44xx_ipu_hwmod_class,
1678         .clkdm_name     = "ducati_clkdm",
1679         .mpu_irqs       = omap44xx_ipu_irqs,
1680         .rst_lines      = omap44xx_ipu_resets,
1681         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1682         .main_clk       = "ducati_clk_mux_ck",
1683         .prcm = {
1684                 .omap4 = {
1685                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1686                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1687                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1688                         .modulemode   = MODULEMODE_HWCTRL,
1689                 },
1690         },
1691 };
1692
1693 /*
1694  * 'iss' class
1695  * external images sensor pixel data processor
1696  */
1697
1698 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1699         .rev_offs       = 0x0000,
1700         .sysc_offs      = 0x0010,
1701         /*
1702          * ISS needs 100 OCP clk cycles delay after a softreset before
1703          * accessing sysconfig again.
1704          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1705          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1706          *
1707          * TODO: Indicate errata when available.
1708          */
1709         .srst_udelay    = 2,
1710         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1711                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1712         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1713                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1714                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1715         .sysc_fields    = &omap_hwmod_sysc_type2,
1716 };
1717
1718 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1719         .name   = "iss",
1720         .sysc   = &omap44xx_iss_sysc,
1721 };
1722
1723 /* iss */
1724 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1725         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1726         { .irq = -1 }
1727 };
1728
1729 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1730         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1731         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1732         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1733         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1734         { .dma_req = -1 }
1735 };
1736
1737 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1738         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1739 };
1740
1741 static struct omap_hwmod omap44xx_iss_hwmod = {
1742         .name           = "iss",
1743         .class          = &omap44xx_iss_hwmod_class,
1744         .clkdm_name     = "iss_clkdm",
1745         .mpu_irqs       = omap44xx_iss_irqs,
1746         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1747         .main_clk       = "ducati_clk_mux_ck",
1748         .prcm = {
1749                 .omap4 = {
1750                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1751                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1752                         .modulemode   = MODULEMODE_SWCTRL,
1753                 },
1754         },
1755         .opt_clks       = iss_opt_clks,
1756         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1757 };
1758
1759 /*
1760  * 'iva' class
1761  * multi-standard video encoder/decoder hardware accelerator
1762  */
1763
1764 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1765         .name   = "iva",
1766 };
1767
1768 /* iva */
1769 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1770         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1771         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1772         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1773         { .irq = -1 }
1774 };
1775
1776 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1777         { .name = "seq0", .rst_shift = 0 },
1778         { .name = "seq1", .rst_shift = 1 },
1779         { .name = "logic", .rst_shift = 2 },
1780 };
1781
1782 static struct omap_hwmod omap44xx_iva_hwmod = {
1783         .name           = "iva",
1784         .class          = &omap44xx_iva_hwmod_class,
1785         .clkdm_name     = "ivahd_clkdm",
1786         .mpu_irqs       = omap44xx_iva_irqs,
1787         .rst_lines      = omap44xx_iva_resets,
1788         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1789         .main_clk       = "dpll_iva_m5x2_ck",
1790         .prcm = {
1791                 .omap4 = {
1792                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1793                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1794                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1795                         .modulemode   = MODULEMODE_HWCTRL,
1796                 },
1797         },
1798 };
1799
1800 /*
1801  * 'kbd' class
1802  * keyboard controller
1803  */
1804
1805 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1806         .rev_offs       = 0x0000,
1807         .sysc_offs      = 0x0010,
1808         .syss_offs      = 0x0014,
1809         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1810                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1811                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1812                            SYSS_HAS_RESET_STATUS),
1813         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1814         .sysc_fields    = &omap_hwmod_sysc_type1,
1815 };
1816
1817 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1818         .name   = "kbd",
1819         .sysc   = &omap44xx_kbd_sysc,
1820 };
1821
1822 /* kbd */
1823 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1824         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1825         { .irq = -1 }
1826 };
1827
1828 static struct omap_hwmod omap44xx_kbd_hwmod = {
1829         .name           = "kbd",
1830         .class          = &omap44xx_kbd_hwmod_class,
1831         .clkdm_name     = "l4_wkup_clkdm",
1832         .mpu_irqs       = omap44xx_kbd_irqs,
1833         .main_clk       = "sys_32k_ck",
1834         .prcm = {
1835                 .omap4 = {
1836                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1837                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1838                         .modulemode   = MODULEMODE_SWCTRL,
1839                 },
1840         },
1841 };
1842
1843 /*
1844  * 'mailbox' class
1845  * mailbox module allowing communication between the on-chip processors using a
1846  * queued mailbox-interrupt mechanism.
1847  */
1848
1849 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1850         .rev_offs       = 0x0000,
1851         .sysc_offs      = 0x0010,
1852         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1853                            SYSC_HAS_SOFTRESET),
1854         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1855         .sysc_fields    = &omap_hwmod_sysc_type2,
1856 };
1857
1858 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1859         .name   = "mailbox",
1860         .sysc   = &omap44xx_mailbox_sysc,
1861 };
1862
1863 /* mailbox */
1864 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1865         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1866         { .irq = -1 }
1867 };
1868
1869 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1870         .name           = "mailbox",
1871         .class          = &omap44xx_mailbox_hwmod_class,
1872         .clkdm_name     = "l4_cfg_clkdm",
1873         .mpu_irqs       = omap44xx_mailbox_irqs,
1874         .prcm = {
1875                 .omap4 = {
1876                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1877                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1878                 },
1879         },
1880 };
1881
1882 /*
1883  * 'mcasp' class
1884  * multi-channel audio serial port controller
1885  */
1886
1887 /* The IP is not compliant to type1 / type2 scheme */
1888 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1889         .sidle_shift    = 0,
1890 };
1891
1892 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1893         .sysc_offs      = 0x0004,
1894         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1895         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1896                            SIDLE_SMART_WKUP),
1897         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1898 };
1899
1900 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1901         .name   = "mcasp",
1902         .sysc   = &omap44xx_mcasp_sysc,
1903 };
1904
1905 /* mcasp */
1906 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1907         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1908         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1909         { .irq = -1 }
1910 };
1911
1912 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1913         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1914         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1915         { .dma_req = -1 }
1916 };
1917
1918 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1919         .name           = "mcasp",
1920         .class          = &omap44xx_mcasp_hwmod_class,
1921         .clkdm_name     = "abe_clkdm",
1922         .mpu_irqs       = omap44xx_mcasp_irqs,
1923         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1924         .main_clk       = "func_mcasp_abe_gfclk",
1925         .prcm = {
1926                 .omap4 = {
1927                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1928                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1929                         .modulemode   = MODULEMODE_SWCTRL,
1930                 },
1931         },
1932 };
1933
1934 /*
1935  * 'mcbsp' class
1936  * multi channel buffered serial port controller
1937  */
1938
1939 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1940         .sysc_offs      = 0x008c,
1941         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1942                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1943         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1944         .sysc_fields    = &omap_hwmod_sysc_type1,
1945 };
1946
1947 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1948         .name   = "mcbsp",
1949         .sysc   = &omap44xx_mcbsp_sysc,
1950         .rev    = MCBSP_CONFIG_TYPE4,
1951 };
1952
1953 /* mcbsp1 */
1954 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1955         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1956         { .irq = -1 }
1957 };
1958
1959 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1960         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1961         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1962         { .dma_req = -1 }
1963 };
1964
1965 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1966         { .role = "pad_fck", .clk = "pad_clks_ck" },
1967         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1968 };
1969
1970 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1971         .name           = "mcbsp1",
1972         .class          = &omap44xx_mcbsp_hwmod_class,
1973         .clkdm_name     = "abe_clkdm",
1974         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1975         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1976         .main_clk       = "func_mcbsp1_gfclk",
1977         .prcm = {
1978                 .omap4 = {
1979                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1980                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1981                         .modulemode   = MODULEMODE_SWCTRL,
1982                 },
1983         },
1984         .opt_clks       = mcbsp1_opt_clks,
1985         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1986 };
1987
1988 /* mcbsp2 */
1989 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1990         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1991         { .irq = -1 }
1992 };
1993
1994 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1995         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1996         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1997         { .dma_req = -1 }
1998 };
1999
2000 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2001         { .role = "pad_fck", .clk = "pad_clks_ck" },
2002         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2003 };
2004
2005 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2006         .name           = "mcbsp2",
2007         .class          = &omap44xx_mcbsp_hwmod_class,
2008         .clkdm_name     = "abe_clkdm",
2009         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2010         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2011         .main_clk       = "func_mcbsp2_gfclk",
2012         .prcm = {
2013                 .omap4 = {
2014                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2015                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2016                         .modulemode   = MODULEMODE_SWCTRL,
2017                 },
2018         },
2019         .opt_clks       = mcbsp2_opt_clks,
2020         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2021 };
2022
2023 /* mcbsp3 */
2024 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2025         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2026         { .irq = -1 }
2027 };
2028
2029 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2030         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2031         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2032         { .dma_req = -1 }
2033 };
2034
2035 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2036         { .role = "pad_fck", .clk = "pad_clks_ck" },
2037         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2038 };
2039
2040 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2041         .name           = "mcbsp3",
2042         .class          = &omap44xx_mcbsp_hwmod_class,
2043         .clkdm_name     = "abe_clkdm",
2044         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2045         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2046         .main_clk       = "func_mcbsp3_gfclk",
2047         .prcm = {
2048                 .omap4 = {
2049                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2050                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2051                         .modulemode   = MODULEMODE_SWCTRL,
2052                 },
2053         },
2054         .opt_clks       = mcbsp3_opt_clks,
2055         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2056 };
2057
2058 /* mcbsp4 */
2059 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2060         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2061         { .irq = -1 }
2062 };
2063
2064 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2065         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2066         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2067         { .dma_req = -1 }
2068 };
2069
2070 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2071         { .role = "pad_fck", .clk = "pad_clks_ck" },
2072         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2073 };
2074
2075 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2076         .name           = "mcbsp4",
2077         .class          = &omap44xx_mcbsp_hwmod_class,
2078         .clkdm_name     = "l4_per_clkdm",
2079         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2080         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2081         .main_clk       = "per_mcbsp4_gfclk",
2082         .prcm = {
2083                 .omap4 = {
2084                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2085                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2086                         .modulemode   = MODULEMODE_SWCTRL,
2087                 },
2088         },
2089         .opt_clks       = mcbsp4_opt_clks,
2090         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2091 };
2092
2093 /*
2094  * 'mcpdm' class
2095  * multi channel pdm controller (proprietary interface with phoenix power
2096  * ic)
2097  */
2098
2099 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2100         .rev_offs       = 0x0000,
2101         .sysc_offs      = 0x0010,
2102         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2103                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2104         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2105                            SIDLE_SMART_WKUP),
2106         .sysc_fields    = &omap_hwmod_sysc_type2,
2107 };
2108
2109 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2110         .name   = "mcpdm",
2111         .sysc   = &omap44xx_mcpdm_sysc,
2112 };
2113
2114 /* mcpdm */
2115 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2116         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2117         { .irq = -1 }
2118 };
2119
2120 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2121         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2122         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2123         { .dma_req = -1 }
2124 };
2125
2126 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2127         .name           = "mcpdm",
2128         .class          = &omap44xx_mcpdm_hwmod_class,
2129         .clkdm_name     = "abe_clkdm",
2130         /*
2131          * It's suspected that the McPDM requires an off-chip main
2132          * functional clock, controlled via I2C.  This IP block is
2133          * currently reset very early during boot, before I2C is
2134          * available, so it doesn't seem that we have any choice in
2135          * the kernel other than to avoid resetting it.
2136          *
2137          * Also, McPDM needs to be configured to NO_IDLE mode when it
2138          * is in used otherwise vital clocks will be gated which
2139          * results 'slow motion' audio playback.
2140          */
2141         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
2142         .mpu_irqs       = omap44xx_mcpdm_irqs,
2143         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2144         .main_clk       = "pad_clks_ck",
2145         .prcm = {
2146                 .omap4 = {
2147                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2148                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2149                         .modulemode   = MODULEMODE_SWCTRL,
2150                 },
2151         },
2152 };
2153
2154 /*
2155  * 'mcspi' class
2156  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2157  * bus
2158  */
2159
2160 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2161         .rev_offs       = 0x0000,
2162         .sysc_offs      = 0x0010,
2163         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2164                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2165         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2166                            SIDLE_SMART_WKUP),
2167         .sysc_fields    = &omap_hwmod_sysc_type2,
2168 };
2169
2170 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2171         .name   = "mcspi",
2172         .sysc   = &omap44xx_mcspi_sysc,
2173         .rev    = OMAP4_MCSPI_REV,
2174 };
2175
2176 /* mcspi1 */
2177 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2178         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2179         { .irq = -1 }
2180 };
2181
2182 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2183         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2184         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2185         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2186         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2187         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2188         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2189         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2190         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2191         { .dma_req = -1 }
2192 };
2193
2194 /* mcspi1 dev_attr */
2195 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2196         .num_chipselect = 4,
2197 };
2198
2199 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2200         .name           = "mcspi1",
2201         .class          = &omap44xx_mcspi_hwmod_class,
2202         .clkdm_name     = "l4_per_clkdm",
2203         .mpu_irqs       = omap44xx_mcspi1_irqs,
2204         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2205         .main_clk       = "func_48m_fclk",
2206         .prcm = {
2207                 .omap4 = {
2208                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2209                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2210                         .modulemode   = MODULEMODE_SWCTRL,
2211                 },
2212         },
2213         .dev_attr       = &mcspi1_dev_attr,
2214 };
2215
2216 /* mcspi2 */
2217 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2218         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2219         { .irq = -1 }
2220 };
2221
2222 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2223         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2224         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2225         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2226         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2227         { .dma_req = -1 }
2228 };
2229
2230 /* mcspi2 dev_attr */
2231 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2232         .num_chipselect = 2,
2233 };
2234
2235 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2236         .name           = "mcspi2",
2237         .class          = &omap44xx_mcspi_hwmod_class,
2238         .clkdm_name     = "l4_per_clkdm",
2239         .mpu_irqs       = omap44xx_mcspi2_irqs,
2240         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2241         .main_clk       = "func_48m_fclk",
2242         .prcm = {
2243                 .omap4 = {
2244                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2245                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2246                         .modulemode   = MODULEMODE_SWCTRL,
2247                 },
2248         },
2249         .dev_attr       = &mcspi2_dev_attr,
2250 };
2251
2252 /* mcspi3 */
2253 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2254         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2255         { .irq = -1 }
2256 };
2257
2258 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2259         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2260         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2261         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2262         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2263         { .dma_req = -1 }
2264 };
2265
2266 /* mcspi3 dev_attr */
2267 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2268         .num_chipselect = 2,
2269 };
2270
2271 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2272         .name           = "mcspi3",
2273         .class          = &omap44xx_mcspi_hwmod_class,
2274         .clkdm_name     = "l4_per_clkdm",
2275         .mpu_irqs       = omap44xx_mcspi3_irqs,
2276         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2277         .main_clk       = "func_48m_fclk",
2278         .prcm = {
2279                 .omap4 = {
2280                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2281                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2282                         .modulemode   = MODULEMODE_SWCTRL,
2283                 },
2284         },
2285         .dev_attr       = &mcspi3_dev_attr,
2286 };
2287
2288 /* mcspi4 */
2289 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2290         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2291         { .irq = -1 }
2292 };
2293
2294 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2295         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2296         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2297         { .dma_req = -1 }
2298 };
2299
2300 /* mcspi4 dev_attr */
2301 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2302         .num_chipselect = 1,
2303 };
2304
2305 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2306         .name           = "mcspi4",
2307         .class          = &omap44xx_mcspi_hwmod_class,
2308         .clkdm_name     = "l4_per_clkdm",
2309         .mpu_irqs       = omap44xx_mcspi4_irqs,
2310         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2311         .main_clk       = "func_48m_fclk",
2312         .prcm = {
2313                 .omap4 = {
2314                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2315                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2316                         .modulemode   = MODULEMODE_SWCTRL,
2317                 },
2318         },
2319         .dev_attr       = &mcspi4_dev_attr,
2320 };
2321
2322 /*
2323  * 'mmc' class
2324  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2325  */
2326
2327 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2328         .rev_offs       = 0x0000,
2329         .sysc_offs      = 0x0010,
2330         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2331                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2332                            SYSC_HAS_SOFTRESET),
2333         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2334                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2335                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2336         .sysc_fields    = &omap_hwmod_sysc_type2,
2337 };
2338
2339 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2340         .name   = "mmc",
2341         .sysc   = &omap44xx_mmc_sysc,
2342 };
2343
2344 /* mmc1 */
2345 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2346         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2347         { .irq = -1 }
2348 };
2349
2350 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2351         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2352         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2353         { .dma_req = -1 }
2354 };
2355
2356 /* mmc1 dev_attr */
2357 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2358         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2359 };
2360
2361 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2362         .name           = "mmc1",
2363         .class          = &omap44xx_mmc_hwmod_class,
2364         .clkdm_name     = "l3_init_clkdm",
2365         .mpu_irqs       = omap44xx_mmc1_irqs,
2366         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2367         .main_clk       = "hsmmc1_fclk",
2368         .prcm = {
2369                 .omap4 = {
2370                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2371                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2372                         .modulemode   = MODULEMODE_SWCTRL,
2373                 },
2374         },
2375         .dev_attr       = &mmc1_dev_attr,
2376 };
2377
2378 /* mmc2 */
2379 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2380         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2381         { .irq = -1 }
2382 };
2383
2384 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2385         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2386         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2387         { .dma_req = -1 }
2388 };
2389
2390 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2391         .name           = "mmc2",
2392         .class          = &omap44xx_mmc_hwmod_class,
2393         .clkdm_name     = "l3_init_clkdm",
2394         .mpu_irqs       = omap44xx_mmc2_irqs,
2395         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2396         .main_clk       = "hsmmc2_fclk",
2397         .prcm = {
2398                 .omap4 = {
2399                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2400                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2401                         .modulemode   = MODULEMODE_SWCTRL,
2402                 },
2403         },
2404 };
2405
2406 /* mmc3 */
2407 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2408         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2409         { .irq = -1 }
2410 };
2411
2412 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2413         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2414         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2415         { .dma_req = -1 }
2416 };
2417
2418 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2419         .name           = "mmc3",
2420         .class          = &omap44xx_mmc_hwmod_class,
2421         .clkdm_name     = "l4_per_clkdm",
2422         .mpu_irqs       = omap44xx_mmc3_irqs,
2423         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2424         .main_clk       = "func_48m_fclk",
2425         .prcm = {
2426                 .omap4 = {
2427                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2428                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2429                         .modulemode   = MODULEMODE_SWCTRL,
2430                 },
2431         },
2432 };
2433
2434 /* mmc4 */
2435 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2436         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2437         { .irq = -1 }
2438 };
2439
2440 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2441         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2442         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2443         { .dma_req = -1 }
2444 };
2445
2446 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2447         .name           = "mmc4",
2448         .class          = &omap44xx_mmc_hwmod_class,
2449         .clkdm_name     = "l4_per_clkdm",
2450         .mpu_irqs       = omap44xx_mmc4_irqs,
2451         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2452         .main_clk       = "func_48m_fclk",
2453         .prcm = {
2454                 .omap4 = {
2455                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2456                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2457                         .modulemode   = MODULEMODE_SWCTRL,
2458                 },
2459         },
2460 };
2461
2462 /* mmc5 */
2463 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2464         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2465         { .irq = -1 }
2466 };
2467
2468 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2469         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2470         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2471         { .dma_req = -1 }
2472 };
2473
2474 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2475         .name           = "mmc5",
2476         .class          = &omap44xx_mmc_hwmod_class,
2477         .clkdm_name     = "l4_per_clkdm",
2478         .mpu_irqs       = omap44xx_mmc5_irqs,
2479         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2480         .main_clk       = "func_48m_fclk",
2481         .prcm = {
2482                 .omap4 = {
2483                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2484                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2485                         .modulemode   = MODULEMODE_SWCTRL,
2486                 },
2487         },
2488 };
2489
2490 /*
2491  * 'mmu' class
2492  * The memory management unit performs virtual to physical address translation
2493  * for its requestors.
2494  */
2495
2496 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2497         .rev_offs       = 0x000,
2498         .sysc_offs      = 0x010,
2499         .syss_offs      = 0x014,
2500         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2501                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2502         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2503         .sysc_fields    = &omap_hwmod_sysc_type1,
2504 };
2505
2506 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2507         .name = "mmu",
2508         .sysc = &mmu_sysc,
2509 };
2510
2511 /* mmu ipu */
2512
2513 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2514         .da_start       = 0x0,
2515         .da_end         = 0xfffff000,
2516         .nr_tlb_entries = 32,
2517 };
2518
2519 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2520 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2521         { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2522         { .irq = -1 }
2523 };
2524
2525 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2526         { .name = "mmu_cache", .rst_shift = 2 },
2527 };
2528
2529 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2530         {
2531                 .pa_start       = 0x55082000,
2532                 .pa_end         = 0x550820ff,
2533                 .flags          = ADDR_TYPE_RT,
2534         },
2535         { }
2536 };
2537
2538 /* l3_main_2 -> mmu_ipu */
2539 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2540         .master         = &omap44xx_l3_main_2_hwmod,
2541         .slave          = &omap44xx_mmu_ipu_hwmod,
2542         .clk            = "l3_div_ck",
2543         .addr           = omap44xx_mmu_ipu_addrs,
2544         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2545 };
2546
2547 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2548         .name           = "mmu_ipu",
2549         .class          = &omap44xx_mmu_hwmod_class,
2550         .clkdm_name     = "ducati_clkdm",
2551         .mpu_irqs       = omap44xx_mmu_ipu_irqs,
2552         .rst_lines      = omap44xx_mmu_ipu_resets,
2553         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2554         .main_clk       = "ducati_clk_mux_ck",
2555         .prcm = {
2556                 .omap4 = {
2557                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2558                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2559                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2560                         .modulemode   = MODULEMODE_HWCTRL,
2561                 },
2562         },
2563         .dev_attr       = &mmu_ipu_dev_attr,
2564 };
2565
2566 /* mmu dsp */
2567
2568 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2569         .da_start       = 0x0,
2570         .da_end         = 0xfffff000,
2571         .nr_tlb_entries = 32,
2572 };
2573
2574 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2575 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2576         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2577         { .irq = -1 }
2578 };
2579
2580 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2581         { .name = "mmu_cache", .rst_shift = 1 },
2582 };
2583
2584 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2585         {
2586                 .pa_start       = 0x4a066000,
2587                 .pa_end         = 0x4a0660ff,
2588                 .flags          = ADDR_TYPE_RT,
2589         },
2590         { }
2591 };
2592
2593 /* l4_cfg -> dsp */
2594 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2595         .master         = &omap44xx_l4_cfg_hwmod,
2596         .slave          = &omap44xx_mmu_dsp_hwmod,
2597         .clk            = "l4_div_ck",
2598         .addr           = omap44xx_mmu_dsp_addrs,
2599         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2600 };
2601
2602 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2603         .name           = "mmu_dsp",
2604         .class          = &omap44xx_mmu_hwmod_class,
2605         .clkdm_name     = "tesla_clkdm",
2606         .mpu_irqs       = omap44xx_mmu_dsp_irqs,
2607         .rst_lines      = omap44xx_mmu_dsp_resets,
2608         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2609         .main_clk       = "dpll_iva_m4x2_ck",
2610         .prcm = {
2611                 .omap4 = {
2612                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2613                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2614                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2615                         .modulemode   = MODULEMODE_HWCTRL,
2616                 },
2617         },
2618         .dev_attr       = &mmu_dsp_dev_attr,
2619 };
2620
2621 /*
2622  * 'mpu' class
2623  * mpu sub-system
2624  */
2625
2626 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2627         .name   = "mpu",
2628 };
2629
2630 /* mpu */
2631 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2632         { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2633         { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2634         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2635         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2636         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2637         { .irq = -1 }
2638 };
2639
2640 static struct omap_hwmod omap44xx_mpu_hwmod = {
2641         .name           = "mpu",
2642         .class          = &omap44xx_mpu_hwmod_class,
2643         .clkdm_name     = "mpuss_clkdm",
2644         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2645         .mpu_irqs       = omap44xx_mpu_irqs,
2646         .main_clk       = "dpll_mpu_m2_ck",
2647         .prcm = {
2648                 .omap4 = {
2649                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2650                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2651                 },
2652         },
2653 };
2654
2655 /*
2656  * 'ocmc_ram' class
2657  * top-level core on-chip ram
2658  */
2659
2660 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2661         .name   = "ocmc_ram",
2662 };
2663
2664 /* ocmc_ram */
2665 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2666         .name           = "ocmc_ram",
2667         .class          = &omap44xx_ocmc_ram_hwmod_class,
2668         .clkdm_name     = "l3_2_clkdm",
2669         .prcm = {
2670                 .omap4 = {
2671                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2672                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2673                 },
2674         },
2675 };
2676
2677 /*
2678  * 'ocp2scp' class
2679  * bridge to transform ocp interface protocol to scp (serial control port)
2680  * protocol
2681  */
2682
2683 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2684         .rev_offs       = 0x0000,
2685         .sysc_offs      = 0x0010,
2686         .syss_offs      = 0x0014,
2687         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2688                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2689         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2690         .sysc_fields    = &omap_hwmod_sysc_type1,
2691 };
2692
2693 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2694         .name   = "ocp2scp",
2695         .sysc   = &omap44xx_ocp2scp_sysc,
2696 };
2697
2698 /* ocp2scp dev_attr */
2699 static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
2700         {
2701                 .name           = "usb_phy",
2702                 .start          = 0x4a0ad080,
2703                 .end            = 0x4a0ae000,
2704                 .flags          = IORESOURCE_MEM,
2705         },
2706         { }
2707 };
2708
2709 static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
2710         {
2711                 .drv_name       = "omap-usb2",
2712                 .res            = omap44xx_usb_phy_and_pll_addrs,
2713         },
2714         { }
2715 };
2716
2717 /* ocp2scp_usb_phy */
2718 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2719         .name           = "ocp2scp_usb_phy",
2720         .class          = &omap44xx_ocp2scp_hwmod_class,
2721         .clkdm_name     = "l3_init_clkdm",
2722         .main_clk       = "func_48m_fclk",
2723         .prcm = {
2724                 .omap4 = {
2725                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2726                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2727                         .modulemode   = MODULEMODE_HWCTRL,
2728                 },
2729         },
2730         .dev_attr       = ocp2scp_dev_attr,
2731 };
2732
2733 /*
2734  * 'prcm' class
2735  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2736  * + clock manager 1 (in always on power domain) + local prm in mpu
2737  */
2738
2739 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2740         .name   = "prcm",
2741 };
2742
2743 /* prcm_mpu */
2744 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2745         .name           = "prcm_mpu",
2746         .class          = &omap44xx_prcm_hwmod_class,
2747         .clkdm_name     = "l4_wkup_clkdm",
2748         .flags          = HWMOD_NO_IDLEST,
2749         .prcm = {
2750                 .omap4 = {
2751                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2752                 },
2753         },
2754 };
2755
2756 /* cm_core_aon */
2757 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2758         .name           = "cm_core_aon",
2759         .class          = &omap44xx_prcm_hwmod_class,
2760         .flags          = HWMOD_NO_IDLEST,
2761         .prcm = {
2762                 .omap4 = {
2763                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2764                 },
2765         },
2766 };
2767
2768 /* cm_core */
2769 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2770         .name           = "cm_core",
2771         .class          = &omap44xx_prcm_hwmod_class,
2772         .flags          = HWMOD_NO_IDLEST,
2773         .prcm = {
2774                 .omap4 = {
2775                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2776                 },
2777         },
2778 };
2779
2780 /* prm */
2781 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2782         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2783         { .irq = -1 }
2784 };
2785
2786 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2787         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2788         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2789 };
2790
2791 static struct omap_hwmod omap44xx_prm_hwmod = {
2792         .name           = "prm",
2793         .class          = &omap44xx_prcm_hwmod_class,
2794         .mpu_irqs       = omap44xx_prm_irqs,
2795         .rst_lines      = omap44xx_prm_resets,
2796         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2797 };
2798
2799 /*
2800  * 'scrm' class
2801  * system clock and reset manager
2802  */
2803
2804 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2805         .name   = "scrm",
2806 };
2807
2808 /* scrm */
2809 static struct omap_hwmod omap44xx_scrm_hwmod = {
2810         .name           = "scrm",
2811         .class          = &omap44xx_scrm_hwmod_class,
2812         .clkdm_name     = "l4_wkup_clkdm",
2813         .prcm = {
2814                 .omap4 = {
2815                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2816                 },
2817         },
2818 };
2819
2820 /*
2821  * 'sl2if' class
2822  * shared level 2 memory interface
2823  */
2824
2825 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2826         .name   = "sl2if",
2827 };
2828
2829 /* sl2if */
2830 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2831         .name           = "sl2if",
2832         .class          = &omap44xx_sl2if_hwmod_class,
2833         .clkdm_name     = "ivahd_clkdm",
2834         .prcm = {
2835                 .omap4 = {
2836                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2837                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2838                         .modulemode   = MODULEMODE_HWCTRL,
2839                 },
2840         },
2841 };
2842
2843 /*
2844  * 'slimbus' class
2845  * bidirectional, multi-drop, multi-channel two-line serial interface between
2846  * the device and external components
2847  */
2848
2849 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2850         .rev_offs       = 0x0000,
2851         .sysc_offs      = 0x0010,
2852         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2853                            SYSC_HAS_SOFTRESET),
2854         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2855                            SIDLE_SMART_WKUP),
2856         .sysc_fields    = &omap_hwmod_sysc_type2,
2857 };
2858
2859 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2860         .name   = "slimbus",
2861         .sysc   = &omap44xx_slimbus_sysc,
2862 };
2863
2864 /* slimbus1 */
2865 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2866         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2867         { .irq = -1 }
2868 };
2869
2870 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2871         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2872         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2873         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2874         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2875         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2876         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2877         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2878         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2879         { .dma_req = -1 }
2880 };
2881
2882 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2883         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2884         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2885         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2886         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2887 };
2888
2889 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2890         .name           = "slimbus1",
2891         .class          = &omap44xx_slimbus_hwmod_class,
2892         .clkdm_name     = "abe_clkdm",
2893         .mpu_irqs       = omap44xx_slimbus1_irqs,
2894         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2895         .prcm = {
2896                 .omap4 = {
2897                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2898                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2899                         .modulemode   = MODULEMODE_SWCTRL,
2900                 },
2901         },
2902         .opt_clks       = slimbus1_opt_clks,
2903         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2904 };
2905
2906 /* slimbus2 */
2907 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2908         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2909         { .irq = -1 }
2910 };
2911
2912 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2913         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2914         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2915         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2916         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2917         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2918         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2919         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2920         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2921         { .dma_req = -1 }
2922 };
2923
2924 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2925         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2926         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2927         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2928 };
2929
2930 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2931         .name           = "slimbus2",
2932         .class          = &omap44xx_slimbus_hwmod_class,
2933         .clkdm_name     = "l4_per_clkdm",
2934         .mpu_irqs       = omap44xx_slimbus2_irqs,
2935         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2936         .prcm = {
2937                 .omap4 = {
2938                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2939                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2940                         .modulemode   = MODULEMODE_SWCTRL,
2941                 },
2942         },
2943         .opt_clks       = slimbus2_opt_clks,
2944         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2945 };
2946
2947 /*
2948  * 'smartreflex' class
2949  * smartreflex module (monitor silicon performance and outputs a measure of
2950  * performance error)
2951  */
2952
2953 /* The IP is not compliant to type1 / type2 scheme */
2954 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2955         .sidle_shift    = 24,
2956         .enwkup_shift   = 26,
2957 };
2958
2959 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2960         .sysc_offs      = 0x0038,
2961         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2962         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2963                            SIDLE_SMART_WKUP),
2964         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2965 };
2966
2967 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2968         .name   = "smartreflex",
2969         .sysc   = &omap44xx_smartreflex_sysc,
2970         .rev    = 2,
2971 };
2972
2973 /* smartreflex_core */
2974 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2975         .sensor_voltdm_name   = "core",
2976 };
2977
2978 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2979         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2980         { .irq = -1 }
2981 };
2982
2983 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2984         .name           = "smartreflex_core",
2985         .class          = &omap44xx_smartreflex_hwmod_class,
2986         .clkdm_name     = "l4_ao_clkdm",
2987         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2988
2989         .main_clk       = "smartreflex_core_fck",
2990         .prcm = {
2991                 .omap4 = {
2992                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2993                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2994                         .modulemode   = MODULEMODE_SWCTRL,
2995                 },
2996         },
2997         .dev_attr       = &smartreflex_core_dev_attr,
2998 };
2999
3000 /* smartreflex_iva */
3001 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
3002         .sensor_voltdm_name     = "iva",
3003 };
3004
3005 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3006         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3007         { .irq = -1 }
3008 };
3009
3010 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3011         .name           = "smartreflex_iva",
3012         .class          = &omap44xx_smartreflex_hwmod_class,
3013         .clkdm_name     = "l4_ao_clkdm",
3014         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3015         .main_clk       = "smartreflex_iva_fck",
3016         .prcm = {
3017                 .omap4 = {
3018                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
3019                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
3020                         .modulemode   = MODULEMODE_SWCTRL,
3021                 },
3022         },
3023         .dev_attr       = &smartreflex_iva_dev_attr,
3024 };
3025
3026 /* smartreflex_mpu */
3027 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
3028         .sensor_voltdm_name     = "mpu",
3029 };
3030
3031 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3032         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3033         { .irq = -1 }
3034 };
3035
3036 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3037         .name           = "smartreflex_mpu",
3038         .class          = &omap44xx_smartreflex_hwmod_class,
3039         .clkdm_name     = "l4_ao_clkdm",
3040         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3041         .main_clk       = "smartreflex_mpu_fck",
3042         .prcm = {
3043                 .omap4 = {
3044                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3045                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3046                         .modulemode   = MODULEMODE_SWCTRL,
3047                 },
3048         },
3049         .dev_attr       = &smartreflex_mpu_dev_attr,
3050 };
3051
3052 /*
3053  * 'spinlock' class
3054  * spinlock provides hardware assistance for synchronizing the processes
3055  * running on multiple processors
3056  */
3057
3058 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3059         .rev_offs       = 0x0000,
3060         .sysc_offs      = 0x0010,
3061         .syss_offs      = 0x0014,
3062         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3063                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3064                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3065         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3066                            SIDLE_SMART_WKUP),
3067         .sysc_fields    = &omap_hwmod_sysc_type1,
3068 };
3069
3070 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3071         .name   = "spinlock",
3072         .sysc   = &omap44xx_spinlock_sysc,
3073 };
3074
3075 /* spinlock */
3076 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3077         .name           = "spinlock",
3078         .class          = &omap44xx_spinlock_hwmod_class,
3079         .clkdm_name     = "l4_cfg_clkdm",
3080         .prcm = {
3081                 .omap4 = {
3082                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3083                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3084                 },
3085         },
3086 };
3087
3088 /*
3089  * 'timer' class
3090  * general purpose timer module with accurate 1ms tick
3091  * This class contains several variants: ['timer_1ms', 'timer']
3092  */
3093
3094 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3095         .rev_offs       = 0x0000,
3096         .sysc_offs      = 0x0010,
3097         .syss_offs      = 0x0014,
3098         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3099                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3100                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3101                            SYSS_HAS_RESET_STATUS),
3102         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3103         .clockact       = CLOCKACT_TEST_ICLK,
3104         .sysc_fields    = &omap_hwmod_sysc_type1,
3105 };
3106
3107 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3108         .name   = "timer",
3109         .sysc   = &omap44xx_timer_1ms_sysc,
3110 };
3111
3112 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3113         .rev_offs       = 0x0000,
3114         .sysc_offs      = 0x0010,
3115         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3116                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3117         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3118                            SIDLE_SMART_WKUP),
3119         .sysc_fields    = &omap_hwmod_sysc_type2,
3120 };
3121
3122 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3123         .name   = "timer",
3124         .sysc   = &omap44xx_timer_sysc,
3125 };
3126
3127 /* always-on timers dev attribute */
3128 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3129         .timer_capability       = OMAP_TIMER_ALWON,
3130 };
3131
3132 /* pwm timers dev attribute */
3133 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3134         .timer_capability       = OMAP_TIMER_HAS_PWM,
3135 };
3136
3137 /* timers with DSP interrupt dev attribute */
3138 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3139         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
3140 };
3141
3142 /* pwm timers with DSP interrupt dev attribute */
3143 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3144         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3145 };
3146
3147 /* timer1 */
3148 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3149         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3150         { .irq = -1 }
3151 };
3152
3153 static struct omap_hwmod omap44xx_timer1_hwmod = {
3154         .name           = "timer1",
3155         .class          = &omap44xx_timer_1ms_hwmod_class,
3156         .clkdm_name     = "l4_wkup_clkdm",
3157         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3158         .mpu_irqs       = omap44xx_timer1_irqs,
3159         .main_clk       = "dmt1_clk_mux",
3160         .prcm = {
3161                 .omap4 = {
3162                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3163                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3164                         .modulemode   = MODULEMODE_SWCTRL,
3165                 },
3166         },
3167         .dev_attr       = &capability_alwon_dev_attr,
3168 };
3169
3170 /* timer2 */
3171 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3172         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3173         { .irq = -1 }
3174 };
3175
3176 static struct omap_hwmod omap44xx_timer2_hwmod = {
3177         .name           = "timer2",
3178         .class          = &omap44xx_timer_1ms_hwmod_class,
3179         .clkdm_name     = "l4_per_clkdm",
3180         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3181         .mpu_irqs       = omap44xx_timer2_irqs,
3182         .main_clk       = "cm2_dm2_mux",
3183         .prcm = {
3184                 .omap4 = {
3185                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3186                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3187                         .modulemode   = MODULEMODE_SWCTRL,
3188                 },
3189         },
3190 };
3191
3192 /* timer3 */
3193 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3194         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3195         { .irq = -1 }
3196 };
3197
3198 static struct omap_hwmod omap44xx_timer3_hwmod = {
3199         .name           = "timer3",
3200         .class          = &omap44xx_timer_hwmod_class,
3201         .clkdm_name     = "l4_per_clkdm",
3202         .mpu_irqs       = omap44xx_timer3_irqs,
3203         .main_clk       = "cm2_dm3_mux",
3204         .prcm = {
3205                 .omap4 = {
3206                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3207                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3208                         .modulemode   = MODULEMODE_SWCTRL,
3209                 },
3210         },
3211 };
3212
3213 /* timer4 */
3214 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3215         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3216         { .irq = -1 }
3217 };
3218
3219 static struct omap_hwmod omap44xx_timer4_hwmod = {
3220         .name           = "timer4",
3221         .class          = &omap44xx_timer_hwmod_class,
3222         .clkdm_name     = "l4_per_clkdm",
3223         .mpu_irqs       = omap44xx_timer4_irqs,
3224         .main_clk       = "cm2_dm4_mux",
3225         .prcm = {
3226                 .omap4 = {
3227                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3228                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3229                         .modulemode   = MODULEMODE_SWCTRL,
3230                 },
3231         },
3232 };
3233
3234 /* timer5 */
3235 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3236         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3237         { .irq = -1 }
3238 };
3239
3240 static struct omap_hwmod omap44xx_timer5_hwmod = {
3241         .name           = "timer5",
3242         .class          = &omap44xx_timer_hwmod_class,
3243         .clkdm_name     = "abe_clkdm",
3244         .mpu_irqs       = omap44xx_timer5_irqs,
3245         .main_clk       = "timer5_sync_mux",
3246         .prcm = {
3247                 .omap4 = {
3248                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3249                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3250                         .modulemode   = MODULEMODE_SWCTRL,
3251                 },
3252         },
3253         .dev_attr       = &capability_dsp_dev_attr,
3254 };
3255
3256 /* timer6 */
3257 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3258         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3259         { .irq = -1 }
3260 };
3261
3262 static struct omap_hwmod omap44xx_timer6_hwmod = {
3263         .name           = "timer6",
3264         .class          = &omap44xx_timer_hwmod_class,
3265         .clkdm_name     = "abe_clkdm",
3266         .mpu_irqs       = omap44xx_timer6_irqs,
3267         .main_clk       = "timer6_sync_mux",
3268         .prcm = {
3269                 .omap4 = {
3270                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3271                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3272                         .modulemode   = MODULEMODE_SWCTRL,
3273                 },
3274         },
3275         .dev_attr       = &capability_dsp_dev_attr,
3276 };
3277
3278 /* timer7 */
3279 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3280         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3281         { .irq = -1 }
3282 };
3283
3284 static struct omap_hwmod omap44xx_timer7_hwmod = {
3285         .name           = "timer7",
3286         .class          = &omap44xx_timer_hwmod_class,
3287         .clkdm_name     = "abe_clkdm",
3288         .mpu_irqs       = omap44xx_timer7_irqs,
3289         .main_clk       = "timer7_sync_mux",
3290         .prcm = {
3291                 .omap4 = {
3292                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3293                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3294                         .modulemode   = MODULEMODE_SWCTRL,
3295                 },
3296         },
3297         .dev_attr       = &capability_dsp_dev_attr,
3298 };
3299
3300 /* timer8 */
3301 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3302         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3303         { .irq = -1 }
3304 };
3305
3306 static struct omap_hwmod omap44xx_timer8_hwmod = {
3307         .name           = "timer8",
3308         .class          = &omap44xx_timer_hwmod_class,
3309         .clkdm_name     = "abe_clkdm",
3310         .mpu_irqs       = omap44xx_timer8_irqs,
3311         .main_clk       = "timer8_sync_mux",
3312         .prcm = {
3313                 .omap4 = {
3314                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3315                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3316                         .modulemode   = MODULEMODE_SWCTRL,
3317                 },
3318         },
3319         .dev_attr       = &capability_dsp_pwm_dev_attr,
3320 };
3321
3322 /* timer9 */
3323 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3324         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3325         { .irq = -1 }
3326 };
3327
3328 static struct omap_hwmod omap44xx_timer9_hwmod = {
3329         .name           = "timer9",
3330         .class          = &omap44xx_timer_hwmod_class,
3331         .clkdm_name     = "l4_per_clkdm",
3332         .mpu_irqs       = omap44xx_timer9_irqs,
3333         .main_clk       = "cm2_dm9_mux",
3334         .prcm = {
3335                 .omap4 = {
3336                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3337                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3338                         .modulemode   = MODULEMODE_SWCTRL,
3339                 },
3340         },
3341         .dev_attr       = &capability_pwm_dev_attr,
3342 };
3343
3344 /* timer10 */
3345 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3346         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3347         { .irq = -1 }
3348 };
3349
3350 static struct omap_hwmod omap44xx_timer10_hwmod = {
3351         .name           = "timer10",
3352         .class          = &omap44xx_timer_1ms_hwmod_class,
3353         .clkdm_name     = "l4_per_clkdm",
3354         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3355         .mpu_irqs       = omap44xx_timer10_irqs,
3356         .main_clk       = "cm2_dm10_mux",
3357         .prcm = {
3358                 .omap4 = {
3359                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3360                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3361                         .modulemode   = MODULEMODE_SWCTRL,
3362                 },
3363         },
3364         .dev_attr       = &capability_pwm_dev_attr,
3365 };
3366
3367 /* timer11 */
3368 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3369         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3370         { .irq = -1 }
3371 };
3372
3373 static struct omap_hwmod omap44xx_timer11_hwmod = {
3374         .name           = "timer11",
3375         .class          = &omap44xx_timer_hwmod_class,
3376         .clkdm_name     = "l4_per_clkdm",
3377         .mpu_irqs       = omap44xx_timer11_irqs,
3378         .main_clk       = "cm2_dm11_mux",
3379         .prcm = {
3380                 .omap4 = {
3381                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3382                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3383                         .modulemode   = MODULEMODE_SWCTRL,
3384                 },
3385         },
3386         .dev_attr       = &capability_pwm_dev_attr,
3387 };
3388
3389 /*
3390  * 'uart' class
3391  * universal asynchronous receiver/transmitter (uart)
3392  */
3393
3394 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3395         .rev_offs       = 0x0050,
3396         .sysc_offs      = 0x0054,
3397         .syss_offs      = 0x0058,
3398         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3399                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3400                            SYSS_HAS_RESET_STATUS),
3401         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3402                            SIDLE_SMART_WKUP),
3403         .sysc_fields    = &omap_hwmod_sysc_type1,
3404 };
3405
3406 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3407         .name   = "uart",
3408         .sysc   = &omap44xx_uart_sysc,
3409 };
3410
3411 /* uart1 */
3412 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3413         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3414         { .irq = -1 }
3415 };
3416
3417 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3418         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3419         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3420         { .dma_req = -1 }
3421 };
3422
3423 static struct omap_hwmod omap44xx_uart1_hwmod = {
3424         .name           = "uart1",
3425         .class          = &omap44xx_uart_hwmod_class,
3426         .clkdm_name     = "l4_per_clkdm",
3427         .mpu_irqs       = omap44xx_uart1_irqs,
3428         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3429         .main_clk       = "func_48m_fclk",
3430         .prcm = {
3431                 .omap4 = {
3432                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3433                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3434                         .modulemode   = MODULEMODE_SWCTRL,
3435                 },
3436         },
3437 };
3438
3439 /* uart2 */
3440 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3441         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3442         { .irq = -1 }
3443 };
3444
3445 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3446         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3447         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3448         { .dma_req = -1 }
3449 };
3450
3451 static struct omap_hwmod omap44xx_uart2_hwmod = {
3452         .name           = "uart2",
3453         .class          = &omap44xx_uart_hwmod_class,
3454         .clkdm_name     = "l4_per_clkdm",
3455         .mpu_irqs       = omap44xx_uart2_irqs,
3456         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3457         .main_clk       = "func_48m_fclk",
3458         .prcm = {
3459                 .omap4 = {
3460                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3461                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3462                         .modulemode   = MODULEMODE_SWCTRL,
3463                 },
3464         },
3465 };
3466
3467 /* uart3 */
3468 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3469         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3470         { .irq = -1 }
3471 };
3472
3473 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3474         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3475         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3476         { .dma_req = -1 }
3477 };
3478
3479 static struct omap_hwmod omap44xx_uart3_hwmod = {
3480         .name           = "uart3",
3481         .class          = &omap44xx_uart_hwmod_class,
3482         .clkdm_name     = "l4_per_clkdm",
3483         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3484         .mpu_irqs       = omap44xx_uart3_irqs,
3485         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3486         .main_clk       = "func_48m_fclk",
3487         .prcm = {
3488                 .omap4 = {
3489                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3490                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3491                         .modulemode   = MODULEMODE_SWCTRL,
3492                 },
3493         },
3494 };
3495
3496 /* uart4 */
3497 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3498         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3499         { .irq = -1 }
3500 };
3501
3502 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3503         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3504         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3505         { .dma_req = -1 }
3506 };
3507
3508 static struct omap_hwmod omap44xx_uart4_hwmod = {
3509         .name           = "uart4",
3510         .class          = &omap44xx_uart_hwmod_class,
3511         .clkdm_name     = "l4_per_clkdm",
3512         .mpu_irqs       = omap44xx_uart4_irqs,
3513         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3514         .main_clk       = "func_48m_fclk",
3515         .prcm = {
3516                 .omap4 = {
3517                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3518                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3519                         .modulemode   = MODULEMODE_SWCTRL,
3520                 },
3521         },
3522 };
3523
3524 /*
3525  * 'usb_host_fs' class
3526  * full-speed usb host controller
3527  */
3528
3529 /* The IP is not compliant to type1 / type2 scheme */
3530 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3531         .midle_shift    = 4,
3532         .sidle_shift    = 2,
3533         .srst_shift     = 1,
3534 };
3535
3536 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3537         .rev_offs       = 0x0000,
3538         .sysc_offs      = 0x0210,
3539         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3540                            SYSC_HAS_SOFTRESET),
3541         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3542                            SIDLE_SMART_WKUP),
3543         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3544 };
3545
3546 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3547         .name   = "usb_host_fs",
3548         .sysc   = &omap44xx_usb_host_fs_sysc,
3549 };
3550
3551 /* usb_host_fs */
3552 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3553         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3554         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3555         { .irq = -1 }
3556 };
3557
3558 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3559         .name           = "usb_host_fs",
3560         .class          = &omap44xx_usb_host_fs_hwmod_class,
3561         .clkdm_name     = "l3_init_clkdm",
3562         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3563         .main_clk       = "usb_host_fs_fck",
3564         .prcm = {
3565                 .omap4 = {
3566                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3567                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3568                         .modulemode   = MODULEMODE_SWCTRL,
3569                 },
3570         },
3571 };
3572
3573 /*
3574  * 'usb_host_hs' class
3575  * high-speed multi-port usb host controller
3576  */
3577
3578 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3579         .rev_offs       = 0x0000,
3580         .sysc_offs      = 0x0010,
3581         .syss_offs      = 0x0014,
3582         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3583                            SYSC_HAS_SOFTRESET),
3584         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3585                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3586                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3587         .sysc_fields    = &omap_hwmod_sysc_type2,
3588 };
3589
3590 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3591         .name   = "usb_host_hs",
3592         .sysc   = &omap44xx_usb_host_hs_sysc,
3593 };
3594
3595 /* usb_host_hs */
3596 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3597         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3598         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3599         { .irq = -1 }
3600 };
3601
3602 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3603         .name           = "usb_host_hs",
3604         .class          = &omap44xx_usb_host_hs_hwmod_class,
3605         .clkdm_name     = "l3_init_clkdm",
3606         .main_clk       = "usb_host_hs_fck",
3607         .prcm = {
3608                 .omap4 = {
3609                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3610                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3611                         .modulemode   = MODULEMODE_SWCTRL,
3612                 },
3613         },
3614         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3615
3616         /*
3617          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3618          * id: i660
3619          *
3620          * Description:
3621          * In the following configuration :
3622          * - USBHOST module is set to smart-idle mode
3623          * - PRCM asserts idle_req to the USBHOST module ( This typically
3624          *   happens when the system is going to a low power mode : all ports
3625          *   have been suspended, the master part of the USBHOST module has
3626          *   entered the standby state, and SW has cut the functional clocks)
3627          * - an USBHOST interrupt occurs before the module is able to answer
3628          *   idle_ack, typically a remote wakeup IRQ.
3629          * Then the USB HOST module will enter a deadlock situation where it
3630          * is no more accessible nor functional.
3631          *
3632          * Workaround:
3633          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3634          */
3635
3636         /*
3637          * Errata: USB host EHCI may stall when entering smart-standby mode
3638          * Id: i571
3639          *
3640          * Description:
3641          * When the USBHOST module is set to smart-standby mode, and when it is
3642          * ready to enter the standby state (i.e. all ports are suspended and
3643          * all attached devices are in suspend mode), then it can wrongly assert
3644          * the Mstandby signal too early while there are still some residual OCP
3645          * transactions ongoing. If this condition occurs, the internal state
3646          * machine may go to an undefined state and the USB link may be stuck
3647          * upon the next resume.
3648          *
3649          * Workaround:
3650          * Don't use smart standby; use only force standby,
3651          * hence HWMOD_SWSUP_MSTANDBY
3652          */
3653
3654         /*
3655          * During system boot; If the hwmod framework resets the module
3656          * the module will have smart idle settings; which can lead to deadlock
3657          * (above Errata Id:i660); so, dont reset the module during boot;
3658          * Use HWMOD_INIT_NO_RESET.
3659          */
3660
3661         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3662                           HWMOD_INIT_NO_RESET,
3663 };
3664
3665 /*
3666  * 'usb_otg_hs' class
3667  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3668  */
3669
3670 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3671         .rev_offs       = 0x0400,
3672         .sysc_offs      = 0x0404,
3673         .syss_offs      = 0x0408,
3674         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3675                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3676                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3677         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3678                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3679                            MSTANDBY_SMART),
3680         .sysc_fields    = &omap_hwmod_sysc_type1,
3681 };
3682
3683 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3684         .name   = "usb_otg_hs",
3685         .sysc   = &omap44xx_usb_otg_hs_sysc,
3686 };
3687
3688 /* usb_otg_hs */
3689 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3690         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3691         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3692         { .irq = -1 }
3693 };
3694
3695 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3696         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3697 };
3698
3699 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3700         .name           = "usb_otg_hs",
3701         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3702         .clkdm_name     = "l3_init_clkdm",
3703         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3704         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3705         .main_clk       = "usb_otg_hs_ick",
3706         .prcm = {
3707                 .omap4 = {
3708                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3709                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3710                         .modulemode   = MODULEMODE_HWCTRL,
3711                 },
3712         },
3713         .opt_clks       = usb_otg_hs_opt_clks,
3714         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3715 };
3716
3717 /*
3718  * 'usb_tll_hs' class
3719  * usb_tll_hs module is the adapter on the usb_host_hs ports
3720  */
3721
3722 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3723         .rev_offs       = 0x0000,
3724         .sysc_offs      = 0x0010,
3725         .syss_offs      = 0x0014,
3726         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3727                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3728                            SYSC_HAS_AUTOIDLE),
3729         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3730         .sysc_fields    = &omap_hwmod_sysc_type1,
3731 };
3732
3733 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3734         .name   = "usb_tll_hs",
3735         .sysc   = &omap44xx_usb_tll_hs_sysc,
3736 };
3737
3738 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3739         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3740         { .irq = -1 }
3741 };
3742
3743 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3744         .name           = "usb_tll_hs",
3745         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3746         .clkdm_name     = "l3_init_clkdm",
3747         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3748         .main_clk       = "usb_tll_hs_ick",
3749         .prcm = {
3750                 .omap4 = {
3751                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3752                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3753                         .modulemode   = MODULEMODE_HWCTRL,
3754                 },
3755         },
3756 };
3757
3758 /*
3759  * 'wd_timer' class
3760  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3761  * overflow condition
3762  */
3763
3764 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3765         .rev_offs       = 0x0000,
3766         .sysc_offs      = 0x0010,
3767         .syss_offs      = 0x0014,
3768         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3769                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3770         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3771                            SIDLE_SMART_WKUP),
3772         .sysc_fields    = &omap_hwmod_sysc_type1,
3773 };
3774
3775 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3776         .name           = "wd_timer",
3777         .sysc           = &omap44xx_wd_timer_sysc,
3778         .pre_shutdown   = &omap2_wd_timer_disable,
3779         .reset          = &omap2_wd_timer_reset,
3780 };
3781
3782 /* wd_timer2 */
3783 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3784         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3785         { .irq = -1 }
3786 };
3787
3788 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3789         .name           = "wd_timer2",
3790         .class          = &omap44xx_wd_timer_hwmod_class,
3791         .clkdm_name     = "l4_wkup_clkdm",
3792         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3793         .main_clk       = "sys_32k_ck",
3794         .prcm = {
3795                 .omap4 = {
3796                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3797                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3798                         .modulemode   = MODULEMODE_SWCTRL,
3799                 },
3800         },
3801 };
3802
3803 /* wd_timer3 */
3804 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3805         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3806         { .irq = -1 }
3807 };
3808
3809 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3810         .name           = "wd_timer3",
3811         .class          = &omap44xx_wd_timer_hwmod_class,
3812         .clkdm_name     = "abe_clkdm",
3813         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3814         .main_clk       = "sys_32k_ck",
3815         .prcm = {
3816                 .omap4 = {
3817                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3818                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3819                         .modulemode   = MODULEMODE_SWCTRL,
3820                 },
3821         },
3822 };
3823
3824
3825 /*
3826  * interfaces
3827  */
3828
3829 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3830         {
3831                 .pa_start       = 0x4a204000,
3832                 .pa_end         = 0x4a2040ff,
3833                 .flags          = ADDR_TYPE_RT
3834         },
3835         { }
3836 };
3837
3838 /* c2c -> c2c_target_fw */
3839 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3840         .master         = &omap44xx_c2c_hwmod,
3841         .slave          = &omap44xx_c2c_target_fw_hwmod,
3842         .clk            = "div_core_ck",
3843         .addr           = omap44xx_c2c_target_fw_addrs,
3844         .user           = OCP_USER_MPU,
3845 };
3846
3847 /* l4_cfg -> c2c_target_fw */
3848 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3849         .master         = &omap44xx_l4_cfg_hwmod,
3850         .slave          = &omap44xx_c2c_target_fw_hwmod,
3851         .clk            = "l4_div_ck",
3852         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3853 };
3854
3855 /* l3_main_1 -> dmm */
3856 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3857         .master         = &omap44xx_l3_main_1_hwmod,
3858         .slave          = &omap44xx_dmm_hwmod,
3859         .clk            = "l3_div_ck",
3860         .user           = OCP_USER_SDMA,
3861 };
3862
3863 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3864         {
3865                 .pa_start       = 0x4e000000,
3866                 .pa_end         = 0x4e0007ff,
3867                 .flags          = ADDR_TYPE_RT
3868         },
3869         { }
3870 };
3871
3872 /* mpu -> dmm */
3873 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3874         .master         = &omap44xx_mpu_hwmod,
3875         .slave          = &omap44xx_dmm_hwmod,
3876         .clk            = "l3_div_ck",
3877         .addr           = omap44xx_dmm_addrs,
3878         .user           = OCP_USER_MPU,
3879 };
3880
3881 /* c2c -> emif_fw */
3882 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3883         .master         = &omap44xx_c2c_hwmod,
3884         .slave          = &omap44xx_emif_fw_hwmod,
3885         .clk            = "div_core_ck",
3886         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3887 };
3888
3889 /* dmm -> emif_fw */
3890 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3891         .master         = &omap44xx_dmm_hwmod,
3892         .slave          = &omap44xx_emif_fw_hwmod,
3893         .clk            = "l3_div_ck",
3894         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3895 };
3896
3897 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3898         {
3899                 .pa_start       = 0x4a20c000,
3900                 .pa_end         = 0x4a20c0ff,
3901                 .flags          = ADDR_TYPE_RT
3902         },
3903         { }
3904 };
3905
3906 /* l4_cfg -> emif_fw */
3907 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3908         .master         = &omap44xx_l4_cfg_hwmod,
3909         .slave          = &omap44xx_emif_fw_hwmod,
3910         .clk            = "l4_div_ck",
3911         .addr           = omap44xx_emif_fw_addrs,
3912         .user           = OCP_USER_MPU,
3913 };
3914
3915 /* iva -> l3_instr */
3916 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3917         .master         = &omap44xx_iva_hwmod,
3918         .slave          = &omap44xx_l3_instr_hwmod,
3919         .clk            = "l3_div_ck",
3920         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3921 };
3922
3923 /* l3_main_3 -> l3_instr */
3924 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3925         .master         = &omap44xx_l3_main_3_hwmod,
3926         .slave          = &omap44xx_l3_instr_hwmod,
3927         .clk            = "l3_div_ck",
3928         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3929 };
3930
3931 /* ocp_wp_noc -> l3_instr */
3932 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3933         .master         = &omap44xx_ocp_wp_noc_hwmod,
3934         .slave          = &omap44xx_l3_instr_hwmod,
3935         .clk            = "l3_div_ck",
3936         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3937 };
3938
3939 /* dsp -> l3_main_1 */
3940 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3941         .master         = &omap44xx_dsp_hwmod,
3942         .slave          = &omap44xx_l3_main_1_hwmod,
3943         .clk            = "l3_div_ck",
3944         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3945 };
3946
3947 /* dss -> l3_main_1 */
3948 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3949         .master         = &omap44xx_dss_hwmod,
3950         .slave          = &omap44xx_l3_main_1_hwmod,
3951         .clk            = "l3_div_ck",
3952         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3953 };
3954
3955 /* l3_main_2 -> l3_main_1 */
3956 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3957         .master         = &omap44xx_l3_main_2_hwmod,
3958         .slave          = &omap44xx_l3_main_1_hwmod,
3959         .clk            = "l3_div_ck",
3960         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3961 };
3962
3963 /* l4_cfg -> l3_main_1 */
3964 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3965         .master         = &omap44xx_l4_cfg_hwmod,
3966         .slave          = &omap44xx_l3_main_1_hwmod,
3967         .clk            = "l4_div_ck",
3968         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3969 };
3970
3971 /* mmc1 -> l3_main_1 */
3972 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3973         .master         = &omap44xx_mmc1_hwmod,
3974         .slave          = &omap44xx_l3_main_1_hwmod,
3975         .clk            = "l3_div_ck",
3976         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3977 };
3978
3979 /* mmc2 -> l3_main_1 */
3980 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3981         .master         = &omap44xx_mmc2_hwmod,
3982         .slave          = &omap44xx_l3_main_1_hwmod,
3983         .clk            = "l3_div_ck",
3984         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3985 };
3986
3987 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3988         {
3989                 .pa_start       = 0x44000000,
3990                 .pa_end         = 0x44000fff,
3991                 .flags          = ADDR_TYPE_RT
3992         },
3993         { }
3994 };
3995
3996 /* mpu -> l3_main_1 */
3997 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3998         .master         = &omap44xx_mpu_hwmod,
3999         .slave          = &omap44xx_l3_main_1_hwmod,
4000         .clk            = "l3_div_ck",
4001         .addr           = omap44xx_l3_main_1_addrs,
4002         .user           = OCP_USER_MPU,
4003 };
4004
4005 /* c2c_target_fw -> l3_main_2 */
4006 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
4007         .master         = &omap44xx_c2c_target_fw_hwmod,
4008         .slave          = &omap44xx_l3_main_2_hwmod,
4009         .clk            = "l3_div_ck",
4010         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4011 };
4012
4013 /* debugss -> l3_main_2 */
4014 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
4015         .master         = &omap44xx_debugss_hwmod,
4016         .slave          = &omap44xx_l3_main_2_hwmod,
4017         .clk            = "dbgclk_mux_ck",
4018         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4019 };
4020
4021 /* dma_system -> l3_main_2 */
4022 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
4023         .master         = &omap44xx_dma_system_hwmod,
4024         .slave          = &omap44xx_l3_main_2_hwmod,
4025         .clk            = "l3_div_ck",
4026         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4027 };
4028
4029 /* fdif -> l3_main_2 */
4030 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
4031         .master         = &omap44xx_fdif_hwmod,
4032         .slave          = &omap44xx_l3_main_2_hwmod,
4033         .clk            = "l3_div_ck",
4034         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4035 };
4036
4037 /* gpu -> l3_main_2 */
4038 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
4039         .master         = &omap44xx_gpu_hwmod,
4040         .slave          = &omap44xx_l3_main_2_hwmod,
4041         .clk            = "l3_div_ck",
4042         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4043 };
4044
4045 /* hsi -> l3_main_2 */
4046 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
4047         .master         = &omap44xx_hsi_hwmod,
4048         .slave          = &omap44xx_l3_main_2_hwmod,
4049         .clk            = "l3_div_ck",
4050         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4051 };
4052
4053 /* ipu -> l3_main_2 */
4054 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
4055         .master         = &omap44xx_ipu_hwmod,
4056         .slave          = &omap44xx_l3_main_2_hwmod,
4057         .clk            = "l3_div_ck",
4058         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4059 };
4060
4061 /* iss -> l3_main_2 */
4062 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
4063         .master         = &omap44xx_iss_hwmod,
4064         .slave          = &omap44xx_l3_main_2_hwmod,
4065         .clk            = "l3_div_ck",
4066         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4067 };
4068
4069 /* iva -> l3_main_2 */
4070 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
4071         .master         = &omap44xx_iva_hwmod,
4072         .slave          = &omap44xx_l3_main_2_hwmod,
4073         .clk            = "l3_div_ck",
4074         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4075 };
4076
4077 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
4078         {
4079                 .pa_start       = 0x44800000,
4080                 .pa_end         = 0x44801fff,
4081                 .flags          = ADDR_TYPE_RT
4082         },
4083         { }
4084 };
4085
4086 /* l3_main_1 -> l3_main_2 */
4087 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
4088         .master         = &omap44xx_l3_main_1_hwmod,
4089         .slave          = &omap44xx_l3_main_2_hwmod,
4090         .clk            = "l3_div_ck",
4091         .addr           = omap44xx_l3_main_2_addrs,
4092         .user           = OCP_USER_MPU,
4093 };
4094
4095 /* l4_cfg -> l3_main_2 */
4096 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
4097         .master         = &omap44xx_l4_cfg_hwmod,
4098         .slave          = &omap44xx_l3_main_2_hwmod,
4099         .clk            = "l4_div_ck",
4100         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4101 };
4102
4103 /* usb_host_fs -> l3_main_2 */
4104 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
4105         .master         = &omap44xx_usb_host_fs_hwmod,
4106         .slave          = &omap44xx_l3_main_2_hwmod,
4107         .clk            = "l3_div_ck",
4108         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4109 };
4110
4111 /* usb_host_hs -> l3_main_2 */
4112 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
4113         .master         = &omap44xx_usb_host_hs_hwmod,
4114         .slave          = &omap44xx_l3_main_2_hwmod,
4115         .clk            = "l3_div_ck",
4116         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4117 };
4118
4119 /* usb_otg_hs -> l3_main_2 */
4120 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
4121         .master         = &omap44xx_usb_otg_hs_hwmod,
4122         .slave          = &omap44xx_l3_main_2_hwmod,
4123         .clk            = "l3_div_ck",
4124         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4125 };
4126
4127 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
4128         {
4129                 .pa_start       = 0x45000000,
4130                 .pa_end         = 0x45000fff,
4131                 .flags          = ADDR_TYPE_RT
4132         },
4133         { }
4134 };
4135
4136 /* l3_main_1 -> l3_main_3 */
4137 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
4138         .master         = &omap44xx_l3_main_1_hwmod,
4139         .slave          = &omap44xx_l3_main_3_hwmod,
4140         .clk            = "l3_div_ck",
4141         .addr           = omap44xx_l3_main_3_addrs,
4142         .user           = OCP_USER_MPU,
4143 };
4144
4145 /* l3_main_2 -> l3_main_3 */
4146 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
4147         .master         = &omap44xx_l3_main_2_hwmod,
4148         .slave          = &omap44xx_l3_main_3_hwmod,
4149         .clk            = "l3_div_ck",
4150         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4151 };
4152
4153 /* l4_cfg -> l3_main_3 */
4154 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
4155         .master         = &omap44xx_l4_cfg_hwmod,
4156         .slave          = &omap44xx_l3_main_3_hwmod,
4157         .clk            = "l4_div_ck",
4158         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4159 };
4160
4161 /* aess -> l4_abe */
4162 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
4163         .master         = &omap44xx_aess_hwmod,
4164         .slave          = &omap44xx_l4_abe_hwmod,
4165         .clk            = "ocp_abe_iclk",
4166         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4167 };
4168
4169 /* dsp -> l4_abe */
4170 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
4171         .master         = &omap44xx_dsp_hwmod,
4172         .slave          = &omap44xx_l4_abe_hwmod,
4173         .clk            = "ocp_abe_iclk",
4174         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4175 };
4176
4177 /* l3_main_1 -> l4_abe */
4178 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
4179         .master         = &omap44xx_l3_main_1_hwmod,
4180         .slave          = &omap44xx_l4_abe_hwmod,
4181         .clk            = "l3_div_ck",
4182         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4183 };
4184
4185 /* mpu -> l4_abe */
4186 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
4187         .master         = &omap44xx_mpu_hwmod,
4188         .slave          = &omap44xx_l4_abe_hwmod,
4189         .clk            = "ocp_abe_iclk",
4190         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4191 };
4192
4193 /* l3_main_1 -> l4_cfg */
4194 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
4195         .master         = &omap44xx_l3_main_1_hwmod,
4196         .slave          = &omap44xx_l4_cfg_hwmod,
4197         .clk            = "l3_div_ck",
4198         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4199 };
4200
4201 /* l3_main_2 -> l4_per */
4202 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
4203         .master         = &omap44xx_l3_main_2_hwmod,
4204         .slave          = &omap44xx_l4_per_hwmod,
4205         .clk            = "l3_div_ck",
4206         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4207 };
4208
4209 /* l4_cfg -> l4_wkup */
4210 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
4211         .master         = &omap44xx_l4_cfg_hwmod,
4212         .slave          = &omap44xx_l4_wkup_hwmod,
4213         .clk            = "l4_div_ck",
4214         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4215 };
4216
4217 /* mpu -> mpu_private */
4218 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4219         .master         = &omap44xx_mpu_hwmod,
4220         .slave          = &omap44xx_mpu_private_hwmod,
4221         .clk            = "l3_div_ck",
4222         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4223 };
4224
4225 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4226         {
4227                 .pa_start       = 0x4a102000,
4228                 .pa_end         = 0x4a10207f,
4229                 .flags          = ADDR_TYPE_RT
4230         },
4231         { }
4232 };
4233
4234 /* l4_cfg -> ocp_wp_noc */
4235 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4236         .master         = &omap44xx_l4_cfg_hwmod,
4237         .slave          = &omap44xx_ocp_wp_noc_hwmod,
4238         .clk            = "l4_div_ck",
4239         .addr           = omap44xx_ocp_wp_noc_addrs,
4240         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4241 };
4242
4243 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4244         {
4245                 .name           = "dmem",
4246                 .pa_start       = 0x40180000,
4247                 .pa_end         = 0x4018ffff
4248         },
4249         {
4250                 .name           = "cmem",
4251                 .pa_start       = 0x401a0000,
4252                 .pa_end         = 0x401a1fff
4253         },
4254         {
4255                 .name           = "smem",
4256                 .pa_start       = 0x401c0000,
4257                 .pa_end         = 0x401c5fff
4258         },
4259         {
4260                 .name           = "pmem",
4261                 .pa_start       = 0x401e0000,
4262                 .pa_end         = 0x401e1fff
4263         },
4264         {
4265                 .name           = "mpu",
4266                 .pa_start       = 0x401f1000,
4267                 .pa_end         = 0x401f13ff,
4268                 .flags          = ADDR_TYPE_RT
4269         },
4270         { }
4271 };
4272
4273 /* l4_abe -> aess */
4274 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4275         .master         = &omap44xx_l4_abe_hwmod,
4276         .slave          = &omap44xx_aess_hwmod,
4277         .clk            = "ocp_abe_iclk",
4278         .addr           = omap44xx_aess_addrs,
4279         .user           = OCP_USER_MPU,
4280 };
4281
4282 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4283         {
4284                 .name           = "dmem_dma",
4285                 .pa_start       = 0x49080000,
4286                 .pa_end         = 0x4908ffff
4287         },
4288         {
4289                 .name           = "cmem_dma",
4290                 .pa_start       = 0x490a0000,
4291                 .pa_end         = 0x490a1fff
4292         },
4293         {
4294                 .name           = "smem_dma",
4295                 .pa_start       = 0x490c0000,
4296                 .pa_end         = 0x490c5fff
4297         },
4298         {
4299                 .name           = "pmem_dma",
4300                 .pa_start       = 0x490e0000,
4301                 .pa_end         = 0x490e1fff
4302         },
4303         {
4304                 .name           = "dma",
4305                 .pa_start       = 0x490f1000,
4306                 .pa_end         = 0x490f13ff,
4307                 .flags          = ADDR_TYPE_RT
4308         },
4309         { }
4310 };
4311
4312 /* l4_abe -> aess (dma) */
4313 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4314         .master         = &omap44xx_l4_abe_hwmod,
4315         .slave          = &omap44xx_aess_hwmod,
4316         .clk            = "ocp_abe_iclk",
4317         .addr           = omap44xx_aess_dma_addrs,
4318         .user           = OCP_USER_SDMA,
4319 };
4320
4321 /* l3_main_2 -> c2c */
4322 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4323         .master         = &omap44xx_l3_main_2_hwmod,
4324         .slave          = &omap44xx_c2c_hwmod,
4325         .clk            = "l3_div_ck",
4326         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4327 };
4328
4329 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4330         {
4331                 .pa_start       = 0x4a304000,
4332                 .pa_end         = 0x4a30401f,
4333                 .flags          = ADDR_TYPE_RT
4334         },
4335         { }
4336 };
4337
4338 /* l4_wkup -> counter_32k */
4339 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4340         .master         = &omap44xx_l4_wkup_hwmod,
4341         .slave          = &omap44xx_counter_32k_hwmod,
4342         .clk            = "l4_wkup_clk_mux_ck",
4343         .addr           = omap44xx_counter_32k_addrs,
4344         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4345 };
4346
4347 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4348         {
4349                 .pa_start       = 0x4a002000,
4350                 .pa_end         = 0x4a0027ff,
4351                 .flags          = ADDR_TYPE_RT
4352         },
4353         { }
4354 };
4355
4356 /* l4_cfg -> ctrl_module_core */
4357 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4358         .master         = &omap44xx_l4_cfg_hwmod,
4359         .slave          = &omap44xx_ctrl_module_core_hwmod,
4360         .clk            = "l4_div_ck",
4361         .addr           = omap44xx_ctrl_module_core_addrs,
4362         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4363 };
4364
4365 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4366         {
4367                 .pa_start       = 0x4a100000,
4368                 .pa_end         = 0x4a1007ff,
4369                 .flags          = ADDR_TYPE_RT
4370         },
4371         { }
4372 };
4373
4374 /* l4_cfg -> ctrl_module_pad_core */
4375 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4376         .master         = &omap44xx_l4_cfg_hwmod,
4377         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4378         .clk            = "l4_div_ck",
4379         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4380         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4381 };
4382
4383 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4384         {
4385                 .pa_start       = 0x4a30c000,
4386                 .pa_end         = 0x4a30c7ff,
4387                 .flags          = ADDR_TYPE_RT
4388         },
4389         { }
4390 };
4391
4392 /* l4_wkup -> ctrl_module_wkup */
4393 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4394         .master         = &omap44xx_l4_wkup_hwmod,
4395         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4396         .clk            = "l4_wkup_clk_mux_ck",
4397         .addr           = omap44xx_ctrl_module_wkup_addrs,
4398         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4399 };
4400
4401 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4402         {
4403                 .pa_start       = 0x4a31e000,
4404                 .pa_end         = 0x4a31e7ff,
4405                 .flags          = ADDR_TYPE_RT
4406         },
4407         { }
4408 };
4409
4410 /* l4_wkup -> ctrl_module_pad_wkup */
4411 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4412         .master         = &omap44xx_l4_wkup_hwmod,
4413         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4414         .clk            = "l4_wkup_clk_mux_ck",
4415         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4416         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4417 };
4418
4419 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4420         {
4421                 .pa_start       = 0x54160000,
4422                 .pa_end         = 0x54167fff,
4423                 .flags          = ADDR_TYPE_RT
4424         },
4425         { }
4426 };
4427
4428 /* l3_instr -> debugss */
4429 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4430         .master         = &omap44xx_l3_instr_hwmod,
4431         .slave          = &omap44xx_debugss_hwmod,
4432         .clk            = "l3_div_ck",
4433         .addr           = omap44xx_debugss_addrs,
4434         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4435 };
4436
4437 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4438         {
4439                 .pa_start       = 0x4a056000,
4440                 .pa_end         = 0x4a056fff,
4441                 .flags          = ADDR_TYPE_RT
4442         },
4443         { }
4444 };
4445
4446 /* l4_cfg -> dma_system */
4447 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4448         .master         = &omap44xx_l4_cfg_hwmod,
4449         .slave          = &omap44xx_dma_system_hwmod,
4450         .clk            = "l4_div_ck",
4451         .addr           = omap44xx_dma_system_addrs,
4452         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4453 };
4454
4455 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4456         {
4457                 .name           = "mpu",
4458                 .pa_start       = 0x4012e000,
4459                 .pa_end         = 0x4012e07f,
4460                 .flags          = ADDR_TYPE_RT
4461         },
4462         { }
4463 };
4464
4465 /* l4_abe -> dmic */
4466 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4467         .master         = &omap44xx_l4_abe_hwmod,
4468         .slave          = &omap44xx_dmic_hwmod,
4469         .clk            = "ocp_abe_iclk",
4470         .addr           = omap44xx_dmic_addrs,
4471         .user           = OCP_USER_MPU,
4472 };
4473
4474 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4475         {
4476                 .name           = "dma",
4477                 .pa_start       = 0x4902e000,
4478                 .pa_end         = 0x4902e07f,
4479                 .flags          = ADDR_TYPE_RT
4480         },
4481         { }
4482 };
4483
4484 /* l4_abe -> dmic (dma) */
4485 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4486         .master         = &omap44xx_l4_abe_hwmod,
4487         .slave          = &omap44xx_dmic_hwmod,
4488         .clk            = "ocp_abe_iclk",
4489         .addr           = omap44xx_dmic_dma_addrs,
4490         .user           = OCP_USER_SDMA,
4491 };
4492
4493 /* dsp -> iva */
4494 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4495         .master         = &omap44xx_dsp_hwmod,
4496         .slave          = &omap44xx_iva_hwmod,
4497         .clk            = "dpll_iva_m5x2_ck",
4498         .user           = OCP_USER_DSP,
4499 };
4500
4501 /* dsp -> sl2if */
4502 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4503         .master         = &omap44xx_dsp_hwmod,
4504         .slave          = &omap44xx_sl2if_hwmod,
4505         .clk            = "dpll_iva_m5x2_ck",
4506         .user           = OCP_USER_DSP,
4507 };
4508
4509 /* l4_cfg -> dsp */
4510 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4511         .master         = &omap44xx_l4_cfg_hwmod,
4512         .slave          = &omap44xx_dsp_hwmod,
4513         .clk            = "l4_div_ck",
4514         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4515 };
4516
4517 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4518         {
4519                 .pa_start       = 0x58000000,
4520                 .pa_end         = 0x5800007f,
4521                 .flags          = ADDR_TYPE_RT
4522         },
4523         { }
4524 };
4525
4526 /* l3_main_2 -> dss */
4527 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4528         .master         = &omap44xx_l3_main_2_hwmod,
4529         .slave          = &omap44xx_dss_hwmod,
4530         .clk            = "dss_fck",
4531         .addr           = omap44xx_dss_dma_addrs,
4532         .user           = OCP_USER_SDMA,
4533 };
4534
4535 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4536         {
4537                 .pa_start       = 0x48040000,
4538                 .pa_end         = 0x4804007f,
4539                 .flags          = ADDR_TYPE_RT
4540         },
4541         { }
4542 };
4543
4544 /* l4_per -> dss */
4545 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4546         .master         = &omap44xx_l4_per_hwmod,
4547         .slave          = &omap44xx_dss_hwmod,
4548         .clk            = "l4_div_ck",
4549         .addr           = omap44xx_dss_addrs,
4550         .user           = OCP_USER_MPU,
4551 };
4552
4553 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4554         {
4555                 .pa_start       = 0x58001000,
4556                 .pa_end         = 0x58001fff,
4557                 .flags          = ADDR_TYPE_RT
4558         },
4559         { }
4560 };
4561
4562 /* l3_main_2 -> dss_dispc */
4563 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4564         .master         = &omap44xx_l3_main_2_hwmod,
4565         .slave          = &omap44xx_dss_dispc_hwmod,
4566         .clk            = "dss_fck",
4567         .addr           = omap44xx_dss_dispc_dma_addrs,
4568         .user           = OCP_USER_SDMA,
4569 };
4570
4571 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4572         {
4573                 .pa_start       = 0x48041000,
4574                 .pa_end         = 0x48041fff,
4575                 .flags          = ADDR_TYPE_RT
4576         },
4577         { }
4578 };
4579
4580 /* l4_per -> dss_dispc */
4581 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4582         .master         = &omap44xx_l4_per_hwmod,
4583         .slave          = &omap44xx_dss_dispc_hwmod,
4584         .clk            = "l4_div_ck",
4585         .addr           = omap44xx_dss_dispc_addrs,
4586         .user           = OCP_USER_MPU,
4587 };
4588
4589 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4590         {
4591                 .pa_start       = 0x58004000,
4592                 .pa_end         = 0x580041ff,
4593                 .flags          = ADDR_TYPE_RT
4594         },
4595         { }
4596 };
4597
4598 /* l3_main_2 -> dss_dsi1 */
4599 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4600         .master         = &omap44xx_l3_main_2_hwmod,
4601         .slave          = &omap44xx_dss_dsi1_hwmod,
4602         .clk            = "dss_fck",
4603         .addr           = omap44xx_dss_dsi1_dma_addrs,
4604         .user           = OCP_USER_SDMA,
4605 };
4606
4607 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4608         {
4609                 .pa_start       = 0x48044000,
4610                 .pa_end         = 0x480441ff,
4611                 .flags          = ADDR_TYPE_RT
4612         },
4613         { }
4614 };
4615
4616 /* l4_per -> dss_dsi1 */
4617 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4618         .master         = &omap44xx_l4_per_hwmod,
4619         .slave          = &omap44xx_dss_dsi1_hwmod,
4620         .clk            = "l4_div_ck",
4621         .addr           = omap44xx_dss_dsi1_addrs,
4622         .user           = OCP_USER_MPU,
4623 };
4624
4625 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4626         {
4627                 .pa_start       = 0x58005000,
4628                 .pa_end         = 0x580051ff,
4629                 .flags          = ADDR_TYPE_RT
4630         },
4631         { }
4632 };
4633
4634 /* l3_main_2 -> dss_dsi2 */
4635 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4636         .master         = &omap44xx_l3_main_2_hwmod,
4637         .slave          = &omap44xx_dss_dsi2_hwmod,
4638         .clk            = "dss_fck",
4639         .addr           = omap44xx_dss_dsi2_dma_addrs,
4640         .user           = OCP_USER_SDMA,
4641 };
4642
4643 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4644         {
4645                 .pa_start       = 0x48045000,
4646                 .pa_end         = 0x480451ff,
4647                 .flags          = ADDR_TYPE_RT
4648         },
4649         { }
4650 };
4651
4652 /* l4_per -> dss_dsi2 */
4653 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4654         .master         = &omap44xx_l4_per_hwmod,
4655         .slave          = &omap44xx_dss_dsi2_hwmod,
4656         .clk            = "l4_div_ck",
4657         .addr           = omap44xx_dss_dsi2_addrs,
4658         .user           = OCP_USER_MPU,
4659 };
4660
4661 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4662         {
4663                 .pa_start       = 0x58006000,
4664                 .pa_end         = 0x58006fff,
4665                 .flags          = ADDR_TYPE_RT
4666         },
4667         { }
4668 };
4669
4670 /* l3_main_2 -> dss_hdmi */
4671 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4672         .master         = &omap44xx_l3_main_2_hwmod,
4673         .slave          = &omap44xx_dss_hdmi_hwmod,
4674         .clk            = "dss_fck",
4675         .addr           = omap44xx_dss_hdmi_dma_addrs,
4676         .user           = OCP_USER_SDMA,
4677 };
4678
4679 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4680         {
4681                 .pa_start       = 0x48046000,
4682                 .pa_end         = 0x48046fff,
4683                 .flags          = ADDR_TYPE_RT
4684         },
4685         { }
4686 };
4687
4688 /* l4_per -> dss_hdmi */
4689 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4690         .master         = &omap44xx_l4_per_hwmod,
4691         .slave          = &omap44xx_dss_hdmi_hwmod,
4692         .clk            = "l4_div_ck",
4693         .addr           = omap44xx_dss_hdmi_addrs,
4694         .user           = OCP_USER_MPU,
4695 };
4696
4697 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4698         {
4699                 .pa_start       = 0x58002000,
4700                 .pa_end         = 0x580020ff,
4701                 .flags          = ADDR_TYPE_RT
4702         },
4703         { }
4704 };
4705
4706 /* l3_main_2 -> dss_rfbi */
4707 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4708         .master         = &omap44xx_l3_main_2_hwmod,
4709         .slave          = &omap44xx_dss_rfbi_hwmod,
4710         .clk            = "dss_fck",
4711         .addr           = omap44xx_dss_rfbi_dma_addrs,
4712         .user           = OCP_USER_SDMA,
4713 };
4714
4715 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4716         {
4717                 .pa_start       = 0x48042000,
4718                 .pa_end         = 0x480420ff,
4719                 .flags          = ADDR_TYPE_RT
4720         },
4721         { }
4722 };
4723
4724 /* l4_per -> dss_rfbi */
4725 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4726         .master         = &omap44xx_l4_per_hwmod,
4727         .slave          = &omap44xx_dss_rfbi_hwmod,
4728         .clk            = "l4_div_ck",
4729         .addr           = omap44xx_dss_rfbi_addrs,
4730         .user           = OCP_USER_MPU,
4731 };
4732
4733 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4734         {
4735                 .pa_start       = 0x58003000,
4736                 .pa_end         = 0x580030ff,
4737                 .flags          = ADDR_TYPE_RT
4738         },
4739         { }
4740 };
4741
4742 /* l3_main_2 -> dss_venc */
4743 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4744         .master         = &omap44xx_l3_main_2_hwmod,
4745         .slave          = &omap44xx_dss_venc_hwmod,
4746         .clk            = "dss_fck",
4747         .addr           = omap44xx_dss_venc_dma_addrs,
4748         .user           = OCP_USER_SDMA,
4749 };
4750
4751 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4752         {
4753                 .pa_start       = 0x48043000,
4754                 .pa_end         = 0x480430ff,
4755                 .flags          = ADDR_TYPE_RT
4756         },
4757         { }
4758 };
4759
4760 /* l4_per -> dss_venc */
4761 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4762         .master         = &omap44xx_l4_per_hwmod,
4763         .slave          = &omap44xx_dss_venc_hwmod,
4764         .clk            = "l4_div_ck",
4765         .addr           = omap44xx_dss_venc_addrs,
4766         .user           = OCP_USER_MPU,
4767 };
4768
4769 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4770         {
4771                 .pa_start       = 0x48078000,
4772                 .pa_end         = 0x48078fff,
4773                 .flags          = ADDR_TYPE_RT
4774         },
4775         { }
4776 };
4777
4778 /* l4_per -> elm */
4779 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4780         .master         = &omap44xx_l4_per_hwmod,
4781         .slave          = &omap44xx_elm_hwmod,
4782         .clk            = "l4_div_ck",
4783         .addr           = omap44xx_elm_addrs,
4784         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4785 };
4786
4787 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4788         {
4789                 .pa_start       = 0x4c000000,
4790                 .pa_end         = 0x4c0000ff,
4791                 .flags          = ADDR_TYPE_RT
4792         },
4793         { }
4794 };
4795
4796 /* emif_fw -> emif1 */
4797 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4798         .master         = &omap44xx_emif_fw_hwmod,
4799         .slave          = &omap44xx_emif1_hwmod,
4800         .clk            = "l3_div_ck",
4801         .addr           = omap44xx_emif1_addrs,
4802         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4803 };
4804
4805 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4806         {
4807                 .pa_start       = 0x4d000000,
4808                 .pa_end         = 0x4d0000ff,
4809                 .flags          = ADDR_TYPE_RT
4810         },
4811         { }
4812 };
4813
4814 /* emif_fw -> emif2 */
4815 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4816         .master         = &omap44xx_emif_fw_hwmod,
4817         .slave          = &omap44xx_emif2_hwmod,
4818         .clk            = "l3_div_ck",
4819         .addr           = omap44xx_emif2_addrs,
4820         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4821 };
4822
4823 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4824         {
4825                 .pa_start       = 0x4a10a000,
4826                 .pa_end         = 0x4a10a1ff,
4827                 .flags          = ADDR_TYPE_RT
4828         },
4829         { }
4830 };
4831
4832 /* l4_cfg -> fdif */
4833 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4834         .master         = &omap44xx_l4_cfg_hwmod,
4835         .slave          = &omap44xx_fdif_hwmod,
4836         .clk            = "l4_div_ck",
4837         .addr           = omap44xx_fdif_addrs,
4838         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4839 };
4840
4841 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4842         {
4843                 .pa_start       = 0x4a310000,
4844                 .pa_end         = 0x4a3101ff,
4845                 .flags          = ADDR_TYPE_RT
4846         },
4847         { }
4848 };
4849
4850 /* l4_wkup -> gpio1 */
4851 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4852         .master         = &omap44xx_l4_wkup_hwmod,
4853         .slave          = &omap44xx_gpio1_hwmod,
4854         .clk            = "l4_wkup_clk_mux_ck",
4855         .addr           = omap44xx_gpio1_addrs,
4856         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4857 };
4858
4859 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4860         {
4861                 .pa_start       = 0x48055000,
4862                 .pa_end         = 0x480551ff,
4863                 .flags          = ADDR_TYPE_RT
4864         },
4865         { }
4866 };
4867
4868 /* l4_per -> gpio2 */
4869 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4870         .master         = &omap44xx_l4_per_hwmod,
4871         .slave          = &omap44xx_gpio2_hwmod,
4872         .clk            = "l4_div_ck",
4873         .addr           = omap44xx_gpio2_addrs,
4874         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4875 };
4876
4877 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4878         {
4879                 .pa_start       = 0x48057000,
4880                 .pa_end         = 0x480571ff,
4881                 .flags          = ADDR_TYPE_RT
4882         },
4883         { }
4884 };
4885
4886 /* l4_per -> gpio3 */
4887 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4888         .master         = &omap44xx_l4_per_hwmod,
4889         .slave          = &omap44xx_gpio3_hwmod,
4890         .clk            = "l4_div_ck",
4891         .addr           = omap44xx_gpio3_addrs,
4892         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4893 };
4894
4895 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4896         {
4897                 .pa_start       = 0x48059000,
4898                 .pa_end         = 0x480591ff,
4899                 .flags          = ADDR_TYPE_RT
4900         },
4901         { }
4902 };
4903
4904 /* l4_per -> gpio4 */
4905 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4906         .master         = &omap44xx_l4_per_hwmod,
4907         .slave          = &omap44xx_gpio4_hwmod,
4908         .clk            = "l4_div_ck",
4909         .addr           = omap44xx_gpio4_addrs,
4910         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4911 };
4912
4913 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4914         {
4915                 .pa_start       = 0x4805b000,
4916                 .pa_end         = 0x4805b1ff,
4917                 .flags          = ADDR_TYPE_RT
4918         },
4919         { }
4920 };
4921
4922 /* l4_per -> gpio5 */
4923 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4924         .master         = &omap44xx_l4_per_hwmod,
4925         .slave          = &omap44xx_gpio5_hwmod,
4926         .clk            = "l4_div_ck",
4927         .addr           = omap44xx_gpio5_addrs,
4928         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4929 };
4930
4931 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4932         {
4933                 .pa_start       = 0x4805d000,
4934                 .pa_end         = 0x4805d1ff,
4935                 .flags          = ADDR_TYPE_RT
4936         },
4937         { }
4938 };
4939
4940 /* l4_per -> gpio6 */
4941 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4942         .master         = &omap44xx_l4_per_hwmod,
4943         .slave          = &omap44xx_gpio6_hwmod,
4944         .clk            = "l4_div_ck",
4945         .addr           = omap44xx_gpio6_addrs,
4946         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4947 };
4948
4949 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4950         {
4951                 .pa_start       = 0x50000000,
4952                 .pa_end         = 0x500003ff,
4953                 .flags          = ADDR_TYPE_RT
4954         },
4955         { }
4956 };
4957
4958 /* l3_main_2 -> gpmc */
4959 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4960         .master         = &omap44xx_l3_main_2_hwmod,
4961         .slave          = &omap44xx_gpmc_hwmod,
4962         .clk            = "l3_div_ck",
4963         .addr           = omap44xx_gpmc_addrs,
4964         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4965 };
4966
4967 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4968         {
4969                 .pa_start       = 0x56000000,
4970                 .pa_end         = 0x5600ffff,
4971                 .flags          = ADDR_TYPE_RT
4972         },
4973         { }
4974 };
4975
4976 /* l3_main_2 -> gpu */
4977 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4978         .master         = &omap44xx_l3_main_2_hwmod,
4979         .slave          = &omap44xx_gpu_hwmod,
4980         .clk            = "l3_div_ck",
4981         .addr           = omap44xx_gpu_addrs,
4982         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4983 };
4984
4985 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4986         {
4987                 .pa_start       = 0x480b2000,
4988                 .pa_end         = 0x480b201f,
4989                 .flags          = ADDR_TYPE_RT
4990         },
4991         { }
4992 };
4993
4994 /* l4_per -> hdq1w */
4995 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4996         .master         = &omap44xx_l4_per_hwmod,
4997         .slave          = &omap44xx_hdq1w_hwmod,
4998         .clk            = "l4_div_ck",
4999         .addr           = omap44xx_hdq1w_addrs,
5000         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5001 };
5002
5003 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
5004         {
5005                 .pa_start       = 0x4a058000,
5006                 .pa_end         = 0x4a05bfff,
5007                 .flags          = ADDR_TYPE_RT
5008         },
5009         { }
5010 };
5011
5012 /* l4_cfg -> hsi */
5013 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
5014         .master         = &omap44xx_l4_cfg_hwmod,
5015         .slave          = &omap44xx_hsi_hwmod,
5016         .clk            = "l4_div_ck",
5017         .addr           = omap44xx_hsi_addrs,
5018         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5019 };
5020
5021 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
5022         {
5023                 .pa_start       = 0x48070000,
5024                 .pa_end         = 0x480700ff,
5025                 .flags          = ADDR_TYPE_RT
5026         },
5027         { }
5028 };
5029
5030 /* l4_per -> i2c1 */
5031 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
5032         .master         = &omap44xx_l4_per_hwmod,
5033         .slave          = &omap44xx_i2c1_hwmod,
5034         .clk            = "l4_div_ck",
5035         .addr           = omap44xx_i2c1_addrs,
5036         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5037 };
5038
5039 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
5040         {
5041                 .pa_start       = 0x48072000,
5042                 .pa_end         = 0x480720ff,
5043                 .flags          = ADDR_TYPE_RT
5044         },
5045         { }
5046 };
5047
5048 /* l4_per -> i2c2 */
5049 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
5050         .master         = &omap44xx_l4_per_hwmod,
5051         .slave          = &omap44xx_i2c2_hwmod,
5052         .clk            = "l4_div_ck",
5053         .addr           = omap44xx_i2c2_addrs,
5054         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5055 };
5056
5057 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
5058         {
5059                 .pa_start       = 0x48060000,
5060                 .pa_end         = 0x480600ff,
5061                 .flags          = ADDR_TYPE_RT
5062         },
5063         { }
5064 };
5065
5066 /* l4_per -> i2c3 */
5067 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
5068         .master         = &omap44xx_l4_per_hwmod,
5069         .slave          = &omap44xx_i2c3_hwmod,
5070         .clk            = "l4_div_ck",
5071         .addr           = omap44xx_i2c3_addrs,
5072         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5073 };
5074
5075 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
5076         {
5077                 .pa_start       = 0x48350000,
5078                 .pa_end         = 0x483500ff,
5079                 .flags          = ADDR_TYPE_RT
5080         },
5081         { }
5082 };
5083
5084 /* l4_per -> i2c4 */
5085 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
5086         .master         = &omap44xx_l4_per_hwmod,
5087         .slave          = &omap44xx_i2c4_hwmod,
5088         .clk            = "l4_div_ck",
5089         .addr           = omap44xx_i2c4_addrs,
5090         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5091 };
5092
5093 /* l3_main_2 -> ipu */
5094 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
5095         .master         = &omap44xx_l3_main_2_hwmod,
5096         .slave          = &omap44xx_ipu_hwmod,
5097         .clk            = "l3_div_ck",
5098         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5099 };
5100
5101 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
5102         {
5103                 .pa_start       = 0x52000000,
5104                 .pa_end         = 0x520000ff,
5105                 .flags          = ADDR_TYPE_RT
5106         },
5107         { }
5108 };
5109
5110 /* l3_main_2 -> iss */
5111 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
5112         .master         = &omap44xx_l3_main_2_hwmod,
5113         .slave          = &omap44xx_iss_hwmod,
5114         .clk            = "l3_div_ck",
5115         .addr           = omap44xx_iss_addrs,
5116         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5117 };
5118
5119 /* iva -> sl2if */
5120 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
5121         .master         = &omap44xx_iva_hwmod,
5122         .slave          = &omap44xx_sl2if_hwmod,
5123         .clk            = "dpll_iva_m5x2_ck",
5124         .user           = OCP_USER_IVA,
5125 };
5126
5127 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
5128         {
5129                 .pa_start       = 0x5a000000,
5130                 .pa_end         = 0x5a07ffff,
5131                 .flags          = ADDR_TYPE_RT
5132         },
5133         { }
5134 };
5135
5136 /* l3_main_2 -> iva */
5137 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
5138         .master         = &omap44xx_l3_main_2_hwmod,
5139         .slave          = &omap44xx_iva_hwmod,
5140         .clk            = "l3_div_ck",
5141         .addr           = omap44xx_iva_addrs,
5142         .user           = OCP_USER_MPU,
5143 };
5144
5145 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
5146         {
5147                 .pa_start       = 0x4a31c000,
5148                 .pa_end         = 0x4a31c07f,
5149                 .flags          = ADDR_TYPE_RT
5150         },
5151         { }
5152 };
5153
5154 /* l4_wkup -> kbd */
5155 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
5156         .master         = &omap44xx_l4_wkup_hwmod,
5157         .slave          = &omap44xx_kbd_hwmod,
5158         .clk            = "l4_wkup_clk_mux_ck",
5159         .addr           = omap44xx_kbd_addrs,
5160         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5161 };
5162
5163 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
5164         {
5165                 .pa_start       = 0x4a0f4000,
5166                 .pa_end         = 0x4a0f41ff,
5167                 .flags          = ADDR_TYPE_RT
5168         },
5169         { }
5170 };
5171
5172 /* l4_cfg -> mailbox */
5173 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
5174         .master         = &omap44xx_l4_cfg_hwmod,
5175         .slave          = &omap44xx_mailbox_hwmod,
5176         .clk            = "l4_div_ck",
5177         .addr           = omap44xx_mailbox_addrs,
5178         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5179 };
5180
5181 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
5182         {
5183                 .pa_start       = 0x40128000,
5184                 .pa_end         = 0x401283ff,
5185                 .flags          = ADDR_TYPE_RT
5186         },
5187         { }
5188 };
5189
5190 /* l4_abe -> mcasp */
5191 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
5192         .master         = &omap44xx_l4_abe_hwmod,
5193         .slave          = &omap44xx_mcasp_hwmod,
5194         .clk            = "ocp_abe_iclk",
5195         .addr           = omap44xx_mcasp_addrs,
5196         .user           = OCP_USER_MPU,
5197 };
5198
5199 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
5200         {
5201                 .pa_start       = 0x49028000,
5202                 .pa_end         = 0x490283ff,
5203                 .flags          = ADDR_TYPE_RT
5204         },
5205         { }
5206 };
5207
5208 /* l4_abe -> mcasp (dma) */
5209 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
5210         .master         = &omap44xx_l4_abe_hwmod,
5211         .slave          = &omap44xx_mcasp_hwmod,
5212         .clk            = "ocp_abe_iclk",
5213         .addr           = omap44xx_mcasp_dma_addrs,
5214         .user           = OCP_USER_SDMA,
5215 };
5216
5217 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
5218         {
5219                 .name           = "mpu",
5220                 .pa_start       = 0x40122000,
5221                 .pa_end         = 0x401220ff,
5222                 .flags          = ADDR_TYPE_RT
5223         },
5224         { }
5225 };
5226
5227 /* l4_abe -> mcbsp1 */
5228 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
5229         .master         = &omap44xx_l4_abe_hwmod,
5230         .slave          = &omap44xx_mcbsp1_hwmod,
5231         .clk            = "ocp_abe_iclk",
5232         .addr           = omap44xx_mcbsp1_addrs,
5233         .user           = OCP_USER_MPU,
5234 };
5235
5236 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
5237         {
5238                 .name           = "dma",
5239                 .pa_start       = 0x49022000,
5240                 .pa_end         = 0x490220ff,
5241                 .flags          = ADDR_TYPE_RT
5242         },
5243         { }
5244 };
5245
5246 /* l4_abe -> mcbsp1 (dma) */
5247 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5248         .master         = &omap44xx_l4_abe_hwmod,
5249         .slave          = &omap44xx_mcbsp1_hwmod,
5250         .clk            = "ocp_abe_iclk",
5251         .addr           = omap44xx_mcbsp1_dma_addrs,
5252         .user           = OCP_USER_SDMA,
5253 };
5254
5255 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5256         {
5257                 .name           = "mpu",
5258                 .pa_start       = 0x40124000,
5259                 .pa_end         = 0x401240ff,
5260                 .flags          = ADDR_TYPE_RT
5261         },
5262         { }
5263 };
5264
5265 /* l4_abe -> mcbsp2 */
5266 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5267         .master         = &omap44xx_l4_abe_hwmod,
5268         .slave          = &omap44xx_mcbsp2_hwmod,
5269         .clk            = "ocp_abe_iclk",
5270         .addr           = omap44xx_mcbsp2_addrs,
5271         .user           = OCP_USER_MPU,
5272 };
5273
5274 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5275         {
5276                 .name           = "dma",
5277                 .pa_start       = 0x49024000,
5278                 .pa_end         = 0x490240ff,
5279                 .flags          = ADDR_TYPE_RT
5280         },
5281         { }
5282 };
5283
5284 /* l4_abe -> mcbsp2 (dma) */
5285 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5286         .master         = &omap44xx_l4_abe_hwmod,
5287         .slave          = &omap44xx_mcbsp2_hwmod,
5288         .clk            = "ocp_abe_iclk",
5289         .addr           = omap44xx_mcbsp2_dma_addrs,
5290         .user           = OCP_USER_SDMA,
5291 };
5292
5293 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5294         {
5295                 .name           = "mpu",
5296                 .pa_start       = 0x40126000,
5297                 .pa_end         = 0x401260ff,
5298                 .flags          = ADDR_TYPE_RT
5299         },
5300         { }
5301 };
5302
5303 /* l4_abe -> mcbsp3 */
5304 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5305         .master         = &omap44xx_l4_abe_hwmod,
5306         .slave          = &omap44xx_mcbsp3_hwmod,
5307         .clk            = "ocp_abe_iclk",
5308         .addr           = omap44xx_mcbsp3_addrs,
5309         .user           = OCP_USER_MPU,
5310 };
5311
5312 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5313         {
5314                 .name           = "dma",
5315                 .pa_start       = 0x49026000,
5316                 .pa_end         = 0x490260ff,
5317                 .flags          = ADDR_TYPE_RT
5318         },
5319         { }
5320 };
5321
5322 /* l4_abe -> mcbsp3 (dma) */
5323 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5324         .master         = &omap44xx_l4_abe_hwmod,
5325         .slave          = &omap44xx_mcbsp3_hwmod,
5326         .clk            = "ocp_abe_iclk",
5327         .addr           = omap44xx_mcbsp3_dma_addrs,
5328         .user           = OCP_USER_SDMA,
5329 };
5330
5331 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5332         {
5333                 .pa_start       = 0x48096000,
5334                 .pa_end         = 0x480960ff,
5335                 .flags          = ADDR_TYPE_RT
5336         },
5337         { }
5338 };
5339
5340 /* l4_per -> mcbsp4 */
5341 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5342         .master         = &omap44xx_l4_per_hwmod,
5343         .slave          = &omap44xx_mcbsp4_hwmod,
5344         .clk            = "l4_div_ck",
5345         .addr           = omap44xx_mcbsp4_addrs,
5346         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5347 };
5348
5349 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5350         {
5351                 .name           = "mpu",
5352                 .pa_start       = 0x40132000,
5353                 .pa_end         = 0x4013207f,
5354                 .flags          = ADDR_TYPE_RT
5355         },
5356         { }
5357 };
5358
5359 /* l4_abe -> mcpdm */
5360 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5361         .master         = &omap44xx_l4_abe_hwmod,
5362         .slave          = &omap44xx_mcpdm_hwmod,
5363         .clk            = "ocp_abe_iclk",
5364         .addr           = omap44xx_mcpdm_addrs,
5365         .user           = OCP_USER_MPU,
5366 };
5367
5368 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5369         {
5370                 .name           = "dma",
5371                 .pa_start       = 0x49032000,
5372                 .pa_end         = 0x4903207f,
5373                 .flags          = ADDR_TYPE_RT
5374         },
5375         { }
5376 };
5377
5378 /* l4_abe -> mcpdm (dma) */
5379 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5380         .master         = &omap44xx_l4_abe_hwmod,
5381         .slave          = &omap44xx_mcpdm_hwmod,
5382         .clk            = "ocp_abe_iclk",
5383         .addr           = omap44xx_mcpdm_dma_addrs,
5384         .user           = OCP_USER_SDMA,
5385 };
5386
5387 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5388         {
5389                 .pa_start       = 0x48098000,
5390                 .pa_end         = 0x480981ff,
5391                 .flags          = ADDR_TYPE_RT
5392         },
5393         { }
5394 };
5395
5396 /* l4_per -> mcspi1 */
5397 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5398         .master         = &omap44xx_l4_per_hwmod,
5399         .slave          = &omap44xx_mcspi1_hwmod,
5400         .clk            = "l4_div_ck",
5401         .addr           = omap44xx_mcspi1_addrs,
5402         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5403 };
5404
5405 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5406         {
5407                 .pa_start       = 0x4809a000,
5408                 .pa_end         = 0x4809a1ff,
5409                 .flags          = ADDR_TYPE_RT
5410         },
5411         { }
5412 };
5413
5414 /* l4_per -> mcspi2 */
5415 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5416         .master         = &omap44xx_l4_per_hwmod,
5417         .slave          = &omap44xx_mcspi2_hwmod,
5418         .clk            = "l4_div_ck",
5419         .addr           = omap44xx_mcspi2_addrs,
5420         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5421 };
5422
5423 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5424         {
5425                 .pa_start       = 0x480b8000,
5426                 .pa_end         = 0x480b81ff,
5427                 .flags          = ADDR_TYPE_RT
5428         },
5429         { }
5430 };
5431
5432 /* l4_per -> mcspi3 */
5433 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5434         .master         = &omap44xx_l4_per_hwmod,
5435         .slave          = &omap44xx_mcspi3_hwmod,
5436         .clk            = "l4_div_ck",
5437         .addr           = omap44xx_mcspi3_addrs,
5438         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5439 };
5440
5441 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5442         {
5443                 .pa_start       = 0x480ba000,
5444                 .pa_end         = 0x480ba1ff,
5445                 .flags          = ADDR_TYPE_RT
5446         },
5447         { }
5448 };
5449
5450 /* l4_per -> mcspi4 */
5451 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5452         .master         = &omap44xx_l4_per_hwmod,
5453         .slave          = &omap44xx_mcspi4_hwmod,
5454         .clk            = "l4_div_ck",
5455         .addr           = omap44xx_mcspi4_addrs,
5456         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5457 };
5458
5459 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5460         {
5461                 .pa_start       = 0x4809c000,
5462                 .pa_end         = 0x4809c3ff,
5463                 .flags          = ADDR_TYPE_RT
5464         },
5465         { }
5466 };
5467
5468 /* l4_per -> mmc1 */
5469 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5470         .master         = &omap44xx_l4_per_hwmod,
5471         .slave          = &omap44xx_mmc1_hwmod,
5472         .clk            = "l4_div_ck",
5473         .addr           = omap44xx_mmc1_addrs,
5474         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5475 };
5476
5477 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5478         {
5479                 .pa_start       = 0x480b4000,
5480                 .pa_end         = 0x480b43ff,
5481                 .flags          = ADDR_TYPE_RT
5482         },
5483         { }
5484 };
5485
5486 /* l4_per -> mmc2 */
5487 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5488         .master         = &omap44xx_l4_per_hwmod,
5489         .slave          = &omap44xx_mmc2_hwmod,
5490         .clk            = "l4_div_ck",
5491         .addr           = omap44xx_mmc2_addrs,
5492         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5493 };
5494
5495 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5496         {
5497                 .pa_start       = 0x480ad000,
5498                 .pa_end         = 0x480ad3ff,
5499                 .flags          = ADDR_TYPE_RT
5500         },
5501         { }
5502 };
5503
5504 /* l4_per -> mmc3 */
5505 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5506         .master         = &omap44xx_l4_per_hwmod,
5507         .slave          = &omap44xx_mmc3_hwmod,
5508         .clk            = "l4_div_ck",
5509         .addr           = omap44xx_mmc3_addrs,
5510         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5511 };
5512
5513 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5514         {
5515                 .pa_start       = 0x480d1000,
5516                 .pa_end         = 0x480d13ff,
5517                 .flags          = ADDR_TYPE_RT
5518         },
5519         { }
5520 };
5521
5522 /* l4_per -> mmc4 */
5523 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5524         .master         = &omap44xx_l4_per_hwmod,
5525         .slave          = &omap44xx_mmc4_hwmod,
5526         .clk            = "l4_div_ck",
5527         .addr           = omap44xx_mmc4_addrs,
5528         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5529 };
5530
5531 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5532         {
5533                 .pa_start       = 0x480d5000,
5534                 .pa_end         = 0x480d53ff,
5535                 .flags          = ADDR_TYPE_RT
5536         },
5537         { }
5538 };
5539
5540 /* l4_per -> mmc5 */
5541 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5542         .master         = &omap44xx_l4_per_hwmod,
5543         .slave          = &omap44xx_mmc5_hwmod,
5544         .clk            = "l4_div_ck",
5545         .addr           = omap44xx_mmc5_addrs,
5546         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5547 };
5548
5549 /* l3_main_2 -> ocmc_ram */
5550 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5551         .master         = &omap44xx_l3_main_2_hwmod,
5552         .slave          = &omap44xx_ocmc_ram_hwmod,
5553         .clk            = "l3_div_ck",
5554         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5555 };
5556
5557 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
5558         {
5559                 .pa_start       = 0x4a0ad000,
5560                 .pa_end         = 0x4a0ad01f,
5561                 .flags          = ADDR_TYPE_RT
5562         },
5563         { }
5564 };
5565
5566 /* l4_cfg -> ocp2scp_usb_phy */
5567 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5568         .master         = &omap44xx_l4_cfg_hwmod,
5569         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5570         .clk            = "l4_div_ck",
5571         .addr           = omap44xx_ocp2scp_usb_phy_addrs,
5572         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5573 };
5574
5575 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5576         {
5577                 .pa_start       = 0x48243000,
5578                 .pa_end         = 0x48243fff,
5579                 .flags          = ADDR_TYPE_RT
5580         },
5581         { }
5582 };
5583
5584 /* mpu_private -> prcm_mpu */
5585 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5586         .master         = &omap44xx_mpu_private_hwmod,
5587         .slave          = &omap44xx_prcm_mpu_hwmod,
5588         .clk            = "l3_div_ck",
5589         .addr           = omap44xx_prcm_mpu_addrs,
5590         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5591 };
5592
5593 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5594         {
5595                 .pa_start       = 0x4a004000,
5596                 .pa_end         = 0x4a004fff,
5597                 .flags          = ADDR_TYPE_RT
5598         },
5599         { }
5600 };
5601
5602 /* l4_wkup -> cm_core_aon */
5603 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5604         .master         = &omap44xx_l4_wkup_hwmod,
5605         .slave          = &omap44xx_cm_core_aon_hwmod,
5606         .clk            = "l4_wkup_clk_mux_ck",
5607         .addr           = omap44xx_cm_core_aon_addrs,
5608         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5609 };
5610
5611 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5612         {
5613                 .pa_start       = 0x4a008000,
5614                 .pa_end         = 0x4a009fff,
5615                 .flags          = ADDR_TYPE_RT
5616         },
5617         { }
5618 };
5619
5620 /* l4_cfg -> cm_core */
5621 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5622         .master         = &omap44xx_l4_cfg_hwmod,
5623         .slave          = &omap44xx_cm_core_hwmod,
5624         .clk            = "l4_div_ck",
5625         .addr           = omap44xx_cm_core_addrs,
5626         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5627 };
5628
5629 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5630         {
5631                 .pa_start       = 0x4a306000,
5632                 .pa_end         = 0x4a307fff,
5633                 .flags          = ADDR_TYPE_RT
5634         },
5635         { }
5636 };
5637
5638 /* l4_wkup -> prm */
5639 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5640         .master         = &omap44xx_l4_wkup_hwmod,
5641         .slave          = &omap44xx_prm_hwmod,
5642         .clk            = "l4_wkup_clk_mux_ck",
5643         .addr           = omap44xx_prm_addrs,
5644         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5645 };
5646
5647 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5648         {
5649                 .pa_start       = 0x4a30a000,
5650                 .pa_end         = 0x4a30a7ff,
5651                 .flags          = ADDR_TYPE_RT
5652         },
5653         { }
5654 };
5655
5656 /* l4_wkup -> scrm */
5657 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5658         .master         = &omap44xx_l4_wkup_hwmod,
5659         .slave          = &omap44xx_scrm_hwmod,
5660         .clk            = "l4_wkup_clk_mux_ck",
5661         .addr           = omap44xx_scrm_addrs,
5662         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5663 };
5664
5665 /* l3_main_2 -> sl2if */
5666 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5667         .master         = &omap44xx_l3_main_2_hwmod,
5668         .slave          = &omap44xx_sl2if_hwmod,
5669         .clk            = "l3_div_ck",
5670         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5671 };
5672
5673 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5674         {
5675                 .pa_start       = 0x4012c000,
5676                 .pa_end         = 0x4012c3ff,
5677                 .flags          = ADDR_TYPE_RT
5678         },
5679         { }
5680 };
5681
5682 /* l4_abe -> slimbus1 */
5683 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5684         .master         = &omap44xx_l4_abe_hwmod,
5685         .slave          = &omap44xx_slimbus1_hwmod,
5686         .clk            = "ocp_abe_iclk",
5687         .addr           = omap44xx_slimbus1_addrs,
5688         .user           = OCP_USER_MPU,
5689 };
5690
5691 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5692         {
5693                 .pa_start       = 0x4902c000,
5694                 .pa_end         = 0x4902c3ff,
5695                 .flags          = ADDR_TYPE_RT
5696         },
5697         { }
5698 };
5699
5700 /* l4_abe -> slimbus1 (dma) */
5701 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5702         .master         = &omap44xx_l4_abe_hwmod,
5703         .slave          = &omap44xx_slimbus1_hwmod,
5704         .clk            = "ocp_abe_iclk",
5705         .addr           = omap44xx_slimbus1_dma_addrs,
5706         .user           = OCP_USER_SDMA,
5707 };
5708
5709 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5710         {
5711                 .pa_start       = 0x48076000,
5712                 .pa_end         = 0x480763ff,
5713                 .flags          = ADDR_TYPE_RT
5714         },
5715         { }
5716 };
5717
5718 /* l4_per -> slimbus2 */
5719 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5720         .master         = &omap44xx_l4_per_hwmod,
5721         .slave          = &omap44xx_slimbus2_hwmod,
5722         .clk            = "l4_div_ck",
5723         .addr           = omap44xx_slimbus2_addrs,
5724         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5725 };
5726
5727 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5728         {
5729                 .pa_start       = 0x4a0dd000,
5730                 .pa_end         = 0x4a0dd03f,
5731                 .flags          = ADDR_TYPE_RT
5732         },
5733         { }
5734 };
5735
5736 /* l4_cfg -> smartreflex_core */
5737 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5738         .master         = &omap44xx_l4_cfg_hwmod,
5739         .slave          = &omap44xx_smartreflex_core_hwmod,
5740         .clk            = "l4_div_ck",
5741         .addr           = omap44xx_smartreflex_core_addrs,
5742         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5743 };
5744
5745 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5746         {
5747                 .pa_start       = 0x4a0db000,
5748                 .pa_end         = 0x4a0db03f,
5749                 .flags          = ADDR_TYPE_RT
5750         },
5751         { }
5752 };
5753
5754 /* l4_cfg -> smartreflex_iva */
5755 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5756         .master         = &omap44xx_l4_cfg_hwmod,
5757         .slave          = &omap44xx_smartreflex_iva_hwmod,
5758         .clk            = "l4_div_ck",
5759         .addr           = omap44xx_smartreflex_iva_addrs,
5760         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5761 };
5762
5763 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5764         {
5765                 .pa_start       = 0x4a0d9000,
5766                 .pa_end         = 0x4a0d903f,
5767                 .flags          = ADDR_TYPE_RT
5768         },
5769         { }
5770 };
5771
5772 /* l4_cfg -> smartreflex_mpu */
5773 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5774         .master         = &omap44xx_l4_cfg_hwmod,
5775         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5776         .clk            = "l4_div_ck",
5777         .addr           = omap44xx_smartreflex_mpu_addrs,
5778         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5779 };
5780
5781 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5782         {
5783                 .pa_start       = 0x4a0f6000,
5784                 .pa_end         = 0x4a0f6fff,
5785                 .flags          = ADDR_TYPE_RT
5786         },
5787         { }
5788 };
5789
5790 /* l4_cfg -> spinlock */
5791 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5792         .master         = &omap44xx_l4_cfg_hwmod,
5793         .slave          = &omap44xx_spinlock_hwmod,
5794         .clk            = "l4_div_ck",
5795         .addr           = omap44xx_spinlock_addrs,
5796         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5797 };
5798
5799 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5800         {
5801                 .pa_start       = 0x4a318000,
5802                 .pa_end         = 0x4a31807f,
5803                 .flags          = ADDR_TYPE_RT
5804         },
5805         { }
5806 };
5807
5808 /* l4_wkup -> timer1 */
5809 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5810         .master         = &omap44xx_l4_wkup_hwmod,
5811         .slave          = &omap44xx_timer1_hwmod,
5812         .clk            = "l4_wkup_clk_mux_ck",
5813         .addr           = omap44xx_timer1_addrs,
5814         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5815 };
5816
5817 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5818         {
5819                 .pa_start       = 0x48032000,
5820                 .pa_end         = 0x4803207f,
5821                 .flags          = ADDR_TYPE_RT
5822         },
5823         { }
5824 };
5825
5826 /* l4_per -> timer2 */
5827 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5828         .master         = &omap44xx_l4_per_hwmod,
5829         .slave          = &omap44xx_timer2_hwmod,
5830         .clk            = "l4_div_ck",
5831         .addr           = omap44xx_timer2_addrs,
5832         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5833 };
5834
5835 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5836         {
5837                 .pa_start       = 0x48034000,
5838                 .pa_end         = 0x4803407f,
5839                 .flags          = ADDR_TYPE_RT
5840         },
5841         { }
5842 };
5843
5844 /* l4_per -> timer3 */
5845 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5846         .master         = &omap44xx_l4_per_hwmod,
5847         .slave          = &omap44xx_timer3_hwmod,
5848         .clk            = "l4_div_ck",
5849         .addr           = omap44xx_timer3_addrs,
5850         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5851 };
5852
5853 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5854         {
5855                 .pa_start       = 0x48036000,
5856                 .pa_end         = 0x4803607f,
5857                 .flags          = ADDR_TYPE_RT
5858         },
5859         { }
5860 };
5861
5862 /* l4_per -> timer4 */
5863 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5864         .master         = &omap44xx_l4_per_hwmod,
5865         .slave          = &omap44xx_timer4_hwmod,
5866         .clk            = "l4_div_ck",
5867         .addr           = omap44xx_timer4_addrs,
5868         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5869 };
5870
5871 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5872         {
5873                 .pa_start       = 0x40138000,
5874                 .pa_end         = 0x4013807f,
5875                 .flags          = ADDR_TYPE_RT
5876         },
5877         { }
5878 };
5879
5880 /* l4_abe -> timer5 */
5881 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5882         .master         = &omap44xx_l4_abe_hwmod,
5883         .slave          = &omap44xx_timer5_hwmod,
5884         .clk            = "ocp_abe_iclk",
5885         .addr           = omap44xx_timer5_addrs,
5886         .user           = OCP_USER_MPU,
5887 };
5888
5889 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5890         {
5891                 .pa_start       = 0x49038000,
5892                 .pa_end         = 0x4903807f,
5893                 .flags          = ADDR_TYPE_RT
5894         },
5895         { }
5896 };
5897
5898 /* l4_abe -> timer5 (dma) */
5899 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5900         .master         = &omap44xx_l4_abe_hwmod,
5901         .slave          = &omap44xx_timer5_hwmod,
5902         .clk            = "ocp_abe_iclk",
5903         .addr           = omap44xx_timer5_dma_addrs,
5904         .user           = OCP_USER_SDMA,
5905 };
5906
5907 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5908         {
5909                 .pa_start       = 0x4013a000,
5910                 .pa_end         = 0x4013a07f,
5911                 .flags          = ADDR_TYPE_RT
5912         },
5913         { }
5914 };
5915
5916 /* l4_abe -> timer6 */
5917 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5918         .master         = &omap44xx_l4_abe_hwmod,
5919         .slave          = &omap44xx_timer6_hwmod,
5920         .clk            = "ocp_abe_iclk",
5921         .addr           = omap44xx_timer6_addrs,
5922         .user           = OCP_USER_MPU,
5923 };
5924
5925 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5926         {
5927                 .pa_start       = 0x4903a000,
5928                 .pa_end         = 0x4903a07f,
5929                 .flags          = ADDR_TYPE_RT
5930         },
5931         { }
5932 };
5933
5934 /* l4_abe -> timer6 (dma) */
5935 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5936         .master         = &omap44xx_l4_abe_hwmod,
5937         .slave          = &omap44xx_timer6_hwmod,
5938         .clk            = "ocp_abe_iclk",
5939         .addr           = omap44xx_timer6_dma_addrs,
5940         .user           = OCP_USER_SDMA,
5941 };
5942
5943 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5944         {
5945                 .pa_start       = 0x4013c000,
5946                 .pa_end         = 0x4013c07f,
5947                 .flags          = ADDR_TYPE_RT
5948         },
5949         { }
5950 };
5951
5952 /* l4_abe -> timer7 */
5953 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5954         .master         = &omap44xx_l4_abe_hwmod,
5955         .slave          = &omap44xx_timer7_hwmod,
5956         .clk            = "ocp_abe_iclk",
5957         .addr           = omap44xx_timer7_addrs,
5958         .user           = OCP_USER_MPU,
5959 };
5960
5961 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5962         {
5963                 .pa_start       = 0x4903c000,
5964                 .pa_end         = 0x4903c07f,
5965                 .flags          = ADDR_TYPE_RT
5966         },
5967         { }
5968 };
5969
5970 /* l4_abe -> timer7 (dma) */
5971 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5972         .master         = &omap44xx_l4_abe_hwmod,
5973         .slave          = &omap44xx_timer7_hwmod,
5974         .clk            = "ocp_abe_iclk",
5975         .addr           = omap44xx_timer7_dma_addrs,
5976         .user           = OCP_USER_SDMA,
5977 };
5978
5979 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5980         {
5981                 .pa_start       = 0x4013e000,
5982                 .pa_end         = 0x4013e07f,
5983                 .flags          = ADDR_TYPE_RT
5984         },
5985         { }
5986 };
5987
5988 /* l4_abe -> timer8 */
5989 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5990         .master         = &omap44xx_l4_abe_hwmod,
5991         .slave          = &omap44xx_timer8_hwmod,
5992         .clk            = "ocp_abe_iclk",
5993         .addr           = omap44xx_timer8_addrs,
5994         .user           = OCP_USER_MPU,
5995 };
5996
5997 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5998         {
5999                 .pa_start       = 0x4903e000,
6000                 .pa_end         = 0x4903e07f,
6001                 .flags          = ADDR_TYPE_RT
6002         },
6003         { }
6004 };
6005
6006 /* l4_abe -> timer8 (dma) */
6007 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
6008         .master         = &omap44xx_l4_abe_hwmod,
6009         .slave          = &omap44xx_timer8_hwmod,
6010         .clk            = "ocp_abe_iclk",
6011         .addr           = omap44xx_timer8_dma_addrs,
6012         .user           = OCP_USER_SDMA,
6013 };
6014
6015 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
6016         {
6017                 .pa_start       = 0x4803e000,
6018                 .pa_end         = 0x4803e07f,
6019                 .flags          = ADDR_TYPE_RT
6020         },
6021         { }
6022 };
6023
6024 /* l4_per -> timer9 */
6025 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
6026         .master         = &omap44xx_l4_per_hwmod,
6027         .slave          = &omap44xx_timer9_hwmod,
6028         .clk            = "l4_div_ck",
6029         .addr           = omap44xx_timer9_addrs,
6030         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6031 };
6032
6033 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
6034         {
6035                 .pa_start       = 0x48086000,
6036                 .pa_end         = 0x4808607f,
6037                 .flags          = ADDR_TYPE_RT
6038         },
6039         { }
6040 };
6041
6042 /* l4_per -> timer10 */
6043 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
6044         .master         = &omap44xx_l4_per_hwmod,
6045         .slave          = &omap44xx_timer10_hwmod,
6046         .clk            = "l4_div_ck",
6047         .addr           = omap44xx_timer10_addrs,
6048         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6049 };
6050
6051 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
6052         {
6053                 .pa_start       = 0x48088000,
6054                 .pa_end         = 0x4808807f,
6055                 .flags          = ADDR_TYPE_RT
6056         },
6057         { }
6058 };
6059
6060 /* l4_per -> timer11 */
6061 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
6062         .master         = &omap44xx_l4_per_hwmod,
6063         .slave          = &omap44xx_timer11_hwmod,
6064         .clk            = "l4_div_ck",
6065         .addr           = omap44xx_timer11_addrs,
6066         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6067 };
6068
6069 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
6070         {
6071                 .pa_start       = 0x4806a000,
6072                 .pa_end         = 0x4806a0ff,
6073                 .flags          = ADDR_TYPE_RT
6074         },
6075         { }
6076 };
6077
6078 /* l4_per -> uart1 */
6079 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
6080         .master         = &omap44xx_l4_per_hwmod,
6081         .slave          = &omap44xx_uart1_hwmod,
6082         .clk            = "l4_div_ck",
6083         .addr           = omap44xx_uart1_addrs,
6084         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6085 };
6086
6087 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
6088         {
6089                 .pa_start       = 0x4806c000,
6090                 .pa_end         = 0x4806c0ff,
6091                 .flags          = ADDR_TYPE_RT
6092         },
6093         { }
6094 };
6095
6096 /* l4_per -> uart2 */
6097 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
6098         .master         = &omap44xx_l4_per_hwmod,
6099         .slave          = &omap44xx_uart2_hwmod,
6100         .clk            = "l4_div_ck",
6101         .addr           = omap44xx_uart2_addrs,
6102         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6103 };
6104
6105 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
6106         {
6107                 .pa_start       = 0x48020000,
6108                 .pa_end         = 0x480200ff,
6109                 .flags          = ADDR_TYPE_RT
6110         },
6111         { }
6112 };
6113
6114 /* l4_per -> uart3 */
6115 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
6116         .master         = &omap44xx_l4_per_hwmod,
6117         .slave          = &omap44xx_uart3_hwmod,
6118         .clk            = "l4_div_ck",
6119         .addr           = omap44xx_uart3_addrs,
6120         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6121 };
6122
6123 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
6124         {
6125                 .pa_start       = 0x4806e000,
6126                 .pa_end         = 0x4806e0ff,
6127                 .flags          = ADDR_TYPE_RT
6128         },
6129         { }
6130 };
6131
6132 /* l4_per -> uart4 */
6133 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
6134         .master         = &omap44xx_l4_per_hwmod,
6135         .slave          = &omap44xx_uart4_hwmod,
6136         .clk            = "l4_div_ck",
6137         .addr           = omap44xx_uart4_addrs,
6138         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6139 };
6140
6141 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
6142         {
6143                 .pa_start       = 0x4a0a9000,
6144                 .pa_end         = 0x4a0a93ff,
6145                 .flags          = ADDR_TYPE_RT
6146         },
6147         { }
6148 };
6149
6150 /* l4_cfg -> usb_host_fs */
6151 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
6152         .master         = &omap44xx_l4_cfg_hwmod,
6153         .slave          = &omap44xx_usb_host_fs_hwmod,
6154         .clk            = "l4_div_ck",
6155         .addr           = omap44xx_usb_host_fs_addrs,
6156         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6157 };
6158
6159 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
6160         {
6161                 .name           = "uhh",
6162                 .pa_start       = 0x4a064000,
6163                 .pa_end         = 0x4a0647ff,
6164                 .flags          = ADDR_TYPE_RT
6165         },
6166         {
6167                 .name           = "ohci",
6168                 .pa_start       = 0x4a064800,
6169                 .pa_end         = 0x4a064bff,
6170         },
6171         {
6172                 .name           = "ehci",
6173                 .pa_start       = 0x4a064c00,
6174                 .pa_end         = 0x4a064fff,
6175         },
6176         {}
6177 };
6178
6179 /* l4_cfg -> usb_host_hs */
6180 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
6181         .master         = &omap44xx_l4_cfg_hwmod,
6182         .slave          = &omap44xx_usb_host_hs_hwmod,
6183         .clk            = "l4_div_ck",
6184         .addr           = omap44xx_usb_host_hs_addrs,
6185         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6186 };
6187
6188 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
6189         {
6190                 .pa_start       = 0x4a0ab000,
6191                 .pa_end         = 0x4a0ab7ff,
6192                 .flags          = ADDR_TYPE_RT
6193         },
6194         { }
6195 };
6196
6197 /* l4_cfg -> usb_otg_hs */
6198 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
6199         .master         = &omap44xx_l4_cfg_hwmod,
6200         .slave          = &omap44xx_usb_otg_hs_hwmod,
6201         .clk            = "l4_div_ck",
6202         .addr           = omap44xx_usb_otg_hs_addrs,
6203         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6204 };
6205
6206 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
6207         {
6208                 .name           = "tll",
6209                 .pa_start       = 0x4a062000,
6210                 .pa_end         = 0x4a063fff,
6211                 .flags          = ADDR_TYPE_RT
6212         },
6213         {}
6214 };
6215
6216 /* l4_cfg -> usb_tll_hs */
6217 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
6218         .master         = &omap44xx_l4_cfg_hwmod,
6219         .slave          = &omap44xx_usb_tll_hs_hwmod,
6220         .clk            = "l4_div_ck",
6221         .addr           = omap44xx_usb_tll_hs_addrs,
6222         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6223 };
6224
6225 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
6226         {
6227                 .pa_start       = 0x4a314000,
6228                 .pa_end         = 0x4a31407f,
6229                 .flags          = ADDR_TYPE_RT
6230         },
6231         { }
6232 };
6233
6234 /* l4_wkup -> wd_timer2 */
6235 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
6236         .master         = &omap44xx_l4_wkup_hwmod,
6237         .slave          = &omap44xx_wd_timer2_hwmod,
6238         .clk            = "l4_wkup_clk_mux_ck",
6239         .addr           = omap44xx_wd_timer2_addrs,
6240         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6241 };
6242
6243 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
6244         {
6245                 .pa_start       = 0x40130000,
6246                 .pa_end         = 0x4013007f,
6247                 .flags          = ADDR_TYPE_RT
6248         },
6249         { }
6250 };
6251
6252 /* l4_abe -> wd_timer3 */
6253 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
6254         .master         = &omap44xx_l4_abe_hwmod,
6255         .slave          = &omap44xx_wd_timer3_hwmod,
6256         .clk            = "ocp_abe_iclk",
6257         .addr           = omap44xx_wd_timer3_addrs,
6258         .user           = OCP_USER_MPU,
6259 };
6260
6261 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
6262         {
6263                 .pa_start       = 0x49030000,
6264                 .pa_end         = 0x4903007f,
6265                 .flags          = ADDR_TYPE_RT
6266         },
6267         { }
6268 };
6269
6270 /* l4_abe -> wd_timer3 (dma) */
6271 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6272         .master         = &omap44xx_l4_abe_hwmod,
6273         .slave          = &omap44xx_wd_timer3_hwmod,
6274         .clk            = "ocp_abe_iclk",
6275         .addr           = omap44xx_wd_timer3_dma_addrs,
6276         .user           = OCP_USER_SDMA,
6277 };
6278
6279 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6280         &omap44xx_c2c__c2c_target_fw,
6281         &omap44xx_l4_cfg__c2c_target_fw,
6282         &omap44xx_l3_main_1__dmm,
6283         &omap44xx_mpu__dmm,
6284         &omap44xx_c2c__emif_fw,
6285         &omap44xx_dmm__emif_fw,
6286         &omap44xx_l4_cfg__emif_fw,
6287         &omap44xx_iva__l3_instr,
6288         &omap44xx_l3_main_3__l3_instr,
6289         &omap44xx_ocp_wp_noc__l3_instr,
6290         &omap44xx_dsp__l3_main_1,
6291         &omap44xx_dss__l3_main_1,
6292         &omap44xx_l3_main_2__l3_main_1,
6293         &omap44xx_l4_cfg__l3_main_1,
6294         &omap44xx_mmc1__l3_main_1,
6295         &omap44xx_mmc2__l3_main_1,
6296         &omap44xx_mpu__l3_main_1,
6297         &omap44xx_c2c_target_fw__l3_main_2,
6298         &omap44xx_debugss__l3_main_2,
6299         &omap44xx_dma_system__l3_main_2,
6300         &omap44xx_fdif__l3_main_2,
6301         &omap44xx_gpu__l3_main_2,
6302         &omap44xx_hsi__l3_main_2,
6303         &omap44xx_ipu__l3_main_2,
6304         &omap44xx_iss__l3_main_2,
6305         &omap44xx_iva__l3_main_2,
6306         &omap44xx_l3_main_1__l3_main_2,
6307         &omap44xx_l4_cfg__l3_main_2,
6308         /* &omap44xx_usb_host_fs__l3_main_2, */
6309         &omap44xx_usb_host_hs__l3_main_2,
6310         &omap44xx_usb_otg_hs__l3_main_2,
6311         &omap44xx_l3_main_1__l3_main_3,
6312         &omap44xx_l3_main_2__l3_main_3,
6313         &omap44xx_l4_cfg__l3_main_3,
6314         &omap44xx_aess__l4_abe,
6315         &omap44xx_dsp__l4_abe,
6316         &omap44xx_l3_main_1__l4_abe,
6317         &omap44xx_mpu__l4_abe,
6318         &omap44xx_l3_main_1__l4_cfg,
6319         &omap44xx_l3_main_2__l4_per,
6320         &omap44xx_l4_cfg__l4_wkup,
6321         &omap44xx_mpu__mpu_private,
6322         &omap44xx_l4_cfg__ocp_wp_noc,
6323         &omap44xx_l4_abe__aess,
6324         &omap44xx_l4_abe__aess_dma,
6325         &omap44xx_l3_main_2__c2c,
6326         &omap44xx_l4_wkup__counter_32k,
6327         &omap44xx_l4_cfg__ctrl_module_core,
6328         &omap44xx_l4_cfg__ctrl_module_pad_core,
6329         &omap44xx_l4_wkup__ctrl_module_wkup,
6330         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6331         &omap44xx_l3_instr__debugss,
6332         &omap44xx_l4_cfg__dma_system,
6333         &omap44xx_l4_abe__dmic,
6334         &omap44xx_l4_abe__dmic_dma,
6335         &omap44xx_dsp__iva,
6336         /* &omap44xx_dsp__sl2if, */
6337         &omap44xx_l4_cfg__dsp,
6338         &omap44xx_l3_main_2__dss,
6339         &omap44xx_l4_per__dss,
6340         &omap44xx_l3_main_2__dss_dispc,
6341         &omap44xx_l4_per__dss_dispc,
6342         &omap44xx_l3_main_2__dss_dsi1,
6343         &omap44xx_l4_per__dss_dsi1,
6344         &omap44xx_l3_main_2__dss_dsi2,
6345         &omap44xx_l4_per__dss_dsi2,
6346         &omap44xx_l3_main_2__dss_hdmi,
6347         &omap44xx_l4_per__dss_hdmi,
6348         &omap44xx_l3_main_2__dss_rfbi,
6349         &omap44xx_l4_per__dss_rfbi,
6350         &omap44xx_l3_main_2__dss_venc,
6351         &omap44xx_l4_per__dss_venc,
6352         &omap44xx_l4_per__elm,
6353         &omap44xx_emif_fw__emif1,
6354         &omap44xx_emif_fw__emif2,
6355         &omap44xx_l4_cfg__fdif,
6356         &omap44xx_l4_wkup__gpio1,
6357         &omap44xx_l4_per__gpio2,
6358         &omap44xx_l4_per__gpio3,
6359         &omap44xx_l4_per__gpio4,
6360         &omap44xx_l4_per__gpio5,
6361         &omap44xx_l4_per__gpio6,
6362         &omap44xx_l3_main_2__gpmc,
6363         &omap44xx_l3_main_2__gpu,
6364         &omap44xx_l4_per__hdq1w,
6365         &omap44xx_l4_cfg__hsi,
6366         &omap44xx_l4_per__i2c1,
6367         &omap44xx_l4_per__i2c2,
6368         &omap44xx_l4_per__i2c3,
6369         &omap44xx_l4_per__i2c4,
6370         &omap44xx_l3_main_2__ipu,
6371         &omap44xx_l3_main_2__iss,
6372         /* &omap44xx_iva__sl2if, */
6373         &omap44xx_l3_main_2__iva,
6374         &omap44xx_l4_wkup__kbd,
6375         &omap44xx_l4_cfg__mailbox,
6376         &omap44xx_l4_abe__mcasp,
6377         &omap44xx_l4_abe__mcasp_dma,
6378         &omap44xx_l4_abe__mcbsp1,
6379         &omap44xx_l4_abe__mcbsp1_dma,
6380         &omap44xx_l4_abe__mcbsp2,
6381         &omap44xx_l4_abe__mcbsp2_dma,
6382         &omap44xx_l4_abe__mcbsp3,
6383         &omap44xx_l4_abe__mcbsp3_dma,
6384         &omap44xx_l4_per__mcbsp4,
6385         &omap44xx_l4_abe__mcpdm,
6386         &omap44xx_l4_abe__mcpdm_dma,
6387         &omap44xx_l4_per__mcspi1,
6388         &omap44xx_l4_per__mcspi2,
6389         &omap44xx_l4_per__mcspi3,
6390         &omap44xx_l4_per__mcspi4,
6391         &omap44xx_l4_per__mmc1,
6392         &omap44xx_l4_per__mmc2,
6393         &omap44xx_l4_per__mmc3,
6394         &omap44xx_l4_per__mmc4,
6395         &omap44xx_l4_per__mmc5,
6396         &omap44xx_l3_main_2__mmu_ipu,
6397         &omap44xx_l4_cfg__mmu_dsp,
6398         &omap44xx_l3_main_2__ocmc_ram,
6399         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6400         &omap44xx_mpu_private__prcm_mpu,
6401         &omap44xx_l4_wkup__cm_core_aon,
6402         &omap44xx_l4_cfg__cm_core,
6403         &omap44xx_l4_wkup__prm,
6404         &omap44xx_l4_wkup__scrm,
6405         /* &omap44xx_l3_main_2__sl2if, */
6406         &omap44xx_l4_abe__slimbus1,
6407         &omap44xx_l4_abe__slimbus1_dma,
6408         &omap44xx_l4_per__slimbus2,
6409         &omap44xx_l4_cfg__smartreflex_core,
6410         &omap44xx_l4_cfg__smartreflex_iva,
6411         &omap44xx_l4_cfg__smartreflex_mpu,
6412         &omap44xx_l4_cfg__spinlock,
6413         &omap44xx_l4_wkup__timer1,
6414         &omap44xx_l4_per__timer2,
6415         &omap44xx_l4_per__timer3,
6416         &omap44xx_l4_per__timer4,
6417         &omap44xx_l4_abe__timer5,
6418         &omap44xx_l4_abe__timer5_dma,
6419         &omap44xx_l4_abe__timer6,
6420         &omap44xx_l4_abe__timer6_dma,
6421         &omap44xx_l4_abe__timer7,
6422         &omap44xx_l4_abe__timer7_dma,
6423         &omap44xx_l4_abe__timer8,
6424         &omap44xx_l4_abe__timer8_dma,
6425         &omap44xx_l4_per__timer9,
6426         &omap44xx_l4_per__timer10,
6427         &omap44xx_l4_per__timer11,
6428         &omap44xx_l4_per__uart1,
6429         &omap44xx_l4_per__uart2,
6430         &omap44xx_l4_per__uart3,
6431         &omap44xx_l4_per__uart4,
6432         /* &omap44xx_l4_cfg__usb_host_fs, */
6433         &omap44xx_l4_cfg__usb_host_hs,
6434         &omap44xx_l4_cfg__usb_otg_hs,
6435         &omap44xx_l4_cfg__usb_tll_hs,
6436         &omap44xx_l4_wkup__wd_timer2,
6437         &omap44xx_l4_abe__wd_timer3,
6438         &omap44xx_l4_abe__wd_timer3_dma,
6439         NULL,
6440 };
6441
6442 int __init omap44xx_hwmod_init(void)
6443 {
6444         omap_hwmod_init();
6445         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6446 }
6447