arch/arm/mach-omap2/omap_hwmod_33xx_data.c

   1 /*
   2  * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
   3  *
   4  * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This file is automatically generated from the AM33XX hardware databases.
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/i2c-omap.h>
  18
  19 #include "omap_hwmod.h"
  20 #include <linux/platform_data/gpio-omap.h>
  21 #include <linux/platform_data/spi-omap2-mcspi.h>
  22
  23 #include "omap_hwmod_common_data.h"
  24
  25 #include "control.h"
  26 #include "cm33xx.h"
  27 #include "prm33xx.h"
  28 #include "prm-regbits-33xx.h"
  29 #include "i2c.h"
  30 #include "mmc.h"
  31 #include "wd_timer.h"
  32
  33 /*
  34  * IP blocks
  35  */
  36
  37 /*
  38  * 'emif_fw' class
  39  * instance(s): emif_fw
  40  */
  41 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
  42         .name           = "emif_fw",
  43 };
  44
  45 /* emif_fw */
  46 static struct omap_hwmod am33xx_emif_fw_hwmod = {
  47         .name           = "emif_fw",
  48         .class          = &am33xx_emif_fw_hwmod_class,
  49         .clkdm_name     = "l4fw_clkdm",
  50         .main_clk       = "l4fw_gclk",
  51         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  52         .prcm           = {
  53                 .omap4  = {
  54                         .clkctrl_offs   = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
  55                         .modulemode     = MODULEMODE_SWCTRL,
  56                 },
  57         },
  58 };
  59
  60 /*
  61  * 'emif' class
  62  * instance(s): emif
  63  */
  64 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
  65         .rev_offs       = 0x0000,
  66 };
  67
  68 static struct omap_hwmod_class am33xx_emif_hwmod_class = {
  69         .name           = "emif",
  70         .sysc           = &am33xx_emif_sysc,
  71 };
  72
  73 static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
  74         { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
  75         { .irq = -1 },
  76 };
  77
  78 /* emif */
  79 static struct omap_hwmod am33xx_emif_hwmod = {
  80         .name           = "emif",
  81         .class          = &am33xx_emif_hwmod_class,
  82         .clkdm_name     = "l3_clkdm",
  83         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  84         .mpu_irqs       = am33xx_emif_irqs,
  85         .main_clk       = "dpll_ddr_m2_div2_ck",
  86         .prcm           = {
  87                 .omap4  = {
  88                         .clkctrl_offs   = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
  89                         .modulemode     = MODULEMODE_SWCTRL,
  90                 },
  91         },
  92 };
  93
  94 /*
  95  * 'l3' class
  96  * instance(s): l3_main, l3_s, l3_instr
  97  */
  98 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
  99         .name           = "l3",
 100 };
 101
 102 /* l3_main (l3_fast) */
 103 static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
 104         { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
 105         { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
 106         { .irq = -1 },
 107 };
 108
 109 static struct omap_hwmod am33xx_l3_main_hwmod = {
 110         .name           = "l3_main",
 111         .class          = &am33xx_l3_hwmod_class,
 112         .clkdm_name     = "l3_clkdm",
 113         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 114         .mpu_irqs       = am33xx_l3_main_irqs,
 115         .main_clk       = "l3_gclk",
 116         .prcm           = {
 117                 .omap4  = {
 118                         .clkctrl_offs   = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
 119                         .modulemode     = MODULEMODE_SWCTRL,
 120                 },
 121         },
 122 };
 123
 124 /* l3_s */
 125 static struct omap_hwmod am33xx_l3_s_hwmod = {
 126         .name           = "l3_s",
 127         .class          = &am33xx_l3_hwmod_class,
 128         .clkdm_name     = "l3s_clkdm",
 129 };
 130
 131 /* l3_instr */
 132 static struct omap_hwmod am33xx_l3_instr_hwmod = {
 133         .name           = "l3_instr",
 134         .class          = &am33xx_l3_hwmod_class,
 135         .clkdm_name     = "l3_clkdm",
 136         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 137         .main_clk       = "l3_gclk",
 138         .prcm           = {
 139                 .omap4  = {
 140                         .clkctrl_offs   = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
 141                         .modulemode     = MODULEMODE_SWCTRL,
 142                 },
 143         },
 144 };
 145
 146 /*
 147  * 'l4' class
 148  * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
 149  */
 150 static struct omap_hwmod_class am33xx_l4_hwmod_class = {
 151         .name           = "l4",
 152 };
 153
 154 /* l4_ls */
 155 static struct omap_hwmod am33xx_l4_ls_hwmod = {
 156         .name           = "l4_ls",
 157         .class          = &am33xx_l4_hwmod_class,
 158         .clkdm_name     = "l4ls_clkdm",
 159         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 160         .main_clk       = "l4ls_gclk",
 161         .prcm           = {
 162                 .omap4  = {
 163                         .clkctrl_offs   = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
 164                         .modulemode     = MODULEMODE_SWCTRL,
 165                 },
 166         },
 167 };
 168
 169 /* l4_hs */
 170 static struct omap_hwmod am33xx_l4_hs_hwmod = {
 171         .name           = "l4_hs",
 172         .class          = &am33xx_l4_hwmod_class,
 173         .clkdm_name     = "l4hs_clkdm",
 174         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 175         .main_clk       = "l4hs_gclk",
 176         .prcm           = {
 177                 .omap4  = {
 178                         .clkctrl_offs   = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
 179                         .modulemode     = MODULEMODE_SWCTRL,
 180                 },
 181         },
 182 };
 183
 184
 185 /* l4_wkup */
 186 static struct omap_hwmod am33xx_l4_wkup_hwmod = {
 187         .name           = "l4_wkup",
 188         .class          = &am33xx_l4_hwmod_class,
 189         .clkdm_name     = "l4_wkup_clkdm",
 190         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 191         .prcm           = {
 192                 .omap4  = {
 193                         .clkctrl_offs   = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 194                         .modulemode     = MODULEMODE_SWCTRL,
 195                 },
 196         },
 197 };
 198
 199 /* l4_fw */
 200 static struct omap_hwmod am33xx_l4_fw_hwmod = {
 201         .name           = "l4_fw",
 202         .class          = &am33xx_l4_hwmod_class,
 203         .clkdm_name     = "l4fw_clkdm",
 204         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 205         .prcm           = {
 206                 .omap4  = {
 207                         .clkctrl_offs   = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
 208                         .modulemode     = MODULEMODE_SWCTRL,
 209                 },
 210         },
 211 };
 212
 213 /*
 214  * 'mpu' class
 215  */
 216 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
 217         .name   = "mpu",
 218 };
 219
 220 /* mpu */
 221 static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
 222         { .name = "emuint", .irq = 0 + OMAP_INTC_START, },
 223         { .name = "commtx", .irq = 1 + OMAP_INTC_START, },
 224         { .name = "commrx", .irq = 2 + OMAP_INTC_START, },
 225         { .name = "bench", .irq = 3 + OMAP_INTC_START, },
 226         { .irq = -1 },
 227 };
 228
 229 static struct omap_hwmod am33xx_mpu_hwmod = {
 230         .name           = "mpu",
 231         .class          = &am33xx_mpu_hwmod_class,
 232         .clkdm_name     = "mpu_clkdm",
 233         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 234         .mpu_irqs       = am33xx_mpu_irqs,
 235         .main_clk       = "dpll_mpu_m2_ck",
 236         .prcm           = {
 237                 .omap4  = {
 238                         .clkctrl_offs   = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
 239                         .modulemode     = MODULEMODE_SWCTRL,
 240                 },
 241         },
 242 };
 243
 244 /*
 245  * 'wakeup m3' class
 246  * Wakeup controller sub-system under wakeup domain
 247  */
 248 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
 249         .name           = "wkup_m3",
 250 };
 251
 252 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
 253         { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
 254 };
 255
 256 static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
 257         { .name = "txev", .irq = 78 + OMAP_INTC_START, },
 258         { .irq = -1 },
 259 };
 260
 261 /* wkup_m3  */
 262 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
 263         .name           = "wkup_m3",
 264         .class          = &am33xx_wkup_m3_hwmod_class,
 265         .clkdm_name     = "l4_wkup_aon_clkdm",
 266         /* Keep hardreset asserted */
 267         .flags          = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
 268         .mpu_irqs       = am33xx_wkup_m3_irqs,
 269         .main_clk       = "dpll_core_m4_div2_ck",
 270         .prcm           = {
 271                 .omap4  = {
 272                         .clkctrl_offs   = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
 273                         .rstctrl_offs   = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
 274                         .rstst_offs     = AM33XX_RM_WKUP_RSTST_OFFSET,
 275                         .modulemode     = MODULEMODE_SWCTRL,
 276                 },
 277         },
 278         .rst_lines      = am33xx_wkup_m3_resets,
 279         .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
 280 };
 281
 282 /*
 283  * 'pru-icss' class
 284  * Programmable Real-Time Unit and Industrial Communication Subsystem
 285  */
 286 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
 287         .name   = "pruss",
 288 };
 289
 290 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
 291         { .name = "pruss", .rst_shift = 1 },
 292 };
 293
 294 static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
 295         { .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
 296         { .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
 297         { .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
 298         { .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
 299         { .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
 300         { .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
 301         { .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
 302         { .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
 303         { .irq = -1 },
 304 };
 305
 306 /* pru-icss */
 307 /* Pseudo hwmod for reset control purpose only */
 308 static struct omap_hwmod am33xx_pruss_hwmod = {
 309         .name           = "pruss",
 310         .class          = &am33xx_pruss_hwmod_class,
 311         .clkdm_name     = "pruss_ocp_clkdm",
 312         .mpu_irqs       = am33xx_pruss_irqs,
 313         .main_clk       = "pruss_ocp_gclk",
 314         .prcm           = {
 315                 .omap4  = {
 316                         .clkctrl_offs   = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
 317                         .rstctrl_offs   = AM33XX_RM_PER_RSTCTRL_OFFSET,
 318                         .modulemode     = MODULEMODE_SWCTRL,
 319                 },
 320         },
 321         .rst_lines      = am33xx_pruss_resets,
 322         .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
 323 };
 324
 325 /* gfx */
 326 /* Pseudo hwmod for reset control purpose only */
 327 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 328         .name   = "gfx",
 329 };
 330
 331 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
 332         { .name = "gfx", .rst_shift = 0 },
 333 };
 334
 335 static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
 336         { .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
 337         { .irq = -1 },
 338 };
 339
 340 static struct omap_hwmod am33xx_gfx_hwmod = {
 341         .name           = "gfx",
 342         .class          = &am33xx_gfx_hwmod_class,
 343         .clkdm_name     = "gfx_l3_clkdm",
 344         .mpu_irqs       = am33xx_gfx_irqs,
 345         .main_clk       = "gfx_fck_div_ck",
 346         .prcm           = {
 347                 .omap4  = {
 348                         .clkctrl_offs   = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
 349                         .rstctrl_offs   = AM33XX_RM_GFX_RSTCTRL_OFFSET,
 350                         .modulemode     = MODULEMODE_SWCTRL,
 351                 },
 352         },
 353         .rst_lines      = am33xx_gfx_resets,
 354         .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
 355 };
 356
 357 /*
 358  * 'prcm' class
 359  * power and reset manager (whole prcm infrastructure)
 360  */
 361 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
 362         .name   = "prcm",
 363 };
 364
 365 /* prcm */
 366 static struct omap_hwmod am33xx_prcm_hwmod = {
 367         .name           = "prcm",
 368         .class          = &am33xx_prcm_hwmod_class,
 369         .clkdm_name     = "l4_wkup_clkdm",
 370 };
 371
 372 /*
 373  * 'adc/tsc' class
 374  * TouchScreen Controller (Anolog-To-Digital Converter)
 375  */
 376 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
 377         .rev_offs       = 0x00,
 378         .sysc_offs      = 0x10,
 379         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 380         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 381                         SIDLE_SMART_WKUP),
 382         .sysc_fields    = &omap_hwmod_sysc_type2,
 383 };
 384
 385 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
 386         .name           = "adc_tsc",
 387         .sysc           = &am33xx_adc_tsc_sysc,
 388 };
 389
 390 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
 391         { .irq = 16 + OMAP_INTC_START, },
 392         { .irq = -1 },
 393 };
 394
 395 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
 396         .name           = "adc_tsc",
 397         .class          = &am33xx_adc_tsc_hwmod_class,
 398         .clkdm_name     = "l4_wkup_clkdm",
 399         .mpu_irqs       = am33xx_adc_tsc_irqs,
 400         .main_clk       = "adc_tsc_fck",
 401         .prcm           = {
 402                 .omap4  = {
 403                         .clkctrl_offs   = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
 404                         .modulemode     = MODULEMODE_SWCTRL,
 405                 },
 406         },
 407 };
 408
 409 /*
 410  * Modules omap_hwmod structures
 411  *
 412  * The following IPs are excluded for the moment because:
 413  * - They do not need an explicit SW control using omap_hwmod API.
 414  * - They still need to be validated with the driver
 415  *   properly adapted to omap_hwmod / omap_device
 416  *
 417  *    - cEFUSE (doesn't fall under any ocp_if)
 418  *    - clkdiv32k
 419  *    - debugss
 420  *    - ocp watch point
 421  */
 422 #if 0
 423 /*
 424  * 'cefuse' class
 425  */
 426 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
 427         .name           = "cefuse",
 428 };
 429
 430 static struct omap_hwmod am33xx_cefuse_hwmod = {
 431         .name           = "cefuse",
 432         .class          = &am33xx_cefuse_hwmod_class,
 433         .clkdm_name     = "l4_cefuse_clkdm",
 434         .main_clk       = "cefuse_fck",
 435         .prcm           = {
 436                 .omap4  = {
 437                         .clkctrl_offs   = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
 438                         .modulemode     = MODULEMODE_SWCTRL,
 439                 },
 440         },
 441 };
 442
 443 /*
 444  * 'clkdiv32k' class
 445  */
 446 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
 447         .name           = "clkdiv32k",
 448 };
 449
 450 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
 451         .name           = "clkdiv32k",
 452         .class          = &am33xx_clkdiv32k_hwmod_class,
 453         .clkdm_name     = "clk_24mhz_clkdm",
 454         .main_clk       = "clkdiv32k_ick",
 455         .prcm           = {
 456                 .omap4  = {
 457                         .clkctrl_offs   = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
 458                         .modulemode     = MODULEMODE_SWCTRL,
 459                 },
 460         },
 461 };
 462
 463 /*
 464  * 'debugss' class
 465  * debug sub system
 466  */
 467 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
 468         .name           = "debugss",
 469 };
 470
 471 static struct omap_hwmod am33xx_debugss_hwmod = {
 472         .name           = "debugss",
 473         .class          = &am33xx_debugss_hwmod_class,
 474         .clkdm_name     = "l3_aon_clkdm",
 475         .main_clk       = "debugss_ick",
 476         .prcm           = {
 477                 .omap4  = {
 478                         .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
 479                         .modulemode     = MODULEMODE_SWCTRL,
 480                 },
 481         },
 482 };
 483
 484 /* ocpwp */
 485 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
 486         .name           = "ocpwp",
 487 };
 488
 489 static struct omap_hwmod am33xx_ocpwp_hwmod = {
 490         .name           = "ocpwp",
 491         .class          = &am33xx_ocpwp_hwmod_class,
 492         .clkdm_name     = "l4ls_clkdm",
 493         .main_clk       = "l4ls_gclk",
 494         .prcm           = {
 495                 .omap4  = {
 496                         .clkctrl_offs   = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
 497                         .modulemode     = MODULEMODE_SWCTRL,
 498                 },
 499         },
 500 };
 501 #endif
 502
 503 /*
 504  * 'aes0' class
 505  */
 506 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
 507         .rev_offs       = 0x80,
 508         .sysc_offs      = 0x84,
 509         .syss_offs      = 0x88,
 510         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 511 };
 512
 513 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
 514         .name           = "aes0",
 515         .sysc           = &am33xx_aes0_sysc,
 516 };
 517
 518 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
 519         { .irq = 103 + OMAP_INTC_START, },
 520         { .irq = -1 },
 521 };
 522
 523 static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = {
 524         { .name = "tx", .dma_req = 6, },
 525         { .name = "rx", .dma_req = 5, },
 526         { .dma_req = -1 }
 527 };
 528
 529 static struct omap_hwmod am33xx_aes0_hwmod = {
 530         .name           = "aes",
 531         .class          = &am33xx_aes0_hwmod_class,
 532         .clkdm_name     = "l3_clkdm",
 533         .mpu_irqs       = am33xx_aes0_irqs,
 534         .sdma_reqs      = am33xx_aes0_edma_reqs,
 535         .main_clk       = "aes0_fck",
 536         .prcm           = {
 537                 .omap4  = {
 538                         .clkctrl_offs   = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
 539                         .modulemode     = MODULEMODE_SWCTRL,
 540                 },
 541         },
 542 };
 543
 544 /* sha0 HIB2 (the 'P' (public) device) */
 545 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
 546         .rev_offs       = 0x100,
 547         .sysc_offs      = 0x110,
 548         .syss_offs      = 0x114,
 549         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 550 };
 551
 552 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
 553         .name           = "sha0",
 554         .sysc           = &am33xx_sha0_sysc,
 555 };
 556
 557 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
 558         { .irq = 109 + OMAP_INTC_START, },
 559         { .irq = -1 },
 560 };
 561
 562 static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = {
 563         { .name = "rx", .dma_req = 36, },
 564         { .dma_req = -1 }
 565 };
 566
 567 static struct omap_hwmod am33xx_sha0_hwmod = {
 568         .name           = "sham",
 569         .class          = &am33xx_sha0_hwmod_class,
 570         .clkdm_name     = "l3_clkdm",
 571         .mpu_irqs       = am33xx_sha0_irqs,
 572         .sdma_reqs      = am33xx_sha0_edma_reqs,
 573         .main_clk       = "l3_gclk",
 574         .prcm           = {
 575                 .omap4  = {
 576                         .clkctrl_offs   = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
 577                         .modulemode     = MODULEMODE_SWCTRL,
 578                 },
 579         },
 580 };
 581
 582 /* ocmcram */
 583 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
 584         .name = "ocmcram",
 585 };
 586
 587 static struct omap_hwmod am33xx_ocmcram_hwmod = {
 588         .name           = "ocmcram",
 589         .class          = &am33xx_ocmcram_hwmod_class,
 590         .clkdm_name     = "l3_clkdm",
 591         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 592         .main_clk       = "l3_gclk",
 593         .prcm           = {
 594                 .omap4  = {
 595                         .clkctrl_offs   = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
 596                         .modulemode     = MODULEMODE_SWCTRL,
 597                 },
 598         },
 599 };
 600
 601 /* 'smartreflex' class */
 602 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 603         .name           = "smartreflex",
 604 };
 605
 606 /* smartreflex0 */
 607 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
 608         { .irq = 120 + OMAP_INTC_START, },
 609         { .irq = -1 },
 610 };
 611
 612 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
 613         .name           = "smartreflex0",
 614         .class          = &am33xx_smartreflex_hwmod_class,
 615         .clkdm_name     = "l4_wkup_clkdm",
 616         .mpu_irqs       = am33xx_smartreflex0_irqs,
 617         .main_clk       = "smartreflex0_fck",
 618         .prcm           = {
 619                 .omap4  = {
 620                         .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
 621                         .modulemode     = MODULEMODE_SWCTRL,
 622                 },
 623         },
 624 };
 625
 626 /* smartreflex1 */
 627 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
 628         { .irq = 121 + OMAP_INTC_START, },
 629         { .irq = -1 },
 630 };
 631
 632 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
 633         .name           = "smartreflex1",
 634         .class          = &am33xx_smartreflex_hwmod_class,
 635         .clkdm_name     = "l4_wkup_clkdm",
 636         .mpu_irqs       = am33xx_smartreflex1_irqs,
 637         .main_clk       = "smartreflex1_fck",
 638         .prcm           = {
 639                 .omap4  = {
 640                         .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
 641                         .modulemode     = MODULEMODE_SWCTRL,
 642                 },
 643         },
 644 };
 645
 646 /*
 647  * 'control' module class
 648  */
 649 static struct omap_hwmod_class am33xx_control_hwmod_class = {
 650         .name           = "control",
 651 };
 652
 653 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
 654         { .irq = 8 + OMAP_INTC_START, },
 655         { .irq = -1 },
 656 };
 657
 658 static struct omap_hwmod am33xx_control_hwmod = {
 659         .name           = "control",
 660         .class          = &am33xx_control_hwmod_class,
 661         .clkdm_name     = "l4_wkup_clkdm",
 662         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 663         .mpu_irqs       = am33xx_control_irqs,
 664         .main_clk       = "dpll_core_m4_div2_ck",
 665         .prcm           = {
 666                 .omap4  = {
 667                         .clkctrl_offs   = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
 668                         .modulemode     = MODULEMODE_SWCTRL,
 669                 },
 670         },
 671 };
 672
 673 /*
 674  * 'cpgmac' class
 675  * cpsw/cpgmac sub system
 676  */
 677 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
 678         .rev_offs       = 0x0,
 679         .sysc_offs      = 0x8,
 680         .syss_offs      = 0x4,
 681         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 682                            SYSS_HAS_RESET_STATUS),
 683         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 684                            MSTANDBY_NO),
 685         .sysc_fields    = &omap_hwmod_sysc_type3,
 686 };
 687
 688 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
 689         .name           = "cpgmac0",
 690         .sysc           = &am33xx_cpgmac_sysc,
 691 };
 692
 693 static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
 694         { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
 695         { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
 696         { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
 697         { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
 698         { .irq = -1 },
 699 };
 700
 701 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
 702         .name           = "cpgmac0",
 703         .class          = &am33xx_cpgmac0_hwmod_class,
 704         .clkdm_name     = "cpsw_125mhz_clkdm",
 705         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 706         .mpu_irqs       = am33xx_cpgmac0_irqs,
 707         .main_clk       = "cpsw_125mhz_gclk",
 708         .prcm           = {
 709                 .omap4  = {
 710                         .clkctrl_offs   = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
 711                         .modulemode     = MODULEMODE_SWCTRL,
 712                 },
 713         },
 714 };
 715
 716 /*
 717  * mdio class
 718  */
 719 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
 720         .name           = "davinci_mdio",
 721 };
 722
 723 static struct omap_hwmod am33xx_mdio_hwmod = {
 724         .name           = "davinci_mdio",
 725         .class          = &am33xx_mdio_hwmod_class,
 726         .clkdm_name     = "cpsw_125mhz_clkdm",
 727         .main_clk       = "cpsw_125mhz_gclk",
 728 };
 729
 730 /*
 731  * dcan class
 732  */
 733 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
 734         .name = "d_can",
 735 };
 736
 737 /* dcan0 */
 738 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
 739         { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
 740         { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
 741         { .irq = -1 },
 742 };
 743
 744 static struct omap_hwmod am33xx_dcan0_hwmod = {
 745         .name           = "d_can0",
 746         .class          = &am33xx_dcan_hwmod_class,
 747         .clkdm_name     = "l4ls_clkdm",
 748         .mpu_irqs       = am33xx_dcan0_irqs,
 749         .main_clk       = "dcan0_fck",
 750         .prcm           = {
 751                 .omap4  = {
 752                         .clkctrl_offs   = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
 753                         .modulemode     = MODULEMODE_SWCTRL,
 754                 },
 755         },
 756 };
 757
 758 /* dcan1 */
 759 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
 760         { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
 761         { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
 762         { .irq = -1 },
 763 };
 764 static struct omap_hwmod am33xx_dcan1_hwmod = {
 765         .name           = "d_can1",
 766         .class          = &am33xx_dcan_hwmod_class,
 767         .clkdm_name     = "l4ls_clkdm",
 768         .mpu_irqs       = am33xx_dcan1_irqs,
 769         .main_clk       = "dcan1_fck",
 770         .prcm           = {
 771                 .omap4  = {
 772                         .clkctrl_offs   = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
 773                         .modulemode     = MODULEMODE_SWCTRL,
 774                 },
 775         },
 776 };
 777
 778 /* elm */
 779 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
 780         .rev_offs       = 0x0000,
 781         .sysc_offs      = 0x0010,
 782         .syss_offs      = 0x0014,
 783         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 784                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 785                         SYSS_HAS_RESET_STATUS),
 786         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 787         .sysc_fields    = &omap_hwmod_sysc_type1,
 788 };
 789
 790 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
 791         .name           = "elm",
 792         .sysc           = &am33xx_elm_sysc,
 793 };
 794
 795 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
 796         { .irq = 4 + OMAP_INTC_START, },
 797         { .irq = -1 },
 798 };
 799
 800 static struct omap_hwmod am33xx_elm_hwmod = {
 801         .name           = "elm",
 802         .class          = &am33xx_elm_hwmod_class,
 803         .clkdm_name     = "l4ls_clkdm",
 804         .mpu_irqs       = am33xx_elm_irqs,
 805         .main_clk       = "l4ls_gclk",
 806         .prcm           = {
 807                 .omap4  = {
 808                         .clkctrl_offs   = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
 809                         .modulemode     = MODULEMODE_SWCTRL,
 810                 },
 811         },
 812 };
 813
 814 /* pwmss  */
 815 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
 816         .rev_offs       = 0x0,
 817         .sysc_offs      = 0x4,
 818         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
 819         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 820                         SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 821                         MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 822         .sysc_fields    = &omap_hwmod_sysc_type2,
 823 };
 824
 825 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
 826         .name           = "epwmss",
 827         .sysc           = &am33xx_epwmss_sysc,
 828 };
 829
 830 static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
 831         .name           = "ecap",
 832 };
 833
 834 static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
 835         .name           = "eqep",
 836 };
 837
 838 static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
 839         .name           = "ehrpwm",
 840 };
 841
 842 /* epwmss0 */
 843 static struct omap_hwmod am33xx_epwmss0_hwmod = {
 844         .name           = "epwmss0",
 845         .class          = &am33xx_epwmss_hwmod_class,
 846         .clkdm_name     = "l4ls_clkdm",
 847         .main_clk       = "l4ls_gclk",
 848         .prcm           = {
 849                 .omap4  = {
 850                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
 851                         .modulemode     = MODULEMODE_SWCTRL,
 852                 },
 853         },
 854 };
 855
 856 /* ecap0 */
 857 static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
 858         { .irq = 31 + OMAP_INTC_START, },
 859         { .irq = -1 },
 860 };
 861
 862 static struct omap_hwmod am33xx_ecap0_hwmod = {
 863         .name           = "ecap0",
 864         .class          = &am33xx_ecap_hwmod_class,
 865         .clkdm_name     = "l4ls_clkdm",
 866         .mpu_irqs       = am33xx_ecap0_irqs,
 867         .main_clk       = "l4ls_gclk",
 868 };
 869
 870 /* eqep0 */
 871 static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
 872         { .irq = 79 + OMAP_INTC_START, },
 873         { .irq = -1 },
 874 };
 875
 876 static struct omap_hwmod am33xx_eqep0_hwmod = {
 877         .name           = "eqep0",
 878         .class          = &am33xx_eqep_hwmod_class,
 879         .clkdm_name     = "l4ls_clkdm",
 880         .mpu_irqs       = am33xx_eqep0_irqs,
 881         .main_clk       = "l4ls_gclk",
 882 };
 883
 884 /* ehrpwm0 */
 885 static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
 886         { .name = "int", .irq = 86 + OMAP_INTC_START, },
 887         { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
 888         { .irq = -1 },
 889 };
 890
 891 static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
 892         .name           = "ehrpwm0",
 893         .class          = &am33xx_ehrpwm_hwmod_class,
 894         .clkdm_name     = "l4ls_clkdm",
 895         .mpu_irqs       = am33xx_ehrpwm0_irqs,
 896         .main_clk       = "l4ls_gclk",
 897 };
 898
 899 /* epwmss1 */
 900 static struct omap_hwmod am33xx_epwmss1_hwmod = {
 901         .name           = "epwmss1",
 902         .class          = &am33xx_epwmss_hwmod_class,
 903         .clkdm_name     = "l4ls_clkdm",
 904         .main_clk       = "l4ls_gclk",
 905         .prcm           = {
 906                 .omap4  = {
 907                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
 908                         .modulemode     = MODULEMODE_SWCTRL,
 909                 },
 910         },
 911 };
 912
 913 /* ecap1 */
 914 static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
 915         { .irq = 47 + OMAP_INTC_START, },
 916         { .irq = -1 },
 917 };
 918
 919 static struct omap_hwmod am33xx_ecap1_hwmod = {
 920         .name           = "ecap1",
 921         .class          = &am33xx_ecap_hwmod_class,
 922         .clkdm_name     = "l4ls_clkdm",
 923         .mpu_irqs       = am33xx_ecap1_irqs,
 924         .main_clk       = "l4ls_gclk",
 925 };
 926
 927 /* eqep1 */
 928 static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
 929         { .irq = 88 + OMAP_INTC_START, },
 930         { .irq = -1 },
 931 };
 932
 933 static struct omap_hwmod am33xx_eqep1_hwmod = {
 934         .name           = "eqep1",
 935         .class          = &am33xx_eqep_hwmod_class,
 936         .clkdm_name     = "l4ls_clkdm",
 937         .mpu_irqs       = am33xx_eqep1_irqs,
 938         .main_clk       = "l4ls_gclk",
 939 };
 940
 941 /* ehrpwm1 */
 942 static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
 943         { .name = "int", .irq = 87 + OMAP_INTC_START, },
 944         { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
 945         { .irq = -1 },
 946 };
 947
 948 static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
 949         .name           = "ehrpwm1",
 950         .class          = &am33xx_ehrpwm_hwmod_class,
 951         .clkdm_name     = "l4ls_clkdm",
 952         .mpu_irqs       = am33xx_ehrpwm1_irqs,
 953         .main_clk       = "l4ls_gclk",
 954 };
 955
 956 /* epwmss2 */
 957 static struct omap_hwmod am33xx_epwmss2_hwmod = {
 958         .name           = "epwmss2",
 959         .class          = &am33xx_epwmss_hwmod_class,
 960         .clkdm_name     = "l4ls_clkdm",
 961         .main_clk       = "l4ls_gclk",
 962         .prcm           = {
 963                 .omap4  = {
 964                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
 965                         .modulemode     = MODULEMODE_SWCTRL,
 966                 },
 967         },
 968 };
 969
 970 /* ecap2 */
 971 static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
 972         { .irq = 61 + OMAP_INTC_START, },
 973         { .irq = -1 },
 974 };
 975
 976 static struct omap_hwmod am33xx_ecap2_hwmod = {
 977         .name           = "ecap2",
 978         .class          = &am33xx_ecap_hwmod_class,
 979         .clkdm_name     = "l4ls_clkdm",
 980         .mpu_irqs       = am33xx_ecap2_irqs,
 981         .main_clk       = "l4ls_gclk",
 982 };
 983
 984 /* eqep2 */
 985 static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
 986         { .irq = 89 + OMAP_INTC_START, },
 987         { .irq = -1 },
 988 };
 989
 990 static struct omap_hwmod am33xx_eqep2_hwmod = {
 991         .name           = "eqep2",
 992         .class          = &am33xx_eqep_hwmod_class,
 993         .clkdm_name     = "l4ls_clkdm",
 994         .mpu_irqs       = am33xx_eqep2_irqs,
 995         .main_clk       = "l4ls_gclk",
 996 };
 997
 998 /* ehrpwm2 */
 999 static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
1000         { .name = "int", .irq = 39 + OMAP_INTC_START, },
1001         { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
1002         { .irq = -1 },
1003 };
1004
1005 static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
1006         .name           = "ehrpwm2",
1007         .class          = &am33xx_ehrpwm_hwmod_class,
1008         .clkdm_name     = "l4ls_clkdm",
1009         .mpu_irqs       = am33xx_ehrpwm2_irqs,
1010         .main_clk       = "l4ls_gclk",
1011 };
1012
1013 /*
1014  * 'gpio' class: for gpio 0,1,2,3
1015  */
1016 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
1017         .rev_offs       = 0x0000,
1018         .sysc_offs      = 0x0010,
1019         .syss_offs      = 0x0114,
1020         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1021                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1022                           SYSS_HAS_RESET_STATUS),
1023         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1024                           SIDLE_SMART_WKUP),
1025         .sysc_fields    = &omap_hwmod_sysc_type1,
1026 };
1027
1028 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
1029         .name           = "gpio",
1030         .sysc           = &am33xx_gpio_sysc,
1031         .rev            = 2,
1032 };
1033
1034 static struct omap_gpio_dev_attr gpio_dev_attr = {
1035         .bank_width     = 32,
1036         .dbck_flag      = true,
1037 };
1038
1039 /* gpio0 */
1040 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
1041         { .role = "dbclk", .clk = "gpio0_dbclk" },
1042 };
1043
1044 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
1045         { .irq = 96 + OMAP_INTC_START, },
1046         { .irq = -1 },
1047 };
1048
1049 static struct omap_hwmod am33xx_gpio0_hwmod = {
1050         .name           = "gpio1",
1051         .class          = &am33xx_gpio_hwmod_class,
1052         .clkdm_name     = "l4_wkup_clkdm",
1053         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1054         .mpu_irqs       = am33xx_gpio0_irqs,
1055         .main_clk       = "dpll_core_m4_div2_ck",
1056         .prcm           = {
1057                 .omap4  = {
1058                         .clkctrl_offs   = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
1059                         .modulemode     = MODULEMODE_SWCTRL,
1060                 },
1061         },
1062         .opt_clks       = gpio0_opt_clks,
1063         .opt_clks_cnt   = ARRAY_SIZE(gpio0_opt_clks),
1064         .dev_attr       = &gpio_dev_attr,
1065 };
1066
1067 /* gpio1 */
1068 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
1069         { .irq = 98 + OMAP_INTC_START, },
1070         { .irq = -1 },
1071 };
1072
1073 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1074         { .role = "dbclk", .clk = "gpio1_dbclk" },
1075 };
1076
1077 static struct omap_hwmod am33xx_gpio1_hwmod = {
1078         .name           = "gpio2",
1079         .class          = &am33xx_gpio_hwmod_class,
1080         .clkdm_name     = "l4ls_clkdm",
1081         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1082         .mpu_irqs       = am33xx_gpio1_irqs,
1083         .main_clk       = "l4ls_gclk",
1084         .prcm           = {
1085                 .omap4  = {
1086                         .clkctrl_offs   = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
1087                         .modulemode     = MODULEMODE_SWCTRL,
1088                 },
1089         },
1090         .opt_clks       = gpio1_opt_clks,
1091         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1092         .dev_attr       = &gpio_dev_attr,
1093 };
1094
1095 /* gpio2 */
1096 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
1097         { .irq = 32 + OMAP_INTC_START, },
1098         { .irq = -1 },
1099 };
1100
1101 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1102         { .role = "dbclk", .clk = "gpio2_dbclk" },
1103 };
1104
1105 static struct omap_hwmod am33xx_gpio2_hwmod = {
1106         .name           = "gpio3",
1107         .class          = &am33xx_gpio_hwmod_class,
1108         .clkdm_name     = "l4ls_clkdm",
1109         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1110         .mpu_irqs       = am33xx_gpio2_irqs,
1111         .main_clk       = "l4ls_gclk",
1112         .prcm           = {
1113                 .omap4  = {
1114                         .clkctrl_offs   = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
1115                         .modulemode     = MODULEMODE_SWCTRL,
1116                 },
1117         },
1118         .opt_clks       = gpio2_opt_clks,
1119         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1120         .dev_attr       = &gpio_dev_attr,
1121 };
1122
1123 /* gpio3 */
1124 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
1125         { .irq = 62 + OMAP_INTC_START, },
1126         { .irq = -1 },
1127 };
1128
1129 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1130         { .role = "dbclk", .clk = "gpio3_dbclk" },
1131 };
1132
1133 static struct omap_hwmod am33xx_gpio3_hwmod = {
1134         .name           = "gpio4",
1135         .class          = &am33xx_gpio_hwmod_class,
1136         .clkdm_name     = "l4ls_clkdm",
1137         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1138         .mpu_irqs       = am33xx_gpio3_irqs,
1139         .main_clk       = "l4ls_gclk",
1140         .prcm           = {
1141                 .omap4  = {
1142                         .clkctrl_offs   = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
1143                         .modulemode     = MODULEMODE_SWCTRL,
1144                 },
1145         },
1146         .opt_clks       = gpio3_opt_clks,
1147         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1148         .dev_attr       = &gpio_dev_attr,
1149 };
1150
1151 /* gpmc */
1152 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
1153         .rev_offs       = 0x0,
1154         .sysc_offs      = 0x10,
1155         .syss_offs      = 0x14,
1156         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1157                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1158         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1159         .sysc_fields    = &omap_hwmod_sysc_type1,
1160 };
1161
1162 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
1163         .name           = "gpmc",
1164         .sysc           = &gpmc_sysc,
1165 };
1166
1167 static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
1168         { .irq = 100 + OMAP_INTC_START, },
1169         { .irq = -1 },
1170 };
1171
1172 static struct omap_hwmod am33xx_gpmc_hwmod = {
1173         .name           = "gpmc",
1174         .class          = &am33xx_gpmc_hwmod_class,
1175         .clkdm_name     = "l3s_clkdm",
1176         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1177         .mpu_irqs       = am33xx_gpmc_irqs,
1178         .main_clk       = "l3s_gclk",
1179         .prcm           = {
1180                 .omap4  = {
1181                         .clkctrl_offs   = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
1182                         .modulemode     = MODULEMODE_SWCTRL,
1183                 },
1184         },
1185 };
1186
1187 /* 'i2c' class */
1188 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
1189         .sysc_offs      = 0x0010,
1190         .syss_offs      = 0x0090,
1191         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1192                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1193                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1194         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1195                           SIDLE_SMART_WKUP),
1196         .sysc_fields    = &omap_hwmod_sysc_type1,
1197 };
1198
1199 static struct omap_hwmod_class i2c_class = {
1200         .name           = "i2c",
1201         .sysc           = &am33xx_i2c_sysc,
1202         .rev            = OMAP_I2C_IP_VERSION_2,
1203         .reset          = &omap_i2c_reset,
1204 };
1205
1206 static struct omap_i2c_dev_attr i2c_dev_attr = {
1207         .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1208 };
1209
1210 /* i2c1 */
1211 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1212         { .irq = 70 + OMAP_INTC_START, },
1213         { .irq = -1 },
1214 };
1215
1216 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
1217         { .name = "tx", .dma_req = 0, },
1218         { .name = "rx", .dma_req = 0, },
1219         { .dma_req = -1 }
1220 };
1221
1222 static struct omap_hwmod am33xx_i2c1_hwmod = {
1223         .name           = "i2c1",
1224         .class          = &i2c_class,
1225         .clkdm_name     = "l4_wkup_clkdm",
1226         .mpu_irqs       = i2c1_mpu_irqs,
1227         .sdma_reqs      = i2c1_edma_reqs,
1228         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1229         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
1230         .prcm           = {
1231                 .omap4  = {
1232                         .clkctrl_offs   = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
1233                         .modulemode     = MODULEMODE_SWCTRL,
1234                 },
1235         },
1236         .dev_attr       = &i2c_dev_attr,
1237 };
1238
1239 /* i2c1 */
1240 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1241         { .irq = 71 + OMAP_INTC_START, },
1242         { .irq = -1 },
1243 };
1244
1245 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
1246         { .name = "tx", .dma_req = 0, },
1247         { .name = "rx", .dma_req = 0, },
1248         { .dma_req = -1 }
1249 };
1250
1251 static struct omap_hwmod am33xx_i2c2_hwmod = {
1252         .name           = "i2c2",
1253         .class          = &i2c_class,
1254         .clkdm_name     = "l4ls_clkdm",
1255         .mpu_irqs       = i2c2_mpu_irqs,
1256         .sdma_reqs      = i2c2_edma_reqs,
1257         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1258         .main_clk       = "dpll_per_m2_div4_ck",
1259         .prcm           = {
1260                 .omap4 = {
1261                         .clkctrl_offs   = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
1262                         .modulemode     = MODULEMODE_SWCTRL,
1263                 },
1264         },
1265         .dev_attr       = &i2c_dev_attr,
1266 };
1267
1268 /* i2c3 */
1269 static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
1270         { .name = "tx", .dma_req = 0, },
1271         { .name = "rx", .dma_req = 0, },
1272         { .dma_req = -1 }
1273 };
1274
1275 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1276         { .irq = 30 + OMAP_INTC_START, },
1277         { .irq = -1 },
1278 };
1279
1280 static struct omap_hwmod am33xx_i2c3_hwmod = {
1281         .name           = "i2c3",
1282         .class          = &i2c_class,
1283         .clkdm_name     = "l4ls_clkdm",
1284         .mpu_irqs       = i2c3_mpu_irqs,
1285         .sdma_reqs      = i2c3_edma_reqs,
1286         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1287         .main_clk       = "dpll_per_m2_div4_ck",
1288         .prcm           = {
1289                 .omap4  = {
1290                         .clkctrl_offs   = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
1291                         .modulemode     = MODULEMODE_SWCTRL,
1292                 },
1293         },
1294         .dev_attr       = &i2c_dev_attr,
1295 };
1296
1297
1298 /* lcdc */
1299 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
1300         .rev_offs       = 0x0,
1301         .sysc_offs      = 0x54,
1302         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1303         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1304         .sysc_fields    = &omap_hwmod_sysc_type2,
1305 };
1306
1307 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1308         .name           = "lcdc",
1309         .sysc           = &lcdc_sysc,
1310 };
1311
1312 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1313         { .irq = 36 + OMAP_INTC_START, },
1314         { .irq = -1 },
1315 };
1316
1317 static struct omap_hwmod am33xx_lcdc_hwmod = {
1318         .name           = "lcdc",
1319         .class          = &am33xx_lcdc_hwmod_class,
1320         .clkdm_name     = "lcdc_clkdm",
1321         .mpu_irqs       = am33xx_lcdc_irqs,
1322         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1323         .main_clk       = "lcd_gclk",
1324         .prcm           = {
1325                 .omap4  = {
1326                         .clkctrl_offs   = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1327                         .modulemode     = MODULEMODE_SWCTRL,
1328                 },
1329         },
1330 };
1331
1332 /*
1333  * 'mailbox' class
1334  * mailbox module allowing communication between the on-chip processors using a
1335  * queued mailbox-interrupt mechanism.
1336  */
1337 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1338         .rev_offs       = 0x0000,
1339         .sysc_offs      = 0x0010,
1340         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1341                           SYSC_HAS_SOFTRESET),
1342         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1343         .sysc_fields    = &omap_hwmod_sysc_type2,
1344 };
1345
1346 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1347         .name   = "mailbox",
1348         .sysc   = &am33xx_mailbox_sysc,
1349 };
1350
1351 static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1352         { .irq = 77 + OMAP_INTC_START, },
1353         { .irq = -1 },
1354 };
1355
1356 static struct omap_hwmod am33xx_mailbox_hwmod = {
1357         .name           = "mailbox",
1358         .class          = &am33xx_mailbox_hwmod_class,
1359         .clkdm_name     = "l4ls_clkdm",
1360         .mpu_irqs       = am33xx_mailbox_irqs,
1361         .main_clk       = "l4ls_gclk",
1362         .prcm = {
1363                 .omap4 = {
1364                         .clkctrl_offs   = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1365                         .modulemode     = MODULEMODE_SWCTRL,
1366                 },
1367         },
1368 };
1369
1370 /*
1371  * 'mcasp' class
1372  */
1373 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
1374         .rev_offs       = 0x0,
1375         .sysc_offs      = 0x4,
1376         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1377         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1378         .sysc_fields    = &omap_hwmod_sysc_type3,
1379 };
1380
1381 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1382         .name           = "mcasp",
1383         .sysc           = &am33xx_mcasp_sysc,
1384 };
1385
1386 /* mcasp0 */
1387 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1388         { .name = "ax", .irq = 80 + OMAP_INTC_START, },
1389         { .name = "ar", .irq = 81 + OMAP_INTC_START, },
1390         { .irq = -1 },
1391 };
1392
1393 static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
1394         { .name = "tx", .dma_req = 8, },
1395         { .name = "rx", .dma_req = 9, },
1396         { .dma_req = -1 }
1397 };
1398
1399 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1400         .name           = "mcasp0",
1401         .class          = &am33xx_mcasp_hwmod_class,
1402         .clkdm_name     = "l3s_clkdm",
1403         .mpu_irqs       = am33xx_mcasp0_irqs,
1404         .sdma_reqs      = am33xx_mcasp0_edma_reqs,
1405         .main_clk       = "mcasp0_fck",
1406         .prcm           = {
1407                 .omap4  = {
1408                         .clkctrl_offs   = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1409                         .modulemode     = MODULEMODE_SWCTRL,
1410                 },
1411         },
1412 };
1413
1414 /* mcasp1 */
1415 static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1416         { .name = "ax", .irq = 82 + OMAP_INTC_START, },
1417         { .name = "ar", .irq = 83 + OMAP_INTC_START, },
1418         { .irq = -1 },
1419 };
1420
1421 static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
1422         { .name = "tx", .dma_req = 10, },
1423         { .name = "rx", .dma_req = 11, },
1424         { .dma_req = -1 }
1425 };
1426
1427 static struct omap_hwmod am33xx_mcasp1_hwmod = {
1428         .name           = "mcasp1",
1429         .class          = &am33xx_mcasp_hwmod_class,
1430         .clkdm_name     = "l3s_clkdm",
1431         .mpu_irqs       = am33xx_mcasp1_irqs,
1432         .sdma_reqs      = am33xx_mcasp1_edma_reqs,
1433         .main_clk       = "mcasp1_fck",
1434         .prcm           = {
1435                 .omap4  = {
1436                         .clkctrl_offs   = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1437                         .modulemode     = MODULEMODE_SWCTRL,
1438                 },
1439         },
1440 };
1441
1442 /* 'mmc' class */
1443 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1444         .rev_offs       = 0x1fc,
1445         .sysc_offs      = 0x10,
1446         .syss_offs      = 0x14,
1447         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1448                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1449                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1450         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1451         .sysc_fields    = &omap_hwmod_sysc_type1,
1452 };
1453
1454 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1455         .name           = "mmc",
1456         .sysc           = &am33xx_mmc_sysc,
1457 };
1458
1459 /* mmc0 */
1460 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1461         { .irq = 64 + OMAP_INTC_START, },
1462         { .irq = -1 },
1463 };
1464
1465 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1466         { .name = "tx", .dma_req = 24, },
1467         { .name = "rx", .dma_req = 25, },
1468         { .dma_req = -1 }
1469 };
1470
1471 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1472         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1473 };
1474
1475 static struct omap_hwmod am33xx_mmc0_hwmod = {
1476         .name           = "mmc1",
1477         .class          = &am33xx_mmc_hwmod_class,
1478         .clkdm_name     = "l4ls_clkdm",
1479         .mpu_irqs       = am33xx_mmc0_irqs,
1480         .sdma_reqs      = am33xx_mmc0_edma_reqs,
1481         .main_clk       = "mmc_clk",
1482         .prcm           = {
1483                 .omap4  = {
1484                         .clkctrl_offs   = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1485                         .modulemode     = MODULEMODE_SWCTRL,
1486                 },
1487         },
1488         .dev_attr       = &am33xx_mmc0_dev_attr,
1489 };
1490
1491 /* mmc1 */
1492 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1493         { .irq = 28 + OMAP_INTC_START, },
1494         { .irq = -1 },
1495 };
1496
1497 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1498         { .name = "tx", .dma_req = 2, },
1499         { .name = "rx", .dma_req = 3, },
1500         { .dma_req = -1 }
1501 };
1502
1503 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1504         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1505 };
1506
1507 static struct omap_hwmod am33xx_mmc1_hwmod = {
1508         .name           = "mmc2",
1509         .class          = &am33xx_mmc_hwmod_class,
1510         .clkdm_name     = "l4ls_clkdm",
1511         .mpu_irqs       = am33xx_mmc1_irqs,
1512         .sdma_reqs      = am33xx_mmc1_edma_reqs,
1513         .main_clk       = "mmc_clk",
1514         .prcm           = {
1515                 .omap4  = {
1516                         .clkctrl_offs   = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1517                         .modulemode     = MODULEMODE_SWCTRL,
1518                 },
1519         },
1520         .dev_attr       = &am33xx_mmc1_dev_attr,
1521 };
1522
1523 /* mmc2 */
1524 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1525         { .irq = 29 + OMAP_INTC_START, },
1526         { .irq = -1 },
1527 };
1528
1529 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1530         { .name = "tx", .dma_req = 64, },
1531         { .name = "rx", .dma_req = 65, },
1532         { .dma_req = -1 }
1533 };
1534
1535 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1536         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1537 };
1538 static struct omap_hwmod am33xx_mmc2_hwmod = {
1539         .name           = "mmc3",
1540         .class          = &am33xx_mmc_hwmod_class,
1541         .clkdm_name     = "l3s_clkdm",
1542         .mpu_irqs       = am33xx_mmc2_irqs,
1543         .sdma_reqs      = am33xx_mmc2_edma_reqs,
1544         .main_clk       = "mmc_clk",
1545         .prcm           = {
1546                 .omap4  = {
1547                         .clkctrl_offs   = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1548                         .modulemode     = MODULEMODE_SWCTRL,
1549                 },
1550         },
1551         .dev_attr       = &am33xx_mmc2_dev_attr,
1552 };
1553
1554 /*
1555  * 'rtc' class
1556  * rtc subsystem
1557  */
1558 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
1559         .rev_offs       = 0x0074,
1560         .sysc_offs      = 0x0078,
1561         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1562         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
1563                           SIDLE_SMART | SIDLE_SMART_WKUP),
1564         .sysc_fields    = &omap_hwmod_sysc_type3,
1565 };
1566
1567 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1568         .name           = "rtc",
1569         .sysc           = &am33xx_rtc_sysc,
1570 };
1571
1572 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1573         { .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
1574         { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
1575         { .irq = -1 },
1576 };
1577
1578 static struct omap_hwmod am33xx_rtc_hwmod = {
1579         .name           = "rtc",
1580         .class          = &am33xx_rtc_hwmod_class,
1581         .clkdm_name     = "l4_rtc_clkdm",
1582         .mpu_irqs       = am33xx_rtc_irqs,
1583         .main_clk       = "clk_32768_ck",
1584         .prcm           = {
1585                 .omap4  = {
1586                         .clkctrl_offs   = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1587                         .modulemode     = MODULEMODE_SWCTRL,
1588                 },
1589         },
1590 };
1591
1592 /* 'spi' class */
1593 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1594         .rev_offs       = 0x0000,
1595         .sysc_offs      = 0x0110,
1596         .syss_offs      = 0x0114,
1597         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1598                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1599                           SYSS_HAS_RESET_STATUS),
1600         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1601         .sysc_fields    = &omap_hwmod_sysc_type1,
1602 };
1603
1604 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1605         .name           = "mcspi",
1606         .sysc           = &am33xx_mcspi_sysc,
1607         .rev            = OMAP4_MCSPI_REV,
1608 };
1609
1610 /* spi0 */
1611 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1612         { .irq = 65 + OMAP_INTC_START, },
1613         { .irq = -1 },
1614 };
1615
1616 static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
1617         { .name = "rx0", .dma_req = 17 },
1618         { .name = "tx0", .dma_req = 16 },
1619         { .name = "rx1", .dma_req = 19 },
1620         { .name = "tx1", .dma_req = 18 },
1621         { .dma_req = -1 }
1622 };
1623
1624 static struct omap2_mcspi_dev_attr mcspi_attrib = {
1625         .num_chipselect = 2,
1626 };
1627 static struct omap_hwmod am33xx_spi0_hwmod = {
1628         .name           = "spi0",
1629         .class          = &am33xx_spi_hwmod_class,
1630         .clkdm_name     = "l4ls_clkdm",
1631         .mpu_irqs       = am33xx_spi0_irqs,
1632         .sdma_reqs      = am33xx_mcspi0_edma_reqs,
1633         .main_clk       = "dpll_per_m2_div4_ck",
1634         .prcm           = {
1635                 .omap4  = {
1636                         .clkctrl_offs   = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1637                         .modulemode     = MODULEMODE_SWCTRL,
1638                 },
1639         },
1640         .dev_attr       = &mcspi_attrib,
1641 };
1642
1643 /* spi1 */
1644 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1645         { .irq = 125 + OMAP_INTC_START, },
1646         { .irq = -1 },
1647 };
1648
1649 static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
1650         { .name = "rx0", .dma_req = 43 },
1651         { .name = "tx0", .dma_req = 42 },
1652         { .name = "rx1", .dma_req = 45 },
1653         { .name = "tx1", .dma_req = 44 },
1654         { .dma_req = -1 }
1655 };
1656
1657 static struct omap_hwmod am33xx_spi1_hwmod = {
1658         .name           = "spi1",
1659         .class          = &am33xx_spi_hwmod_class,
1660         .clkdm_name     = "l4ls_clkdm",
1661         .mpu_irqs       = am33xx_spi1_irqs,
1662         .sdma_reqs      = am33xx_mcspi1_edma_reqs,
1663         .main_clk       = "dpll_per_m2_div4_ck",
1664         .prcm           = {
1665                 .omap4  = {
1666                         .clkctrl_offs   = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1667                         .modulemode     = MODULEMODE_SWCTRL,
1668                 },
1669         },
1670         .dev_attr       = &mcspi_attrib,
1671 };
1672
1673 /*
1674  * 'spinlock' class
1675  * spinlock provides hardware assistance for synchronizing the
1676  * processes running on multiple processors
1677  */
1678 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1679         .name           = "spinlock",
1680 };
1681
1682 static struct omap_hwmod am33xx_spinlock_hwmod = {
1683         .name           = "spinlock",
1684         .class          = &am33xx_spinlock_hwmod_class,
1685         .clkdm_name     = "l4ls_clkdm",
1686         .main_clk       = "l4ls_gclk",
1687         .prcm           = {
1688                 .omap4  = {
1689                         .clkctrl_offs   = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1690                         .modulemode     = MODULEMODE_SWCTRL,
1691                 },
1692         },
1693 };
1694
1695 /* 'timer 2-7' class */
1696 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1697         .rev_offs       = 0x0000,
1698         .sysc_offs      = 0x0010,
1699         .syss_offs      = 0x0014,
1700         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1701         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1702                           SIDLE_SMART_WKUP),
1703         .sysc_fields    = &omap_hwmod_sysc_type2,
1704 };
1705
1706 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1707         .name           = "timer",
1708         .sysc           = &am33xx_timer_sysc,
1709 };
1710
1711 /* timer1 1ms */
1712 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1713         .rev_offs       = 0x0000,
1714         .sysc_offs      = 0x0010,
1715         .syss_offs      = 0x0014,
1716         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1717                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1718                         SYSS_HAS_RESET_STATUS),
1719         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1720         .sysc_fields    = &omap_hwmod_sysc_type1,
1721 };
1722
1723 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1724         .name           = "timer",
1725         .sysc           = &am33xx_timer1ms_sysc,
1726 };
1727
1728 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1729         { .irq = 67 + OMAP_INTC_START, },
1730         { .irq = -1 },
1731 };
1732
1733 static struct omap_hwmod am33xx_timer1_hwmod = {
1734         .name           = "timer1",
1735         .class          = &am33xx_timer1ms_hwmod_class,
1736         .clkdm_name     = "l4_wkup_clkdm",
1737         .mpu_irqs       = am33xx_timer1_irqs,
1738         .main_clk       = "timer1_fck",
1739         .prcm           = {
1740                 .omap4  = {
1741                         .clkctrl_offs   = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1742                         .modulemode     = MODULEMODE_SWCTRL,
1743                 },
1744         },
1745 };
1746
1747 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1748         { .irq = 68 + OMAP_INTC_START, },
1749         { .irq = -1 },
1750 };
1751
1752 static struct omap_hwmod am33xx_timer2_hwmod = {
1753         .name           = "timer2",
1754         .class          = &am33xx_timer_hwmod_class,
1755         .clkdm_name     = "l4ls_clkdm",
1756         .mpu_irqs       = am33xx_timer2_irqs,
1757         .main_clk       = "timer2_fck",
1758         .prcm           = {
1759                 .omap4  = {
1760                         .clkctrl_offs   = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1761                         .modulemode     = MODULEMODE_SWCTRL,
1762                 },
1763         },
1764 };
1765
1766 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1767         { .irq = 69 + OMAP_INTC_START, },
1768         { .irq = -1 },
1769 };
1770
1771 static struct omap_hwmod am33xx_timer3_hwmod = {
1772         .name           = "timer3",
1773         .class          = &am33xx_timer_hwmod_class,
1774         .clkdm_name     = "l4ls_clkdm",
1775         .mpu_irqs       = am33xx_timer3_irqs,
1776         .main_clk       = "timer3_fck",
1777         .prcm           = {
1778                 .omap4  = {
1779                         .clkctrl_offs   = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1780                         .modulemode     = MODULEMODE_SWCTRL,
1781                 },
1782         },
1783 };
1784
1785 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1786         { .irq = 92 + OMAP_INTC_START, },
1787         { .irq = -1 },
1788 };
1789
1790 static struct omap_hwmod am33xx_timer4_hwmod = {
1791         .name           = "timer4",
1792         .class          = &am33xx_timer_hwmod_class,
1793         .clkdm_name     = "l4ls_clkdm",
1794         .mpu_irqs       = am33xx_timer4_irqs,
1795         .main_clk       = "timer4_fck",
1796         .prcm           = {
1797                 .omap4  = {
1798                         .clkctrl_offs   = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1799                         .modulemode     = MODULEMODE_SWCTRL,
1800                 },
1801         },
1802 };
1803
1804 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1805         { .irq = 93 + OMAP_INTC_START, },
1806         { .irq = -1 },
1807 };
1808
1809 static struct omap_hwmod am33xx_timer5_hwmod = {
1810         .name           = "timer5",
1811         .class          = &am33xx_timer_hwmod_class,
1812         .clkdm_name     = "l4ls_clkdm",
1813         .mpu_irqs       = am33xx_timer5_irqs,
1814         .main_clk       = "timer5_fck",
1815         .prcm           = {
1816                 .omap4  = {
1817                         .clkctrl_offs   = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1818                         .modulemode     = MODULEMODE_SWCTRL,
1819                 },
1820         },
1821 };
1822
1823 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
1824         { .irq = 94 + OMAP_INTC_START, },
1825         { .irq = -1 },
1826 };
1827
1828 static struct omap_hwmod am33xx_timer6_hwmod = {
1829         .name           = "timer6",
1830         .class          = &am33xx_timer_hwmod_class,
1831         .clkdm_name     = "l4ls_clkdm",
1832         .mpu_irqs       = am33xx_timer6_irqs,
1833         .main_clk       = "timer6_fck",
1834         .prcm           = {
1835                 .omap4  = {
1836                         .clkctrl_offs   = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1837                         .modulemode     = MODULEMODE_SWCTRL,
1838                 },
1839         },
1840 };
1841
1842 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
1843         { .irq = 95 + OMAP_INTC_START, },
1844         { .irq = -1 },
1845 };
1846
1847 static struct omap_hwmod am33xx_timer7_hwmod = {
1848         .name           = "timer7",
1849         .class          = &am33xx_timer_hwmod_class,
1850         .clkdm_name     = "l4ls_clkdm",
1851         .mpu_irqs       = am33xx_timer7_irqs,
1852         .main_clk       = "timer7_fck",
1853         .prcm           = {
1854                 .omap4  = {
1855                         .clkctrl_offs   = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1856                         .modulemode     = MODULEMODE_SWCTRL,
1857                 },
1858         },
1859 };
1860
1861 /* tpcc */
1862 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1863         .name           = "tpcc",
1864 };
1865
1866 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
1867         { .name = "edma0", .irq = 12 + OMAP_INTC_START, },
1868         { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
1869         { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
1870         { .irq = -1 },
1871 };
1872
1873 static struct omap_hwmod am33xx_tpcc_hwmod = {
1874         .name           = "tpcc",
1875         .class          = &am33xx_tpcc_hwmod_class,
1876         .clkdm_name     = "l3_clkdm",
1877         .mpu_irqs       = am33xx_tpcc_irqs,
1878         .main_clk       = "l3_gclk",
1879         .prcm           = {
1880                 .omap4  = {
1881                         .clkctrl_offs   = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
1882                         .modulemode     = MODULEMODE_SWCTRL,
1883                 },
1884         },
1885 };
1886
1887 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1888         .rev_offs       = 0x0,
1889         .sysc_offs      = 0x10,
1890         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1891                           SYSC_HAS_MIDLEMODE),
1892         .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1893         .sysc_fields    = &omap_hwmod_sysc_type2,
1894 };
1895
1896 /* 'tptc' class */
1897 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1898         .name           = "tptc",
1899         .sysc           = &am33xx_tptc_sysc,
1900 };
1901
1902 /* tptc0 */
1903 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
1904         { .irq = 112 + OMAP_INTC_START, },
1905         { .irq = -1 },
1906 };
1907
1908 static struct omap_hwmod am33xx_tptc0_hwmod = {
1909         .name           = "tptc0",
1910         .class          = &am33xx_tptc_hwmod_class,
1911         .clkdm_name     = "l3_clkdm",
1912         .mpu_irqs       = am33xx_tptc0_irqs,
1913         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1914         .main_clk       = "l3_gclk",
1915         .prcm           = {
1916                 .omap4  = {
1917                         .clkctrl_offs   = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
1918                         .modulemode     = MODULEMODE_SWCTRL,
1919                 },
1920         },
1921 };
1922
1923 /* tptc1 */
1924 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
1925         { .irq = 113 + OMAP_INTC_START, },
1926         { .irq = -1 },
1927 };
1928
1929 static struct omap_hwmod am33xx_tptc1_hwmod = {
1930         .name           = "tptc1",
1931         .class          = &am33xx_tptc_hwmod_class,
1932         .clkdm_name     = "l3_clkdm",
1933         .mpu_irqs       = am33xx_tptc1_irqs,
1934         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1935         .main_clk       = "l3_gclk",
1936         .prcm           = {
1937                 .omap4  = {
1938                         .clkctrl_offs   = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
1939                         .modulemode     = MODULEMODE_SWCTRL,
1940                 },
1941         },
1942 };
1943
1944 /* tptc2 */
1945 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
1946         { .irq = 114 + OMAP_INTC_START, },
1947         { .irq = -1 },
1948 };
1949
1950 static struct omap_hwmod am33xx_tptc2_hwmod = {
1951         .name           = "tptc2",
1952         .class          = &am33xx_tptc_hwmod_class,
1953         .clkdm_name     = "l3_clkdm",
1954         .mpu_irqs       = am33xx_tptc2_irqs,
1955         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1956         .main_clk       = "l3_gclk",
1957         .prcm           = {
1958                 .omap4  = {
1959                         .clkctrl_offs   = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
1960                         .modulemode     = MODULEMODE_SWCTRL,
1961                 },
1962         },
1963 };
1964
1965 /* 'uart' class */
1966 static struct omap_hwmod_class_sysconfig uart_sysc = {
1967         .rev_offs       = 0x50,
1968         .sysc_offs      = 0x54,
1969         .syss_offs      = 0x58,
1970         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1971                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1972         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1973                           SIDLE_SMART_WKUP),
1974         .sysc_fields    = &omap_hwmod_sysc_type1,
1975 };
1976
1977 static struct omap_hwmod_class uart_class = {
1978         .name           = "uart",
1979         .sysc           = &uart_sysc,
1980 };
1981
1982 /* uart1 */
1983 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
1984         { .name = "tx", .dma_req = 26, },
1985         { .name = "rx", .dma_req = 27, },
1986         { .dma_req = -1 }
1987 };
1988
1989 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
1990         { .irq = 72 + OMAP_INTC_START, },
1991         { .irq = -1 },
1992 };
1993
1994 static struct omap_hwmod am33xx_uart1_hwmod = {
1995         .name           = "uart1",
1996         .class          = &uart_class,
1997         .clkdm_name     = "l4_wkup_clkdm",
1998         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1999         .mpu_irqs       = am33xx_uart1_irqs,
2000         .sdma_reqs      = uart1_edma_reqs,
2001         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
2002         .prcm           = {
2003                 .omap4  = {
2004                         .clkctrl_offs   = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
2005                         .modulemode     = MODULEMODE_SWCTRL,
2006                 },
2007         },
2008 };
2009
2010 /* uart2 */
2011 static struct omap_hwmod_dma_info uart2_edma_reqs[] = {
2012         { .name = "tx", .dma_req = 28, },
2013         { .name = "rx", .dma_req = 29, },
2014         { .dma_req = -1 }
2015 };
2016
2017 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2018         { .irq = 73 + OMAP_INTC_START, },
2019         { .irq = -1 },
2020 };
2021
2022 static struct omap_hwmod am33xx_uart2_hwmod = {
2023         .name           = "uart2",
2024         .class          = &uart_class,
2025         .clkdm_name     = "l4ls_clkdm",
2026         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2027         .mpu_irqs       = am33xx_uart2_irqs,
2028         .sdma_reqs      = uart2_edma_reqs,
2029         .main_clk       = "dpll_per_m2_div4_ck",
2030         .prcm           = {
2031                 .omap4  = {
2032                         .clkctrl_offs   = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
2033                         .modulemode     = MODULEMODE_SWCTRL,
2034                 },
2035         },
2036 };
2037
2038 /* uart3 */
2039 static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
2040         { .name = "tx", .dma_req = 30, },
2041         { .name = "rx", .dma_req = 31, },
2042         { .dma_req = -1 }
2043 };
2044
2045 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2046         { .irq = 74 + OMAP_INTC_START, },
2047         { .irq = -1 },
2048 };
2049
2050 static struct omap_hwmod am33xx_uart3_hwmod = {
2051         .name           = "uart3",
2052         .class          = &uart_class,
2053         .clkdm_name     = "l4ls_clkdm",
2054         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2055         .mpu_irqs       = am33xx_uart3_irqs,
2056         .sdma_reqs      = uart3_edma_reqs,
2057         .main_clk       = "dpll_per_m2_div4_ck",
2058         .prcm           = {
2059                 .omap4  = {
2060                         .clkctrl_offs   = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2061                         .modulemode     = MODULEMODE_SWCTRL,
2062                 },
2063         },
2064 };
2065
2066 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2067         { .irq = 44 + OMAP_INTC_START, },
2068         { .irq = -1 },
2069 };
2070
2071 static struct omap_hwmod am33xx_uart4_hwmod = {
2072         .name           = "uart4",
2073         .class          = &uart_class,
2074         .clkdm_name     = "l4ls_clkdm",
2075         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2076         .mpu_irqs       = am33xx_uart4_irqs,
2077         .sdma_reqs      = uart1_edma_reqs,
2078         .main_clk       = "dpll_per_m2_div4_ck",
2079         .prcm           = {
2080                 .omap4  = {
2081                         .clkctrl_offs   = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2082                         .modulemode     = MODULEMODE_SWCTRL,
2083                 },
2084         },
2085 };
2086
2087 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2088         { .irq = 45 + OMAP_INTC_START, },
2089         { .irq = -1 },
2090 };
2091
2092 static struct omap_hwmod am33xx_uart5_hwmod = {
2093         .name           = "uart5",
2094         .class          = &uart_class,
2095         .clkdm_name     = "l4ls_clkdm",
2096         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2097         .mpu_irqs       = am33xx_uart5_irqs,
2098         .sdma_reqs      = uart1_edma_reqs,
2099         .main_clk       = "dpll_per_m2_div4_ck",
2100         .prcm           = {
2101                 .omap4  = {
2102                         .clkctrl_offs   = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2103                         .modulemode     = MODULEMODE_SWCTRL,
2104                 },
2105         },
2106 };
2107
2108 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2109         { .irq = 46 + OMAP_INTC_START, },
2110         { .irq = -1 },
2111 };
2112
2113 static struct omap_hwmod am33xx_uart6_hwmod = {
2114         .name           = "uart6",
2115         .class          = &uart_class,
2116         .clkdm_name     = "l4ls_clkdm",
2117         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2118         .mpu_irqs       = am33xx_uart6_irqs,
2119         .sdma_reqs      = uart1_edma_reqs,
2120         .main_clk       = "dpll_per_m2_div4_ck",
2121         .prcm           = {
2122                 .omap4  = {
2123                         .clkctrl_offs   = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2124                         .modulemode     = MODULEMODE_SWCTRL,
2125                 },
2126         },
2127 };
2128
2129 /* 'wd_timer' class */
2130 static struct omap_hwmod_class_sysconfig wdt_sysc = {
2131         .rev_offs       = 0x0,
2132         .sysc_offs      = 0x10,
2133         .syss_offs      = 0x14,
2134         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2135                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2136         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2137                         SIDLE_SMART_WKUP),
2138         .sysc_fields    = &omap_hwmod_sysc_type1,
2139 };
2140
2141 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2142         .name           = "wd_timer",
2143         .sysc           = &wdt_sysc,
2144         .pre_shutdown   = &omap2_wd_timer_disable,
2145 };
2146
2147 /*
2148  * XXX: device.c file uses hardcoded name for watchdog timer
2149  * driver "wd_timer2, so we are also using same name as of now...
2150  */
2151 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2152         .name           = "wd_timer2",
2153         .class          = &am33xx_wd_timer_hwmod_class,
2154         .clkdm_name     = "l4_wkup_clkdm",
2155         .flags          = HWMOD_SWSUP_SIDLE,
2156         .main_clk       = "wdt1_fck",
2157         .prcm           = {
2158                 .omap4  = {
2159                         .clkctrl_offs   = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2160                         .modulemode     = MODULEMODE_SWCTRL,
2161                 },
2162         },
2163 };
2164
2165 /*
2166  * 'usb_otg' class
2167  * high-speed on-the-go universal serial bus (usb_otg) controller
2168  */
2169 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2170         .rev_offs       = 0x0,
2171         .sysc_offs      = 0x10,
2172         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
2173         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2174                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2175         .sysc_fields    = &omap_hwmod_sysc_type2,
2176 };
2177
2178 static struct omap_hwmod_class am33xx_usbotg_class = {
2179         .name           = "usbotg",
2180         .sysc           = &am33xx_usbhsotg_sysc,
2181 };
2182
2183 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2184         { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
2185         { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
2186         { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
2187         { .irq = -1, },
2188 };
2189
2190 static struct omap_hwmod am33xx_usbss_hwmod = {
2191         .name           = "usb_otg_hs",
2192         .class          = &am33xx_usbotg_class,
2193         .clkdm_name     = "l3s_clkdm",
2194         .mpu_irqs       = am33xx_usbss_mpu_irqs,
2195         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2196         .main_clk       = "usbotg_fck",
2197         .prcm           = {
2198                 .omap4  = {
2199                         .clkctrl_offs   = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2200                         .modulemode     = MODULEMODE_SWCTRL,
2201                 },
2202         },
2203 };
2204
2205
2206 /*
2207  * Interfaces
2208  */
2209
2210 /* l4 fw -> emif fw */
2211 static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
2212         .master         = &am33xx_l4_fw_hwmod,
2213         .slave          = &am33xx_emif_fw_hwmod,
2214         .clk            = "l4fw_gclk",
2215         .user           = OCP_USER_MPU,
2216 };
2217
2218 static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
2219         {
2220                 .pa_start       = 0x4c000000,
2221                 .pa_end         = 0x4c000fff,
2222                 .flags          = ADDR_TYPE_RT
2223         },
2224         { }
2225 };
2226 /* l3 main -> emif */
2227 static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
2228         .master         = &am33xx_l3_main_hwmod,
2229         .slave          = &am33xx_emif_hwmod,
2230         .clk            = "dpll_core_m4_ck",
2231         .addr           = am33xx_emif_addrs,
2232         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2233 };
2234
2235 /* mpu -> l3 main */
2236 static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
2237         .master         = &am33xx_mpu_hwmod,
2238         .slave          = &am33xx_l3_main_hwmod,
2239         .clk            = "dpll_mpu_m2_ck",
2240         .user           = OCP_USER_MPU,
2241 };
2242
2243 /* l3 main -> l4 hs */
2244 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
2245         .master         = &am33xx_l3_main_hwmod,
2246         .slave          = &am33xx_l4_hs_hwmod,
2247         .clk            = "l3s_gclk",
2248         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2249 };
2250
2251 /* l3 main -> l3 s */
2252 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
2253         .master         = &am33xx_l3_main_hwmod,
2254         .slave          = &am33xx_l3_s_hwmod,
2255         .clk            = "l3s_gclk",
2256         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2257 };
2258
2259 /* l3 s -> l4 per/ls */
2260 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
2261         .master         = &am33xx_l3_s_hwmod,
2262         .slave          = &am33xx_l4_ls_hwmod,
2263         .clk            = "l3s_gclk",
2264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2265 };
2266
2267 /* l3 s -> l4 wkup */
2268 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
2269         .master         = &am33xx_l3_s_hwmod,
2270         .slave          = &am33xx_l4_wkup_hwmod,
2271         .clk            = "l3s_gclk",
2272         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2273 };
2274
2275 /* l3 s -> l4 fw */
2276 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
2277         .master         = &am33xx_l3_s_hwmod,
2278         .slave          = &am33xx_l4_fw_hwmod,
2279         .clk            = "l3s_gclk",
2280         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2281 };
2282
2283 /* l3 main -> l3 instr */
2284 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
2285         .master         = &am33xx_l3_main_hwmod,
2286         .slave          = &am33xx_l3_instr_hwmod,
2287         .clk            = "l3s_gclk",
2288         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2289 };
2290
2291 /* mpu -> prcm */
2292 static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
2293         .master         = &am33xx_mpu_hwmod,
2294         .slave          = &am33xx_prcm_hwmod,
2295         .clk            = "dpll_mpu_m2_ck",
2296         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2297 };
2298
2299 /* l3 s -> l3 main*/
2300 static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
2301         .master         = &am33xx_l3_s_hwmod,
2302         .slave          = &am33xx_l3_main_hwmod,
2303         .clk            = "l3s_gclk",
2304         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2305 };
2306
2307 /* pru-icss -> l3 main */
2308 static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
2309         .master         = &am33xx_pruss_hwmod,
2310         .slave          = &am33xx_l3_main_hwmod,
2311         .clk            = "l3_gclk",
2312         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2313 };
2314
2315 /* wkup m3 -> l4 wkup */
2316 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
2317         .master         = &am33xx_wkup_m3_hwmod,
2318         .slave          = &am33xx_l4_wkup_hwmod,
2319         .clk            = "dpll_core_m4_div2_ck",
2320         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2321 };
2322
2323 /* gfx -> l3 main */
2324 static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
2325         .master         = &am33xx_gfx_hwmod,
2326         .slave          = &am33xx_l3_main_hwmod,
2327         .clk            = "dpll_core_m4_ck",
2328         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2329 };
2330
2331 /* l4 wkup -> wkup m3 */
2332 static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
2333         {
2334                 .name           = "umem",
2335                 .pa_start       = 0x44d00000,
2336                 .pa_end         = 0x44d00000 + SZ_16K - 1,
2337                 .flags          = ADDR_TYPE_RT
2338         },
2339         {
2340                 .name           = "dmem",
2341                 .pa_start       = 0x44d80000,
2342                 .pa_end         = 0x44d80000 + SZ_8K - 1,
2343                 .flags          = ADDR_TYPE_RT
2344         },
2345         { }
2346 };
2347
2348 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
2349         .master         = &am33xx_l4_wkup_hwmod,
2350         .slave          = &am33xx_wkup_m3_hwmod,
2351         .clk            = "dpll_core_m4_div2_ck",
2352         .addr           = am33xx_wkup_m3_addrs,
2353         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2354 };
2355
2356 /* l4 hs -> pru-icss */
2357 static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
2358         {
2359                 .pa_start       = 0x4a300000,
2360                 .pa_end         = 0x4a300000 + SZ_512K - 1,
2361                 .flags          = ADDR_TYPE_RT
2362         },
2363         { }
2364 };
2365
2366 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
2367         .master         = &am33xx_l4_hs_hwmod,
2368         .slave          = &am33xx_pruss_hwmod,
2369         .clk            = "dpll_core_m4_ck",
2370         .addr           = am33xx_pruss_addrs,
2371         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2372 };
2373
2374 /* l3 main -> gfx */
2375 static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
2376         {
2377                 .pa_start       = 0x56000000,
2378                 .pa_end         = 0x56000000 + SZ_16M - 1,
2379                 .flags          = ADDR_TYPE_RT
2380         },
2381         { }
2382 };
2383
2384 static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
2385         .master         = &am33xx_l3_main_hwmod,
2386         .slave          = &am33xx_gfx_hwmod,
2387         .clk            = "dpll_core_m4_ck",
2388         .addr           = am33xx_gfx_addrs,
2389         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2390 };
2391
2392 /* l4 wkup -> smartreflex0 */
2393 static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
2394         {
2395                 .pa_start       = 0x44e37000,
2396                 .pa_end         = 0x44e37000 + SZ_4K - 1,
2397                 .flags          = ADDR_TYPE_RT
2398         },
2399         { }
2400 };
2401
2402 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
2403         .master         = &am33xx_l4_wkup_hwmod,
2404         .slave          = &am33xx_smartreflex0_hwmod,
2405         .clk            = "dpll_core_m4_div2_ck",
2406         .addr           = am33xx_smartreflex0_addrs,
2407         .user           = OCP_USER_MPU,
2408 };
2409
2410 /* l4 wkup -> smartreflex1 */
2411 static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
2412         {
2413                 .pa_start       = 0x44e39000,
2414                 .pa_end         = 0x44e39000 + SZ_4K - 1,
2415                 .flags          = ADDR_TYPE_RT
2416         },
2417         { }
2418 };
2419
2420 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
2421         .master         = &am33xx_l4_wkup_hwmod,
2422         .slave          = &am33xx_smartreflex1_hwmod,
2423         .clk            = "dpll_core_m4_div2_ck",
2424         .addr           = am33xx_smartreflex1_addrs,
2425         .user           = OCP_USER_MPU,
2426 };
2427
2428 /* l4 wkup -> control */
2429 static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
2430         {
2431                 .pa_start       = 0x44e10000,
2432                 .pa_end         = 0x44e10000 + SZ_8K - 1,
2433                 .flags          = ADDR_TYPE_RT
2434         },
2435         { }
2436 };
2437
2438 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
2439         .master         = &am33xx_l4_wkup_hwmod,
2440         .slave          = &am33xx_control_hwmod,
2441         .clk            = "dpll_core_m4_div2_ck",
2442         .addr           = am33xx_control_addrs,
2443         .user           = OCP_USER_MPU,
2444 };
2445
2446 /* l4 wkup -> rtc */
2447 static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
2448         {
2449                 .pa_start       = 0x44e3e000,
2450                 .pa_end         = 0x44e3e000 + SZ_4K - 1,
2451                 .flags          = ADDR_TYPE_RT
2452         },
2453         { }
2454 };
2455
2456 static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
2457         .master         = &am33xx_l4_wkup_hwmod,
2458         .slave          = &am33xx_rtc_hwmod,
2459         .clk            = "clkdiv32k_ick",
2460         .addr           = am33xx_rtc_addrs,
2461         .user           = OCP_USER_MPU,
2462 };
2463
2464 /* l4 per/ls -> DCAN0 */
2465 static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
2466         {
2467                 .pa_start       = 0x481CC000,
2468                 .pa_end         = 0x481CC000 + SZ_4K - 1,
2469                 .flags          = ADDR_TYPE_RT
2470         },
2471         { }
2472 };
2473
2474 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
2475         .master         = &am33xx_l4_ls_hwmod,
2476         .slave          = &am33xx_dcan0_hwmod,
2477         .clk            = "l4ls_gclk",
2478         .addr           = am33xx_dcan0_addrs,
2479         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2480 };
2481
2482 /* l4 per/ls -> DCAN1 */
2483 static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
2484         {
2485                 .pa_start       = 0x481D0000,
2486                 .pa_end         = 0x481D0000 + SZ_4K - 1,
2487                 .flags          = ADDR_TYPE_RT
2488         },
2489         { }
2490 };
2491
2492 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
2493         .master         = &am33xx_l4_ls_hwmod,
2494         .slave          = &am33xx_dcan1_hwmod,
2495         .clk            = "l4ls_gclk",
2496         .addr           = am33xx_dcan1_addrs,
2497         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2498 };
2499
2500 /* l4 per/ls -> GPIO2 */
2501 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
2502         {
2503                 .pa_start       = 0x4804C000,
2504                 .pa_end         = 0x4804C000 + SZ_4K - 1,
2505                 .flags          = ADDR_TYPE_RT,
2506         },
2507         { }
2508 };
2509
2510 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
2511         .master         = &am33xx_l4_ls_hwmod,
2512         .slave          = &am33xx_gpio1_hwmod,
2513         .clk            = "l4ls_gclk",
2514         .addr           = am33xx_gpio1_addrs,
2515         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2516 };
2517
2518 /* l4 per/ls -> gpio3 */
2519 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
2520         {
2521                 .pa_start       = 0x481AC000,
2522                 .pa_end         = 0x481AC000 + SZ_4K - 1,
2523                 .flags          = ADDR_TYPE_RT,
2524         },
2525         { }
2526 };
2527
2528 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
2529         .master         = &am33xx_l4_ls_hwmod,
2530         .slave          = &am33xx_gpio2_hwmod,
2531         .clk            = "l4ls_gclk",
2532         .addr           = am33xx_gpio2_addrs,
2533         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2534 };
2535
2536 /* l4 per/ls -> gpio4 */
2537 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
2538         {
2539                 .pa_start       = 0x481AE000,
2540                 .pa_end         = 0x481AE000 + SZ_4K - 1,
2541                 .flags          = ADDR_TYPE_RT,
2542         },
2543         { }
2544 };
2545
2546 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
2547         .master         = &am33xx_l4_ls_hwmod,
2548         .slave          = &am33xx_gpio3_hwmod,
2549         .clk            = "l4ls_gclk",
2550         .addr           = am33xx_gpio3_addrs,
2551         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2552 };
2553
2554 /* L4 WKUP -> I2C1 */
2555 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
2556         {
2557                 .pa_start       = 0x44E0B000,
2558                 .pa_end         = 0x44E0B000 + SZ_4K - 1,
2559                 .flags          = ADDR_TYPE_RT,
2560         },
2561         { }
2562 };
2563
2564 static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
2565         .master         = &am33xx_l4_wkup_hwmod,
2566         .slave          = &am33xx_i2c1_hwmod,
2567         .clk            = "dpll_core_m4_div2_ck",
2568         .addr           = am33xx_i2c1_addr_space,
2569         .user           = OCP_USER_MPU,
2570 };
2571
2572 /* L4 WKUP -> GPIO1 */
2573 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
2574         {
2575                 .pa_start       = 0x44E07000,
2576                 .pa_end         = 0x44E07000 + SZ_4K - 1,
2577                 .flags          = ADDR_TYPE_RT,
2578         },
2579         { }
2580 };
2581
2582 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
2583         .master         = &am33xx_l4_wkup_hwmod,
2584         .slave          = &am33xx_gpio0_hwmod,
2585         .clk            = "dpll_core_m4_div2_ck",
2586         .addr           = am33xx_gpio0_addrs,
2587         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2588 };
2589
2590 /* L4 WKUP -> ADC_TSC */
2591 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
2592         {
2593                 .pa_start       = 0x44E0D000,
2594                 .pa_end         = 0x44E0D000 + SZ_8K - 1,
2595                 .flags          = ADDR_TYPE_RT
2596         },
2597         { }
2598 };
2599
2600 static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
2601         .master         = &am33xx_l4_wkup_hwmod,
2602         .slave          = &am33xx_adc_tsc_hwmod,
2603         .clk            = "dpll_core_m4_div2_ck",
2604         .addr           = am33xx_adc_tsc_addrs,
2605         .user           = OCP_USER_MPU,
2606 };
2607
2608 static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
2609         /* cpsw ss */
2610         {
2611                 .pa_start       = 0x4a100000,
2612                 .pa_end         = 0x4a100000 + SZ_2K - 1,
2613         },
2614         /* cpsw wr */
2615         {
2616                 .pa_start       = 0x4a101200,
2617                 .pa_end         = 0x4a101200 + SZ_256 - 1,
2618                 .flags          = ADDR_TYPE_RT,
2619         },
2620         { }
2621 };
2622
2623 static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
2624         .master         = &am33xx_l4_hs_hwmod,
2625         .slave          = &am33xx_cpgmac0_hwmod,
2626         .clk            = "cpsw_125mhz_gclk",
2627         .addr           = am33xx_cpgmac0_addr_space,
2628         .user           = OCP_USER_MPU,
2629 };
2630
2631 static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
2632         {
2633                 .pa_start       = 0x4A101000,
2634                 .pa_end         = 0x4A101000 + SZ_256 - 1,
2635         },
2636         { }
2637 };
2638
2639 static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
2640         .master         = &am33xx_cpgmac0_hwmod,
2641         .slave          = &am33xx_mdio_hwmod,
2642         .addr           = am33xx_mdio_addr_space,
2643         .user           = OCP_USER_MPU,
2644 };
2645
2646 static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
2647         {
2648                 .pa_start       = 0x48080000,
2649                 .pa_end         = 0x48080000 + SZ_8K - 1,
2650                 .flags          = ADDR_TYPE_RT
2651         },
2652         { }
2653 };
2654
2655 static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
2656         .master         = &am33xx_l4_ls_hwmod,
2657         .slave          = &am33xx_elm_hwmod,
2658         .clk            = "l4ls_gclk",
2659         .addr           = am33xx_elm_addr_space,
2660         .user           = OCP_USER_MPU,
2661 };
2662
2663 static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
2664         {
2665                 .pa_start       = 0x48300000,
2666                 .pa_end         = 0x48300000 + SZ_16 - 1,
2667                 .flags          = ADDR_TYPE_RT
2668         },
2669         { }
2670 };
2671
2672 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
2673         .master         = &am33xx_l4_ls_hwmod,
2674         .slave          = &am33xx_epwmss0_hwmod,
2675         .clk            = "l4ls_gclk",
2676         .addr           = am33xx_epwmss0_addr_space,
2677         .user           = OCP_USER_MPU,
2678 };
2679
2680 static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
2681         {
2682                 .pa_start       = 0x48300100,
2683                 .pa_end         = 0x48300100 + SZ_128 - 1,
2684         },
2685         { }
2686 };
2687
2688 static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
2689         .master         = &am33xx_epwmss0_hwmod,
2690         .slave          = &am33xx_ecap0_hwmod,
2691         .clk            = "l4ls_gclk",
2692         .addr           = am33xx_ecap0_addr_space,
2693         .user           = OCP_USER_MPU,
2694 };
2695
2696 static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
2697         {
2698                 .pa_start       = 0x48300180,
2699                 .pa_end         = 0x48300180 + SZ_128 - 1,
2700         },
2701         { }
2702 };
2703
2704 static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
2705         .master         = &am33xx_epwmss0_hwmod,
2706         .slave          = &am33xx_eqep0_hwmod,
2707         .clk            = "l4ls_gclk",
2708         .addr           = am33xx_eqep0_addr_space,
2709         .user           = OCP_USER_MPU,
2710 };
2711
2712 static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
2713         {
2714                 .pa_start       = 0x48300200,
2715                 .pa_end         = 0x48300200 + SZ_128 - 1,
2716         },
2717         { }
2718 };
2719
2720 static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
2721         .master         = &am33xx_epwmss0_hwmod,
2722         .slave          = &am33xx_ehrpwm0_hwmod,
2723         .clk            = "l4ls_gclk",
2724         .addr           = am33xx_ehrpwm0_addr_space,
2725         .user           = OCP_USER_MPU,
2726 };
2727
2728
2729 static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
2730         {
2731                 .pa_start       = 0x48302000,
2732                 .pa_end         = 0x48302000 + SZ_16 - 1,
2733                 .flags          = ADDR_TYPE_RT
2734         },
2735         { }
2736 };
2737
2738 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
2739         .master         = &am33xx_l4_ls_hwmod,
2740         .slave          = &am33xx_epwmss1_hwmod,
2741         .clk            = "l4ls_gclk",
2742         .addr           = am33xx_epwmss1_addr_space,
2743         .user           = OCP_USER_MPU,
2744 };
2745
2746 static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
2747         {
2748                 .pa_start       = 0x48302100,
2749                 .pa_end         = 0x48302100 + SZ_128 - 1,
2750         },
2751         { }
2752 };
2753
2754 static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
2755         .master         = &am33xx_epwmss1_hwmod,
2756         .slave          = &am33xx_ecap1_hwmod,
2757         .clk            = "l4ls_gclk",
2758         .addr           = am33xx_ecap1_addr_space,
2759         .user           = OCP_USER_MPU,
2760 };
2761
2762 static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
2763         {
2764                 .pa_start       = 0x48302180,
2765                 .pa_end         = 0x48302180 + SZ_128 - 1,
2766         },
2767         { }
2768 };
2769
2770 static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
2771         .master         = &am33xx_epwmss1_hwmod,
2772         .slave          = &am33xx_eqep1_hwmod,
2773         .clk            = "l4ls_gclk",
2774         .addr           = am33xx_eqep1_addr_space,
2775         .user           = OCP_USER_MPU,
2776 };
2777
2778 static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
2779         {
2780                 .pa_start       = 0x48302200,
2781                 .pa_end         = 0x48302200 + SZ_128 - 1,
2782         },
2783         { }
2784 };
2785
2786 static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
2787         .master         = &am33xx_epwmss1_hwmod,
2788         .slave          = &am33xx_ehrpwm1_hwmod,
2789         .clk            = "l4ls_gclk",
2790         .addr           = am33xx_ehrpwm1_addr_space,
2791         .user           = OCP_USER_MPU,
2792 };
2793
2794 static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
2795         {
2796                 .pa_start       = 0x48304000,
2797                 .pa_end         = 0x48304000 + SZ_16 - 1,
2798                 .flags          = ADDR_TYPE_RT
2799         },
2800         { }
2801 };
2802
2803 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
2804         .master         = &am33xx_l4_ls_hwmod,
2805         .slave          = &am33xx_epwmss2_hwmod,
2806         .clk            = "l4ls_gclk",
2807         .addr           = am33xx_epwmss2_addr_space,
2808         .user           = OCP_USER_MPU,
2809 };
2810
2811 static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
2812         {
2813                 .pa_start       = 0x48304100,
2814                 .pa_end         = 0x48304100 + SZ_128 - 1,
2815         },
2816         { }
2817 };
2818
2819 static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
2820         .master         = &am33xx_epwmss2_hwmod,
2821         .slave          = &am33xx_ecap2_hwmod,
2822         .clk            = "l4ls_gclk",
2823         .addr           = am33xx_ecap2_addr_space,
2824         .user           = OCP_USER_MPU,
2825 };
2826
2827 static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
2828         {
2829                 .pa_start       = 0x48304180,
2830                 .pa_end         = 0x48304180 + SZ_128 - 1,
2831         },
2832         { }
2833 };
2834
2835 static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
2836         .master         = &am33xx_epwmss2_hwmod,
2837         .slave          = &am33xx_eqep2_hwmod,
2838         .clk            = "l4ls_gclk",
2839         .addr           = am33xx_eqep2_addr_space,
2840         .user           = OCP_USER_MPU,
2841 };
2842
2843 static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
2844         {
2845                 .pa_start       = 0x48304200,
2846                 .pa_end         = 0x48304200 + SZ_128 - 1,
2847         },
2848         { }
2849 };
2850
2851 static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
2852         .master         = &am33xx_epwmss2_hwmod,
2853         .slave          = &am33xx_ehrpwm2_hwmod,
2854         .clk            = "l4ls_gclk",
2855         .addr           = am33xx_ehrpwm2_addr_space,
2856         .user           = OCP_USER_MPU,
2857 };
2858
2859 /* l3s cfg -> gpmc */
2860 static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
2861         {
2862                 .pa_start       = 0x50000000,
2863                 .pa_end         = 0x50000000 + SZ_8K - 1,
2864                 .flags          = ADDR_TYPE_RT,
2865         },
2866         { }
2867 };
2868
2869 static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
2870         .master         = &am33xx_l3_s_hwmod,
2871         .slave          = &am33xx_gpmc_hwmod,
2872         .clk            = "l3s_gclk",
2873         .addr           = am33xx_gpmc_addr_space,
2874         .user           = OCP_USER_MPU,
2875 };
2876
2877 /* i2c2 */
2878 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
2879         {
2880                 .pa_start       = 0x4802A000,
2881                 .pa_end         = 0x4802A000 + SZ_4K - 1,
2882                 .flags          = ADDR_TYPE_RT,
2883         },
2884         { }
2885 };
2886
2887 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
2888         .master         = &am33xx_l4_ls_hwmod,
2889         .slave          = &am33xx_i2c2_hwmod,
2890         .clk            = "l4ls_gclk",
2891         .addr           = am33xx_i2c2_addr_space,
2892         .user           = OCP_USER_MPU,
2893 };
2894
2895 static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
2896         {
2897                 .pa_start       = 0x4819C000,
2898                 .pa_end         = 0x4819C000 + SZ_4K - 1,
2899                 .flags          = ADDR_TYPE_RT
2900         },
2901         { }
2902 };
2903
2904 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
2905         .master         = &am33xx_l4_ls_hwmod,
2906         .slave          = &am33xx_i2c3_hwmod,
2907         .clk            = "l4ls_gclk",
2908         .addr           = am33xx_i2c3_addr_space,
2909         .user           = OCP_USER_MPU,
2910 };
2911
2912 static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
2913         {
2914                 .pa_start       = 0x4830E000,
2915                 .pa_end         = 0x4830E000 + SZ_8K - 1,
2916                 .flags          = ADDR_TYPE_RT,
2917         },
2918         { }
2919 };
2920
2921 static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
2922         .master         = &am33xx_l3_main_hwmod,
2923         .slave          = &am33xx_lcdc_hwmod,
2924         .clk            = "dpll_core_m4_ck",
2925         .addr           = am33xx_lcdc_addr_space,
2926         .user           = OCP_USER_MPU,
2927 };
2928
2929 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
2930         {
2931                 .pa_start       = 0x480C8000,
2932                 .pa_end         = 0x480C8000 + (SZ_4K - 1),
2933                 .flags          = ADDR_TYPE_RT
2934         },
2935         { }
2936 };
2937
2938 /* l4 ls -> mailbox */
2939 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
2940         .master         = &am33xx_l4_ls_hwmod,
2941         .slave          = &am33xx_mailbox_hwmod,
2942         .clk            = "l4ls_gclk",
2943         .addr           = am33xx_mailbox_addrs,
2944         .user           = OCP_USER_MPU,
2945 };
2946
2947 /* l4 ls -> spinlock */
2948 static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
2949         {
2950                 .pa_start       = 0x480Ca000,
2951                 .pa_end         = 0x480Ca000 + SZ_4K - 1,
2952                 .flags          = ADDR_TYPE_RT
2953         },
2954         { }
2955 };
2956
2957 static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
2958         .master         = &am33xx_l4_ls_hwmod,
2959         .slave          = &am33xx_spinlock_hwmod,
2960         .clk            = "l4ls_gclk",
2961         .addr           = am33xx_spinlock_addrs,
2962         .user           = OCP_USER_MPU,
2963 };
2964
2965 /* l4 ls -> mcasp0 */
2966 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
2967         {
2968                 .pa_start       = 0x48038000,
2969                 .pa_end         = 0x48038000 + SZ_8K - 1,
2970                 .flags          = ADDR_TYPE_RT
2971         },
2972         { }
2973 };
2974
2975 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
2976         .master         = &am33xx_l4_ls_hwmod,
2977         .slave          = &am33xx_mcasp0_hwmod,
2978         .clk            = "l4ls_gclk",
2979         .addr           = am33xx_mcasp0_addr_space,
2980         .user           = OCP_USER_MPU,
2981 };
2982
2983 /* l3 s -> mcasp0 data */
2984 static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
2985         {
2986                 .pa_start       = 0x46000000,
2987                 .pa_end         = 0x46000000 + SZ_4M - 1,
2988                 .flags          = ADDR_TYPE_RT
2989         },
2990         { }
2991 };
2992
2993 static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
2994         .master         = &am33xx_l3_s_hwmod,
2995         .slave          = &am33xx_mcasp0_hwmod,
2996         .clk            = "l3s_gclk",
2997         .addr           = am33xx_mcasp0_data_addr_space,
2998         .user           = OCP_USER_SDMA,
2999 };
3000
3001 /* l4 ls -> mcasp1 */
3002 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
3003         {
3004                 .pa_start       = 0x4803C000,
3005                 .pa_end         = 0x4803C000 + SZ_8K - 1,
3006                 .flags          = ADDR_TYPE_RT
3007         },
3008         { }
3009 };
3010
3011 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
3012         .master         = &am33xx_l4_ls_hwmod,
3013         .slave          = &am33xx_mcasp1_hwmod,
3014         .clk            = "l4ls_gclk",
3015         .addr           = am33xx_mcasp1_addr_space,
3016         .user           = OCP_USER_MPU,
3017 };
3018
3019 /* l3 s -> mcasp1 data */
3020 static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
3021         {
3022                 .pa_start       = 0x46400000,
3023                 .pa_end         = 0x46400000 + SZ_4M - 1,
3024                 .flags          = ADDR_TYPE_RT
3025         },
3026         { }
3027 };
3028
3029 static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
3030         .master         = &am33xx_l3_s_hwmod,
3031         .slave          = &am33xx_mcasp1_hwmod,
3032         .clk            = "l3s_gclk",
3033         .addr           = am33xx_mcasp1_data_addr_space,
3034         .user           = OCP_USER_SDMA,
3035 };
3036
3037 /* l4 ls -> mmc0 */
3038 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
3039         {
3040                 .pa_start       = 0x48060100,
3041                 .pa_end         = 0x48060100 + SZ_4K - 1,
3042                 .flags          = ADDR_TYPE_RT,
3043         },
3044         { }
3045 };
3046
3047 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
3048         .master         = &am33xx_l4_ls_hwmod,
3049         .slave          = &am33xx_mmc0_hwmod,
3050         .clk            = "l4ls_gclk",
3051         .addr           = am33xx_mmc0_addr_space,
3052         .user           = OCP_USER_MPU,
3053 };
3054
3055 /* l4 ls -> mmc1 */
3056 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
3057         {
3058                 .pa_start       = 0x481d8100,
3059                 .pa_end         = 0x481d8100 + SZ_4K - 1,
3060                 .flags          = ADDR_TYPE_RT,
3061         },
3062         { }
3063 };
3064
3065 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
3066         .master         = &am33xx_l4_ls_hwmod,
3067         .slave          = &am33xx_mmc1_hwmod,
3068         .clk            = "l4ls_gclk",
3069         .addr           = am33xx_mmc1_addr_space,
3070         .user           = OCP_USER_MPU,
3071 };
3072
3073 /* l3 s -> mmc2 */
3074 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
3075         {
3076                 .pa_start       = 0x47810100,
3077                 .pa_end         = 0x47810100 + SZ_64K - 1,
3078                 .flags          = ADDR_TYPE_RT,
3079         },
3080         { }
3081 };
3082
3083 static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
3084         .master         = &am33xx_l3_s_hwmod,
3085         .slave          = &am33xx_mmc2_hwmod,
3086         .clk            = "l3s_gclk",
3087         .addr           = am33xx_mmc2_addr_space,
3088         .user           = OCP_USER_MPU,
3089 };
3090
3091 /* l4 ls -> mcspi0 */
3092 static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
3093         {
3094                 .pa_start       = 0x48030000,
3095                 .pa_end         = 0x48030000 + SZ_1K - 1,
3096                 .flags          = ADDR_TYPE_RT,
3097         },
3098         { }
3099 };
3100
3101 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
3102         .master         = &am33xx_l4_ls_hwmod,
3103         .slave          = &am33xx_spi0_hwmod,
3104         .clk            = "l4ls_gclk",
3105         .addr           = am33xx_mcspi0_addr_space,
3106         .user           = OCP_USER_MPU,
3107 };
3108
3109 /* l4 ls -> mcspi1 */
3110 static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
3111         {
3112                 .pa_start       = 0x481A0000,
3113                 .pa_end         = 0x481A0000 + SZ_1K - 1,
3114                 .flags          = ADDR_TYPE_RT,
3115         },
3116         { }
3117 };
3118
3119 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
3120         .master         = &am33xx_l4_ls_hwmod,
3121         .slave          = &am33xx_spi1_hwmod,
3122         .clk            = "l4ls_gclk",
3123         .addr           = am33xx_mcspi1_addr_space,
3124         .user           = OCP_USER_MPU,
3125 };
3126
3127 /* l4 wkup -> timer1 */
3128 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
3129         {
3130                 .pa_start       = 0x44E31000,
3131                 .pa_end         = 0x44E31000 + SZ_1K - 1,
3132                 .flags          = ADDR_TYPE_RT
3133         },
3134         { }
3135 };
3136
3137 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
3138         .master         = &am33xx_l4_wkup_hwmod,
3139         .slave          = &am33xx_timer1_hwmod,
3140         .clk            = "dpll_core_m4_div2_ck",
3141         .addr           = am33xx_timer1_addr_space,
3142         .user           = OCP_USER_MPU,
3143 };
3144
3145 /* l4 per -> timer2 */
3146 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
3147         {
3148                 .pa_start       = 0x48040000,
3149                 .pa_end         = 0x48040000 + SZ_1K - 1,
3150                 .flags          = ADDR_TYPE_RT
3151         },
3152         { }
3153 };
3154
3155 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
3156         .master         = &am33xx_l4_ls_hwmod,
3157         .slave          = &am33xx_timer2_hwmod,
3158         .clk            = "l4ls_gclk",
3159         .addr           = am33xx_timer2_addr_space,
3160         .user           = OCP_USER_MPU,
3161 };
3162
3163 /* l4 per -> timer3 */
3164 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
3165         {
3166                 .pa_start       = 0x48042000,
3167                 .pa_end         = 0x48042000 + SZ_1K - 1,
3168                 .flags          = ADDR_TYPE_RT
3169         },
3170         { }
3171 };
3172
3173 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
3174         .master         = &am33xx_l4_ls_hwmod,
3175         .slave          = &am33xx_timer3_hwmod,
3176         .clk            = "l4ls_gclk",
3177         .addr           = am33xx_timer3_addr_space,
3178         .user           = OCP_USER_MPU,
3179 };
3180
3181 /* l4 per -> timer4 */
3182 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
3183         {
3184                 .pa_start       = 0x48044000,
3185                 .pa_end         = 0x48044000 + SZ_1K - 1,
3186                 .flags          = ADDR_TYPE_RT
3187         },
3188         { }
3189 };
3190
3191 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
3192         .master         = &am33xx_l4_ls_hwmod,
3193         .slave          = &am33xx_timer4_hwmod,
3194         .clk            = "l4ls_gclk",
3195         .addr           = am33xx_timer4_addr_space,
3196         .user           = OCP_USER_MPU,
3197 };
3198
3199 /* l4 per -> timer5 */
3200 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
3201         {
3202                 .pa_start       = 0x48046000,
3203                 .pa_end         = 0x48046000 + SZ_1K - 1,
3204                 .flags          = ADDR_TYPE_RT
3205         },
3206         { }
3207 };
3208
3209 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
3210         .master         = &am33xx_l4_ls_hwmod,
3211         .slave          = &am33xx_timer5_hwmod,
3212         .clk            = "l4ls_gclk",
3213         .addr           = am33xx_timer5_addr_space,
3214         .user           = OCP_USER_MPU,
3215 };
3216
3217 /* l4 per -> timer6 */
3218 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
3219         {
3220                 .pa_start       = 0x48048000,
3221                 .pa_end         = 0x48048000 + SZ_1K - 1,
3222                 .flags          = ADDR_TYPE_RT
3223         },
3224         { }
3225 };
3226
3227 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
3228         .master         = &am33xx_l4_ls_hwmod,
3229         .slave          = &am33xx_timer6_hwmod,
3230         .clk            = "l4ls_gclk",
3231         .addr           = am33xx_timer6_addr_space,
3232         .user           = OCP_USER_MPU,
3233 };
3234
3235 /* l4 per -> timer7 */
3236 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
3237         {
3238                 .pa_start       = 0x4804A000,
3239                 .pa_end         = 0x4804A000 + SZ_1K - 1,
3240                 .flags          = ADDR_TYPE_RT
3241         },
3242         { }
3243 };
3244
3245 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
3246         .master         = &am33xx_l4_ls_hwmod,
3247         .slave          = &am33xx_timer7_hwmod,
3248         .clk            = "l4ls_gclk",
3249         .addr           = am33xx_timer7_addr_space,
3250         .user           = OCP_USER_MPU,
3251 };
3252
3253 /* l3 main -> tpcc */
3254 static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
3255         {
3256                 .pa_start       = 0x49000000,
3257                 .pa_end         = 0x49000000 + SZ_32K - 1,
3258                 .flags          = ADDR_TYPE_RT
3259         },
3260         { }
3261 };
3262
3263 static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
3264         .master         = &am33xx_l3_main_hwmod,
3265         .slave          = &am33xx_tpcc_hwmod,
3266         .clk            = "l3_gclk",
3267         .addr           = am33xx_tpcc_addr_space,
3268         .user           = OCP_USER_MPU,
3269 };
3270
3271 /* l3 main -> tpcc0 */
3272 static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
3273         {
3274                 .pa_start       = 0x49800000,
3275                 .pa_end         = 0x49800000 + SZ_8K - 1,
3276                 .flags          = ADDR_TYPE_RT,
3277         },
3278         { }
3279 };
3280
3281 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
3282         .master         = &am33xx_l3_main_hwmod,
3283         .slave          = &am33xx_tptc0_hwmod,
3284         .clk            = "l3_gclk",
3285         .addr           = am33xx_tptc0_addr_space,
3286         .user           = OCP_USER_MPU,
3287 };
3288
3289 /* l3 main -> tpcc1 */
3290 static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
3291         {
3292                 .pa_start       = 0x49900000,
3293                 .pa_end         = 0x49900000 + SZ_8K - 1,
3294                 .flags          = ADDR_TYPE_RT,
3295         },
3296         { }
3297 };
3298
3299 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
3300         .master         = &am33xx_l3_main_hwmod,
3301         .slave          = &am33xx_tptc1_hwmod,
3302         .clk            = "l3_gclk",
3303         .addr           = am33xx_tptc1_addr_space,
3304         .user           = OCP_USER_MPU,
3305 };
3306
3307 /* l3 main -> tpcc2 */
3308 static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
3309         {
3310                 .pa_start       = 0x49a00000,
3311                 .pa_end         = 0x49a00000 + SZ_8K - 1,
3312                 .flags          = ADDR_TYPE_RT,
3313         },
3314         { }
3315 };
3316
3317 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
3318         .master         = &am33xx_l3_main_hwmod,
3319         .slave          = &am33xx_tptc2_hwmod,
3320         .clk            = "l3_gclk",
3321         .addr           = am33xx_tptc2_addr_space,
3322         .user           = OCP_USER_MPU,
3323 };
3324
3325 /* l4 wkup -> uart1 */
3326 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
3327         {
3328                 .pa_start       = 0x44E09000,
3329                 .pa_end         = 0x44E09000 + SZ_8K - 1,
3330                 .flags          = ADDR_TYPE_RT,
3331         },
3332         { }
3333 };
3334
3335 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
3336         .master         = &am33xx_l4_wkup_hwmod,
3337         .slave          = &am33xx_uart1_hwmod,
3338         .clk            = "dpll_core_m4_div2_ck",
3339         .addr           = am33xx_uart1_addr_space,
3340         .user           = OCP_USER_MPU,
3341 };
3342
3343 /* l4 ls -> uart2 */
3344 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
3345         {
3346                 .pa_start       = 0x48022000,
3347                 .pa_end         = 0x48022000 + SZ_8K - 1,
3348                 .flags          = ADDR_TYPE_RT,
3349         },
3350         { }
3351 };
3352
3353 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
3354         .master         = &am33xx_l4_ls_hwmod,
3355         .slave          = &am33xx_uart2_hwmod,
3356         .clk            = "l4ls_gclk",
3357         .addr           = am33xx_uart2_addr_space,
3358         .user           = OCP_USER_MPU,
3359 };
3360
3361 /* l4 ls -> uart3 */
3362 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
3363         {
3364                 .pa_start       = 0x48024000,
3365                 .pa_end         = 0x48024000 + SZ_8K - 1,
3366                 .flags          = ADDR_TYPE_RT,
3367         },
3368         { }
3369 };
3370
3371 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
3372         .master         = &am33xx_l4_ls_hwmod,
3373         .slave          = &am33xx_uart3_hwmod,
3374         .clk            = "l4ls_gclk",
3375         .addr           = am33xx_uart3_addr_space,
3376         .user           = OCP_USER_MPU,
3377 };
3378
3379 /* l4 ls -> uart4 */
3380 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
3381         {
3382                 .pa_start       = 0x481A6000,
3383                 .pa_end         = 0x481A6000 + SZ_8K - 1,
3384                 .flags          = ADDR_TYPE_RT,
3385         },
3386         { }
3387 };
3388
3389 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
3390         .master         = &am33xx_l4_ls_hwmod,
3391         .slave          = &am33xx_uart4_hwmod,
3392         .clk            = "l4ls_gclk",
3393         .addr           = am33xx_uart4_addr_space,
3394         .user           = OCP_USER_MPU,
3395 };
3396
3397 /* l4 ls -> uart5 */
3398 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
3399         {
3400                 .pa_start       = 0x481A8000,
3401                 .pa_end         = 0x481A8000 + SZ_8K - 1,
3402                 .flags          = ADDR_TYPE_RT,
3403         },
3404         { }
3405 };
3406
3407 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
3408         .master         = &am33xx_l4_ls_hwmod,
3409         .slave          = &am33xx_uart5_hwmod,
3410         .clk            = "l4ls_gclk",
3411         .addr           = am33xx_uart5_addr_space,
3412         .user           = OCP_USER_MPU,
3413 };
3414
3415 /* l4 ls -> uart6 */
3416 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
3417         {
3418                 .pa_start       = 0x481aa000,
3419                 .pa_end         = 0x481aa000 + SZ_8K - 1,
3420                 .flags          = ADDR_TYPE_RT,
3421         },
3422         { }
3423 };
3424
3425 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
3426         .master         = &am33xx_l4_ls_hwmod,
3427         .slave          = &am33xx_uart6_hwmod,
3428         .clk            = "l4ls_gclk",
3429         .addr           = am33xx_uart6_addr_space,
3430         .user           = OCP_USER_MPU,
3431 };
3432
3433 /* l4 wkup -> wd_timer1 */
3434 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
3435         {
3436                 .pa_start       = 0x44e35000,
3437                 .pa_end         = 0x44e35000 + SZ_4K - 1,
3438                 .flags          = ADDR_TYPE_RT
3439         },
3440         { }
3441 };
3442
3443 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
3444         .master         = &am33xx_l4_wkup_hwmod,
3445         .slave          = &am33xx_wd_timer1_hwmod,
3446         .clk            = "dpll_core_m4_div2_ck",
3447         .addr           = am33xx_wd_timer1_addrs,
3448         .user           = OCP_USER_MPU,
3449 };
3450
3451 /* usbss */
3452 /* l3 s -> USBSS interface */
3453 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
3454         {
3455                 .name           = "usbss",
3456                 .pa_start       = 0x47400000,
3457                 .pa_end         = 0x47400000 + SZ_4K - 1,
3458                 .flags          = ADDR_TYPE_RT
3459         },
3460         {
3461                 .name           = "musb0",
3462                 .pa_start       = 0x47401000,
3463                 .pa_end         = 0x47401000 + SZ_2K - 1,
3464                 .flags          = ADDR_TYPE_RT
3465         },
3466         {
3467                 .name           = "musb1",
3468                 .pa_start       = 0x47401800,
3469                 .pa_end         = 0x47401800 + SZ_2K - 1,
3470                 .flags          = ADDR_TYPE_RT
3471         },
3472         { }
3473 };
3474
3475 static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
3476         .master         = &am33xx_l3_s_hwmod,
3477         .slave          = &am33xx_usbss_hwmod,
3478         .clk            = "l3s_gclk",
3479         .addr           = am33xx_usbss_addr_space,
3480         .user           = OCP_USER_MPU,
3481         .flags          = OCPIF_SWSUP_IDLE,
3482 };
3483
3484 /* l3 main -> ocmc */
3485 static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
3486         .master         = &am33xx_l3_main_hwmod,
3487         .slave          = &am33xx_ocmcram_hwmod,
3488         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3489 };
3490
3491 /* l3 main -> sha0 HIB2 */
3492 static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
3493         {
3494                 .pa_start       = 0x53100000,
3495                 .pa_end         = 0x53100000 + SZ_512 - 1,
3496                 .flags          = ADDR_TYPE_RT
3497         },
3498         { }
3499 };
3500
3501 static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
3502         .master         = &am33xx_l3_main_hwmod,
3503         .slave          = &am33xx_sha0_hwmod,
3504         .clk            = "sha0_fck",
3505         .addr           = am33xx_sha0_addrs,
3506         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3507 };
3508
3509 /* l3 main -> AES0 HIB2 */
3510 static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
3511         {
3512                 .pa_start       = 0x53500000,
3513                 .pa_end         = 0x53500000 + SZ_1M - 1,
3514                 .flags          = ADDR_TYPE_RT
3515         },
3516         { }
3517 };
3518
3519 static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
3520         .master         = &am33xx_l3_main_hwmod,
3521         .slave          = &am33xx_aes0_hwmod,
3522         .clk            = "aes0_fck",
3523         .addr           = am33xx_aes0_addrs,
3524         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3525 };
3526
3527 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3528         &am33xx_l4_fw__emif_fw,
3529         &am33xx_l3_main__emif,
3530         &am33xx_mpu__l3_main,
3531         &am33xx_mpu__prcm,
3532         &am33xx_l3_s__l4_ls,
3533         &am33xx_l3_s__l4_wkup,
3534         &am33xx_l3_s__l4_fw,
3535         &am33xx_l3_main__l4_hs,
3536         &am33xx_l3_main__l3_s,
3537         &am33xx_l3_main__l3_instr,
3538         &am33xx_l3_main__gfx,
3539         &am33xx_l3_s__l3_main,
3540         &am33xx_pruss__l3_main,
3541         &am33xx_wkup_m3__l4_wkup,
3542         &am33xx_gfx__l3_main,
3543         &am33xx_l4_wkup__wkup_m3,
3544         &am33xx_l4_wkup__control,
3545         &am33xx_l4_wkup__smartreflex0,
3546         &am33xx_l4_wkup__smartreflex1,
3547         &am33xx_l4_wkup__uart1,
3548         &am33xx_l4_wkup__timer1,
3549         &am33xx_l4_wkup__rtc,
3550         &am33xx_l4_wkup__i2c1,
3551         &am33xx_l4_wkup__gpio0,
3552         &am33xx_l4_wkup__adc_tsc,
3553         &am33xx_l4_wkup__wd_timer1,
3554         &am33xx_l4_hs__pruss,
3555         &am33xx_l4_per__dcan0,
3556         &am33xx_l4_per__dcan1,
3557         &am33xx_l4_per__gpio1,
3558         &am33xx_l4_per__gpio2,
3559         &am33xx_l4_per__gpio3,
3560         &am33xx_l4_per__i2c2,
3561         &am33xx_l4_per__i2c3,
3562         &am33xx_l4_per__mailbox,
3563         &am33xx_l4_ls__mcasp0,
3564         &am33xx_l3_s__mcasp0_data,
3565         &am33xx_l4_ls__mcasp1,
3566         &am33xx_l3_s__mcasp1_data,
3567         &am33xx_l4_ls__mmc0,
3568         &am33xx_l4_ls__mmc1,
3569         &am33xx_l3_s__mmc2,
3570         &am33xx_l4_ls__timer2,
3571         &am33xx_l4_ls__timer3,
3572         &am33xx_l4_ls__timer4,
3573         &am33xx_l4_ls__timer5,
3574         &am33xx_l4_ls__timer6,
3575         &am33xx_l4_ls__timer7,
3576         &am33xx_l3_main__tpcc,
3577         &am33xx_l4_ls__uart2,
3578         &am33xx_l4_ls__uart3,
3579         &am33xx_l4_ls__uart4,
3580         &am33xx_l4_ls__uart5,
3581         &am33xx_l4_ls__uart6,
3582         &am33xx_l4_ls__spinlock,
3583         &am33xx_l4_ls__elm,
3584         &am33xx_l4_ls__epwmss0,
3585         &am33xx_epwmss0__ecap0,
3586         &am33xx_epwmss0__eqep0,
3587         &am33xx_epwmss0__ehrpwm0,
3588         &am33xx_l4_ls__epwmss1,
3589         &am33xx_epwmss1__ecap1,
3590         &am33xx_epwmss1__eqep1,
3591         &am33xx_epwmss1__ehrpwm1,
3592         &am33xx_l4_ls__epwmss2,
3593         &am33xx_epwmss2__ecap2,
3594         &am33xx_epwmss2__eqep2,
3595         &am33xx_epwmss2__ehrpwm2,
3596         &am33xx_l3_s__gpmc,
3597         &am33xx_l3_main__lcdc,
3598         &am33xx_l4_ls__mcspi0,
3599         &am33xx_l4_ls__mcspi1,
3600         &am33xx_l3_main__tptc0,
3601         &am33xx_l3_main__tptc1,
3602         &am33xx_l3_main__tptc2,
3603         &am33xx_l3_main__ocmc,
3604         &am33xx_l3_s__usbss,
3605         &am33xx_l4_hs__cpgmac0,
3606         &am33xx_cpgmac0__mdio,
3607         &am33xx_l3_main__sha0,
3608         &am33xx_l3_main__aes0,
3609         NULL,
3610 };
3611
3612 int __init am33xx_hwmod_init(void)
3613 {
3614         omap_hwmod_init();
3615         return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
3616 }