arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c

   1 /*
   2  *
   3  * Copyright (C) 2013 Texas Instruments Incorporated
   4  *
   5  * Hwmod common for AM335x and AM43x
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/platform_data/gpio-omap.h>
  18 #include <linux/platform_data/hsmmc-omap.h>
  19 #include <linux/platform_data/spi-omap2-mcspi.h>
  20 #include "omap_hwmod.h"
  21 #include "i2c.h"
  22 #include "wd_timer.h"
  23 #include "cm33xx.h"
  24 #include "prm33xx.h"
  25 #include "omap_hwmod_33xx_43xx_common_data.h"
  26 #include "prcm43xx.h"
  27 #include "common.h"
  28
  29 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
  30 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
  31 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
  32
  33 /*
  34  * 'l3' class
  35  * instance(s): l3_main, l3_s, l3_instr
  36  */
  37 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
  38         .name           = "l3",
  39 };
  40
  41 struct omap_hwmod am33xx_l3_main_hwmod = {
  42         .name           = "l3_main",
  43         .class          = &am33xx_l3_hwmod_class,
  44         .clkdm_name     = "l3_clkdm",
  45         .flags          = HWMOD_INIT_NO_IDLE,
  46         .main_clk       = "l3_gclk",
  47         .prcm           = {
  48                 .omap4  = {
  49                         .modulemode     = MODULEMODE_SWCTRL,
  50                 },
  51         },
  52 };
  53
  54 /* l3_s */
  55 struct omap_hwmod am33xx_l3_s_hwmod = {
  56         .name           = "l3_s",
  57         .class          = &am33xx_l3_hwmod_class,
  58         .clkdm_name     = "l3s_clkdm",
  59 };
  60
  61 /* l3_instr */
  62 struct omap_hwmod am33xx_l3_instr_hwmod = {
  63         .name           = "l3_instr",
  64         .class          = &am33xx_l3_hwmod_class,
  65         .clkdm_name     = "l3_clkdm",
  66         .flags          = HWMOD_INIT_NO_IDLE,
  67         .main_clk       = "l3_gclk",
  68         .prcm           = {
  69                 .omap4  = {
  70                         .modulemode     = MODULEMODE_SWCTRL,
  71                 },
  72         },
  73 };
  74
  75 /*
  76  * 'l4' class
  77  * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
  78  */
  79 struct omap_hwmod_class am33xx_l4_hwmod_class = {
  80         .name           = "l4",
  81 };
  82
  83 /* l4_ls */
  84 struct omap_hwmod am33xx_l4_ls_hwmod = {
  85         .name           = "l4_ls",
  86         .class          = &am33xx_l4_hwmod_class,
  87         .clkdm_name     = "l4ls_clkdm",
  88         .flags          = HWMOD_INIT_NO_IDLE,
  89         .main_clk       = "l4ls_gclk",
  90         .prcm           = {
  91                 .omap4  = {
  92                         .modulemode     = MODULEMODE_SWCTRL,
  93                 },
  94         },
  95 };
  96
  97 /* l4_wkup */
  98 struct omap_hwmod am33xx_l4_wkup_hwmod = {
  99         .name           = "l4_wkup",
 100         .class          = &am33xx_l4_hwmod_class,
 101         .clkdm_name     = "l4_wkup_clkdm",
 102         .flags          = HWMOD_INIT_NO_IDLE,
 103         .prcm           = {
 104                 .omap4  = {
 105                         .modulemode     = MODULEMODE_SWCTRL,
 106                 },
 107         },
 108 };
 109
 110 /*
 111  * 'mpu' class
 112  */
 113 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
 114         .name   = "mpu",
 115 };
 116
 117 struct omap_hwmod am33xx_mpu_hwmod = {
 118         .name           = "mpu",
 119         .class          = &am33xx_mpu_hwmod_class,
 120         .clkdm_name     = "mpu_clkdm",
 121         .flags          = HWMOD_INIT_NO_IDLE,
 122         .main_clk       = "dpll_mpu_m2_ck",
 123         .prcm           = {
 124                 .omap4  = {
 125                         .modulemode     = MODULEMODE_SWCTRL,
 126                 },
 127         },
 128 };
 129
 130 /*
 131  * 'wakeup m3' class
 132  * Wakeup controller sub-system under wakeup domain
 133  */
 134 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
 135         .name           = "wkup_m3",
 136 };
 137
 138 /*
 139  * 'pru-icss' class
 140  * Programmable Real-Time Unit and Industrial Communication Subsystem
 141  */
 142 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
 143         .name   = "pruss",
 144 };
 145
 146 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
 147         { .name = "pruss", .rst_shift = 1 },
 148 };
 149
 150 /* pru-icss */
 151 /* Pseudo hwmod for reset control purpose only */
 152 struct omap_hwmod am33xx_pruss_hwmod = {
 153         .name           = "pruss",
 154         .class          = &am33xx_pruss_hwmod_class,
 155         .clkdm_name     = "pruss_ocp_clkdm",
 156         .main_clk       = "pruss_ocp_gclk",
 157         .prcm           = {
 158                 .omap4  = {
 159                         .modulemode     = MODULEMODE_SWCTRL,
 160                 },
 161         },
 162         .rst_lines      = am33xx_pruss_resets,
 163         .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
 164 };
 165
 166 /* gfx */
 167 /* Pseudo hwmod for reset control purpose only */
 168 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 169         .name   = "gfx",
 170 };
 171
 172 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
 173         { .name = "gfx", .rst_shift = 0, .st_shift = 0},
 174 };
 175
 176 struct omap_hwmod am33xx_gfx_hwmod = {
 177         .name           = "gfx",
 178         .class          = &am33xx_gfx_hwmod_class,
 179         .clkdm_name     = "gfx_l3_clkdm",
 180         .main_clk       = "gfx_fck_div_ck",
 181         .prcm           = {
 182                 .omap4  = {
 183                         .modulemode     = MODULEMODE_SWCTRL,
 184                 },
 185         },
 186         .rst_lines      = am33xx_gfx_resets,
 187         .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
 188 };
 189
 190 /*
 191  * 'prcm' class
 192  * power and reset manager (whole prcm infrastructure)
 193  */
 194 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
 195         .name   = "prcm",
 196 };
 197
 198 /* prcm */
 199 struct omap_hwmod am33xx_prcm_hwmod = {
 200         .name           = "prcm",
 201         .class          = &am33xx_prcm_hwmod_class,
 202         .clkdm_name     = "l4_wkup_clkdm",
 203 };
 204
 205 /*
 206  * 'aes0' class
 207  */
 208 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
 209         .rev_offs       = 0x80,
 210         .sysc_offs      = 0x84,
 211         .syss_offs      = 0x88,
 212         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 213 };
 214
 215 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
 216         .name           = "aes0",
 217         .sysc           = &am33xx_aes0_sysc,
 218 };
 219
 220 struct omap_hwmod am33xx_aes0_hwmod = {
 221         .name           = "aes",
 222         .class          = &am33xx_aes0_hwmod_class,
 223         .clkdm_name     = "l3_clkdm",
 224         .main_clk       = "aes0_fck",
 225         .prcm           = {
 226                 .omap4  = {
 227                         .modulemode     = MODULEMODE_SWCTRL,
 228                 },
 229         },
 230 };
 231
 232 /* sha0 HIB2 (the 'P' (public) device) */
 233 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
 234         .rev_offs       = 0x100,
 235         .sysc_offs      = 0x110,
 236         .syss_offs      = 0x114,
 237         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 238 };
 239
 240 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
 241         .name           = "sha0",
 242         .sysc           = &am33xx_sha0_sysc,
 243 };
 244
 245 struct omap_hwmod am33xx_sha0_hwmod = {
 246         .name           = "sham",
 247         .class          = &am33xx_sha0_hwmod_class,
 248         .clkdm_name     = "l3_clkdm",
 249         .main_clk       = "l3_gclk",
 250         .prcm           = {
 251                 .omap4  = {
 252                         .modulemode     = MODULEMODE_SWCTRL,
 253                 },
 254         },
 255 };
 256
 257 /* ocmcram */
 258 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
 259         .name = "ocmcram",
 260 };
 261
 262 struct omap_hwmod am33xx_ocmcram_hwmod = {
 263         .name           = "ocmcram",
 264         .class          = &am33xx_ocmcram_hwmod_class,
 265         .clkdm_name     = "l3_clkdm",
 266         .flags          = HWMOD_INIT_NO_IDLE,
 267         .main_clk       = "l3_gclk",
 268         .prcm           = {
 269                 .omap4  = {
 270                         .modulemode     = MODULEMODE_SWCTRL,
 271                 },
 272         },
 273 };
 274
 275 /* 'smartreflex' class */
 276 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 277         .name           = "smartreflex",
 278 };
 279
 280 /* smartreflex0 */
 281 struct omap_hwmod am33xx_smartreflex0_hwmod = {
 282         .name           = "smartreflex0",
 283         .class          = &am33xx_smartreflex_hwmod_class,
 284         .clkdm_name     = "l4_wkup_clkdm",
 285         .main_clk       = "smartreflex0_fck",
 286         .prcm           = {
 287                 .omap4  = {
 288                         .modulemode     = MODULEMODE_SWCTRL,
 289                 },
 290         },
 291 };
 292
 293 /* smartreflex1 */
 294 struct omap_hwmod am33xx_smartreflex1_hwmod = {
 295         .name           = "smartreflex1",
 296         .class          = &am33xx_smartreflex_hwmod_class,
 297         .clkdm_name     = "l4_wkup_clkdm",
 298         .main_clk       = "smartreflex1_fck",
 299         .prcm           = {
 300                 .omap4  = {
 301                         .modulemode     = MODULEMODE_SWCTRL,
 302                 },
 303         },
 304 };
 305
 306 /*
 307  * 'control' module class
 308  */
 309 struct omap_hwmod_class am33xx_control_hwmod_class = {
 310         .name           = "control",
 311 };
 312
 313 /*
 314  * 'cpgmac' class
 315  * cpsw/cpgmac sub system
 316  */
 317 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
 318         .rev_offs       = 0x0,
 319         .sysc_offs      = 0x8,
 320         .syss_offs      = 0x4,
 321         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 322                            SYSS_HAS_RESET_STATUS),
 323         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 324                            MSTANDBY_NO),
 325         .sysc_fields    = &omap_hwmod_sysc_type3,
 326 };
 327
 328 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
 329         .name           = "cpgmac0",
 330         .sysc           = &am33xx_cpgmac_sysc,
 331 };
 332
 333 struct omap_hwmod am33xx_cpgmac0_hwmod = {
 334         .name           = "cpgmac0",
 335         .class          = &am33xx_cpgmac0_hwmod_class,
 336         .clkdm_name     = "cpsw_125mhz_clkdm",
 337         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 338         .main_clk       = "cpsw_125mhz_gclk",
 339         .mpu_rt_idx     = 1,
 340         .prcm           = {
 341                 .omap4  = {
 342                         .modulemode     = MODULEMODE_SWCTRL,
 343                 },
 344         },
 345 };
 346
 347 /*
 348  * mdio class
 349  */
 350 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
 351         .name           = "davinci_mdio",
 352 };
 353
 354 struct omap_hwmod am33xx_mdio_hwmod = {
 355         .name           = "davinci_mdio",
 356         .class          = &am33xx_mdio_hwmod_class,
 357         .clkdm_name     = "cpsw_125mhz_clkdm",
 358         .main_clk       = "cpsw_125mhz_gclk",
 359 };
 360
 361 /*
 362  * dcan class
 363  */
 364 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
 365         .name = "d_can",
 366 };
 367
 368 /* dcan0 */
 369 struct omap_hwmod am33xx_dcan0_hwmod = {
 370         .name           = "d_can0",
 371         .class          = &am33xx_dcan_hwmod_class,
 372         .clkdm_name     = "l4ls_clkdm",
 373         .main_clk       = "dcan0_fck",
 374         .prcm           = {
 375                 .omap4  = {
 376                         .modulemode     = MODULEMODE_SWCTRL,
 377                 },
 378         },
 379 };
 380
 381 /* dcan1 */
 382 struct omap_hwmod am33xx_dcan1_hwmod = {
 383         .name           = "d_can1",
 384         .class          = &am33xx_dcan_hwmod_class,
 385         .clkdm_name     = "l4ls_clkdm",
 386         .main_clk       = "dcan1_fck",
 387         .prcm           = {
 388                 .omap4  = {
 389                         .modulemode     = MODULEMODE_SWCTRL,
 390                 },
 391         },
 392 };
 393
 394 /* elm */
 395 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
 396         .rev_offs       = 0x0000,
 397         .sysc_offs      = 0x0010,
 398         .syss_offs      = 0x0014,
 399         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 400                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 401                         SYSS_HAS_RESET_STATUS),
 402         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 403         .sysc_fields    = &omap_hwmod_sysc_type1,
 404 };
 405
 406 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
 407         .name           = "elm",
 408         .sysc           = &am33xx_elm_sysc,
 409 };
 410
 411 struct omap_hwmod am33xx_elm_hwmod = {
 412         .name           = "elm",
 413         .class          = &am33xx_elm_hwmod_class,
 414         .clkdm_name     = "l4ls_clkdm",
 415         .main_clk       = "l4ls_gclk",
 416         .prcm           = {
 417                 .omap4  = {
 418                         .modulemode     = MODULEMODE_SWCTRL,
 419                 },
 420         },
 421 };
 422
 423 /* pwmss  */
 424 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
 425         .rev_offs       = 0x0,
 426         .sysc_offs      = 0x4,
 427         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
 428         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 429                         SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 430                         MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 431         .sysc_fields    = &omap_hwmod_sysc_type2,
 432 };
 433
 434 struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
 435         .name           = "epwmss",
 436         .sysc           = &am33xx_epwmss_sysc,
 437 };
 438
 439 static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
 440         .name           = "ecap",
 441 };
 442
 443 static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
 444         .name           = "eqep",
 445 };
 446
 447 struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
 448         .name           = "ehrpwm",
 449 };
 450
 451 /* epwmss0 */
 452 struct omap_hwmod am33xx_epwmss0_hwmod = {
 453         .name           = "epwmss0",
 454         .class          = &am33xx_epwmss_hwmod_class,
 455         .clkdm_name     = "l4ls_clkdm",
 456         .main_clk       = "l4ls_gclk",
 457         .prcm           = {
 458                 .omap4  = {
 459                         .modulemode     = MODULEMODE_SWCTRL,
 460                 },
 461         },
 462 };
 463
 464 /* ecap0 */
 465 struct omap_hwmod am33xx_ecap0_hwmod = {
 466         .name           = "ecap0",
 467         .class          = &am33xx_ecap_hwmod_class,
 468         .clkdm_name     = "l4ls_clkdm",
 469         .main_clk       = "l4ls_gclk",
 470 };
 471
 472 /* eqep0 */
 473 struct omap_hwmod am33xx_eqep0_hwmod = {
 474         .name           = "eqep0",
 475         .class          = &am33xx_eqep_hwmod_class,
 476         .clkdm_name     = "l4ls_clkdm",
 477         .main_clk       = "l4ls_gclk",
 478 };
 479
 480 /* ehrpwm0 */
 481 struct omap_hwmod am33xx_ehrpwm0_hwmod = {
 482         .name           = "ehrpwm0",
 483         .class          = &am33xx_ehrpwm_hwmod_class,
 484         .clkdm_name     = "l4ls_clkdm",
 485         .main_clk       = "l4ls_gclk",
 486 };
 487
 488 /* epwmss1 */
 489 struct omap_hwmod am33xx_epwmss1_hwmod = {
 490         .name           = "epwmss1",
 491         .class          = &am33xx_epwmss_hwmod_class,
 492         .clkdm_name     = "l4ls_clkdm",
 493         .main_clk       = "l4ls_gclk",
 494         .prcm           = {
 495                 .omap4  = {
 496                         .modulemode     = MODULEMODE_SWCTRL,
 497                 },
 498         },
 499 };
 500
 501 /* ecap1 */
 502 struct omap_hwmod am33xx_ecap1_hwmod = {
 503         .name           = "ecap1",
 504         .class          = &am33xx_ecap_hwmod_class,
 505         .clkdm_name     = "l4ls_clkdm",
 506         .main_clk       = "l4ls_gclk",
 507 };
 508
 509 /* eqep1 */
 510 struct omap_hwmod am33xx_eqep1_hwmod = {
 511         .name           = "eqep1",
 512         .class          = &am33xx_eqep_hwmod_class,
 513         .clkdm_name     = "l4ls_clkdm",
 514         .main_clk       = "l4ls_gclk",
 515 };
 516
 517 /* ehrpwm1 */
 518 struct omap_hwmod am33xx_ehrpwm1_hwmod = {
 519         .name           = "ehrpwm1",
 520         .class          = &am33xx_ehrpwm_hwmod_class,
 521         .clkdm_name     = "l4ls_clkdm",
 522         .main_clk       = "l4ls_gclk",
 523 };
 524
 525 /* epwmss2 */
 526 struct omap_hwmod am33xx_epwmss2_hwmod = {
 527         .name           = "epwmss2",
 528         .class          = &am33xx_epwmss_hwmod_class,
 529         .clkdm_name     = "l4ls_clkdm",
 530         .main_clk       = "l4ls_gclk",
 531         .prcm           = {
 532                 .omap4  = {
 533                         .modulemode     = MODULEMODE_SWCTRL,
 534                 },
 535         },
 536 };
 537
 538 /* ecap2 */
 539 struct omap_hwmod am33xx_ecap2_hwmod = {
 540         .name           = "ecap2",
 541         .class          = &am33xx_ecap_hwmod_class,
 542         .clkdm_name     = "l4ls_clkdm",
 543         .main_clk       = "l4ls_gclk",
 544 };
 545
 546 /* eqep2 */
 547 struct omap_hwmod am33xx_eqep2_hwmod = {
 548         .name           = "eqep2",
 549         .class          = &am33xx_eqep_hwmod_class,
 550         .clkdm_name     = "l4ls_clkdm",
 551         .main_clk       = "l4ls_gclk",
 552 };
 553
 554 /* ehrpwm2 */
 555 struct omap_hwmod am33xx_ehrpwm2_hwmod = {
 556         .name           = "ehrpwm2",
 557         .class          = &am33xx_ehrpwm_hwmod_class,
 558         .clkdm_name     = "l4ls_clkdm",
 559         .main_clk       = "l4ls_gclk",
 560 };
 561
 562 /*
 563  * 'gpio' class: for gpio 0,1,2,3
 564  */
 565 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
 566         .rev_offs       = 0x0000,
 567         .sysc_offs      = 0x0010,
 568         .syss_offs      = 0x0114,
 569         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 570                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 571                           SYSS_HAS_RESET_STATUS),
 572         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 573                           SIDLE_SMART_WKUP),
 574         .sysc_fields    = &omap_hwmod_sysc_type1,
 575 };
 576
 577 struct omap_hwmod_class am33xx_gpio_hwmod_class = {
 578         .name           = "gpio",
 579         .sysc           = &am33xx_gpio_sysc,
 580         .rev            = 2,
 581 };
 582
 583 struct omap_gpio_dev_attr gpio_dev_attr = {
 584         .bank_width     = 32,
 585         .dbck_flag      = true,
 586 };
 587
 588 /* gpio1 */
 589 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 590         { .role = "dbclk", .clk = "gpio1_dbclk" },
 591 };
 592
 593 struct omap_hwmod am33xx_gpio1_hwmod = {
 594         .name           = "gpio2",
 595         .class          = &am33xx_gpio_hwmod_class,
 596         .clkdm_name     = "l4ls_clkdm",
 597         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 598         .main_clk       = "l4ls_gclk",
 599         .prcm           = {
 600                 .omap4  = {
 601                         .modulemode     = MODULEMODE_SWCTRL,
 602                 },
 603         },
 604         .opt_clks       = gpio1_opt_clks,
 605         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 606         .dev_attr       = &gpio_dev_attr,
 607 };
 608
 609 /* gpio2 */
 610 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 611         { .role = "dbclk", .clk = "gpio2_dbclk" },
 612 };
 613
 614 struct omap_hwmod am33xx_gpio2_hwmod = {
 615         .name           = "gpio3",
 616         .class          = &am33xx_gpio_hwmod_class,
 617         .clkdm_name     = "l4ls_clkdm",
 618         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 619         .main_clk       = "l4ls_gclk",
 620         .prcm           = {
 621                 .omap4  = {
 622                         .modulemode     = MODULEMODE_SWCTRL,
 623                 },
 624         },
 625         .opt_clks       = gpio2_opt_clks,
 626         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 627         .dev_attr       = &gpio_dev_attr,
 628 };
 629
 630 /* gpio3 */
 631 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 632         { .role = "dbclk", .clk = "gpio3_dbclk" },
 633 };
 634
 635 struct omap_hwmod am33xx_gpio3_hwmod = {
 636         .name           = "gpio4",
 637         .class          = &am33xx_gpio_hwmod_class,
 638         .clkdm_name     = "l4ls_clkdm",
 639         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 640         .main_clk       = "l4ls_gclk",
 641         .prcm           = {
 642                 .omap4  = {
 643                         .modulemode     = MODULEMODE_SWCTRL,
 644                 },
 645         },
 646         .opt_clks       = gpio3_opt_clks,
 647         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 648         .dev_attr       = &gpio_dev_attr,
 649 };
 650
 651 /* gpmc */
 652 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
 653         .rev_offs       = 0x0,
 654         .sysc_offs      = 0x10,
 655         .syss_offs      = 0x14,
 656         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 657                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 658         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 659         .sysc_fields    = &omap_hwmod_sysc_type1,
 660 };
 661
 662 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
 663         .name           = "gpmc",
 664         .sysc           = &gpmc_sysc,
 665 };
 666
 667 struct omap_hwmod am33xx_gpmc_hwmod = {
 668         .name           = "gpmc",
 669         .class          = &am33xx_gpmc_hwmod_class,
 670         .clkdm_name     = "l3s_clkdm",
 671         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 672         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 673         .main_clk       = "l3s_gclk",
 674         .prcm           = {
 675                 .omap4  = {
 676                         .modulemode     = MODULEMODE_SWCTRL,
 677                 },
 678         },
 679 };
 680
 681 /* 'i2c' class */
 682 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
 683         .sysc_offs      = 0x0010,
 684         .syss_offs      = 0x0090,
 685         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 686                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 687                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 688         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 689                           SIDLE_SMART_WKUP),
 690         .sysc_fields    = &omap_hwmod_sysc_type1,
 691 };
 692
 693 static struct omap_hwmod_class i2c_class = {
 694         .name           = "i2c",
 695         .sysc           = &am33xx_i2c_sysc,
 696         .rev            = OMAP_I2C_IP_VERSION_2,
 697         .reset          = &omap_i2c_reset,
 698 };
 699
 700 static struct omap_i2c_dev_attr i2c_dev_attr = {
 701         .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 702 };
 703
 704 /* i2c1 */
 705 struct omap_hwmod am33xx_i2c1_hwmod = {
 706         .name           = "i2c1",
 707         .class          = &i2c_class,
 708         .clkdm_name     = "l4_wkup_clkdm",
 709         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 710         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
 711         .prcm           = {
 712                 .omap4  = {
 713                         .modulemode     = MODULEMODE_SWCTRL,
 714                 },
 715         },
 716         .dev_attr       = &i2c_dev_attr,
 717 };
 718
 719 /* i2c1 */
 720 struct omap_hwmod am33xx_i2c2_hwmod = {
 721         .name           = "i2c2",
 722         .class          = &i2c_class,
 723         .clkdm_name     = "l4ls_clkdm",
 724         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 725         .main_clk       = "dpll_per_m2_div4_ck",
 726         .prcm           = {
 727                 .omap4 = {
 728                         .modulemode     = MODULEMODE_SWCTRL,
 729                 },
 730         },
 731         .dev_attr       = &i2c_dev_attr,
 732 };
 733
 734 /* i2c3 */
 735 struct omap_hwmod am33xx_i2c3_hwmod = {
 736         .name           = "i2c3",
 737         .class          = &i2c_class,
 738         .clkdm_name     = "l4ls_clkdm",
 739         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 740         .main_clk       = "dpll_per_m2_div4_ck",
 741         .prcm           = {
 742                 .omap4  = {
 743                         .modulemode     = MODULEMODE_SWCTRL,
 744                 },
 745         },
 746         .dev_attr       = &i2c_dev_attr,
 747 };
 748
 749 /*
 750  * 'mailbox' class
 751  * mailbox module allowing communication between the on-chip processors using a
 752  * queued mailbox-interrupt mechanism.
 753  */
 754 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
 755         .rev_offs       = 0x0000,
 756         .sysc_offs      = 0x0010,
 757         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 758                           SYSC_HAS_SOFTRESET),
 759         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 760         .sysc_fields    = &omap_hwmod_sysc_type2,
 761 };
 762
 763 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
 764         .name   = "mailbox",
 765         .sysc   = &am33xx_mailbox_sysc,
 766 };
 767
 768 struct omap_hwmod am33xx_mailbox_hwmod = {
 769         .name           = "mailbox",
 770         .class          = &am33xx_mailbox_hwmod_class,
 771         .clkdm_name     = "l4ls_clkdm",
 772         .main_clk       = "l4ls_gclk",
 773         .prcm = {
 774                 .omap4 = {
 775                         .modulemode     = MODULEMODE_SWCTRL,
 776                 },
 777         },
 778 };
 779
 780 /*
 781  * 'mcasp' class
 782  */
 783 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
 784         .rev_offs       = 0x0,
 785         .sysc_offs      = 0x4,
 786         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 787         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 788         .sysc_fields    = &omap_hwmod_sysc_type3,
 789 };
 790
 791 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
 792         .name           = "mcasp",
 793         .sysc           = &am33xx_mcasp_sysc,
 794 };
 795
 796 /* mcasp0 */
 797 struct omap_hwmod am33xx_mcasp0_hwmod = {
 798         .name           = "mcasp0",
 799         .class          = &am33xx_mcasp_hwmod_class,
 800         .clkdm_name     = "l3s_clkdm",
 801         .main_clk       = "mcasp0_fck",
 802         .prcm           = {
 803                 .omap4  = {
 804                         .modulemode     = MODULEMODE_SWCTRL,
 805                 },
 806         },
 807 };
 808
 809 /* mcasp1 */
 810 struct omap_hwmod am33xx_mcasp1_hwmod = {
 811         .name           = "mcasp1",
 812         .class          = &am33xx_mcasp_hwmod_class,
 813         .clkdm_name     = "l3s_clkdm",
 814         .main_clk       = "mcasp1_fck",
 815         .prcm           = {
 816                 .omap4  = {
 817                         .modulemode     = MODULEMODE_SWCTRL,
 818                 },
 819         },
 820 };
 821
 822 /* 'mmc' class */
 823 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
 824         .rev_offs       = 0x1fc,
 825         .sysc_offs      = 0x10,
 826         .syss_offs      = 0x14,
 827         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 828                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 829                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 830         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 831         .sysc_fields    = &omap_hwmod_sysc_type1,
 832 };
 833
 834 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
 835         .name           = "mmc",
 836         .sysc           = &am33xx_mmc_sysc,
 837 };
 838
 839 /* mmc0 */
 840 static struct omap_hsmmc_dev_attr am33xx_mmc0_dev_attr = {
 841         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 842 };
 843
 844 struct omap_hwmod am33xx_mmc0_hwmod = {
 845         .name           = "mmc1",
 846         .class          = &am33xx_mmc_hwmod_class,
 847         .clkdm_name     = "l4ls_clkdm",
 848         .main_clk       = "mmc_clk",
 849         .prcm           = {
 850                 .omap4  = {
 851                         .modulemode     = MODULEMODE_SWCTRL,
 852                 },
 853         },
 854         .dev_attr       = &am33xx_mmc0_dev_attr,
 855 };
 856
 857 /* mmc1 */
 858 static struct omap_hsmmc_dev_attr am33xx_mmc1_dev_attr = {
 859         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 860 };
 861
 862 struct omap_hwmod am33xx_mmc1_hwmod = {
 863         .name           = "mmc2",
 864         .class          = &am33xx_mmc_hwmod_class,
 865         .clkdm_name     = "l4ls_clkdm",
 866         .main_clk       = "mmc_clk",
 867         .prcm           = {
 868                 .omap4  = {
 869                         .modulemode     = MODULEMODE_SWCTRL,
 870                 },
 871         },
 872         .dev_attr       = &am33xx_mmc1_dev_attr,
 873 };
 874
 875 /* mmc2 */
 876 static struct omap_hsmmc_dev_attr am33xx_mmc2_dev_attr = {
 877         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 878 };
 879 struct omap_hwmod am33xx_mmc2_hwmod = {
 880         .name           = "mmc3",
 881         .class          = &am33xx_mmc_hwmod_class,
 882         .clkdm_name     = "l3s_clkdm",
 883         .main_clk       = "mmc_clk",
 884         .prcm           = {
 885                 .omap4  = {
 886                         .modulemode     = MODULEMODE_SWCTRL,
 887                 },
 888         },
 889         .dev_attr       = &am33xx_mmc2_dev_attr,
 890 };
 891
 892 /*
 893  * 'rtc' class
 894  * rtc subsystem
 895  */
 896 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
 897         .rev_offs       = 0x0074,
 898         .sysc_offs      = 0x0078,
 899         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 900         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
 901                           SIDLE_SMART | SIDLE_SMART_WKUP),
 902         .sysc_fields    = &omap_hwmod_sysc_type3,
 903 };
 904
 905 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
 906         .name           = "rtc",
 907         .sysc           = &am33xx_rtc_sysc,
 908 };
 909
 910 struct omap_hwmod am33xx_rtc_hwmod = {
 911         .name           = "rtc",
 912         .class          = &am33xx_rtc_hwmod_class,
 913         .clkdm_name     = "l4_rtc_clkdm",
 914         .main_clk       = "clk_32768_ck",
 915         .prcm           = {
 916                 .omap4  = {
 917                         .modulemode     = MODULEMODE_SWCTRL,
 918                 },
 919         },
 920 };
 921
 922 /* 'spi' class */
 923 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
 924         .rev_offs       = 0x0000,
 925         .sysc_offs      = 0x0110,
 926         .syss_offs      = 0x0114,
 927         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 928                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 929                           SYSS_HAS_RESET_STATUS),
 930         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 931         .sysc_fields    = &omap_hwmod_sysc_type1,
 932 };
 933
 934 struct omap_hwmod_class am33xx_spi_hwmod_class = {
 935         .name           = "mcspi",
 936         .sysc           = &am33xx_mcspi_sysc,
 937         .rev            = OMAP4_MCSPI_REV,
 938 };
 939
 940 /* spi0 */
 941 struct omap2_mcspi_dev_attr mcspi_attrib = {
 942         .num_chipselect = 2,
 943 };
 944 struct omap_hwmod am33xx_spi0_hwmod = {
 945         .name           = "spi0",
 946         .class          = &am33xx_spi_hwmod_class,
 947         .clkdm_name     = "l4ls_clkdm",
 948         .main_clk       = "dpll_per_m2_div4_ck",
 949         .prcm           = {
 950                 .omap4  = {
 951                         .modulemode     = MODULEMODE_SWCTRL,
 952                 },
 953         },
 954         .dev_attr       = &mcspi_attrib,
 955 };
 956
 957 /* spi1 */
 958 struct omap_hwmod am33xx_spi1_hwmod = {
 959         .name           = "spi1",
 960         .class          = &am33xx_spi_hwmod_class,
 961         .clkdm_name     = "l4ls_clkdm",
 962         .main_clk       = "dpll_per_m2_div4_ck",
 963         .prcm           = {
 964                 .omap4  = {
 965                         .modulemode     = MODULEMODE_SWCTRL,
 966                 },
 967         },
 968         .dev_attr       = &mcspi_attrib,
 969 };
 970
 971 /*
 972  * 'spinlock' class
 973  * spinlock provides hardware assistance for synchronizing the
 974  * processes running on multiple processors
 975  */
 976
 977 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
 978         .rev_offs       = 0x0000,
 979         .sysc_offs      = 0x0010,
 980         .syss_offs      = 0x0014,
 981         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 982                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 983                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 984         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 985         .sysc_fields    = &omap_hwmod_sysc_type1,
 986 };
 987
 988 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
 989         .name           = "spinlock",
 990         .sysc           = &am33xx_spinlock_sysc,
 991 };
 992
 993 struct omap_hwmod am33xx_spinlock_hwmod = {
 994         .name           = "spinlock",
 995         .class          = &am33xx_spinlock_hwmod_class,
 996         .clkdm_name     = "l4ls_clkdm",
 997         .main_clk       = "l4ls_gclk",
 998         .prcm           = {
 999                 .omap4  = {
1000                         .modulemode     = MODULEMODE_SWCTRL,
1001                 },
1002         },
1003 };
1004
1005 /* 'timer 2-7' class */
1006 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1007         .rev_offs       = 0x0000,
1008         .sysc_offs      = 0x0010,
1009         .syss_offs      = 0x0014,
1010         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1011         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1012                           SIDLE_SMART_WKUP),
1013         .sysc_fields    = &omap_hwmod_sysc_type2,
1014 };
1015
1016 struct omap_hwmod_class am33xx_timer_hwmod_class = {
1017         .name           = "timer",
1018         .sysc           = &am33xx_timer_sysc,
1019 };
1020
1021 /* timer1 1ms */
1022 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1023         .rev_offs       = 0x0000,
1024         .sysc_offs      = 0x0010,
1025         .syss_offs      = 0x0014,
1026         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1027                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1028                         SYSS_HAS_RESET_STATUS),
1029         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1030         .sysc_fields    = &omap_hwmod_sysc_type1,
1031 };
1032
1033 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1034         .name           = "timer",
1035         .sysc           = &am33xx_timer1ms_sysc,
1036 };
1037
1038 struct omap_hwmod am33xx_timer1_hwmod = {
1039         .name           = "timer1",
1040         .class          = &am33xx_timer1ms_hwmod_class,
1041         .clkdm_name     = "l4_wkup_clkdm",
1042         .main_clk       = "timer1_fck",
1043         .prcm           = {
1044                 .omap4  = {
1045                         .modulemode     = MODULEMODE_SWCTRL,
1046                 },
1047         },
1048 };
1049
1050 struct omap_hwmod am33xx_timer2_hwmod = {
1051         .name           = "timer2",
1052         .class          = &am33xx_timer_hwmod_class,
1053         .clkdm_name     = "l4ls_clkdm",
1054         .main_clk       = "timer2_fck",
1055         .prcm           = {
1056                 .omap4  = {
1057                         .modulemode     = MODULEMODE_SWCTRL,
1058                 },
1059         },
1060 };
1061
1062 struct omap_hwmod am33xx_timer3_hwmod = {
1063         .name           = "timer3",
1064         .class          = &am33xx_timer_hwmod_class,
1065         .clkdm_name     = "l4ls_clkdm",
1066         .main_clk       = "timer3_fck",
1067         .prcm           = {
1068                 .omap4  = {
1069                         .modulemode     = MODULEMODE_SWCTRL,
1070                 },
1071         },
1072 };
1073
1074 struct omap_hwmod am33xx_timer4_hwmod = {
1075         .name           = "timer4",
1076         .class          = &am33xx_timer_hwmod_class,
1077         .clkdm_name     = "l4ls_clkdm",
1078         .main_clk       = "timer4_fck",
1079         .prcm           = {
1080                 .omap4  = {
1081                         .modulemode     = MODULEMODE_SWCTRL,
1082                 },
1083         },
1084 };
1085
1086 struct omap_hwmod am33xx_timer5_hwmod = {
1087         .name           = "timer5",
1088         .class          = &am33xx_timer_hwmod_class,
1089         .clkdm_name     = "l4ls_clkdm",
1090         .main_clk       = "timer5_fck",
1091         .prcm           = {
1092                 .omap4  = {
1093                         .modulemode     = MODULEMODE_SWCTRL,
1094                 },
1095         },
1096 };
1097
1098 struct omap_hwmod am33xx_timer6_hwmod = {
1099         .name           = "timer6",
1100         .class          = &am33xx_timer_hwmod_class,
1101         .clkdm_name     = "l4ls_clkdm",
1102         .main_clk       = "timer6_fck",
1103         .prcm           = {
1104                 .omap4  = {
1105                         .modulemode     = MODULEMODE_SWCTRL,
1106                 },
1107         },
1108 };
1109
1110 struct omap_hwmod am33xx_timer7_hwmod = {
1111         .name           = "timer7",
1112         .class          = &am33xx_timer_hwmod_class,
1113         .clkdm_name     = "l4ls_clkdm",
1114         .main_clk       = "timer7_fck",
1115         .prcm           = {
1116                 .omap4  = {
1117                         .modulemode     = MODULEMODE_SWCTRL,
1118                 },
1119         },
1120 };
1121
1122 /* tpcc */
1123 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1124         .name           = "tpcc",
1125 };
1126
1127 struct omap_hwmod am33xx_tpcc_hwmod = {
1128         .name           = "tpcc",
1129         .class          = &am33xx_tpcc_hwmod_class,
1130         .clkdm_name     = "l3_clkdm",
1131         .main_clk       = "l3_gclk",
1132         .prcm           = {
1133                 .omap4  = {
1134                         .modulemode     = MODULEMODE_SWCTRL,
1135                 },
1136         },
1137 };
1138
1139 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1140         .rev_offs       = 0x0,
1141         .sysc_offs      = 0x10,
1142         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1143                           SYSC_HAS_MIDLEMODE),
1144         .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1145         .sysc_fields    = &omap_hwmod_sysc_type2,
1146 };
1147
1148 /* 'tptc' class */
1149 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1150         .name           = "tptc",
1151         .sysc           = &am33xx_tptc_sysc,
1152 };
1153
1154 /* tptc0 */
1155 struct omap_hwmod am33xx_tptc0_hwmod = {
1156         .name           = "tptc0",
1157         .class          = &am33xx_tptc_hwmod_class,
1158         .clkdm_name     = "l3_clkdm",
1159         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1160         .main_clk       = "l3_gclk",
1161         .prcm           = {
1162                 .omap4  = {
1163                         .modulemode     = MODULEMODE_SWCTRL,
1164                 },
1165         },
1166 };
1167
1168 /* tptc1 */
1169 struct omap_hwmod am33xx_tptc1_hwmod = {
1170         .name           = "tptc1",
1171         .class          = &am33xx_tptc_hwmod_class,
1172         .clkdm_name     = "l3_clkdm",
1173         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1174         .main_clk       = "l3_gclk",
1175         .prcm           = {
1176                 .omap4  = {
1177                         .modulemode     = MODULEMODE_SWCTRL,
1178                 },
1179         },
1180 };
1181
1182 /* tptc2 */
1183 struct omap_hwmod am33xx_tptc2_hwmod = {
1184         .name           = "tptc2",
1185         .class          = &am33xx_tptc_hwmod_class,
1186         .clkdm_name     = "l3_clkdm",
1187         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1188         .main_clk       = "l3_gclk",
1189         .prcm           = {
1190                 .omap4  = {
1191                         .modulemode     = MODULEMODE_SWCTRL,
1192                 },
1193         },
1194 };
1195
1196 /* 'uart' class */
1197 static struct omap_hwmod_class_sysconfig uart_sysc = {
1198         .rev_offs       = 0x50,
1199         .sysc_offs      = 0x54,
1200         .syss_offs      = 0x58,
1201         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1202                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1203         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1204                           SIDLE_SMART_WKUP),
1205         .sysc_fields    = &omap_hwmod_sysc_type1,
1206 };
1207
1208 static struct omap_hwmod_class uart_class = {
1209         .name           = "uart",
1210         .sysc           = &uart_sysc,
1211 };
1212
1213 struct omap_hwmod am33xx_uart1_hwmod = {
1214         .name           = "uart1",
1215         .class          = &uart_class,
1216         .clkdm_name     = "l4_wkup_clkdm",
1217         .flags          = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1218         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
1219         .prcm           = {
1220                 .omap4  = {
1221                         .modulemode     = MODULEMODE_SWCTRL,
1222                 },
1223         },
1224 };
1225
1226 struct omap_hwmod am33xx_uart2_hwmod = {
1227         .name           = "uart2",
1228         .class          = &uart_class,
1229         .clkdm_name     = "l4ls_clkdm",
1230         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1231         .main_clk       = "dpll_per_m2_div4_ck",
1232         .prcm           = {
1233                 .omap4  = {
1234                         .modulemode     = MODULEMODE_SWCTRL,
1235                 },
1236         },
1237 };
1238
1239 /* uart3 */
1240 struct omap_hwmod am33xx_uart3_hwmod = {
1241         .name           = "uart3",
1242         .class          = &uart_class,
1243         .clkdm_name     = "l4ls_clkdm",
1244         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1245         .main_clk       = "dpll_per_m2_div4_ck",
1246         .prcm           = {
1247                 .omap4  = {
1248                         .modulemode     = MODULEMODE_SWCTRL,
1249                 },
1250         },
1251 };
1252
1253 struct omap_hwmod am33xx_uart4_hwmod = {
1254         .name           = "uart4",
1255         .class          = &uart_class,
1256         .clkdm_name     = "l4ls_clkdm",
1257         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1258         .main_clk       = "dpll_per_m2_div4_ck",
1259         .prcm           = {
1260                 .omap4  = {
1261                         .modulemode     = MODULEMODE_SWCTRL,
1262                 },
1263         },
1264 };
1265
1266 struct omap_hwmod am33xx_uart5_hwmod = {
1267         .name           = "uart5",
1268         .class          = &uart_class,
1269         .clkdm_name     = "l4ls_clkdm",
1270         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1271         .main_clk       = "dpll_per_m2_div4_ck",
1272         .prcm           = {
1273                 .omap4  = {
1274                         .modulemode     = MODULEMODE_SWCTRL,
1275                 },
1276         },
1277 };
1278
1279 struct omap_hwmod am33xx_uart6_hwmod = {
1280         .name           = "uart6",
1281         .class          = &uart_class,
1282         .clkdm_name     = "l4ls_clkdm",
1283         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1284         .main_clk       = "dpll_per_m2_div4_ck",
1285         .prcm           = {
1286                 .omap4  = {
1287                         .modulemode     = MODULEMODE_SWCTRL,
1288                 },
1289         },
1290 };
1291
1292 /* 'wd_timer' class */
1293 static struct omap_hwmod_class_sysconfig wdt_sysc = {
1294         .rev_offs       = 0x0,
1295         .sysc_offs      = 0x10,
1296         .syss_offs      = 0x14,
1297         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1298                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1299         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1300                         SIDLE_SMART_WKUP),
1301         .sysc_fields    = &omap_hwmod_sysc_type1,
1302 };
1303
1304 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
1305         .name           = "wd_timer",
1306         .sysc           = &wdt_sysc,
1307         .pre_shutdown   = &omap2_wd_timer_disable,
1308 };
1309
1310 /*
1311  * XXX: device.c file uses hardcoded name for watchdog timer
1312  * driver "wd_timer2, so we are also using same name as of now...
1313  */
1314 struct omap_hwmod am33xx_wd_timer1_hwmod = {
1315         .name           = "wd_timer2",
1316         .class          = &am33xx_wd_timer_hwmod_class,
1317         .clkdm_name     = "l4_wkup_clkdm",
1318         .flags          = HWMOD_SWSUP_SIDLE,
1319         .main_clk       = "wdt1_fck",
1320         .prcm           = {
1321                 .omap4  = {
1322                         .modulemode     = MODULEMODE_SWCTRL,
1323                 },
1324         },
1325 };
1326
1327 static void omap_hwmod_am33xx_clkctrl(void)
1328 {
1329         CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
1330         CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
1331         CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
1332         CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
1333         CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
1334         CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1335         CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1336         CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
1337         CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1338         CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1339         CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1340         CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1341         CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1342         CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1343         CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1344         CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1345         CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1346         CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1347         CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1348         CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1349         CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1350         CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1351         CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1352         CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1353         CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1354         CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1355         CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1356         CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1357         CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1358         CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1359         CLKCTRL(am33xx_smartreflex0_hwmod,
1360                 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1361         CLKCTRL(am33xx_smartreflex1_hwmod,
1362                 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1363         CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1364         CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1365         CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1366         CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1367         CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1368         CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1369         CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1370         CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1371         CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1372         CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
1373         CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1374         CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1375         CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1376         CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1377         CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1378         CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1379         CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1380         CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1381         CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1382         CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1383         CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1384         CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
1385 }
1386
1387 static void omap_hwmod_am33xx_rst(void)
1388 {
1389         RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
1390         RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
1391         RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
1392 }
1393
1394 void omap_hwmod_am33xx_reg(void)
1395 {
1396         omap_hwmod_am33xx_clkctrl();
1397         omap_hwmod_am33xx_rst();
1398 }
1399
1400 static void omap_hwmod_am43xx_clkctrl(void)
1401 {
1402         CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
1403         CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
1404         CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
1405         CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
1406         CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
1407         CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1408         CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1409         CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
1410         CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1411         CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1412         CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1413         CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1414         CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1415         CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1416         CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1417         CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1418         CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1419         CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1420         CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1421         CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1422         CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1423         CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1424         CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1425         CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1426         CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1427         CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1428         CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1429         CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1430         CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1431         CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1432         CLKCTRL(am33xx_smartreflex0_hwmod,
1433                 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1434         CLKCTRL(am33xx_smartreflex1_hwmod,
1435                 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1436         CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1437         CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1438         CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1439         CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1440         CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1441         CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1442         CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1443         CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1444         CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1445         CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
1446         CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1447         CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1448         CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1449         CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1450         CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1451         CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1452         CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1453         CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1454         CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1455         CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1456         CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1457         CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1458 }
1459
1460 static void omap_hwmod_am43xx_rst(void)
1461 {
1462         RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
1463         RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
1464         RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
1465 }
1466
1467 void omap_hwmod_am43xx_reg(void)
1468 {
1469         omap_hwmod_am43xx_clkctrl();
1470         omap_hwmod_am43xx_rst();
1471 }