arch/arm/mach-omap2/gpmc-onenand.c

   1 /*
   2  * linux/arch/arm/mach-omap2/gpmc-onenand.c
   3  *
   4  * Copyright (C) 2006 - 2009 Nokia Corporation
   5  * Contacts:    Juha Yrjola
   6  *              Tony Lindgren
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/string.h>
  14 #include <linux/kernel.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/mtd/onenand_regs.h>
  17 #include <linux/io.h>
  18 #include <linux/platform_data/mtd-onenand-omap2.h>
  19 #include <linux/err.h>
  20
  21 #include <asm/mach/flash.h>
  22
  23 #include "gpmc.h"
  24 #include "soc.h"
  25 #include "gpmc-onenand.h"
  26
  27 #define ONENAND_IO_SIZE SZ_128K
  28
  29 #define ONENAND_FLAG_SYNCREAD   (1 << 0)
  30 #define ONENAND_FLAG_SYNCWRITE  (1 << 1)
  31 #define ONENAND_FLAG_HF         (1 << 2)
  32 #define ONENAND_FLAG_VHF        (1 << 3)
  33
  34 static unsigned onenand_flags;
  35 static unsigned latency;
  36
  37 static struct omap_onenand_platform_data *gpmc_onenand_data;
  38
  39 static struct resource gpmc_onenand_resource = {
  40         .flags          = IORESOURCE_MEM,
  41 };
  42
  43 static struct platform_device gpmc_onenand_device = {
  44         .name           = "omap2-onenand",
  45         .id             = -1,
  46         .num_resources  = 1,
  47         .resource       = &gpmc_onenand_resource,
  48 };
  49
  50 static struct gpmc_settings onenand_async = {
  51         .device_width   = GPMC_DEVWIDTH_16BIT,
  52         .mux_add_data   = GPMC_MUX_AD,
  53 };
  54
  55 static struct gpmc_settings onenand_sync = {
  56         .burst_read     = true,
  57         .burst_wrap     = true,
  58         .burst_len      = GPMC_BURST_16,
  59         .device_width   = GPMC_DEVWIDTH_16BIT,
  60         .mux_add_data   = GPMC_MUX_AD,
  61         .wait_pin       = 0,
  62 };
  63
  64 static void omap2_onenand_calc_async_timings(struct gpmc_timings *t)
  65 {
  66         struct gpmc_device_timings dev_t;
  67         const int t_cer = 15;
  68         const int t_avdp = 12;
  69         const int t_aavdh = 7;
  70         const int t_ce = 76;
  71         const int t_aa = 76;
  72         const int t_oe = 20;
  73         const int t_cez = 20; /* max of t_cez, t_oez */
  74         const int t_wpl = 40;
  75         const int t_wph = 30;
  76
  77         memset(&dev_t, 0, sizeof(dev_t));
  78
  79         dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;
  80         dev_t.t_avdp_w = dev_t.t_avdp_r;
  81         dev_t.t_aavdh = t_aavdh * 1000;
  82         dev_t.t_aa = t_aa * 1000;
  83         dev_t.t_ce = t_ce * 1000;
  84         dev_t.t_oe = t_oe * 1000;
  85         dev_t.t_cez_r = t_cez * 1000;
  86         dev_t.t_cez_w = dev_t.t_cez_r;
  87         dev_t.t_wpl = t_wpl * 1000;
  88         dev_t.t_wph = t_wph * 1000;
  89
  90         gpmc_calc_timings(t, &onenand_async, &dev_t);
  91 }
  92
  93 static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
  94 {
  95         u32 reg;
  96
  97         /* Ensure sync read and sync write are disabled */
  98         reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
  99         reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
 100         writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
 101 }
 102
 103 static void set_onenand_cfg(void __iomem *onenand_base)
 104 {
 105         u32 reg;
 106
 107         reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
 108         reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
 109         reg |=  (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
 110                 ONENAND_SYS_CFG1_BL_16;
 111         if (onenand_flags & ONENAND_FLAG_SYNCREAD)
 112                 reg |= ONENAND_SYS_CFG1_SYNC_READ;
 113         else
 114                 reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
 115         if (onenand_flags & ONENAND_FLAG_SYNCWRITE)
 116                 reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
 117         else
 118                 reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
 119         if (onenand_flags & ONENAND_FLAG_HF)
 120                 reg |= ONENAND_SYS_CFG1_HF;
 121         else
 122                 reg &= ~ONENAND_SYS_CFG1_HF;
 123         if (onenand_flags & ONENAND_FLAG_VHF)
 124                 reg |= ONENAND_SYS_CFG1_VHF;
 125         else
 126                 reg &= ~ONENAND_SYS_CFG1_VHF;
 127         writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
 128 }
 129
 130 static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
 131                                   void __iomem *onenand_base)
 132 {
 133         u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
 134         int freq;
 135
 136         switch ((ver >> 4) & 0xf) {
 137         case 0:
 138                 freq = 40;
 139                 break;
 140         case 1:
 141                 freq = 54;
 142                 break;
 143         case 2:
 144                 freq = 66;
 145                 break;
 146         case 3:
 147                 freq = 83;
 148                 break;
 149         case 4:
 150                 freq = 104;
 151                 break;
 152         default:
 153                 freq = 54;
 154                 break;
 155         }
 156
 157         return freq;
 158 }
 159
 160 static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
 161                                             unsigned int flags,
 162                                             int freq)
 163 {
 164         struct gpmc_device_timings dev_t;
 165         const int t_cer  = 15;
 166         const int t_avdp = 12;
 167         const int t_cez  = 20; /* max of t_cez, t_oez */
 168         const int t_wpl  = 40;
 169         const int t_wph  = 30;
 170         int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
 171         int div, gpmc_clk_ns;
 172
 173         if (flags & ONENAND_SYNC_READ)
 174                 onenand_flags = ONENAND_FLAG_SYNCREAD;
 175         else if (flags & ONENAND_SYNC_READWRITE)
 176                 onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
 177
 178         switch (freq) {
 179         case 104:
 180                 min_gpmc_clk_period = 9600; /* 104 MHz */
 181                 t_ces   = 3;
 182                 t_avds  = 4;
 183                 t_avdh  = 2;
 184                 t_ach   = 3;
 185                 t_aavdh = 6;
 186                 t_rdyo  = 6;
 187                 break;
 188         case 83:
 189                 min_gpmc_clk_period = 12000; /* 83 MHz */
 190                 t_ces   = 5;
 191                 t_avds  = 4;
 192                 t_avdh  = 2;
 193                 t_ach   = 6;
 194                 t_aavdh = 6;
 195                 t_rdyo  = 9;
 196                 break;
 197         case 66:
 198                 min_gpmc_clk_period = 15000; /* 66 MHz */
 199                 t_ces   = 6;
 200                 t_avds  = 5;
 201                 t_avdh  = 2;
 202                 t_ach   = 6;
 203                 t_aavdh = 6;
 204                 t_rdyo  = 11;
 205                 break;
 206         default:
 207                 min_gpmc_clk_period = 18500; /* 54 MHz */
 208                 t_ces   = 7;
 209                 t_avds  = 7;
 210                 t_avdh  = 7;
 211                 t_ach   = 9;
 212                 t_aavdh = 7;
 213                 t_rdyo  = 15;
 214                 onenand_flags &= ~ONENAND_FLAG_SYNCWRITE;
 215                 break;
 216         }
 217
 218         div = gpmc_calc_divider(min_gpmc_clk_period);
 219         gpmc_clk_ns = gpmc_ticks_to_ns(div);
 220         if (gpmc_clk_ns < 15) /* >66Mhz */
 221                 onenand_flags |= ONENAND_FLAG_HF;
 222         else
 223                 onenand_flags &= ~ONENAND_FLAG_HF;
 224         if (gpmc_clk_ns < 12) /* >83Mhz */
 225                 onenand_flags |= ONENAND_FLAG_VHF;
 226         else
 227                 onenand_flags &= ~ONENAND_FLAG_VHF;
 228         if (onenand_flags & ONENAND_FLAG_VHF)
 229                 latency = 8;
 230         else if (onenand_flags & ONENAND_FLAG_HF)
 231                 latency = 6;
 232         else if (gpmc_clk_ns >= 25) /* 40 MHz*/
 233                 latency = 3;
 234         else
 235                 latency = 4;
 236
 237         /* Set synchronous read timings */
 238         memset(&dev_t, 0, sizeof(dev_t));
 239
 240         if (onenand_flags & ONENAND_FLAG_SYNCREAD)
 241                 onenand_sync.sync_read = true;
 242         if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
 243                 onenand_sync.sync_write = true;
 244                 onenand_sync.burst_write = true;
 245         } else {
 246                 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
 247                 dev_t.t_wpl = t_wpl * 1000;
 248                 dev_t.t_wph = t_wph * 1000;
 249                 dev_t.t_aavdh = t_aavdh * 1000;
 250         }
 251         dev_t.ce_xdelay = true;
 252         dev_t.avd_xdelay = true;
 253         dev_t.oe_xdelay = true;
 254         dev_t.we_xdelay = true;
 255         dev_t.clk = min_gpmc_clk_period;
 256         dev_t.t_bacc = dev_t.clk;
 257         dev_t.t_ces = t_ces * 1000;
 258         dev_t.t_avds = t_avds * 1000;
 259         dev_t.t_avdh = t_avdh * 1000;
 260         dev_t.t_ach = t_ach * 1000;
 261         dev_t.cyc_iaa = (latency + 1);
 262         dev_t.t_cez_r = t_cez * 1000;
 263         dev_t.t_cez_w = dev_t.t_cez_r;
 264         dev_t.cyc_aavdh_oe = 1;
 265         dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
 266
 267         gpmc_calc_timings(t, &onenand_sync, &dev_t);
 268 }
 269
 270 static int omap2_onenand_setup_async(void __iomem *onenand_base)
 271 {
 272         struct gpmc_timings t;
 273         int ret;
 274
 275         if (gpmc_onenand_data->of_node)
 276                 gpmc_read_settings_dt(gpmc_onenand_data->of_node,
 277                                       &onenand_async);
 278
 279         omap2_onenand_set_async_mode(onenand_base);
 280
 281         omap2_onenand_calc_async_timings(&t);
 282
 283         ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
 284         if (ret < 0)
 285                 return ret;
 286
 287         ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
 288         if (ret < 0)
 289                 return ret;
 290
 291         omap2_onenand_set_async_mode(onenand_base);
 292
 293         return 0;
 294 }
 295
 296 static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
 297 {
 298         int ret, freq = *freq_ptr;
 299         struct gpmc_timings t;
 300
 301         if (!freq) {
 302                 /* Very first call freq is not known */
 303                 freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base);
 304                 set_onenand_cfg(onenand_base);
 305         }
 306
 307         if (gpmc_onenand_data->of_node) {
 308                 gpmc_read_settings_dt(gpmc_onenand_data->of_node,
 309                                       &onenand_sync);
 310         } else {
 311                 /*
 312                  * FIXME: Appears to be legacy code from initial ONENAND commit.
 313                  * Unclear what boards this is for and if this can be removed.
 314                  */
 315                 if (!cpu_is_omap34xx())
 316                         onenand_sync.wait_on_read = true;
 317         }
 318
 319         omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq);
 320
 321         ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync);
 322         if (ret < 0)
 323                 return ret;
 324
 325         ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
 326         if (ret < 0)
 327                 return ret;
 328
 329         set_onenand_cfg(onenand_base);
 330
 331         *freq_ptr = freq;
 332
 333         return 0;
 334 }
 335
 336 static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
 337 {
 338         struct device *dev = &gpmc_onenand_device.dev;
 339         unsigned l = ONENAND_SYNC_READ | ONENAND_SYNC_READWRITE;
 340         int ret;
 341
 342         ret = omap2_onenand_setup_async(onenand_base);
 343         if (ret) {
 344                 dev_err(dev, "unable to set to async mode\n");
 345                 return ret;
 346         }
 347
 348         if (!(gpmc_onenand_data->flags & l))
 349                 return 0;
 350
 351         ret = omap2_onenand_setup_sync(onenand_base, freq_ptr);
 352         if (ret)
 353                 dev_err(dev, "unable to set to sync mode\n");
 354         return ret;
 355 }
 356
 357 void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
 358 {
 359         int err;
 360         struct device *dev = &gpmc_onenand_device.dev;
 361
 362         gpmc_onenand_data = _onenand_data;
 363         gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
 364         gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
 365
 366         if (cpu_is_omap24xx() &&
 367                         (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
 368                 dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n");
 369                 gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
 370                 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
 371         }
 372
 373         if (cpu_is_omap34xx())
 374                 gpmc_onenand_data->flags |= ONENAND_IN_OMAP34XX;
 375         else
 376                 gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX;
 377
 378         err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
 379                                 (unsigned long *)&gpmc_onenand_resource.start);
 380         if (err < 0) {
 381                 dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
 382                         gpmc_onenand_data->cs, err);
 383                 return;
 384         }
 385
 386         gpmc_onenand_resource.end = gpmc_onenand_resource.start +
 387                                                         ONENAND_IO_SIZE - 1;
 388
 389         if (platform_device_register(&gpmc_onenand_device) < 0) {
 390                 dev_err(dev, "Unable to register OneNAND device\n");
 391                 gpmc_cs_free(gpmc_onenand_data->cs);
 392                 return;
 393         }
 394 }