arch/arm/mach-omap2/display.c

   1 /*
   2  * OMAP2plus display device setup / initialization.
   3  *
   4  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   5  *      Senthilvadivu Guruswamy
   6  *      Sumit Semwal
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/string.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/io.h>
  23 #include <linux/clk.h>
  24 #include <linux/err.h>
  25 #include <linux/delay.h>
  26 #include <linux/of.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/slab.h>
  29 #include <linux/mfd/syscon.h>
  30 #include <linux/regmap.h>
  31
  32 #include <video/omapdss.h>
  33 #include "omap_hwmod.h"
  34 #include "omap_device.h"
  35 #include "omap-pm.h"
  36 #include "common.h"
  37
  38 #include "soc.h"
  39 #include "iomap.h"
  40 #include "control.h"
  41 #include "display.h"
  42 #include "prm.h"
  43
  44 #define DISPC_CONTROL           0x0040
  45 #define DISPC_CONTROL2          0x0238
  46 #define DISPC_CONTROL3          0x0848
  47 #define DISPC_IRQSTATUS         0x0018
  48
  49 #define DSS_SYSCONFIG           0x10
  50 #define DSS_SYSSTATUS           0x14
  51 #define DSS_CONTROL             0x40
  52 #define DSS_SDI_CONTROL         0x44
  53 #define DSS_PLL_CONTROL         0x48
  54
  55 #define LCD_EN_MASK             (0x1 << 0)
  56 #define DIGIT_EN_MASK           (0x1 << 1)
  57
  58 #define FRAMEDONE_IRQ_SHIFT     0
  59 #define EVSYNC_EVEN_IRQ_SHIFT   2
  60 #define EVSYNC_ODD_IRQ_SHIFT    3
  61 #define FRAMEDONE2_IRQ_SHIFT    22
  62 #define FRAMEDONE3_IRQ_SHIFT    30
  63 #define FRAMEDONETV_IRQ_SHIFT   24
  64
  65 /*
  66  * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
  67  *     reset before deciding that something has gone wrong
  68  */
  69 #define FRAMEDONE_IRQ_TIMEOUT           100
  70
  71 static struct platform_device omap_display_device = {
  72         .name          = "omapdss",
  73         .id            = -1,
  74         .dev            = {
  75                 .platform_data = NULL,
  76         },
  77 };
  78
  79 struct omap_dss_hwmod_data {
  80         const char *oh_name;
  81         const char *dev_name;
  82         const int id;
  83 };
  84
  85 static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
  86         { "dss_core", "omapdss_dss", -1 },
  87         { "dss_dispc", "omapdss_dispc", -1 },
  88         { "dss_rfbi", "omapdss_rfbi", -1 },
  89         { "dss_venc", "omapdss_venc", -1 },
  90 };
  91
  92 static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
  93         { "dss_core", "omapdss_dss", -1 },
  94         { "dss_dispc", "omapdss_dispc", -1 },
  95         { "dss_rfbi", "omapdss_rfbi", -1 },
  96         { "dss_venc", "omapdss_venc", -1 },
  97         { "dss_dsi1", "omapdss_dsi", 0 },
  98 };
  99
 100 static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
 101         { "dss_core", "omapdss_dss", -1 },
 102         { "dss_dispc", "omapdss_dispc", -1 },
 103         { "dss_rfbi", "omapdss_rfbi", -1 },
 104         { "dss_dsi1", "omapdss_dsi", 0 },
 105         { "dss_dsi2", "omapdss_dsi", 1 },
 106         { "dss_hdmi", "omapdss_hdmi", -1 },
 107 };
 108
 109 #define OMAP4_DSIPHY_SYSCON_OFFSET              0x78
 110
 111 static struct regmap *omap4_dsi_mux_syscon;
 112
 113 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
 114 {
 115         u32 enable_mask, enable_shift;
 116         u32 pipd_mask, pipd_shift;
 117         u32 reg;
 118
 119         if (dsi_id == 0) {
 120                 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
 121                 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
 122                 pipd_mask = OMAP4_DSI1_PIPD_MASK;
 123                 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
 124         } else if (dsi_id == 1) {
 125                 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
 126                 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
 127                 pipd_mask = OMAP4_DSI2_PIPD_MASK;
 128                 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
 129         } else {
 130                 return -ENODEV;
 131         }
 132
 133         regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, &reg);
 134
 135         reg &= ~enable_mask;
 136         reg &= ~pipd_mask;
 137
 138         reg |= (lanes << enable_shift) & enable_mask;
 139         reg |= (lanes << pipd_shift) & pipd_mask;
 140
 141         regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg);
 142
 143         return 0;
 144 }
 145
 146 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
 147 {
 148         if (cpu_is_omap44xx())
 149                 return omap4_dsi_mux_pads(dsi_id, lane_mask);
 150
 151         return 0;
 152 }
 153
 154 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
 155 {
 156         if (cpu_is_omap44xx())
 157                 omap4_dsi_mux_pads(dsi_id, 0);
 158 }
 159
 160 static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
 161 {
 162         return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
 163 }
 164
 165 static struct platform_device *create_dss_pdev(const char *pdev_name,
 166                 int pdev_id, const char *oh_name, void *pdata, int pdata_len,
 167                 struct platform_device *parent)
 168 {
 169         struct platform_device *pdev;
 170         struct omap_device *od;
 171         struct omap_hwmod *ohs[1];
 172         struct omap_hwmod *oh;
 173         int r;
 174
 175         oh = omap_hwmod_lookup(oh_name);
 176         if (!oh) {
 177                 pr_err("Could not look up %s\n", oh_name);
 178                 r = -ENODEV;
 179                 goto err;
 180         }
 181
 182         pdev = platform_device_alloc(pdev_name, pdev_id);
 183         if (!pdev) {
 184                 pr_err("Could not create pdev for %s\n", pdev_name);
 185                 r = -ENOMEM;
 186                 goto err;
 187         }
 188
 189         if (parent != NULL)
 190                 pdev->dev.parent = &parent->dev;
 191
 192         if (pdev->id != -1)
 193                 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
 194         else
 195                 dev_set_name(&pdev->dev, "%s", pdev->name);
 196
 197         ohs[0] = oh;
 198         od = omap_device_alloc(pdev, ohs, 1);
 199         if (IS_ERR(od)) {
 200                 pr_err("Could not alloc omap_device for %s\n", pdev_name);
 201                 r = -ENOMEM;
 202                 goto err;
 203         }
 204
 205         r = platform_device_add_data(pdev, pdata, pdata_len);
 206         if (r) {
 207                 pr_err("Could not set pdata for %s\n", pdev_name);
 208                 goto err;
 209         }
 210
 211         r = omap_device_register(pdev);
 212         if (r) {
 213                 pr_err("Could not register omap_device for %s\n", pdev_name);
 214                 goto err;
 215         }
 216
 217         return pdev;
 218
 219 err:
 220         return ERR_PTR(r);
 221 }
 222
 223 static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
 224                 int pdev_id, void *pdata, int pdata_len,
 225                 struct platform_device *parent)
 226 {
 227         struct platform_device *pdev;
 228         int r;
 229
 230         pdev = platform_device_alloc(pdev_name, pdev_id);
 231         if (!pdev) {
 232                 pr_err("Could not create pdev for %s\n", pdev_name);
 233                 r = -ENOMEM;
 234                 goto err;
 235         }
 236
 237         if (parent != NULL)
 238                 pdev->dev.parent = &parent->dev;
 239
 240         if (pdev->id != -1)
 241                 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
 242         else
 243                 dev_set_name(&pdev->dev, "%s", pdev->name);
 244
 245         r = platform_device_add_data(pdev, pdata, pdata_len);
 246         if (r) {
 247                 pr_err("Could not set pdata for %s\n", pdev_name);
 248                 goto err;
 249         }
 250
 251         r = platform_device_add(pdev);
 252         if (r) {
 253                 pr_err("Could not register platform_device for %s\n", pdev_name);
 254                 goto err;
 255         }
 256
 257         return pdev;
 258
 259 err:
 260         return ERR_PTR(r);
 261 }
 262
 263 static enum omapdss_version __init omap_display_get_version(void)
 264 {
 265         if (cpu_is_omap24xx())
 266                 return OMAPDSS_VER_OMAP24xx;
 267         else if (cpu_is_omap3630())
 268                 return OMAPDSS_VER_OMAP3630;
 269         else if (cpu_is_omap34xx()) {
 270                 if (soc_is_am35xx()) {
 271                         return OMAPDSS_VER_AM35xx;
 272                 } else {
 273                         if (omap_rev() < OMAP3430_REV_ES3_0)
 274                                 return OMAPDSS_VER_OMAP34xx_ES1;
 275                         else
 276                                 return OMAPDSS_VER_OMAP34xx_ES3;
 277                 }
 278         } else if (omap_rev() == OMAP4430_REV_ES1_0)
 279                 return OMAPDSS_VER_OMAP4430_ES1;
 280         else if (omap_rev() == OMAP4430_REV_ES2_0 ||
 281                         omap_rev() == OMAP4430_REV_ES2_1 ||
 282                         omap_rev() == OMAP4430_REV_ES2_2)
 283                 return OMAPDSS_VER_OMAP4430_ES2;
 284         else if (cpu_is_omap44xx())
 285                 return OMAPDSS_VER_OMAP4;
 286         else if (soc_is_omap54xx())
 287                 return OMAPDSS_VER_OMAP5;
 288         else if (soc_is_am43xx())
 289                 return OMAPDSS_VER_AM43xx;
 290         else if (soc_is_dra7xx())
 291                 return OMAPDSS_VER_DRA7xx;
 292         else
 293                 return OMAPDSS_VER_UNKNOWN;
 294 }
 295
 296 int __init omap_display_init(struct omap_dss_board_info *board_data)
 297 {
 298         int r = 0;
 299         struct platform_device *pdev;
 300         int i, oh_count;
 301         const struct omap_dss_hwmod_data *curr_dss_hwmod;
 302         struct platform_device *dss_pdev;
 303         enum omapdss_version ver;
 304
 305         /* create omapdss device */
 306
 307         ver = omap_display_get_version();
 308
 309         if (ver == OMAPDSS_VER_UNKNOWN) {
 310                 pr_err("DSS not supported on this SoC\n");
 311                 return -ENODEV;
 312         }
 313
 314         board_data->version = ver;
 315         board_data->dsi_enable_pads = omap_dsi_enable_pads;
 316         board_data->dsi_disable_pads = omap_dsi_disable_pads;
 317         board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
 318
 319         omap_display_device.dev.platform_data = board_data;
 320
 321         r = platform_device_register(&omap_display_device);
 322         if (r < 0) {
 323                 pr_err("Unable to register omapdss device\n");
 324                 return r;
 325         }
 326
 327         /* create devices for dss hwmods */
 328
 329         if (cpu_is_omap24xx()) {
 330                 curr_dss_hwmod = omap2_dss_hwmod_data;
 331                 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
 332         } else if (cpu_is_omap34xx()) {
 333                 curr_dss_hwmod = omap3_dss_hwmod_data;
 334                 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
 335         } else {
 336                 curr_dss_hwmod = omap4_dss_hwmod_data;
 337                 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
 338         }
 339
 340         /*
 341          * First create the pdev for dss_core, which is used as a parent device
 342          * by the other dss pdevs. Note: dss_core has to be the first item in
 343          * the hwmod list.
 344          */
 345         dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
 346                         curr_dss_hwmod[0].id,
 347                         curr_dss_hwmod[0].oh_name,
 348                         board_data, sizeof(*board_data),
 349                         NULL);
 350
 351         if (IS_ERR(dss_pdev)) {
 352                 pr_err("Could not build omap_device for %s\n",
 353                                 curr_dss_hwmod[0].oh_name);
 354
 355                 return PTR_ERR(dss_pdev);
 356         }
 357
 358         for (i = 1; i < oh_count; i++) {
 359                 pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
 360                                 curr_dss_hwmod[i].id,
 361                                 curr_dss_hwmod[i].oh_name,
 362                                 board_data, sizeof(*board_data),
 363                                 dss_pdev);
 364
 365                 if (IS_ERR(pdev)) {
 366                         pr_err("Could not build omap_device for %s\n",
 367                                         curr_dss_hwmod[i].oh_name);
 368
 369                         return PTR_ERR(pdev);
 370                 }
 371         }
 372
 373         /* Create devices for DPI and SDI */
 374
 375         pdev = create_simple_dss_pdev("omapdss_dpi", 0,
 376                         board_data, sizeof(*board_data), dss_pdev);
 377         if (IS_ERR(pdev)) {
 378                 pr_err("Could not build platform_device for omapdss_dpi\n");
 379                 return PTR_ERR(pdev);
 380         }
 381
 382         if (cpu_is_omap34xx()) {
 383                 pdev = create_simple_dss_pdev("omapdss_sdi", 0,
 384                                 board_data, sizeof(*board_data), dss_pdev);
 385                 if (IS_ERR(pdev)) {
 386                         pr_err("Could not build platform_device for omapdss_sdi\n");
 387                         return PTR_ERR(pdev);
 388                 }
 389         }
 390
 391         /* create DRM device */
 392         r = omap_init_drm();
 393         if (r < 0) {
 394                 pr_err("Unable to register omapdrm device\n");
 395                 return r;
 396         }
 397
 398         /* create vrfb device */
 399         r = omap_init_vrfb();
 400         if (r < 0) {
 401                 pr_err("Unable to register omapvrfb device\n");
 402                 return r;
 403         }
 404
 405         /* create FB device */
 406         r = omap_init_fb();
 407         if (r < 0) {
 408                 pr_err("Unable to register omapfb device\n");
 409                 return r;
 410         }
 411
 412         /* create V4L2 display device */
 413         r = omap_init_vout();
 414         if (r < 0) {
 415                 pr_err("Unable to register omap_vout device\n");
 416                 return r;
 417         }
 418
 419         return 0;
 420 }
 421
 422 static void dispc_disable_outputs(void)
 423 {
 424         u32 v, irq_mask = 0;
 425         bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
 426         int i;
 427         struct omap_dss_dispc_dev_attr *da;
 428         struct omap_hwmod *oh;
 429
 430         oh = omap_hwmod_lookup("dss_dispc");
 431         if (!oh) {
 432                 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
 433                 return;
 434         }
 435
 436         if (!oh->dev_attr) {
 437                 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
 438                 return;
 439         }
 440
 441         da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
 442
 443         /* store value of LCDENABLE and DIGITENABLE bits */
 444         v = omap_hwmod_read(oh, DISPC_CONTROL);
 445         lcd_en = v & LCD_EN_MASK;
 446         digit_en = v & DIGIT_EN_MASK;
 447
 448         /* store value of LCDENABLE for LCD2 */
 449         if (da->manager_count > 2) {
 450                 v = omap_hwmod_read(oh, DISPC_CONTROL2);
 451                 lcd2_en = v & LCD_EN_MASK;
 452         }
 453
 454         /* store value of LCDENABLE for LCD3 */
 455         if (da->manager_count > 3) {
 456                 v = omap_hwmod_read(oh, DISPC_CONTROL3);
 457                 lcd3_en = v & LCD_EN_MASK;
 458         }
 459
 460         if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
 461                 return; /* no managers currently enabled */
 462
 463         /*
 464          * If any manager was enabled, we need to disable it before
 465          * DSS clocks are disabled or DISPC module is reset
 466          */
 467         if (lcd_en)
 468                 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
 469
 470         if (digit_en) {
 471                 if (da->has_framedonetv_irq) {
 472                         irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
 473                 } else {
 474                         irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
 475                                 1 << EVSYNC_ODD_IRQ_SHIFT;
 476                 }
 477         }
 478
 479         if (lcd2_en)
 480                 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
 481         if (lcd3_en)
 482                 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;
 483
 484         /*
 485          * clear any previous FRAMEDONE, FRAMEDONETV,
 486          * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
 487          */
 488         omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
 489
 490         /* disable LCD and TV managers */
 491         v = omap_hwmod_read(oh, DISPC_CONTROL);
 492         v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
 493         omap_hwmod_write(v, oh, DISPC_CONTROL);
 494
 495         /* disable LCD2 manager */
 496         if (da->manager_count > 2) {
 497                 v = omap_hwmod_read(oh, DISPC_CONTROL2);
 498                 v &= ~LCD_EN_MASK;
 499                 omap_hwmod_write(v, oh, DISPC_CONTROL2);
 500         }
 501
 502         /* disable LCD3 manager */
 503         if (da->manager_count > 3) {
 504                 v = omap_hwmod_read(oh, DISPC_CONTROL3);
 505                 v &= ~LCD_EN_MASK;
 506                 omap_hwmod_write(v, oh, DISPC_CONTROL3);
 507         }
 508
 509         i = 0;
 510         while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
 511                irq_mask) {
 512                 i++;
 513                 if (i > FRAMEDONE_IRQ_TIMEOUT) {
 514                         pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
 515                         break;
 516                 }
 517                 mdelay(1);
 518         }
 519 }
 520
 521 int omap_dss_reset(struct omap_hwmod *oh)
 522 {
 523         struct omap_hwmod_opt_clk *oc;
 524         int c = 0;
 525         int i, r;
 526
 527         if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
 528                 pr_err("dss_core: hwmod data doesn't contain reset data\n");
 529                 return -EINVAL;
 530         }
 531
 532         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
 533                 if (oc->_clk)
 534                         clk_prepare_enable(oc->_clk);
 535
 536         dispc_disable_outputs();
 537
 538         /* clear SDI registers */
 539         if (cpu_is_omap3430()) {
 540                 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
 541                 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
 542         }
 543
 544         /*
 545          * clear DSS_CONTROL register to switch DSS clock sources to
 546          * PRCM clock, if any
 547          */
 548         omap_hwmod_write(0x0, oh, DSS_CONTROL);
 549
 550         omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
 551                                 & SYSS_RESETDONE_MASK),
 552                         MAX_MODULE_SOFTRESET_WAIT, c);
 553
 554         if (c == MAX_MODULE_SOFTRESET_WAIT)
 555                 pr_warn("dss_core: waiting for reset to finish failed\n");
 556         else
 557                 pr_debug("dss_core: softreset done\n");
 558
 559         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
 560                 if (oc->_clk)
 561                         clk_disable_unprepare(oc->_clk);
 562
 563         r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
 564
 565         return r;
 566 }
 567
 568 void __init omapdss_early_init_of(void)
 569 {
 570
 571 }
 572
 573 static const char * const omapdss_compat_names[] __initconst = {
 574         "ti,omap2-dss",
 575         "ti,omap3-dss",
 576         "ti,omap4-dss",
 577         "ti,omap5-dss",
 578         "ti,dra7-dss",
 579 };
 580
 581 struct device_node * __init omapdss_find_dss_of_node(void)
 582 {
 583         struct device_node *node;
 584         int i;
 585
 586         for (i = 0; i < ARRAY_SIZE(omapdss_compat_names); ++i) {
 587                 node = of_find_compatible_node(NULL, NULL,
 588                         omapdss_compat_names[i]);
 589                 if (node)
 590                         return node;
 591         }
 592
 593         return NULL;
 594 }
 595
 596 int __init omapdss_init_of(void)
 597 {
 598         int r;
 599         enum omapdss_version ver;
 600         struct device_node *node;
 601         struct platform_device *pdev;
 602
 603         static struct omap_dss_board_info board_data = {
 604                 .dsi_enable_pads = omap_dsi_enable_pads,
 605                 .dsi_disable_pads = omap_dsi_disable_pads,
 606                 .set_min_bus_tput = omap_dss_set_min_bus_tput,
 607         };
 608
 609         /* only create dss helper devices if dss is enabled in the .dts */
 610
 611         node = omapdss_find_dss_of_node();
 612         if (!node)
 613                 return 0;
 614
 615         if (!of_device_is_available(node))
 616                 return 0;
 617
 618         ver = omap_display_get_version();
 619
 620         if (ver == OMAPDSS_VER_UNKNOWN) {
 621                 pr_err("DSS not supported on this SoC\n");
 622                 return -ENODEV;
 623         }
 624
 625         pdev = of_find_device_by_node(node);
 626
 627         if (!pdev) {
 628                 pr_err("Unable to find DSS platform device\n");
 629                 return -ENODEV;
 630         }
 631
 632         r = of_platform_populate(node, NULL, NULL, &pdev->dev);
 633         if (r) {
 634                 pr_err("Unable to populate DSS submodule devices\n");
 635                 return r;
 636         }
 637
 638         board_data.version = ver;
 639
 640         omap_display_device.dev.platform_data = &board_data;
 641
 642         r = platform_device_register(&omap_display_device);
 643         if (r < 0) {
 644                 pr_err("Unable to register omapdss device\n");
 645                 return r;
 646         }
 647
 648         /* create DRM device */
 649         r = omap_init_drm();
 650         if (r < 0) {
 651                 pr_err("Unable to register omapdrm device\n");
 652                 return r;
 653         }
 654
 655         /* create vrfb device */
 656         r = omap_init_vrfb();
 657         if (r < 0) {
 658                 pr_err("Unable to register omapvrfb device\n");
 659                 return r;
 660         }
 661
 662         /* create FB device */
 663         r = omap_init_fb();
 664         if (r < 0) {
 665                 pr_err("Unable to register omapfb device\n");
 666                 return r;
 667         }
 668
 669         /* create V4L2 display device */
 670         r = omap_init_vout();
 671         if (r < 0) {
 672                 pr_err("Unable to register omap_vout device\n");
 673                 return r;
 674         }
 675
 676         /* add DSI info for omap4 */
 677         node = of_find_node_by_name(NULL, "omap4_padconf_global");
 678         if (node)
 679                 omap4_dsi_mux_syscon = syscon_node_to_regmap(node);
 680
 681         return 0;
 682 }