arch/arm/mach-omap2/cclock3xxx_data.c

   1 /*
   2  * OMAP3 clock data
   3  *
   4  * Copyright (C) 2007-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2011 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * Updated to COMMON clk data format by Rajendra Nayak <rnayak@ti.com>
   9  * With many device clock fixes by Kevin Hilman and Jouni Högander
  10  * DPLL bypass clock support added by Roman Tereshonkov
  11  *
  12  */
  13
  14 /*
  15  * Virtual clocks are introduced as convenient tools.
  16  * They are sources for other clocks and not supposed
  17  * to be requested from drivers directly.
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/clk.h>
  22 #include <linux/clk-private.h>
  23 #include <linux/list.h>
  24 #include <linux/io.h>
  25
  26 #include "soc.h"
  27 #include "iomap.h"
  28 #include "clock.h"
  29 #include "clock3xxx.h"
  30 #include "clock34xx.h"
  31 #include "clock36xx.h"
  32 #include "clock3517.h"
  33 #include "cm3xxx.h"
  34 #include "cm-regbits-34xx.h"
  35 #include "prm3xxx.h"
  36 #include "prm-regbits-34xx.h"
  37 #include "control.h"
  38
  39 /*
  40  * clocks
  41  */
  42
  43 #define OMAP_CM_REGADDR         OMAP34XX_CM_REGADDR
  44
  45 /* Maximum DPLL multiplier, divider values for OMAP3 */
  46 #define OMAP3_MAX_DPLL_MULT             2047
  47 #define OMAP3630_MAX_JTYPE_DPLL_MULT    4095
  48 #define OMAP3_MAX_DPLL_DIV              128
  49
  50 DEFINE_CLK_FIXED_RATE(dummy_apb_pclk, CLK_IS_ROOT, 0x0, 0x0);
  51
  52 DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
  53
  54 DEFINE_CLK_FIXED_RATE(omap_32k_fck, CLK_IS_ROOT, 32768, 0x0);
  55
  56 DEFINE_CLK_FIXED_RATE(pclk_ck, CLK_IS_ROOT, 27000000, 0x0);
  57
  58 DEFINE_CLK_FIXED_RATE(rmii_ck, CLK_IS_ROOT, 50000000, 0x0);
  59
  60 DEFINE_CLK_FIXED_RATE(secure_32k_fck, CLK_IS_ROOT, 32768, 0x0);
  61
  62 DEFINE_CLK_FIXED_RATE(sys_altclk, CLK_IS_ROOT, 0x0, 0x0);
  63
  64 DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0);
  65
  66 DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0);
  67
  68 DEFINE_CLK_FIXED_RATE(virt_16_8m_ck, CLK_IS_ROOT, 16800000, 0x0);
  69
  70 DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
  71
  72 DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
  73
  74 DEFINE_CLK_FIXED_RATE(virt_38_4m_ck, CLK_IS_ROOT, 38400000, 0x0);
  75
  76 static const char *osc_sys_ck_parent_names[] = {
  77         "virt_12m_ck", "virt_13m_ck", "virt_19200000_ck", "virt_26000000_ck",
  78         "virt_38_4m_ck", "virt_16_8m_ck",
  79 };
  80
  81 DEFINE_CLK_MUX(osc_sys_ck, osc_sys_ck_parent_names, NULL, 0x0,
  82                OMAP3430_PRM_CLKSEL, OMAP3430_SYS_CLKIN_SEL_SHIFT,
  83                OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0, NULL);
  84
  85 DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck, 0x0,
  86                    OMAP3430_PRM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
  87                    OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
  88
  89 static struct dpll_data dpll3_dd = {
  90         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  91         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
  92         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
  93         .clk_bypass     = &sys_ck,
  94         .clk_ref        = &sys_ck,
  95         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
  96         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  97         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
  98         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
  99         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 100         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 101         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 102         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 103         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 104         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 105         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 106         .min_divider    = 1,
 107         .max_divider    = OMAP3_MAX_DPLL_DIV,
 108 };
 109
 110 static struct clk dpll3_ck;
 111
 112 static const char *dpll3_ck_parent_names[] = {
 113         "sys_ck",
 114 };
 115
 116 static const struct clk_ops dpll3_ck_ops = {
 117         .init           = &omap2_init_clk_clkdm,
 118         .get_parent     = &omap2_init_dpll_parent,
 119         .recalc_rate    = &omap3_dpll_recalc,
 120         .round_rate     = &omap2_dpll_round_rate,
 121 };
 122
 123 static struct clk_hw_omap dpll3_ck_hw = {
 124         .hw = {
 125                 .clk = &dpll3_ck,
 126         },
 127         .ops            = &clkhwops_omap3_dpll,
 128         .dpll_data      = &dpll3_dd,
 129         .clkdm_name     = "dpll3_clkdm",
 130 };
 131
 132 DEFINE_STRUCT_CLK(dpll3_ck, dpll3_ck_parent_names, dpll3_ck_ops);
 133
 134 DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck, 0x0,
 135                    OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 136                    OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT,
 137                    OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH,
 138                    CLK_DIVIDER_ONE_BASED, NULL);
 139
 140 static struct clk core_ck;
 141
 142 static const char *core_ck_parent_names[] = {
 143         "dpll3_m2_ck",
 144 };
 145
 146 static const struct clk_ops core_ck_ops = {};
 147
 148 DEFINE_STRUCT_CLK_HW_OMAP(core_ck, NULL);
 149 DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
 150
 151 DEFINE_CLK_DIVIDER(l3_ick, "core_ck", &core_ck, 0x0,
 152                    OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 153                    OMAP3430_CLKSEL_L3_SHIFT, OMAP3430_CLKSEL_L3_WIDTH,
 154                    CLK_DIVIDER_ONE_BASED, NULL);
 155
 156 DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick, 0x0,
 157                    OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 158                    OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH,
 159                    CLK_DIVIDER_ONE_BASED, NULL);
 160
 161 static struct clk security_l4_ick2;
 162
 163 static const char *security_l4_ick2_parent_names[] = {
 164         "l4_ick",
 165 };
 166
 167 DEFINE_STRUCT_CLK_HW_OMAP(security_l4_ick2, NULL);
 168 DEFINE_STRUCT_CLK(security_l4_ick2, security_l4_ick2_parent_names, core_ck_ops);
 169
 170 static struct clk aes1_ick;
 171
 172 static const char *aes1_ick_parent_names[] = {
 173         "security_l4_ick2",
 174 };
 175
 176 static const struct clk_ops aes1_ick_ops = {
 177         .enable         = &omap2_dflt_clk_enable,
 178         .disable        = &omap2_dflt_clk_disable,
 179         .is_enabled     = &omap2_dflt_clk_is_enabled,
 180 };
 181
 182 static struct clk_hw_omap aes1_ick_hw = {
 183         .hw = {
 184                 .clk = &aes1_ick,
 185         },
 186         .ops            = &clkhwops_iclk_wait,
 187         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 188         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
 189 };
 190
 191 DEFINE_STRUCT_CLK(aes1_ick, aes1_ick_parent_names, aes1_ick_ops);
 192
 193 static struct clk core_l4_ick;
 194
 195 static const struct clk_ops core_l4_ick_ops = {
 196         .init           = &omap2_init_clk_clkdm,
 197 };
 198
 199 DEFINE_STRUCT_CLK_HW_OMAP(core_l4_ick, "core_l4_clkdm");
 200 DEFINE_STRUCT_CLK(core_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
 201
 202 static struct clk aes2_ick;
 203
 204 static const char *aes2_ick_parent_names[] = {
 205         "core_l4_ick",
 206 };
 207
 208 static const struct clk_ops aes2_ick_ops = {
 209         .init           = &omap2_init_clk_clkdm,
 210         .enable         = &omap2_dflt_clk_enable,
 211         .disable        = &omap2_dflt_clk_disable,
 212         .is_enabled     = &omap2_dflt_clk_is_enabled,
 213 };
 214
 215 static struct clk_hw_omap aes2_ick_hw = {
 216         .hw = {
 217                 .clk = &aes2_ick,
 218         },
 219         .ops            = &clkhwops_iclk_wait,
 220         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 221         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
 222         .clkdm_name     = "core_l4_clkdm",
 223 };
 224
 225 DEFINE_STRUCT_CLK(aes2_ick, aes2_ick_parent_names, aes2_ick_ops);
 226
 227 static struct clk dpll1_fck;
 228
 229 static struct dpll_data dpll1_dd = {
 230         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 231         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 232         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 233         .clk_bypass     = &dpll1_fck,
 234         .clk_ref        = &sys_ck,
 235         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 236         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 237         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 238         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 239         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 240         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 241         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 242         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 243         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 244         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 245         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 246         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 247         .min_divider    = 1,
 248         .max_divider    = OMAP3_MAX_DPLL_DIV,
 249 };
 250
 251 static struct clk dpll1_ck;
 252
 253 static const struct clk_ops dpll1_ck_ops = {
 254         .init           = &omap2_init_clk_clkdm,
 255         .enable         = &omap3_noncore_dpll_enable,
 256         .disable        = &omap3_noncore_dpll_disable,
 257         .get_parent     = &omap2_init_dpll_parent,
 258         .recalc_rate    = &omap3_dpll_recalc,
 259         .set_rate       = &omap3_noncore_dpll_set_rate,
 260         .round_rate     = &omap2_dpll_round_rate,
 261 };
 262
 263 static struct clk_hw_omap dpll1_ck_hw = {
 264         .hw = {
 265                 .clk = &dpll1_ck,
 266         },
 267         .ops            = &clkhwops_omap3_dpll,
 268         .dpll_data      = &dpll1_dd,
 269         .clkdm_name     = "dpll1_clkdm",
 270 };
 271
 272 DEFINE_STRUCT_CLK(dpll1_ck, dpll3_ck_parent_names, dpll1_ck_ops);
 273
 274 DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck, "dpll1_ck", &dpll1_ck, 0x0, 2, 1);
 275
 276 DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck, 0x0,
 277                    OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 278                    OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT,
 279                    OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH,
 280                    CLK_DIVIDER_ONE_BASED, NULL);
 281
 282 static struct clk mpu_ck;
 283
 284 static const char *mpu_ck_parent_names[] = {
 285         "dpll1_x2m2_ck",
 286 };
 287
 288 DEFINE_STRUCT_CLK_HW_OMAP(mpu_ck, "mpu_clkdm");
 289 DEFINE_STRUCT_CLK(mpu_ck, mpu_ck_parent_names, core_l4_ick_ops);
 290
 291 DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck, 0x0,
 292                    OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 293                    OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH,
 294                    0x0, NULL);
 295
 296 static struct clk cam_ick;
 297
 298 static struct clk_hw_omap cam_ick_hw = {
 299         .hw = {
 300                 .clk = &cam_ick,
 301         },
 302         .ops            = &clkhwops_iclk,
 303         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
 304         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
 305         .clkdm_name     = "cam_clkdm",
 306 };
 307
 308 DEFINE_STRUCT_CLK(cam_ick, security_l4_ick2_parent_names, aes2_ick_ops);
 309
 310 /* DPLL4 */
 311 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 312 /* Type: DPLL */
 313 static struct dpll_data dpll4_dd;
 314
 315 static struct dpll_data dpll4_dd_34xx __initdata = {
 316         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 317         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 318         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 319         .clk_bypass     = &sys_ck,
 320         .clk_ref        = &sys_ck,
 321         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 322         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 323         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 324         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 325         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 326         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 327         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 328         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 329         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 330         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 331         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 332         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 333         .min_divider    = 1,
 334         .max_divider    = OMAP3_MAX_DPLL_DIV,
 335 };
 336
 337 static struct dpll_data dpll4_dd_3630 __initdata = {
 338         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 339         .mult_mask      = OMAP3630_PERIPH_DPLL_MULT_MASK,
 340         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 341         .clk_bypass     = &sys_ck,
 342         .clk_ref        = &sys_ck,
 343         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 344         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 345         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 346         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 347         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 348         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 349         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 350         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 351         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 352         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 353         .dco_mask       = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
 354         .sddiv_mask     = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
 355         .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
 356         .min_divider    = 1,
 357         .max_divider    = OMAP3_MAX_DPLL_DIV,
 358         .flags          = DPLL_J_TYPE
 359 };
 360
 361 static struct clk dpll4_ck;
 362
 363 static const struct clk_ops dpll4_ck_ops = {
 364         .init           = &omap2_init_clk_clkdm,
 365         .enable         = &omap3_noncore_dpll_enable,
 366         .disable        = &omap3_noncore_dpll_disable,
 367         .get_parent     = &omap2_init_dpll_parent,
 368         .recalc_rate    = &omap3_dpll_recalc,
 369         .set_rate       = &omap3_dpll4_set_rate,
 370         .round_rate     = &omap2_dpll_round_rate,
 371 };
 372
 373 static struct clk_hw_omap dpll4_ck_hw = {
 374         .hw = {
 375                 .clk = &dpll4_ck,
 376         },
 377         .dpll_data      = &dpll4_dd,
 378         .ops            = &clkhwops_omap3_dpll,
 379         .clkdm_name     = "dpll4_clkdm",
 380 };
 381
 382 DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops);
 383
 384 DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0,
 385                    OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 386                    OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH,
 387                    CLK_DIVIDER_ONE_BASED, NULL);
 388
 389 static struct clk dpll4_m5x2_ck;
 390
 391 static const char *dpll4_m5x2_ck_parent_names[] = {
 392         "dpll4_m5_ck",
 393 };
 394
 395 static const struct clk_ops dpll4_m5x2_ck_ops = {
 396         .init           = &omap2_init_clk_clkdm,
 397         .enable         = &omap2_dflt_clk_enable,
 398         .disable        = &omap2_dflt_clk_disable,
 399         .is_enabled     = &omap2_dflt_clk_is_enabled,
 400         .recalc_rate    = &omap3_clkoutx2_recalc,
 401 };
 402
 403 static const struct clk_ops dpll4_m5x2_ck_3630_ops = {
 404         .init           = &omap2_init_clk_clkdm,
 405         .enable         = &omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
 406         .disable        = &omap2_dflt_clk_disable,
 407         .recalc_rate    = &omap3_clkoutx2_recalc,
 408 };
 409
 410 static struct clk_hw_omap dpll4_m5x2_ck_hw = {
 411         .hw = {
 412                 .clk = &dpll4_m5x2_ck,
 413         },
 414         .ops            = &clkhwops_wait,
 415         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 416         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 417         .flags          = INVERT_ENABLE,
 418         .clkdm_name     = "dpll4_clkdm",
 419 };
 420
 421 DEFINE_STRUCT_CLK_FLAGS(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names,
 422                         dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
 423
 424 static struct clk dpll4_m5x2_ck_3630 = {
 425         .name           = "dpll4_m5x2_ck",
 426         .hw             = &dpll4_m5x2_ck_hw.hw,
 427         .parent_names   = dpll4_m5x2_ck_parent_names,
 428         .num_parents    = ARRAY_SIZE(dpll4_m5x2_ck_parent_names),
 429         .ops            = &dpll4_m5x2_ck_3630_ops,
 430         .flags          = CLK_SET_RATE_PARENT,
 431 };
 432
 433 static struct clk cam_mclk;
 434
 435 static const char *cam_mclk_parent_names[] = {
 436         "dpll4_m5x2_ck",
 437 };
 438
 439 static struct clk_hw_omap cam_mclk_hw = {
 440         .hw = {
 441                 .clk = &cam_mclk,
 442         },
 443         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
 444         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
 445         .clkdm_name     = "cam_clkdm",
 446 };
 447
 448 static struct clk cam_mclk = {
 449         .name           = "cam_mclk",
 450         .hw             = &cam_mclk_hw.hw,
 451         .parent_names   = cam_mclk_parent_names,
 452         .num_parents    = ARRAY_SIZE(cam_mclk_parent_names),
 453         .ops            = &aes2_ick_ops,
 454         .flags          = CLK_SET_RATE_PARENT,
 455 };
 456
 457 static const struct clksel_rate clkout2_src_core_rates[] = {
 458         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 459         { .div = 0 }
 460 };
 461
 462 static const struct clksel_rate clkout2_src_sys_rates[] = {
 463         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 464         { .div = 0 }
 465 };
 466
 467 static const struct clksel_rate clkout2_src_96m_rates[] = {
 468         { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
 469         { .div = 0 }
 470 };
 471
 472 DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck, 0x0,
 473                    OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 474                    OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH,
 475                    CLK_DIVIDER_ONE_BASED, NULL);
 476
 477 static struct clk dpll4_m2x2_ck;
 478
 479 static const char *dpll4_m2x2_ck_parent_names[] = {
 480         "dpll4_m2_ck",
 481 };
 482
 483 static struct clk_hw_omap dpll4_m2x2_ck_hw = {
 484         .hw = {
 485                 .clk = &dpll4_m2x2_ck,
 486         },
 487         .ops            = &clkhwops_wait,
 488         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 489         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 490         .flags          = INVERT_ENABLE,
 491         .clkdm_name     = "dpll4_clkdm",
 492 };
 493
 494 DEFINE_STRUCT_CLK(dpll4_m2x2_ck, dpll4_m2x2_ck_parent_names, dpll4_m5x2_ck_ops);
 495
 496 static struct clk dpll4_m2x2_ck_3630 = {
 497         .name           = "dpll4_m2x2_ck",
 498         .hw             = &dpll4_m2x2_ck_hw.hw,
 499         .parent_names   = dpll4_m2x2_ck_parent_names,
 500         .num_parents    = ARRAY_SIZE(dpll4_m2x2_ck_parent_names),
 501         .ops            = &dpll4_m5x2_ck_3630_ops,
 502 };
 503
 504 static struct clk omap_96m_alwon_fck;
 505
 506 static const char *omap_96m_alwon_fck_parent_names[] = {
 507         "dpll4_m2x2_ck",
 508 };
 509
 510 DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck, NULL);
 511 DEFINE_STRUCT_CLK(omap_96m_alwon_fck, omap_96m_alwon_fck_parent_names,
 512                   core_ck_ops);
 513
 514 static struct clk cm_96m_fck;
 515
 516 static const char *cm_96m_fck_parent_names[] = {
 517         "omap_96m_alwon_fck",
 518 };
 519
 520 DEFINE_STRUCT_CLK_HW_OMAP(cm_96m_fck, NULL);
 521 DEFINE_STRUCT_CLK(cm_96m_fck, cm_96m_fck_parent_names, core_ck_ops);
 522
 523 static const struct clksel_rate clkout2_src_54m_rates[] = {
 524         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
 525         { .div = 0 }
 526 };
 527
 528 DEFINE_CLK_DIVIDER(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0,
 529                    OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 530                    OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,
 531                    CLK_DIVIDER_ONE_BASED, NULL);
 532
 533 static struct clk dpll4_m3x2_ck;
 534
 535 static const char *dpll4_m3x2_ck_parent_names[] = {
 536         "dpll4_m3_ck",
 537 };
 538
 539 static struct clk_hw_omap dpll4_m3x2_ck_hw = {
 540         .hw = {
 541                 .clk = &dpll4_m3x2_ck,
 542         },
 543         .ops            = &clkhwops_wait,
 544         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 545         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 546         .flags          = INVERT_ENABLE,
 547         .clkdm_name     = "dpll4_clkdm",
 548 };
 549
 550 DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
 551
 552 static struct clk dpll4_m3x2_ck_3630 = {
 553         .name           = "dpll4_m3x2_ck",
 554         .hw             = &dpll4_m3x2_ck_hw.hw,
 555         .parent_names   = dpll4_m3x2_ck_parent_names,
 556         .num_parents    = ARRAY_SIZE(dpll4_m3x2_ck_parent_names),
 557         .ops            = &dpll4_m5x2_ck_3630_ops,
 558 };
 559
 560 static const char *omap_54m_fck_parent_names[] = {
 561         "dpll4_m3x2_ck", "sys_altclk",
 562 };
 563
 564 DEFINE_CLK_MUX(omap_54m_fck, omap_54m_fck_parent_names, NULL, 0x0,
 565                OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP3430_SOURCE_54M_SHIFT,
 566                OMAP3430_SOURCE_54M_WIDTH, 0x0, NULL);
 567
 568 static const struct clksel clkout2_src_clksel[] = {
 569         { .parent = &core_ck, .rates = clkout2_src_core_rates },
 570         { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
 571         { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
 572         { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
 573         { .parent = NULL },
 574 };
 575
 576 static const char *clkout2_src_ck_parent_names[] = {
 577         "core_ck", "sys_ck", "cm_96m_fck", "omap_54m_fck",
 578 };
 579
 580 static const struct clk_ops clkout2_src_ck_ops = {
 581         .init           = &omap2_init_clk_clkdm,
 582         .enable         = &omap2_dflt_clk_enable,
 583         .disable        = &omap2_dflt_clk_disable,
 584         .is_enabled     = &omap2_dflt_clk_is_enabled,
 585         .recalc_rate    = &omap2_clksel_recalc,
 586         .get_parent     = &omap2_clksel_find_parent_index,
 587         .set_parent     = &omap2_clksel_set_parent,
 588 };
 589
 590 DEFINE_CLK_OMAP_MUX_GATE(clkout2_src_ck, "core_clkdm",
 591                          clkout2_src_clksel, OMAP3430_CM_CLKOUT_CTRL,
 592                          OMAP3430_CLKOUT2SOURCE_MASK,
 593                          OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_EN_SHIFT,
 594                          NULL, clkout2_src_ck_parent_names, clkout2_src_ck_ops);
 595
 596 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 597         { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
 598         { .div = 0 }
 599 };
 600
 601 static const struct clksel_rate omap_48m_alt_rates[] = {
 602         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 603         { .div = 0 }
 604 };
 605
 606 static const struct clksel omap_48m_clksel[] = {
 607         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 608         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 609         { .parent = NULL },
 610 };
 611
 612 static const char *omap_48m_fck_parent_names[] = {
 613         "cm_96m_fck", "sys_altclk",
 614 };
 615
 616 static struct clk omap_48m_fck;
 617
 618 static const struct clk_ops omap_48m_fck_ops = {
 619         .recalc_rate    = &omap2_clksel_recalc,
 620         .get_parent     = &omap2_clksel_find_parent_index,
 621         .set_parent     = &omap2_clksel_set_parent,
 622 };
 623
 624 static struct clk_hw_omap omap_48m_fck_hw = {
 625         .hw = {
 626                 .clk = &omap_48m_fck,
 627         },
 628         .clksel         = omap_48m_clksel,
 629         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 630         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 631 };
 632
 633 DEFINE_STRUCT_CLK(omap_48m_fck, omap_48m_fck_parent_names, omap_48m_fck_ops);
 634
 635 DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck, 0x0, 1, 4);
 636
 637 static struct clk core_12m_fck;
 638
 639 static const char *core_12m_fck_parent_names[] = {
 640         "omap_12m_fck",
 641 };
 642
 643 DEFINE_STRUCT_CLK_HW_OMAP(core_12m_fck, "core_l4_clkdm");
 644 DEFINE_STRUCT_CLK(core_12m_fck, core_12m_fck_parent_names, core_l4_ick_ops);
 645
 646 static struct clk core_48m_fck;
 647
 648 static const char *core_48m_fck_parent_names[] = {
 649         "omap_48m_fck",
 650 };
 651
 652 DEFINE_STRUCT_CLK_HW_OMAP(core_48m_fck, "core_l4_clkdm");
 653 DEFINE_STRUCT_CLK(core_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
 654
 655 static const char *omap_96m_fck_parent_names[] = {
 656         "cm_96m_fck", "sys_ck",
 657 };
 658
 659 DEFINE_CLK_MUX(omap_96m_fck, omap_96m_fck_parent_names, NULL, 0x0,
 660                OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 661                OMAP3430_SOURCE_96M_SHIFT, OMAP3430_SOURCE_96M_WIDTH, 0x0, NULL);
 662
 663 static struct clk core_96m_fck;
 664
 665 static const char *core_96m_fck_parent_names[] = {
 666         "omap_96m_fck",
 667 };
 668
 669 DEFINE_STRUCT_CLK_HW_OMAP(core_96m_fck, "core_l4_clkdm");
 670 DEFINE_STRUCT_CLK(core_96m_fck, core_96m_fck_parent_names, core_l4_ick_ops);
 671
 672 static struct clk core_l3_ick;
 673
 674 static const char *core_l3_ick_parent_names[] = {
 675         "l3_ick",
 676 };
 677
 678 DEFINE_STRUCT_CLK_HW_OMAP(core_l3_ick, "core_l3_clkdm");
 679 DEFINE_STRUCT_CLK(core_l3_ick, core_l3_ick_parent_names, core_l4_ick_ops);
 680
 681 DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck, 0x0, 2, 1);
 682
 683 static struct clk corex2_fck;
 684
 685 static const char *corex2_fck_parent_names[] = {
 686         "dpll3_m2x2_ck",
 687 };
 688
 689 DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL);
 690 DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops);
 691
 692 static struct clk cpefuse_fck;
 693
 694 static struct clk_hw_omap cpefuse_fck_hw = {
 695         .hw = {
 696                 .clk = &cpefuse_fck,
 697         },
 698         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
 699         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
 700         .clkdm_name     = "core_l4_clkdm",
 701 };
 702
 703 DEFINE_STRUCT_CLK(cpefuse_fck, dpll3_ck_parent_names, aes2_ick_ops);
 704
 705 static struct clk csi2_96m_fck;
 706
 707 static const char *csi2_96m_fck_parent_names[] = {
 708         "core_96m_fck",
 709 };
 710
 711 static struct clk_hw_omap csi2_96m_fck_hw = {
 712         .hw = {
 713                 .clk = &csi2_96m_fck,
 714         },
 715         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
 716         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
 717         .clkdm_name     = "cam_clkdm",
 718 };
 719
 720 DEFINE_STRUCT_CLK(csi2_96m_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
 721
 722 static struct clk d2d_26m_fck;
 723
 724 static struct clk_hw_omap d2d_26m_fck_hw = {
 725         .hw = {
 726                 .clk = &d2d_26m_fck,
 727         },
 728         .ops            = &clkhwops_wait,
 729         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 730         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
 731         .clkdm_name     = "d2d_clkdm",
 732 };
 733
 734 DEFINE_STRUCT_CLK(d2d_26m_fck, dpll3_ck_parent_names, aes2_ick_ops);
 735
 736 static struct clk des1_ick;
 737
 738 static struct clk_hw_omap des1_ick_hw = {
 739         .hw = {
 740                 .clk = &des1_ick,
 741         },
 742         .ops            = &clkhwops_iclk_wait,
 743         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 744         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
 745 };
 746
 747 DEFINE_STRUCT_CLK(des1_ick, aes1_ick_parent_names, aes1_ick_ops);
 748
 749 static struct clk des2_ick;
 750
 751 static struct clk_hw_omap des2_ick_hw = {
 752         .hw = {
 753                 .clk = &des2_ick,
 754         },
 755         .ops            = &clkhwops_iclk_wait,
 756         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 757         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
 758         .clkdm_name     = "core_l4_clkdm",
 759 };
 760
 761 DEFINE_STRUCT_CLK(des2_ick, aes2_ick_parent_names, aes2_ick_ops);
 762
 763 DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck, 0x0,
 764                    OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 765                    OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH,
 766                    CLK_DIVIDER_ONE_BASED, NULL);
 767
 768 static struct clk dpll2_fck;
 769
 770 static struct dpll_data dpll2_dd = {
 771         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 772         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 773         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 774         .clk_bypass     = &dpll2_fck,
 775         .clk_ref        = &sys_ck,
 776         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 777         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 778         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 779         .modes          = ((1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 780                            (1 << DPLL_LOW_POWER_BYPASS)),
 781         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 782         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 783         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 784         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 785         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 786         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 787         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 788         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 789         .min_divider    = 1,
 790         .max_divider    = OMAP3_MAX_DPLL_DIV,
 791 };
 792
 793 static struct clk dpll2_ck;
 794
 795 static struct clk_hw_omap dpll2_ck_hw = {
 796         .hw = {
 797                 .clk = &dpll2_ck,
 798         },
 799         .ops            = &clkhwops_omap3_dpll,
 800         .dpll_data      = &dpll2_dd,
 801         .clkdm_name     = "dpll2_clkdm",
 802 };
 803
 804 DEFINE_STRUCT_CLK(dpll2_ck, dpll3_ck_parent_names, dpll1_ck_ops);
 805
 806 DEFINE_CLK_DIVIDER(dpll2_fck, "core_ck", &core_ck, 0x0,
 807                    OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 808                    OMAP3430_IVA2_CLK_SRC_SHIFT, OMAP3430_IVA2_CLK_SRC_WIDTH,
 809                    CLK_DIVIDER_ONE_BASED, NULL);
 810
 811 DEFINE_CLK_DIVIDER(dpll2_m2_ck, "dpll2_ck", &dpll2_ck, 0x0,
 812                    OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
 813                    OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT,
 814                    OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH,
 815                    CLK_DIVIDER_ONE_BASED, NULL);
 816
 817 DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck, 0x0,
 818                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 819                    OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH,
 820                    CLK_DIVIDER_ONE_BASED, NULL);
 821
 822 static struct clk dpll3_m3x2_ck;
 823
 824 static const char *dpll3_m3x2_ck_parent_names[] = {
 825         "dpll3_m3_ck",
 826 };
 827
 828 static struct clk_hw_omap dpll3_m3x2_ck_hw = {
 829         .hw = {
 830                 .clk = &dpll3_m3x2_ck,
 831         },
 832         .ops            = &clkhwops_wait,
 833         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 834         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 835         .flags          = INVERT_ENABLE,
 836         .clkdm_name     = "dpll3_clkdm",
 837 };
 838
 839 DEFINE_STRUCT_CLK(dpll3_m3x2_ck, dpll3_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
 840
 841 static struct clk dpll3_m3x2_ck_3630 = {
 842         .name           = "dpll3_m3x2_ck",
 843         .hw             = &dpll3_m3x2_ck_hw.hw,
 844         .parent_names   = dpll3_m3x2_ck_parent_names,
 845         .num_parents    = ARRAY_SIZE(dpll3_m3x2_ck_parent_names),
 846         .ops            = &dpll4_m5x2_ck_3630_ops,
 847 };
 848
 849 DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1);
 850
 851 DEFINE_CLK_DIVIDER(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0,
 852                    OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 853                    OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH,
 854                    CLK_DIVIDER_ONE_BASED, NULL);
 855
 856 static struct clk dpll4_m4x2_ck;
 857
 858 static const char *dpll4_m4x2_ck_parent_names[] = {
 859         "dpll4_m4_ck",
 860 };
 861
 862 static struct clk_hw_omap dpll4_m4x2_ck_hw = {
 863         .hw = {
 864                 .clk = &dpll4_m4x2_ck,
 865         },
 866         .ops            = &clkhwops_wait,
 867         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 868         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 869         .flags          = INVERT_ENABLE,
 870         .clkdm_name     = "dpll4_clkdm",
 871 };
 872
 873 DEFINE_STRUCT_CLK(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names, dpll4_m5x2_ck_ops);
 874
 875 static struct clk dpll4_m4x2_ck_3630 = {
 876         .name           = "dpll4_m4x2_ck",
 877         .hw             = &dpll4_m4x2_ck_hw.hw,
 878         .parent_names   = dpll4_m4x2_ck_parent_names,
 879         .num_parents    = ARRAY_SIZE(dpll4_m4x2_ck_parent_names),
 880         .ops            = &dpll4_m5x2_ck_3630_ops,
 881 };
 882
 883 DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0,
 884                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 885                    OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH,
 886                    CLK_DIVIDER_ONE_BASED, NULL);
 887
 888 static struct clk dpll4_m6x2_ck;
 889
 890 static const char *dpll4_m6x2_ck_parent_names[] = {
 891         "dpll4_m6_ck",
 892 };
 893
 894 static struct clk_hw_omap dpll4_m6x2_ck_hw = {
 895         .hw = {
 896                 .clk = &dpll4_m6x2_ck,
 897         },
 898         .ops            = &clkhwops_wait,
 899         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 900         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 901         .flags          = INVERT_ENABLE,
 902         .clkdm_name     = "dpll4_clkdm",
 903 };
 904
 905 DEFINE_STRUCT_CLK(dpll4_m6x2_ck, dpll4_m6x2_ck_parent_names, dpll4_m5x2_ck_ops);
 906
 907 static struct clk dpll4_m6x2_ck_3630 = {
 908         .name           = "dpll4_m6x2_ck",
 909         .hw             = &dpll4_m6x2_ck_hw.hw,
 910         .parent_names   = dpll4_m6x2_ck_parent_names,
 911         .num_parents    = ARRAY_SIZE(dpll4_m6x2_ck_parent_names),
 912         .ops            = &dpll4_m5x2_ck_3630_ops,
 913 };
 914
 915 DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck, "dpll4_ck", &dpll4_ck, 0x0, 2, 1);
 916
 917 static struct dpll_data dpll5_dd = {
 918         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 919         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 920         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 921         .clk_bypass     = &sys_ck,
 922         .clk_ref        = &sys_ck,
 923         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 924         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 925         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 926         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 927         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 928         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 929         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 930         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 931         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 932         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 933         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 934         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 935         .min_divider    = 1,
 936         .max_divider    = OMAP3_MAX_DPLL_DIV,
 937 };
 938
 939 static struct clk dpll5_ck;
 940
 941 static struct clk_hw_omap dpll5_ck_hw = {
 942         .hw = {
 943                 .clk = &dpll5_ck,
 944         },
 945         .ops            = &clkhwops_omap3_dpll,
 946         .dpll_data      = &dpll5_dd,
 947         .clkdm_name     = "dpll5_clkdm",
 948 };
 949
 950 DEFINE_STRUCT_CLK(dpll5_ck, dpll3_ck_parent_names, dpll1_ck_ops);
 951
 952 DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck, 0x0,
 953                    OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 954                    OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH,
 955                    CLK_DIVIDER_ONE_BASED, NULL);
 956
 957 static struct clk dss1_alwon_fck_3430es1;
 958
 959 static const char *dss1_alwon_fck_3430es1_parent_names[] = {
 960         "dpll4_m4x2_ck",
 961 };
 962
 963 static struct clk_hw_omap dss1_alwon_fck_3430es1_hw = {
 964         .hw = {
 965                 .clk = &dss1_alwon_fck_3430es1,
 966         },
 967         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
 968         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
 969         .clkdm_name     = "dss_clkdm",
 970 };
 971
 972 DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es1, dss1_alwon_fck_3430es1_parent_names,
 973                   aes2_ick_ops);
 974
 975 static struct clk dss1_alwon_fck_3430es2;
 976
 977 static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = {
 978         .hw = {
 979                 .clk = &dss1_alwon_fck_3430es2,
 980         },
 981         .ops            = &clkhwops_omap3430es2_dss_usbhost_wait,
 982         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
 983         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
 984         .clkdm_name     = "dss_clkdm",
 985 };
 986
 987 DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es2, dss1_alwon_fck_3430es1_parent_names,
 988                   aes2_ick_ops);
 989
 990 static struct clk dss2_alwon_fck;
 991
 992 static struct clk_hw_omap dss2_alwon_fck_hw = {
 993         .hw = {
 994                 .clk = &dss2_alwon_fck,
 995         },
 996         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
 997         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
 998         .clkdm_name     = "dss_clkdm",
 999 };
1000
1001 DEFINE_STRUCT_CLK(dss2_alwon_fck, dpll3_ck_parent_names, aes2_ick_ops);
1002
1003 static struct clk dss_96m_fck;
1004
1005 static struct clk_hw_omap dss_96m_fck_hw = {
1006         .hw = {
1007                 .clk = &dss_96m_fck,
1008         },
1009         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1010         .enable_bit     = OMAP3430_EN_TV_SHIFT,
1011         .clkdm_name     = "dss_clkdm",
1012 };
1013
1014 DEFINE_STRUCT_CLK(dss_96m_fck, core_96m_fck_parent_names, aes2_ick_ops);
1015
1016 static struct clk dss_ick_3430es1;
1017
1018 static struct clk_hw_omap dss_ick_3430es1_hw = {
1019         .hw = {
1020                 .clk = &dss_ick_3430es1,
1021         },
1022         .ops            = &clkhwops_iclk,
1023         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1024         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1025         .clkdm_name     = "dss_clkdm",
1026 };
1027
1028 DEFINE_STRUCT_CLK(dss_ick_3430es1, security_l4_ick2_parent_names, aes2_ick_ops);
1029
1030 static struct clk dss_ick_3430es2;
1031
1032 static struct clk_hw_omap dss_ick_3430es2_hw = {
1033         .hw = {
1034                 .clk = &dss_ick_3430es2,
1035         },
1036         .ops            = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
1037         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1038         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1039         .clkdm_name     = "dss_clkdm",
1040 };
1041
1042 DEFINE_STRUCT_CLK(dss_ick_3430es2, security_l4_ick2_parent_names, aes2_ick_ops);
1043
1044 static struct clk dss_tv_fck;
1045
1046 static const char *dss_tv_fck_parent_names[] = {
1047         "omap_54m_fck",
1048 };
1049
1050 static struct clk_hw_omap dss_tv_fck_hw = {
1051         .hw = {
1052                 .clk = &dss_tv_fck,
1053         },
1054         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1055         .enable_bit     = OMAP3430_EN_TV_SHIFT,
1056         .clkdm_name     = "dss_clkdm",
1057 };
1058
1059 DEFINE_STRUCT_CLK(dss_tv_fck, dss_tv_fck_parent_names, aes2_ick_ops);
1060
1061 static struct clk emac_fck;
1062
1063 static const char *emac_fck_parent_names[] = {
1064         "rmii_ck",
1065 };
1066
1067 static struct clk_hw_omap emac_fck_hw = {
1068         .hw = {
1069                 .clk = &emac_fck,
1070         },
1071         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1072         .enable_bit     = AM35XX_CPGMAC_FCLK_SHIFT,
1073 };
1074
1075 DEFINE_STRUCT_CLK(emac_fck, emac_fck_parent_names, aes1_ick_ops);
1076
1077 static struct clk ipss_ick;
1078
1079 static const char *ipss_ick_parent_names[] = {
1080         "core_l3_ick",
1081 };
1082
1083 static struct clk_hw_omap ipss_ick_hw = {
1084         .hw = {
1085                 .clk = &ipss_ick,
1086         },
1087         .ops            = &clkhwops_am35xx_ipss_wait,
1088         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1089         .enable_bit     = AM35XX_EN_IPSS_SHIFT,
1090         .clkdm_name     = "core_l3_clkdm",
1091 };
1092
1093 DEFINE_STRUCT_CLK(ipss_ick, ipss_ick_parent_names, aes2_ick_ops);
1094
1095 static struct clk emac_ick;
1096
1097 static const char *emac_ick_parent_names[] = {
1098         "ipss_ick",
1099 };
1100
1101 static struct clk_hw_omap emac_ick_hw = {
1102         .hw = {
1103                 .clk = &emac_ick,
1104         },
1105         .ops            = &clkhwops_am35xx_ipss_module_wait,
1106         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1107         .enable_bit     = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
1108         .clkdm_name     = "core_l3_clkdm",
1109 };
1110
1111 DEFINE_STRUCT_CLK(emac_ick, emac_ick_parent_names, aes2_ick_ops);
1112
1113 static struct clk emu_core_alwon_ck;
1114
1115 static const char *emu_core_alwon_ck_parent_names[] = {
1116         "dpll3_m3x2_ck",
1117 };
1118
1119 DEFINE_STRUCT_CLK_HW_OMAP(emu_core_alwon_ck, "dpll3_clkdm");
1120 DEFINE_STRUCT_CLK(emu_core_alwon_ck, emu_core_alwon_ck_parent_names,
1121                   core_l4_ick_ops);
1122
1123 static struct clk emu_mpu_alwon_ck;
1124
1125 static const char *emu_mpu_alwon_ck_parent_names[] = {
1126         "mpu_ck",
1127 };
1128
1129 DEFINE_STRUCT_CLK_HW_OMAP(emu_mpu_alwon_ck, NULL);
1130 DEFINE_STRUCT_CLK(emu_mpu_alwon_ck, emu_mpu_alwon_ck_parent_names, core_ck_ops);
1131
1132 static struct clk emu_per_alwon_ck;
1133
1134 static const char *emu_per_alwon_ck_parent_names[] = {
1135         "dpll4_m6x2_ck",
1136 };
1137
1138 DEFINE_STRUCT_CLK_HW_OMAP(emu_per_alwon_ck, "dpll4_clkdm");
1139 DEFINE_STRUCT_CLK(emu_per_alwon_ck, emu_per_alwon_ck_parent_names,
1140                   core_l4_ick_ops);
1141
1142 static const char *emu_src_ck_parent_names[] = {
1143         "sys_ck", "emu_core_alwon_ck", "emu_per_alwon_ck", "emu_mpu_alwon_ck",
1144 };
1145
1146 static const struct clksel_rate emu_src_sys_rates[] = {
1147         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1148         { .div = 0 },
1149 };
1150
1151 static const struct clksel_rate emu_src_core_rates[] = {
1152         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1153         { .div = 0 },
1154 };
1155
1156 static const struct clksel_rate emu_src_per_rates[] = {
1157         { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
1158         { .div = 0 },
1159 };
1160
1161 static const struct clksel_rate emu_src_mpu_rates[] = {
1162         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1163         { .div = 0 },
1164 };
1165
1166 static const struct clksel emu_src_clksel[] = {
1167         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
1168         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
1169         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
1170         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
1171         { .parent = NULL },
1172 };
1173
1174 static const struct clk_ops emu_src_ck_ops = {
1175         .init           = &omap2_init_clk_clkdm,
1176         .recalc_rate    = &omap2_clksel_recalc,
1177         .get_parent     = &omap2_clksel_find_parent_index,
1178         .set_parent     = &omap2_clksel_set_parent,
1179         .enable         = &omap2_clkops_enable_clkdm,
1180         .disable        = &omap2_clkops_disable_clkdm,
1181 };
1182
1183 static struct clk emu_src_ck;
1184
1185 static struct clk_hw_omap emu_src_ck_hw = {
1186         .hw = {
1187                 .clk = &emu_src_ck,
1188         },
1189         .clksel         = emu_src_clksel,
1190         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1191         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
1192         .clkdm_name     = "emu_clkdm",
1193 };
1194
1195 DEFINE_STRUCT_CLK(emu_src_ck, emu_src_ck_parent_names, emu_src_ck_ops);
1196
1197 DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
1198                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1199                    OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH,
1200                    CLK_DIVIDER_ONE_BASED, NULL);
1201
1202 static struct clk fac_ick;
1203
1204 static struct clk_hw_omap fac_ick_hw = {
1205         .hw = {
1206                 .clk = &fac_ick,
1207         },
1208         .ops            = &clkhwops_iclk_wait,
1209         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1210         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1211         .clkdm_name     = "core_l4_clkdm",
1212 };
1213
1214 DEFINE_STRUCT_CLK(fac_ick, aes2_ick_parent_names, aes2_ick_ops);
1215
1216 static struct clk fshostusb_fck;
1217
1218 static const char *fshostusb_fck_parent_names[] = {
1219         "core_48m_fck",
1220 };
1221
1222 static struct clk_hw_omap fshostusb_fck_hw = {
1223         .hw = {
1224                 .clk = &fshostusb_fck,
1225         },
1226         .ops            = &clkhwops_wait,
1227         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1228         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1229         .clkdm_name     = "core_l4_clkdm",
1230 };
1231
1232 DEFINE_STRUCT_CLK(fshostusb_fck, fshostusb_fck_parent_names, aes2_ick_ops);
1233
1234 static struct clk gfx_l3_ck;
1235
1236 static struct clk_hw_omap gfx_l3_ck_hw = {
1237         .hw = {
1238                 .clk = &gfx_l3_ck,
1239         },
1240         .ops            = &clkhwops_wait,
1241         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1242         .enable_bit     = OMAP_EN_GFX_SHIFT,
1243         .clkdm_name     = "gfx_3430es1_clkdm",
1244 };
1245
1246 DEFINE_STRUCT_CLK(gfx_l3_ck, core_l3_ick_parent_names, aes1_ick_ops);
1247
1248 DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick, 0x0,
1249                    OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1250                    OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH,
1251                    CLK_DIVIDER_ONE_BASED, NULL);
1252
1253 static struct clk gfx_cg1_ck;
1254
1255 static const char *gfx_cg1_ck_parent_names[] = {
1256         "gfx_l3_fck",
1257 };
1258
1259 static struct clk_hw_omap gfx_cg1_ck_hw = {
1260         .hw = {
1261                 .clk = &gfx_cg1_ck,
1262         },
1263         .ops            = &clkhwops_wait,
1264         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1265         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1266         .clkdm_name     = "gfx_3430es1_clkdm",
1267 };
1268
1269 DEFINE_STRUCT_CLK(gfx_cg1_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1270
1271 static struct clk gfx_cg2_ck;
1272
1273 static struct clk_hw_omap gfx_cg2_ck_hw = {
1274         .hw = {
1275                 .clk = &gfx_cg2_ck,
1276         },
1277         .ops            = &clkhwops_wait,
1278         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1279         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1280         .clkdm_name     = "gfx_3430es1_clkdm",
1281 };
1282
1283 DEFINE_STRUCT_CLK(gfx_cg2_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1284
1285 static struct clk gfx_l3_ick;
1286
1287 static const char *gfx_l3_ick_parent_names[] = {
1288         "gfx_l3_ck",
1289 };
1290
1291 DEFINE_STRUCT_CLK_HW_OMAP(gfx_l3_ick, "gfx_3430es1_clkdm");
1292 DEFINE_STRUCT_CLK(gfx_l3_ick, gfx_l3_ick_parent_names, core_l4_ick_ops);
1293
1294 static struct clk wkup_32k_fck;
1295
1296 static const char *wkup_32k_fck_parent_names[] = {
1297         "omap_32k_fck",
1298 };
1299
1300 DEFINE_STRUCT_CLK_HW_OMAP(wkup_32k_fck, "wkup_clkdm");
1301 DEFINE_STRUCT_CLK(wkup_32k_fck, wkup_32k_fck_parent_names, core_l4_ick_ops);
1302
1303 static struct clk gpio1_dbck;
1304
1305 static const char *gpio1_dbck_parent_names[] = {
1306         "wkup_32k_fck",
1307 };
1308
1309 static struct clk_hw_omap gpio1_dbck_hw = {
1310         .hw = {
1311                 .clk = &gpio1_dbck,
1312         },
1313         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1314         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
1315         .clkdm_name     = "wkup_clkdm",
1316 };
1317
1318 DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops);
1319
1320 static struct clk wkup_l4_ick;
1321
1322 DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm");
1323 DEFINE_STRUCT_CLK(wkup_l4_ick, dpll3_ck_parent_names, core_l4_ick_ops);
1324
1325 static struct clk gpio1_ick;
1326
1327 static const char *gpio1_ick_parent_names[] = {
1328         "wkup_l4_ick",
1329 };
1330
1331 static struct clk_hw_omap gpio1_ick_hw = {
1332         .hw = {
1333                 .clk = &gpio1_ick,
1334         },
1335         .ops            = &clkhwops_iclk_wait,
1336         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1337         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
1338         .clkdm_name     = "wkup_clkdm",
1339 };
1340
1341 DEFINE_STRUCT_CLK(gpio1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1342
1343 static struct clk per_32k_alwon_fck;
1344
1345 DEFINE_STRUCT_CLK_HW_OMAP(per_32k_alwon_fck, "per_clkdm");
1346 DEFINE_STRUCT_CLK(per_32k_alwon_fck, wkup_32k_fck_parent_names,
1347                   core_l4_ick_ops);
1348
1349 static struct clk gpio2_dbck;
1350
1351 static const char *gpio2_dbck_parent_names[] = {
1352         "per_32k_alwon_fck",
1353 };
1354
1355 static struct clk_hw_omap gpio2_dbck_hw = {
1356         .hw = {
1357                 .clk = &gpio2_dbck,
1358         },
1359         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1360         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
1361         .clkdm_name     = "per_clkdm",
1362 };
1363
1364 DEFINE_STRUCT_CLK(gpio2_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1365
1366 static struct clk per_l4_ick;
1367
1368 DEFINE_STRUCT_CLK_HW_OMAP(per_l4_ick, "per_clkdm");
1369 DEFINE_STRUCT_CLK(per_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
1370
1371 static struct clk gpio2_ick;
1372
1373 static const char *gpio2_ick_parent_names[] = {
1374         "per_l4_ick",
1375 };
1376
1377 static struct clk_hw_omap gpio2_ick_hw = {
1378         .hw = {
1379                 .clk = &gpio2_ick,
1380         },
1381         .ops            = &clkhwops_iclk_wait,
1382         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1383         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
1384         .clkdm_name     = "per_clkdm",
1385 };
1386
1387 DEFINE_STRUCT_CLK(gpio2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1388
1389 static struct clk gpio3_dbck;
1390
1391 static struct clk_hw_omap gpio3_dbck_hw = {
1392         .hw = {
1393                 .clk = &gpio3_dbck,
1394         },
1395         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1396         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
1397         .clkdm_name     = "per_clkdm",
1398 };
1399
1400 DEFINE_STRUCT_CLK(gpio3_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1401
1402 static struct clk gpio3_ick;
1403
1404 static struct clk_hw_omap gpio3_ick_hw = {
1405         .hw = {
1406                 .clk = &gpio3_ick,
1407         },
1408         .ops            = &clkhwops_iclk_wait,
1409         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1410         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
1411         .clkdm_name     = "per_clkdm",
1412 };
1413
1414 DEFINE_STRUCT_CLK(gpio3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1415
1416 static struct clk gpio4_dbck;
1417
1418 static struct clk_hw_omap gpio4_dbck_hw = {
1419         .hw = {
1420                 .clk = &gpio4_dbck,
1421         },
1422         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1423         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
1424         .clkdm_name     = "per_clkdm",
1425 };
1426
1427 DEFINE_STRUCT_CLK(gpio4_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1428
1429 static struct clk gpio4_ick;
1430
1431 static struct clk_hw_omap gpio4_ick_hw = {
1432         .hw = {
1433                 .clk = &gpio4_ick,
1434         },
1435         .ops            = &clkhwops_iclk_wait,
1436         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1437         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
1438         .clkdm_name     = "per_clkdm",
1439 };
1440
1441 DEFINE_STRUCT_CLK(gpio4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1442
1443 static struct clk gpio5_dbck;
1444
1445 static struct clk_hw_omap gpio5_dbck_hw = {
1446         .hw = {
1447                 .clk = &gpio5_dbck,
1448         },
1449         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1450         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
1451         .clkdm_name     = "per_clkdm",
1452 };
1453
1454 DEFINE_STRUCT_CLK(gpio5_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1455
1456 static struct clk gpio5_ick;
1457
1458 static struct clk_hw_omap gpio5_ick_hw = {
1459         .hw = {
1460                 .clk = &gpio5_ick,
1461         },
1462         .ops            = &clkhwops_iclk_wait,
1463         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1464         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
1465         .clkdm_name     = "per_clkdm",
1466 };
1467
1468 DEFINE_STRUCT_CLK(gpio5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1469
1470 static struct clk gpio6_dbck;
1471
1472 static struct clk_hw_omap gpio6_dbck_hw = {
1473         .hw = {
1474                 .clk = &gpio6_dbck,
1475         },
1476         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1477         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
1478         .clkdm_name     = "per_clkdm",
1479 };
1480
1481 DEFINE_STRUCT_CLK(gpio6_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1482
1483 static struct clk gpio6_ick;
1484
1485 static struct clk_hw_omap gpio6_ick_hw = {
1486         .hw = {
1487                 .clk = &gpio6_ick,
1488         },
1489         .ops            = &clkhwops_iclk_wait,
1490         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1491         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
1492         .clkdm_name     = "per_clkdm",
1493 };
1494
1495 DEFINE_STRUCT_CLK(gpio6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1496
1497 static struct clk gpmc_fck;
1498
1499 static struct clk_hw_omap gpmc_fck_hw = {
1500         .hw = {
1501                 .clk = &gpmc_fck,
1502         },
1503         .flags          = ENABLE_ON_INIT,
1504         .clkdm_name     = "core_l3_clkdm",
1505 };
1506
1507 DEFINE_STRUCT_CLK(gpmc_fck, ipss_ick_parent_names, core_l4_ick_ops);
1508
1509 static const struct clksel omap343x_gpt_clksel[] = {
1510         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1511         { .parent = &sys_ck, .rates = gpt_sys_rates },
1512         { .parent = NULL },
1513 };
1514
1515 static const char *gpt10_fck_parent_names[] = {
1516         "omap_32k_fck", "sys_ck",
1517 };
1518
1519 DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1520                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1521                          OMAP3430_CLKSEL_GPT10_MASK,
1522                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1523                          OMAP3430_EN_GPT10_SHIFT, &clkhwops_wait,
1524                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1525
1526 static struct clk gpt10_ick;
1527
1528 static struct clk_hw_omap gpt10_ick_hw = {
1529         .hw = {
1530                 .clk = &gpt10_ick,
1531         },
1532         .ops            = &clkhwops_iclk_wait,
1533         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1534         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1535         .clkdm_name     = "core_l4_clkdm",
1536 };
1537
1538 DEFINE_STRUCT_CLK(gpt10_ick, aes2_ick_parent_names, aes2_ick_ops);
1539
1540 DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1541                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1542                          OMAP3430_CLKSEL_GPT11_MASK,
1543                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1544                          OMAP3430_EN_GPT11_SHIFT, &clkhwops_wait,
1545                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1546
1547 static struct clk gpt11_ick;
1548
1549 static struct clk_hw_omap gpt11_ick_hw = {
1550         .hw = {
1551                 .clk = &gpt11_ick,
1552         },
1553         .ops            = &clkhwops_iclk_wait,
1554         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1555         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1556         .clkdm_name     = "core_l4_clkdm",
1557 };
1558
1559 DEFINE_STRUCT_CLK(gpt11_ick, aes2_ick_parent_names, aes2_ick_ops);
1560
1561 static struct clk gpt12_fck;
1562
1563 static const char *gpt12_fck_parent_names[] = {
1564         "secure_32k_fck",
1565 };
1566
1567 DEFINE_STRUCT_CLK_HW_OMAP(gpt12_fck, "wkup_clkdm");
1568 DEFINE_STRUCT_CLK(gpt12_fck, gpt12_fck_parent_names, core_l4_ick_ops);
1569
1570 static struct clk gpt12_ick;
1571
1572 static struct clk_hw_omap gpt12_ick_hw = {
1573         .hw = {
1574                 .clk = &gpt12_ick,
1575         },
1576         .ops            = &clkhwops_iclk_wait,
1577         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1578         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
1579         .clkdm_name     = "wkup_clkdm",
1580 };
1581
1582 DEFINE_STRUCT_CLK(gpt12_ick, gpio1_ick_parent_names, aes2_ick_ops);
1583
1584 DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "wkup_clkdm", omap343x_gpt_clksel,
1585                          OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1586                          OMAP3430_CLKSEL_GPT1_MASK,
1587                          OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1588                          OMAP3430_EN_GPT1_SHIFT, &clkhwops_wait,
1589                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1590
1591 static struct clk gpt1_ick;
1592
1593 static struct clk_hw_omap gpt1_ick_hw = {
1594         .hw = {
1595                 .clk = &gpt1_ick,
1596         },
1597         .ops            = &clkhwops_iclk_wait,
1598         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1599         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
1600         .clkdm_name     = "wkup_clkdm",
1601 };
1602
1603 DEFINE_STRUCT_CLK(gpt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1604
1605 DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "per_clkdm", omap343x_gpt_clksel,
1606                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1607                          OMAP3430_CLKSEL_GPT2_MASK,
1608                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1609                          OMAP3430_EN_GPT2_SHIFT, &clkhwops_wait,
1610                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1611
1612 static struct clk gpt2_ick;
1613
1614 static struct clk_hw_omap gpt2_ick_hw = {
1615         .hw = {
1616                 .clk = &gpt2_ick,
1617         },
1618         .ops            = &clkhwops_iclk_wait,
1619         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1620         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
1621         .clkdm_name     = "per_clkdm",
1622 };
1623
1624 DEFINE_STRUCT_CLK(gpt2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1625
1626 DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "per_clkdm", omap343x_gpt_clksel,
1627                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1628                          OMAP3430_CLKSEL_GPT3_MASK,
1629                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1630                          OMAP3430_EN_GPT3_SHIFT, &clkhwops_wait,
1631                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1632
1633 static struct clk gpt3_ick;
1634
1635 static struct clk_hw_omap gpt3_ick_hw = {
1636         .hw = {
1637                 .clk = &gpt3_ick,
1638         },
1639         .ops            = &clkhwops_iclk_wait,
1640         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1641         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
1642         .clkdm_name     = "per_clkdm",
1643 };
1644
1645 DEFINE_STRUCT_CLK(gpt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1646
1647 DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "per_clkdm", omap343x_gpt_clksel,
1648                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1649                          OMAP3430_CLKSEL_GPT4_MASK,
1650                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1651                          OMAP3430_EN_GPT4_SHIFT, &clkhwops_wait,
1652                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1653
1654 static struct clk gpt4_ick;
1655
1656 static struct clk_hw_omap gpt4_ick_hw = {
1657         .hw = {
1658                 .clk = &gpt4_ick,
1659         },
1660         .ops            = &clkhwops_iclk_wait,
1661         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1662         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
1663         .clkdm_name     = "per_clkdm",
1664 };
1665
1666 DEFINE_STRUCT_CLK(gpt4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1667
1668 DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "per_clkdm", omap343x_gpt_clksel,
1669                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1670                          OMAP3430_CLKSEL_GPT5_MASK,
1671                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1672                          OMAP3430_EN_GPT5_SHIFT, &clkhwops_wait,
1673                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1674
1675 static struct clk gpt5_ick;
1676
1677 static struct clk_hw_omap gpt5_ick_hw = {
1678         .hw = {
1679                 .clk = &gpt5_ick,
1680         },
1681         .ops            = &clkhwops_iclk_wait,
1682         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1683         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
1684         .clkdm_name     = "per_clkdm",
1685 };
1686
1687 DEFINE_STRUCT_CLK(gpt5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1688
1689 DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "per_clkdm", omap343x_gpt_clksel,
1690                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1691                          OMAP3430_CLKSEL_GPT6_MASK,
1692                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1693                          OMAP3430_EN_GPT6_SHIFT, &clkhwops_wait,
1694                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1695
1696 static struct clk gpt6_ick;
1697
1698 static struct clk_hw_omap gpt6_ick_hw = {
1699         .hw = {
1700                 .clk = &gpt6_ick,
1701         },
1702         .ops            = &clkhwops_iclk_wait,
1703         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1704         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
1705         .clkdm_name     = "per_clkdm",
1706 };
1707
1708 DEFINE_STRUCT_CLK(gpt6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1709
1710 DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "per_clkdm", omap343x_gpt_clksel,
1711                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1712                          OMAP3430_CLKSEL_GPT7_MASK,
1713                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1714                          OMAP3430_EN_GPT7_SHIFT, &clkhwops_wait,
1715                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1716
1717 static struct clk gpt7_ick;
1718
1719 static struct clk_hw_omap gpt7_ick_hw = {
1720         .hw = {
1721                 .clk = &gpt7_ick,
1722         },
1723         .ops            = &clkhwops_iclk_wait,
1724         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1725         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
1726         .clkdm_name     = "per_clkdm",
1727 };
1728
1729 DEFINE_STRUCT_CLK(gpt7_ick, gpio2_ick_parent_names, aes2_ick_ops);
1730
1731 DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "per_clkdm", omap343x_gpt_clksel,
1732                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1733                          OMAP3430_CLKSEL_GPT8_MASK,
1734                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1735                          OMAP3430_EN_GPT8_SHIFT, &clkhwops_wait,
1736                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1737
1738 static struct clk gpt8_ick;
1739
1740 static struct clk_hw_omap gpt8_ick_hw = {
1741         .hw = {
1742                 .clk = &gpt8_ick,
1743         },
1744         .ops            = &clkhwops_iclk_wait,
1745         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1746         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
1747         .clkdm_name     = "per_clkdm",
1748 };
1749
1750 DEFINE_STRUCT_CLK(gpt8_ick, gpio2_ick_parent_names, aes2_ick_ops);
1751
1752 DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "per_clkdm", omap343x_gpt_clksel,
1753                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1754                          OMAP3430_CLKSEL_GPT9_MASK,
1755                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1756                          OMAP3430_EN_GPT9_SHIFT, &clkhwops_wait,
1757                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1758
1759 static struct clk gpt9_ick;
1760
1761 static struct clk_hw_omap gpt9_ick_hw = {
1762         .hw = {
1763                 .clk = &gpt9_ick,
1764         },
1765         .ops            = &clkhwops_iclk_wait,
1766         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1767         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
1768         .clkdm_name     = "per_clkdm",
1769 };
1770
1771 DEFINE_STRUCT_CLK(gpt9_ick, gpio2_ick_parent_names, aes2_ick_ops);
1772
1773 static struct clk hdq_fck;
1774
1775 static const char *hdq_fck_parent_names[] = {
1776         "core_12m_fck",
1777 };
1778
1779 static struct clk_hw_omap hdq_fck_hw = {
1780         .hw = {
1781                 .clk = &hdq_fck,
1782         },
1783         .ops            = &clkhwops_wait,
1784         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1785         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1786         .clkdm_name     = "core_l4_clkdm",
1787 };
1788
1789 DEFINE_STRUCT_CLK(hdq_fck, hdq_fck_parent_names, aes2_ick_ops);
1790
1791 static struct clk hdq_ick;
1792
1793 static struct clk_hw_omap hdq_ick_hw = {
1794         .hw = {
1795                 .clk = &hdq_ick,
1796         },
1797         .ops            = &clkhwops_iclk_wait,
1798         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1799         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1800         .clkdm_name     = "core_l4_clkdm",
1801 };
1802
1803 DEFINE_STRUCT_CLK(hdq_ick, aes2_ick_parent_names, aes2_ick_ops);
1804
1805 static struct clk hecc_ck;
1806
1807 static struct clk_hw_omap hecc_ck_hw = {
1808         .hw = {
1809                 .clk = &hecc_ck,
1810         },
1811         .ops            = &clkhwops_am35xx_ipss_module_wait,
1812         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1813         .enable_bit     = AM35XX_HECC_VBUSP_CLK_SHIFT,
1814         .clkdm_name     = "core_l3_clkdm",
1815 };
1816
1817 DEFINE_STRUCT_CLK(hecc_ck, dpll3_ck_parent_names, aes2_ick_ops);
1818
1819 static struct clk hsotgusb_fck_am35xx;
1820
1821 static struct clk_hw_omap hsotgusb_fck_am35xx_hw = {
1822         .hw = {
1823                 .clk = &hsotgusb_fck_am35xx,
1824         },
1825         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1826         .enable_bit     = AM35XX_USBOTG_FCLK_SHIFT,
1827         .clkdm_name     = "core_l3_clkdm",
1828 };
1829
1830 DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, dpll3_ck_parent_names, aes2_ick_ops);
1831
1832 static struct clk hsotgusb_ick_3430es1;
1833
1834 static struct clk_hw_omap hsotgusb_ick_3430es1_hw = {
1835         .hw = {
1836                 .clk = &hsotgusb_ick_3430es1,
1837         },
1838         .ops            = &clkhwops_iclk,
1839         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1840         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1841         .clkdm_name     = "core_l3_clkdm",
1842 };
1843
1844 DEFINE_STRUCT_CLK(hsotgusb_ick_3430es1, ipss_ick_parent_names, aes2_ick_ops);
1845
1846 static struct clk hsotgusb_ick_3430es2;
1847
1848 static struct clk_hw_omap hsotgusb_ick_3430es2_hw = {
1849         .hw = {
1850                 .clk = &hsotgusb_ick_3430es2,
1851         },
1852         .ops            = &clkhwops_omap3430es2_iclk_hsotgusb_wait,
1853         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1854         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1855         .clkdm_name     = "core_l3_clkdm",
1856 };
1857
1858 DEFINE_STRUCT_CLK(hsotgusb_ick_3430es2, ipss_ick_parent_names, aes2_ick_ops);
1859
1860 static struct clk hsotgusb_ick_am35xx;
1861
1862 static struct clk_hw_omap hsotgusb_ick_am35xx_hw = {
1863         .hw = {
1864                 .clk = &hsotgusb_ick_am35xx,
1865         },
1866         .ops            = &clkhwops_am35xx_ipss_module_wait,
1867         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1868         .enable_bit     = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
1869         .clkdm_name     = "core_l3_clkdm",
1870 };
1871
1872 DEFINE_STRUCT_CLK(hsotgusb_ick_am35xx, emac_ick_parent_names, aes2_ick_ops);
1873
1874 static struct clk i2c1_fck;
1875
1876 static struct clk_hw_omap i2c1_fck_hw = {
1877         .hw = {
1878                 .clk = &i2c1_fck,
1879         },
1880         .ops            = &clkhwops_wait,
1881         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1882         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1883         .clkdm_name     = "core_l4_clkdm",
1884 };
1885
1886 DEFINE_STRUCT_CLK(i2c1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1887
1888 static struct clk i2c1_ick;
1889
1890 static struct clk_hw_omap i2c1_ick_hw = {
1891         .hw = {
1892                 .clk = &i2c1_ick,
1893         },
1894         .ops            = &clkhwops_iclk_wait,
1895         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1896         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1897         .clkdm_name     = "core_l4_clkdm",
1898 };
1899
1900 DEFINE_STRUCT_CLK(i2c1_ick, aes2_ick_parent_names, aes2_ick_ops);
1901
1902 static struct clk i2c2_fck;
1903
1904 static struct clk_hw_omap i2c2_fck_hw = {
1905         .hw = {
1906                 .clk = &i2c2_fck,
1907         },
1908         .ops            = &clkhwops_wait,
1909         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1910         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1911         .clkdm_name     = "core_l4_clkdm",
1912 };
1913
1914 DEFINE_STRUCT_CLK(i2c2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1915
1916 static struct clk i2c2_ick;
1917
1918 static struct clk_hw_omap i2c2_ick_hw = {
1919         .hw = {
1920                 .clk = &i2c2_ick,
1921         },
1922         .ops            = &clkhwops_iclk_wait,
1923         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1924         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1925         .clkdm_name     = "core_l4_clkdm",
1926 };
1927
1928 DEFINE_STRUCT_CLK(i2c2_ick, aes2_ick_parent_names, aes2_ick_ops);
1929
1930 static struct clk i2c3_fck;
1931
1932 static struct clk_hw_omap i2c3_fck_hw = {
1933         .hw = {
1934                 .clk = &i2c3_fck,
1935         },
1936         .ops            = &clkhwops_wait,
1937         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1938         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1939         .clkdm_name     = "core_l4_clkdm",
1940 };
1941
1942 DEFINE_STRUCT_CLK(i2c3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1943
1944 static struct clk i2c3_ick;
1945
1946 static struct clk_hw_omap i2c3_ick_hw = {
1947         .hw = {
1948                 .clk = &i2c3_ick,
1949         },
1950         .ops            = &clkhwops_iclk_wait,
1951         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1952         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1953         .clkdm_name     = "core_l4_clkdm",
1954 };
1955
1956 DEFINE_STRUCT_CLK(i2c3_ick, aes2_ick_parent_names, aes2_ick_ops);
1957
1958 static struct clk icr_ick;
1959
1960 static struct clk_hw_omap icr_ick_hw = {
1961         .hw = {
1962                 .clk = &icr_ick,
1963         },
1964         .ops            = &clkhwops_iclk_wait,
1965         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1966         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1967         .clkdm_name     = "core_l4_clkdm",
1968 };
1969
1970 DEFINE_STRUCT_CLK(icr_ick, aes2_ick_parent_names, aes2_ick_ops);
1971
1972 static struct clk iva2_ck;
1973
1974 static const char *iva2_ck_parent_names[] = {
1975         "dpll2_m2_ck",
1976 };
1977
1978 static struct clk_hw_omap iva2_ck_hw = {
1979         .hw = {
1980                 .clk = &iva2_ck,
1981         },
1982         .ops            = &clkhwops_wait,
1983         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1984         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1985         .clkdm_name     = "iva2_clkdm",
1986 };
1987
1988 DEFINE_STRUCT_CLK(iva2_ck, iva2_ck_parent_names, aes2_ick_ops);
1989
1990 static struct clk mad2d_ick;
1991
1992 static struct clk_hw_omap mad2d_ick_hw = {
1993         .hw = {
1994                 .clk = &mad2d_ick,
1995         },
1996         .ops            = &clkhwops_iclk_wait,
1997         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1998         .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
1999         .clkdm_name     = "d2d_clkdm",
2000 };
2001
2002 DEFINE_STRUCT_CLK(mad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
2003
2004 static struct clk mailboxes_ick;
2005
2006 static struct clk_hw_omap mailboxes_ick_hw = {
2007         .hw = {
2008                 .clk = &mailboxes_ick,
2009         },
2010         .ops            = &clkhwops_iclk_wait,
2011         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2012         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2013         .clkdm_name     = "core_l4_clkdm",
2014 };
2015
2016 DEFINE_STRUCT_CLK(mailboxes_ick, aes2_ick_parent_names, aes2_ick_ops);
2017
2018 static const struct clksel_rate common_mcbsp_96m_rates[] = {
2019         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2020         { .div = 0 }
2021 };
2022
2023 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
2024         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2025         { .div = 0 }
2026 };
2027
2028 static const struct clksel mcbsp_15_clksel[] = {
2029         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2030         { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2031         { .parent = NULL },
2032 };
2033
2034 static const char *mcbsp1_fck_parent_names[] = {
2035         "core_96m_fck", "mcbsp_clks",
2036 };
2037
2038 DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_15_clksel,
2039                          OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2040                          OMAP2_MCBSP1_CLKS_MASK,
2041                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2042                          OMAP3430_EN_MCBSP1_SHIFT, &clkhwops_wait,
2043                          mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2044
2045 static struct clk mcbsp1_ick;
2046
2047 static struct clk_hw_omap mcbsp1_ick_hw = {
2048         .hw = {
2049                 .clk = &mcbsp1_ick,
2050         },
2051         .ops            = &clkhwops_iclk_wait,
2052         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2053         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2054         .clkdm_name     = "core_l4_clkdm",
2055 };
2056
2057 DEFINE_STRUCT_CLK(mcbsp1_ick, aes2_ick_parent_names, aes2_ick_ops);
2058
2059 static struct clk per_96m_fck;
2060
2061 DEFINE_STRUCT_CLK_HW_OMAP(per_96m_fck, "per_clkdm");
2062 DEFINE_STRUCT_CLK(per_96m_fck, cm_96m_fck_parent_names, core_l4_ick_ops);
2063
2064 static const struct clksel mcbsp_234_clksel[] = {
2065         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2066         { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2067         { .parent = NULL },
2068 };
2069
2070 static const char *mcbsp2_fck_parent_names[] = {
2071         "per_96m_fck", "mcbsp_clks",
2072 };
2073
2074 DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "per_clkdm", mcbsp_234_clksel,
2075                          OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2076                          OMAP2_MCBSP2_CLKS_MASK,
2077                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2078                          OMAP3430_EN_MCBSP2_SHIFT, &clkhwops_wait,
2079                          mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2080
2081 static struct clk mcbsp2_ick;
2082
2083 static struct clk_hw_omap mcbsp2_ick_hw = {
2084         .hw = {
2085                 .clk = &mcbsp2_ick,
2086         },
2087         .ops            = &clkhwops_iclk_wait,
2088         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2089         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2090         .clkdm_name     = "per_clkdm",
2091 };
2092
2093 DEFINE_STRUCT_CLK(mcbsp2_ick, gpio2_ick_parent_names, aes2_ick_ops);
2094
2095 DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "per_clkdm", mcbsp_234_clksel,
2096                          OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2097                          OMAP2_MCBSP3_CLKS_MASK,
2098                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2099                          OMAP3430_EN_MCBSP3_SHIFT, &clkhwops_wait,
2100                          mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2101
2102 static struct clk mcbsp3_ick;
2103
2104 static struct clk_hw_omap mcbsp3_ick_hw = {
2105         .hw = {
2106                 .clk = &mcbsp3_ick,
2107         },
2108         .ops            = &clkhwops_iclk_wait,
2109         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2110         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2111         .clkdm_name     = "per_clkdm",
2112 };
2113
2114 DEFINE_STRUCT_CLK(mcbsp3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2115
2116 DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "per_clkdm", mcbsp_234_clksel,
2117                          OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2118                          OMAP2_MCBSP4_CLKS_MASK,
2119                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2120                          OMAP3430_EN_MCBSP4_SHIFT, &clkhwops_wait,
2121                          mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2122
2123 static struct clk mcbsp4_ick;
2124
2125 static struct clk_hw_omap mcbsp4_ick_hw = {
2126         .hw = {
2127                 .clk = &mcbsp4_ick,
2128         },
2129         .ops            = &clkhwops_iclk_wait,
2130         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2131         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2132         .clkdm_name     = "per_clkdm",
2133 };
2134
2135 DEFINE_STRUCT_CLK(mcbsp4_ick, gpio2_ick_parent_names, aes2_ick_ops);
2136
2137 DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_15_clksel,
2138                          OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2139                          OMAP2_MCBSP5_CLKS_MASK,
2140                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2141                          OMAP3430_EN_MCBSP5_SHIFT, &clkhwops_wait,
2142                          mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2143
2144 static struct clk mcbsp5_ick;
2145
2146 static struct clk_hw_omap mcbsp5_ick_hw = {
2147         .hw = {
2148                 .clk = &mcbsp5_ick,
2149         },
2150         .ops            = &clkhwops_iclk_wait,
2151         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2152         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2153         .clkdm_name     = "core_l4_clkdm",
2154 };
2155
2156 DEFINE_STRUCT_CLK(mcbsp5_ick, aes2_ick_parent_names, aes2_ick_ops);
2157
2158 static struct clk mcspi1_fck;
2159
2160 static struct clk_hw_omap mcspi1_fck_hw = {
2161         .hw = {
2162                 .clk = &mcspi1_fck,
2163         },
2164         .ops            = &clkhwops_wait,
2165         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2166         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
2167         .clkdm_name     = "core_l4_clkdm",
2168 };
2169
2170 DEFINE_STRUCT_CLK(mcspi1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2171
2172 static struct clk mcspi1_ick;
2173
2174 static struct clk_hw_omap mcspi1_ick_hw = {
2175         .hw = {
2176                 .clk = &mcspi1_ick,
2177         },
2178         .ops            = &clkhwops_iclk_wait,
2179         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2180         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
2181         .clkdm_name     = "core_l4_clkdm",
2182 };
2183
2184 DEFINE_STRUCT_CLK(mcspi1_ick, aes2_ick_parent_names, aes2_ick_ops);
2185
2186 static struct clk mcspi2_fck;
2187
2188 static struct clk_hw_omap mcspi2_fck_hw = {
2189         .hw = {
2190                 .clk = &mcspi2_fck,
2191         },
2192         .ops            = &clkhwops_wait,
2193         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2194         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
2195         .clkdm_name     = "core_l4_clkdm",
2196 };
2197
2198 DEFINE_STRUCT_CLK(mcspi2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2199
2200 static struct clk mcspi2_ick;
2201
2202 static struct clk_hw_omap mcspi2_ick_hw = {
2203         .hw = {
2204                 .clk = &mcspi2_ick,
2205         },
2206         .ops            = &clkhwops_iclk_wait,
2207         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2208         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
2209         .clkdm_name     = "core_l4_clkdm",
2210 };
2211
2212 DEFINE_STRUCT_CLK(mcspi2_ick, aes2_ick_parent_names, aes2_ick_ops);
2213
2214 static struct clk mcspi3_fck;
2215
2216 static struct clk_hw_omap mcspi3_fck_hw = {
2217         .hw = {
2218                 .clk = &mcspi3_fck,
2219         },
2220         .ops            = &clkhwops_wait,
2221         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2222         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
2223         .clkdm_name     = "core_l4_clkdm",
2224 };
2225
2226 DEFINE_STRUCT_CLK(mcspi3_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2227
2228 static struct clk mcspi3_ick;
2229
2230 static struct clk_hw_omap mcspi3_ick_hw = {
2231         .hw = {
2232                 .clk = &mcspi3_ick,
2233         },
2234         .ops            = &clkhwops_iclk_wait,
2235         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2236         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
2237         .clkdm_name     = "core_l4_clkdm",
2238 };
2239
2240 DEFINE_STRUCT_CLK(mcspi3_ick, aes2_ick_parent_names, aes2_ick_ops);
2241
2242 static struct clk mcspi4_fck;
2243
2244 static struct clk_hw_omap mcspi4_fck_hw = {
2245         .hw = {
2246                 .clk = &mcspi4_fck,
2247         },
2248         .ops            = &clkhwops_wait,
2249         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2250         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
2251         .clkdm_name     = "core_l4_clkdm",
2252 };
2253
2254 DEFINE_STRUCT_CLK(mcspi4_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2255
2256 static struct clk mcspi4_ick;
2257
2258 static struct clk_hw_omap mcspi4_ick_hw = {
2259         .hw = {
2260                 .clk = &mcspi4_ick,
2261         },
2262         .ops            = &clkhwops_iclk_wait,
2263         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2264         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
2265         .clkdm_name     = "core_l4_clkdm",
2266 };
2267
2268 DEFINE_STRUCT_CLK(mcspi4_ick, aes2_ick_parent_names, aes2_ick_ops);
2269
2270 static struct clk mmchs1_fck;
2271
2272 static struct clk_hw_omap mmchs1_fck_hw = {
2273         .hw = {
2274                 .clk = &mmchs1_fck,
2275         },
2276         .ops            = &clkhwops_wait,
2277         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2278         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
2279         .clkdm_name     = "core_l4_clkdm",
2280 };
2281
2282 DEFINE_STRUCT_CLK(mmchs1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2283
2284 static struct clk mmchs1_ick;
2285
2286 static struct clk_hw_omap mmchs1_ick_hw = {
2287         .hw = {
2288                 .clk = &mmchs1_ick,
2289         },
2290         .ops            = &clkhwops_iclk_wait,
2291         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2292         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
2293         .clkdm_name     = "core_l4_clkdm",
2294 };
2295
2296 DEFINE_STRUCT_CLK(mmchs1_ick, aes2_ick_parent_names, aes2_ick_ops);
2297
2298 static struct clk mmchs2_fck;
2299
2300 static struct clk_hw_omap mmchs2_fck_hw = {
2301         .hw = {
2302                 .clk = &mmchs2_fck,
2303         },
2304         .ops            = &clkhwops_wait,
2305         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2306         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
2307         .clkdm_name     = "core_l4_clkdm",
2308 };
2309
2310 DEFINE_STRUCT_CLK(mmchs2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2311
2312 static struct clk mmchs2_ick;
2313
2314 static struct clk_hw_omap mmchs2_ick_hw = {
2315         .hw = {
2316                 .clk = &mmchs2_ick,
2317         },
2318         .ops            = &clkhwops_iclk_wait,
2319         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2320         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
2321         .clkdm_name     = "core_l4_clkdm",
2322 };
2323
2324 DEFINE_STRUCT_CLK(mmchs2_ick, aes2_ick_parent_names, aes2_ick_ops);
2325
2326 static struct clk mmchs3_fck;
2327
2328 static struct clk_hw_omap mmchs3_fck_hw = {
2329         .hw = {
2330                 .clk = &mmchs3_fck,
2331         },
2332         .ops            = &clkhwops_wait,
2333         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2334         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
2335         .clkdm_name     = "core_l4_clkdm",
2336 };
2337
2338 DEFINE_STRUCT_CLK(mmchs3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2339
2340 static struct clk mmchs3_ick;
2341
2342 static struct clk_hw_omap mmchs3_ick_hw = {
2343         .hw = {
2344                 .clk = &mmchs3_ick,
2345         },
2346         .ops            = &clkhwops_iclk_wait,
2347         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2348         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
2349         .clkdm_name     = "core_l4_clkdm",
2350 };
2351
2352 DEFINE_STRUCT_CLK(mmchs3_ick, aes2_ick_parent_names, aes2_ick_ops);
2353
2354 static struct clk modem_fck;
2355
2356 static struct clk_hw_omap modem_fck_hw = {
2357         .hw = {
2358                 .clk = &modem_fck,
2359         },
2360         .ops            = &clkhwops_iclk_wait,
2361         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2362         .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
2363         .clkdm_name     = "d2d_clkdm",
2364 };
2365
2366 DEFINE_STRUCT_CLK(modem_fck, dpll3_ck_parent_names, aes2_ick_ops);
2367
2368 static struct clk mspro_fck;
2369
2370 static struct clk_hw_omap mspro_fck_hw = {
2371         .hw = {
2372                 .clk = &mspro_fck,
2373         },
2374         .ops            = &clkhwops_wait,
2375         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2376         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
2377         .clkdm_name     = "core_l4_clkdm",
2378 };
2379
2380 DEFINE_STRUCT_CLK(mspro_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2381
2382 static struct clk mspro_ick;
2383
2384 static struct clk_hw_omap mspro_ick_hw = {
2385         .hw = {
2386                 .clk = &mspro_ick,
2387         },
2388         .ops            = &clkhwops_iclk_wait,
2389         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2390         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
2391         .clkdm_name     = "core_l4_clkdm",
2392 };
2393
2394 DEFINE_STRUCT_CLK(mspro_ick, aes2_ick_parent_names, aes2_ick_ops);
2395
2396 static struct clk omap_192m_alwon_fck;
2397
2398 DEFINE_STRUCT_CLK_HW_OMAP(omap_192m_alwon_fck, NULL);
2399 DEFINE_STRUCT_CLK(omap_192m_alwon_fck, omap_96m_alwon_fck_parent_names,
2400                   core_ck_ops);
2401
2402 static struct clk omap_32ksync_ick;
2403
2404 static struct clk_hw_omap omap_32ksync_ick_hw = {
2405         .hw = {
2406                 .clk = &omap_32ksync_ick,
2407         },
2408         .ops            = &clkhwops_iclk_wait,
2409         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2410         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2411         .clkdm_name     = "wkup_clkdm",
2412 };
2413
2414 DEFINE_STRUCT_CLK(omap_32ksync_ick, gpio1_ick_parent_names, aes2_ick_ops);
2415
2416 static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
2417         { .div = 1, .val = 1, .flags = RATE_IN_36XX },
2418         { .div = 2, .val = 2, .flags = RATE_IN_36XX },
2419         { .div = 0 }
2420 };
2421
2422 static const struct clksel omap_96m_alwon_fck_clksel[] = {
2423         { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
2424         { .parent = NULL }
2425 };
2426
2427 static struct clk omap_96m_alwon_fck_3630;
2428
2429 static const char *omap_96m_alwon_fck_3630_parent_names[] = {
2430         "omap_192m_alwon_fck",
2431 };
2432
2433 static const struct clk_ops omap_96m_alwon_fck_3630_ops = {
2434         .set_rate       = &omap2_clksel_set_rate,
2435         .recalc_rate    = &omap2_clksel_recalc,
2436         .round_rate     = &omap2_clksel_round_rate,
2437 };
2438
2439 static struct clk_hw_omap omap_96m_alwon_fck_3630_hw = {
2440         .hw = {
2441                 .clk = &omap_96m_alwon_fck_3630,
2442         },
2443         .clksel         = omap_96m_alwon_fck_clksel,
2444         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2445         .clksel_mask    = OMAP3630_CLKSEL_96M_MASK,
2446 };
2447
2448 static struct clk omap_96m_alwon_fck_3630 = {
2449         .name   = "omap_96m_alwon_fck",
2450         .hw     = &omap_96m_alwon_fck_3630_hw.hw,
2451         .parent_names   = omap_96m_alwon_fck_3630_parent_names,
2452         .num_parents    = ARRAY_SIZE(omap_96m_alwon_fck_3630_parent_names),
2453         .ops    = &omap_96m_alwon_fck_3630_ops,
2454 };
2455
2456 static struct clk omapctrl_ick;
2457
2458 static struct clk_hw_omap omapctrl_ick_hw = {
2459         .hw = {
2460                 .clk = &omapctrl_ick,
2461         },
2462         .ops            = &clkhwops_iclk_wait,
2463         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2464         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2465         .flags          = ENABLE_ON_INIT,
2466         .clkdm_name     = "core_l4_clkdm",
2467 };
2468
2469 DEFINE_STRUCT_CLK(omapctrl_ick, aes2_ick_parent_names, aes2_ick_ops);
2470
2471 DEFINE_CLK_DIVIDER(pclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
2472                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2473                    OMAP3430_CLKSEL_PCLK_SHIFT, OMAP3430_CLKSEL_PCLK_WIDTH,
2474                    CLK_DIVIDER_ONE_BASED, NULL);
2475
2476 DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck, 0x0,
2477                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2478                    OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH,
2479                    CLK_DIVIDER_ONE_BASED, NULL);
2480
2481 static struct clk per_48m_fck;
2482
2483 DEFINE_STRUCT_CLK_HW_OMAP(per_48m_fck, "per_clkdm");
2484 DEFINE_STRUCT_CLK(per_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
2485
2486 static struct clk security_l3_ick;
2487
2488 DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick, NULL);
2489 DEFINE_STRUCT_CLK(security_l3_ick, core_l3_ick_parent_names, core_ck_ops);
2490
2491 static struct clk pka_ick;
2492
2493 static const char *pka_ick_parent_names[] = {
2494         "security_l3_ick",
2495 };
2496
2497 static struct clk_hw_omap pka_ick_hw = {
2498         .hw = {
2499                 .clk = &pka_ick,
2500         },
2501         .ops            = &clkhwops_iclk_wait,
2502         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2503         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
2504 };
2505
2506 DEFINE_STRUCT_CLK(pka_ick, pka_ick_parent_names, aes1_ick_ops);
2507
2508 DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick, 0x0,
2509                    OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2510                    OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH,
2511                    CLK_DIVIDER_ONE_BASED, NULL);
2512
2513 static struct clk rng_ick;
2514
2515 static struct clk_hw_omap rng_ick_hw = {
2516         .hw = {
2517                 .clk = &rng_ick,
2518         },
2519         .ops            = &clkhwops_iclk_wait,
2520         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2521         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2522 };
2523
2524 DEFINE_STRUCT_CLK(rng_ick, aes1_ick_parent_names, aes1_ick_ops);
2525
2526 static struct clk sad2d_ick;
2527
2528 static struct clk_hw_omap sad2d_ick_hw = {
2529         .hw = {
2530                 .clk = &sad2d_ick,
2531         },
2532         .ops            = &clkhwops_iclk_wait,
2533         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2534         .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
2535         .clkdm_name     = "d2d_clkdm",
2536 };
2537
2538 DEFINE_STRUCT_CLK(sad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
2539
2540 static struct clk sdrc_ick;
2541
2542 static struct clk_hw_omap sdrc_ick_hw = {
2543         .hw = {
2544                 .clk = &sdrc_ick,
2545         },
2546         .ops            = &clkhwops_wait,
2547         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2548         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
2549         .flags          = ENABLE_ON_INIT,
2550         .clkdm_name     = "core_l3_clkdm",
2551 };
2552
2553 DEFINE_STRUCT_CLK(sdrc_ick, ipss_ick_parent_names, aes2_ick_ops);
2554
2555 static const struct clksel_rate sgx_core_rates[] = {
2556         { .div = 2, .val = 5, .flags = RATE_IN_36XX },
2557         { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
2558         { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
2559         { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
2560         { .div = 0 }
2561 };
2562
2563 static const struct clksel_rate sgx_96m_rates[] = {
2564         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2565         { .div = 0 }
2566 };
2567
2568 static const struct clksel_rate sgx_192m_rates[] = {
2569         { .div = 1, .val = 4, .flags = RATE_IN_36XX },
2570         { .div = 0 }
2571 };
2572
2573 static const struct clksel_rate sgx_corex2_rates[] = {
2574         { .div = 3, .val = 6, .flags = RATE_IN_36XX },
2575         { .div = 5, .val = 7, .flags = RATE_IN_36XX },
2576         { .div = 0 }
2577 };
2578
2579 static const struct clksel sgx_clksel[] = {
2580         { .parent = &core_ck, .rates = sgx_core_rates },
2581         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
2582         { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
2583         { .parent = &corex2_fck, .rates = sgx_corex2_rates },
2584         { .parent = NULL },
2585 };
2586
2587 static const char *sgx_fck_parent_names[] = {
2588         "core_ck", "cm_96m_fck", "omap_192m_alwon_fck", "corex2_fck",
2589 };
2590
2591 static struct clk sgx_fck;
2592
2593 static const struct clk_ops sgx_fck_ops = {
2594         .init           = &omap2_init_clk_clkdm,
2595         .enable         = &omap2_dflt_clk_enable,
2596         .disable        = &omap2_dflt_clk_disable,
2597         .is_enabled     = &omap2_dflt_clk_is_enabled,
2598         .recalc_rate    = &omap2_clksel_recalc,
2599         .set_rate       = &omap2_clksel_set_rate,
2600         .round_rate     = &omap2_clksel_round_rate,
2601         .get_parent     = &omap2_clksel_find_parent_index,
2602         .set_parent     = &omap2_clksel_set_parent,
2603 };
2604
2605 DEFINE_CLK_OMAP_MUX_GATE(sgx_fck, "sgx_clkdm", sgx_clksel,
2606                          OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
2607                          OMAP3430ES2_CLKSEL_SGX_MASK,
2608                          OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
2609                          OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
2610                          &clkhwops_wait, sgx_fck_parent_names, sgx_fck_ops);
2611
2612 static struct clk sgx_ick;
2613
2614 static struct clk_hw_omap sgx_ick_hw = {
2615         .hw = {
2616                 .clk = &sgx_ick,
2617         },
2618         .ops            = &clkhwops_wait,
2619         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
2620         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
2621         .clkdm_name     = "sgx_clkdm",
2622 };
2623
2624 DEFINE_STRUCT_CLK(sgx_ick, core_l3_ick_parent_names, aes2_ick_ops);
2625
2626 static struct clk sha11_ick;
2627
2628 static struct clk_hw_omap sha11_ick_hw = {
2629         .hw = {
2630                 .clk = &sha11_ick,
2631         },
2632         .ops            = &clkhwops_iclk_wait,
2633         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2634         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2635 };
2636
2637 DEFINE_STRUCT_CLK(sha11_ick, aes1_ick_parent_names, aes1_ick_ops);
2638
2639 static struct clk sha12_ick;
2640
2641 static struct clk_hw_omap sha12_ick_hw = {
2642         .hw = {
2643                 .clk = &sha12_ick,
2644         },
2645         .ops            = &clkhwops_iclk_wait,
2646         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2647         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
2648         .clkdm_name     = "core_l4_clkdm",
2649 };
2650
2651 DEFINE_STRUCT_CLK(sha12_ick, aes2_ick_parent_names, aes2_ick_ops);
2652
2653 static struct clk sr1_fck;
2654
2655 static struct clk_hw_omap sr1_fck_hw = {
2656         .hw = {
2657                 .clk = &sr1_fck,
2658         },
2659         .ops            = &clkhwops_wait,
2660         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2661         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2662         .clkdm_name     = "wkup_clkdm",
2663 };
2664
2665 DEFINE_STRUCT_CLK(sr1_fck, dpll3_ck_parent_names, aes2_ick_ops);
2666
2667 static struct clk sr2_fck;
2668
2669 static struct clk_hw_omap sr2_fck_hw = {
2670         .hw = {
2671                 .clk = &sr2_fck,
2672         },
2673         .ops            = &clkhwops_wait,
2674         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2675         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
2676         .clkdm_name     = "wkup_clkdm",
2677 };
2678
2679 DEFINE_STRUCT_CLK(sr2_fck, dpll3_ck_parent_names, aes2_ick_ops);
2680
2681 static struct clk sr_l4_ick;
2682
2683 DEFINE_STRUCT_CLK_HW_OMAP(sr_l4_ick, "core_l4_clkdm");
2684 DEFINE_STRUCT_CLK(sr_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2685
2686 static struct clk ssi_l4_ick;
2687
2688 DEFINE_STRUCT_CLK_HW_OMAP(ssi_l4_ick, "core_l4_clkdm");
2689 DEFINE_STRUCT_CLK(ssi_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2690
2691 static struct clk ssi_ick_3430es1;
2692
2693 static const char *ssi_ick_3430es1_parent_names[] = {
2694         "ssi_l4_ick",
2695 };
2696
2697 static struct clk_hw_omap ssi_ick_3430es1_hw = {
2698         .hw = {
2699                 .clk = &ssi_ick_3430es1,
2700         },
2701         .ops            = &clkhwops_iclk,
2702         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2703         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2704         .clkdm_name     = "core_l4_clkdm",
2705 };
2706
2707 DEFINE_STRUCT_CLK(ssi_ick_3430es1, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2708
2709 static struct clk ssi_ick_3430es2;
2710
2711 static struct clk_hw_omap ssi_ick_3430es2_hw = {
2712         .hw = {
2713                 .clk = &ssi_ick_3430es2,
2714         },
2715         .ops            = &clkhwops_omap3430es2_iclk_ssi_wait,
2716         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2717         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2718         .clkdm_name     = "core_l4_clkdm",
2719 };
2720
2721 DEFINE_STRUCT_CLK(ssi_ick_3430es2, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2722
2723 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
2724         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2725         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2726         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2727         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2728         { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2729         { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
2730         { .div = 0 }
2731 };
2732
2733 static const struct clksel ssi_ssr_clksel[] = {
2734         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
2735         { .parent = NULL },
2736 };
2737
2738 static const char *ssi_ssr_fck_3430es1_parent_names[] = {
2739         "corex2_fck",
2740 };
2741
2742 static const struct clk_ops ssi_ssr_fck_3430es1_ops = {
2743         .init           = &omap2_init_clk_clkdm,
2744         .enable         = &omap2_dflt_clk_enable,
2745         .disable        = &omap2_dflt_clk_disable,
2746         .is_enabled     = &omap2_dflt_clk_is_enabled,
2747         .recalc_rate    = &omap2_clksel_recalc,
2748         .set_rate       = &omap2_clksel_set_rate,
2749         .round_rate     = &omap2_clksel_round_rate,
2750 };
2751
2752 DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es1, "core_l4_clkdm",
2753                          ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2754                          OMAP3430_CLKSEL_SSI_MASK,
2755                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2756                          OMAP3430_EN_SSI_SHIFT,
2757                          NULL, ssi_ssr_fck_3430es1_parent_names,
2758                          ssi_ssr_fck_3430es1_ops);
2759
2760 DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es2, "core_l4_clkdm",
2761                          ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2762                          OMAP3430_CLKSEL_SSI_MASK,
2763                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2764                          OMAP3430_EN_SSI_SHIFT,
2765                          NULL, ssi_ssr_fck_3430es1_parent_names,
2766                          ssi_ssr_fck_3430es1_ops);
2767
2768 DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1, "ssi_ssr_fck_3430es1",
2769                         &ssi_ssr_fck_3430es1, 0x0, 1, 2);
2770
2771 DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2, "ssi_ssr_fck_3430es2",
2772                         &ssi_ssr_fck_3430es2, 0x0, 1, 2);
2773
2774 static struct clk sys_clkout1;
2775
2776 static const char *sys_clkout1_parent_names[] = {
2777         "osc_sys_ck",
2778 };
2779
2780 static struct clk_hw_omap sys_clkout1_hw = {
2781         .hw = {
2782                 .clk = &sys_clkout1,
2783         },
2784         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
2785         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
2786 };
2787
2788 DEFINE_STRUCT_CLK(sys_clkout1, sys_clkout1_parent_names, aes1_ick_ops);
2789
2790 DEFINE_CLK_DIVIDER(sys_clkout2, "clkout2_src_ck", &clkout2_src_ck, 0x0,
2791                    OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_DIV_SHIFT,
2792                    OMAP3430_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
2793
2794 DEFINE_CLK_MUX(traceclk_src_fck, emu_src_ck_parent_names, NULL, 0x0,
2795                OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2796                OMAP3430_TRACE_MUX_CTRL_SHIFT, OMAP3430_TRACE_MUX_CTRL_WIDTH,
2797                0x0, NULL);
2798
2799 DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck, 0x0,
2800                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2801                    OMAP3430_CLKSEL_TRACECLK_SHIFT,
2802                    OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
2803
2804 static struct clk ts_fck;
2805
2806 static struct clk_hw_omap ts_fck_hw = {
2807         .hw = {
2808                 .clk = &ts_fck,
2809         },
2810         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
2811         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
2812         .clkdm_name     = "core_l4_clkdm",
2813 };
2814
2815 DEFINE_STRUCT_CLK(ts_fck, wkup_32k_fck_parent_names, aes2_ick_ops);
2816
2817 static struct clk uart1_fck;
2818
2819 static struct clk_hw_omap uart1_fck_hw = {
2820         .hw = {
2821                 .clk = &uart1_fck,
2822         },
2823         .ops            = &clkhwops_wait,
2824         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2825         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
2826         .clkdm_name     = "core_l4_clkdm",
2827 };
2828
2829 DEFINE_STRUCT_CLK(uart1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2830
2831 static struct clk uart1_ick;
2832
2833 static struct clk_hw_omap uart1_ick_hw = {
2834         .hw = {
2835                 .clk = &uart1_ick,
2836         },
2837         .ops            = &clkhwops_iclk_wait,
2838         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2839         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
2840         .clkdm_name     = "core_l4_clkdm",
2841 };
2842
2843 DEFINE_STRUCT_CLK(uart1_ick, aes2_ick_parent_names, aes2_ick_ops);
2844
2845 static struct clk uart2_fck;
2846
2847 static struct clk_hw_omap uart2_fck_hw = {
2848         .hw = {
2849                 .clk = &uart2_fck,
2850         },
2851         .ops            = &clkhwops_wait,
2852         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2853         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
2854         .clkdm_name     = "core_l4_clkdm",
2855 };
2856
2857 DEFINE_STRUCT_CLK(uart2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2858
2859 static struct clk uart2_ick;
2860
2861 static struct clk_hw_omap uart2_ick_hw = {
2862         .hw = {
2863                 .clk = &uart2_ick,
2864         },
2865         .ops            = &clkhwops_iclk_wait,
2866         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2867         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
2868         .clkdm_name     = "core_l4_clkdm",
2869 };
2870
2871 DEFINE_STRUCT_CLK(uart2_ick, aes2_ick_parent_names, aes2_ick_ops);
2872
2873 static struct clk uart3_fck;
2874
2875 static const char *uart3_fck_parent_names[] = {
2876         "per_48m_fck",
2877 };
2878
2879 static struct clk_hw_omap uart3_fck_hw = {
2880         .hw = {
2881                 .clk = &uart3_fck,
2882         },
2883         .ops            = &clkhwops_wait,
2884         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2885         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2886         .clkdm_name     = "per_clkdm",
2887 };
2888
2889 DEFINE_STRUCT_CLK(uart3_fck, uart3_fck_parent_names, aes2_ick_ops);
2890
2891 static struct clk uart3_ick;
2892
2893 static struct clk_hw_omap uart3_ick_hw = {
2894         .hw = {
2895                 .clk = &uart3_ick,
2896         },
2897         .ops            = &clkhwops_iclk_wait,
2898         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2899         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2900         .clkdm_name     = "per_clkdm",
2901 };
2902
2903 DEFINE_STRUCT_CLK(uart3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2904
2905 static struct clk uart4_fck;
2906
2907 static struct clk_hw_omap uart4_fck_hw = {
2908         .hw = {
2909                 .clk = &uart4_fck,
2910         },
2911         .ops            = &clkhwops_wait,
2912         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2913         .enable_bit     = OMAP3630_EN_UART4_SHIFT,
2914         .clkdm_name     = "per_clkdm",
2915 };
2916
2917 DEFINE_STRUCT_CLK(uart4_fck, uart3_fck_parent_names, aes2_ick_ops);
2918
2919 static struct clk uart4_fck_am35xx;
2920
2921 static struct clk_hw_omap uart4_fck_am35xx_hw = {
2922         .hw = {
2923                 .clk = &uart4_fck_am35xx,
2924         },
2925         .ops            = &clkhwops_wait,
2926         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2927         .enable_bit     = AM35XX_EN_UART4_SHIFT,
2928         .clkdm_name     = "core_l4_clkdm",
2929 };
2930
2931 DEFINE_STRUCT_CLK(uart4_fck_am35xx, fshostusb_fck_parent_names, aes2_ick_ops);
2932
2933 static struct clk uart4_ick;
2934
2935 static struct clk_hw_omap uart4_ick_hw = {
2936         .hw = {
2937                 .clk = &uart4_ick,
2938         },
2939         .ops            = &clkhwops_iclk_wait,
2940         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2941         .enable_bit     = OMAP3630_EN_UART4_SHIFT,
2942         .clkdm_name     = "per_clkdm",
2943 };
2944
2945 DEFINE_STRUCT_CLK(uart4_ick, gpio2_ick_parent_names, aes2_ick_ops);
2946
2947 static struct clk uart4_ick_am35xx;
2948
2949 static struct clk_hw_omap uart4_ick_am35xx_hw = {
2950         .hw = {
2951                 .clk = &uart4_ick_am35xx,
2952         },
2953         .ops            = &clkhwops_iclk_wait,
2954         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2955         .enable_bit     = AM35XX_EN_UART4_SHIFT,
2956         .clkdm_name     = "core_l4_clkdm",
2957 };
2958
2959 DEFINE_STRUCT_CLK(uart4_ick_am35xx, aes2_ick_parent_names, aes2_ick_ops);
2960
2961 static const struct clksel_rate div2_rates[] = {
2962         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2963         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2964         { .div = 0 }
2965 };
2966
2967 static const struct clksel usb_l4_clksel[] = {
2968         { .parent = &l4_ick, .rates = div2_rates },
2969         { .parent = NULL },
2970 };
2971
2972 static const char *usb_l4_ick_parent_names[] = {
2973         "l4_ick",
2974 };
2975
2976 DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_clksel,
2977                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2978                          OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2979                          OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2980                          OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2981                          &clkhwops_iclk_wait, usb_l4_ick_parent_names,
2982                          ssi_ssr_fck_3430es1_ops);
2983
2984 static struct clk usbhost_120m_fck;
2985
2986 static const char *usbhost_120m_fck_parent_names[] = {
2987         "dpll5_m2_ck",
2988 };
2989
2990 static struct clk_hw_omap usbhost_120m_fck_hw = {
2991         .hw = {
2992                 .clk = &usbhost_120m_fck,
2993         },
2994         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2995         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2996         .clkdm_name     = "usbhost_clkdm",
2997 };
2998
2999 DEFINE_STRUCT_CLK(usbhost_120m_fck, usbhost_120m_fck_parent_names,
3000                   aes2_ick_ops);
3001
3002 static struct clk usbhost_48m_fck;
3003
3004 static struct clk_hw_omap usbhost_48m_fck_hw = {
3005         .hw = {
3006                 .clk = &usbhost_48m_fck,
3007         },
3008         .ops            = &clkhwops_omap3430es2_dss_usbhost_wait,
3009         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
3010         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
3011         .clkdm_name     = "usbhost_clkdm",
3012 };
3013
3014 DEFINE_STRUCT_CLK(usbhost_48m_fck, core_48m_fck_parent_names, aes2_ick_ops);
3015
3016 static struct clk usbhost_ick;
3017
3018 static struct clk_hw_omap usbhost_ick_hw = {
3019         .hw = {
3020                 .clk = &usbhost_ick,
3021         },
3022         .ops            = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
3023         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
3024         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
3025         .clkdm_name     = "usbhost_clkdm",
3026 };
3027
3028 DEFINE_STRUCT_CLK(usbhost_ick, security_l4_ick2_parent_names, aes2_ick_ops);
3029
3030 static struct clk usbtll_fck;
3031
3032 static struct clk_hw_omap usbtll_fck_hw = {
3033         .hw = {
3034                 .clk = &usbtll_fck,
3035         },
3036         .ops            = &clkhwops_wait,
3037         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
3038         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
3039         .clkdm_name     = "core_l4_clkdm",
3040 };
3041
3042 DEFINE_STRUCT_CLK(usbtll_fck, usbhost_120m_fck_parent_names, aes2_ick_ops);
3043
3044 static struct clk usbtll_ick;
3045
3046 static struct clk_hw_omap usbtll_ick_hw = {
3047         .hw = {
3048                 .clk = &usbtll_ick,
3049         },
3050         .ops            = &clkhwops_iclk_wait,
3051         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
3052         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
3053         .clkdm_name     = "core_l4_clkdm",
3054 };
3055
3056 DEFINE_STRUCT_CLK(usbtll_ick, aes2_ick_parent_names, aes2_ick_ops);
3057
3058 static const struct clksel_rate usim_96m_rates[] = {
3059         { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
3060         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3061         { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
3062         { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
3063         { .div = 0 }
3064 };
3065
3066 static const struct clksel_rate usim_120m_rates[] = {
3067         { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
3068         { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
3069         { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
3070         { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
3071         { .div = 0 }
3072 };
3073
3074 static const struct clksel usim_clksel[] = {
3075         { .parent = &omap_96m_fck, .rates = usim_96m_rates },
3076         { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
3077         { .parent = &sys_ck, .rates = div2_rates },
3078         { .parent = NULL },
3079 };
3080
3081 static const char *usim_fck_parent_names[] = {
3082         "omap_96m_fck", "dpll5_m2_ck", "sys_ck",
3083 };
3084
3085 static struct clk usim_fck;
3086
3087 static const struct clk_ops usim_fck_ops = {
3088         .enable         = &omap2_dflt_clk_enable,
3089         .disable        = &omap2_dflt_clk_disable,
3090         .is_enabled     = &omap2_dflt_clk_is_enabled,
3091         .recalc_rate    = &omap2_clksel_recalc,
3092         .get_parent     = &omap2_clksel_find_parent_index,
3093         .set_parent     = &omap2_clksel_set_parent,
3094 };
3095
3096 DEFINE_CLK_OMAP_MUX_GATE(usim_fck, NULL, usim_clksel,
3097                          OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
3098                          OMAP3430ES2_CLKSEL_USIMOCP_MASK,
3099                          OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3100                          OMAP3430ES2_EN_USIMOCP_SHIFT, &clkhwops_wait,
3101                          usim_fck_parent_names, usim_fck_ops);
3102
3103 static struct clk usim_ick;
3104
3105 static struct clk_hw_omap usim_ick_hw = {
3106         .hw = {
3107                 .clk = &usim_ick,
3108         },
3109         .ops            = &clkhwops_iclk_wait,
3110         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3111         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
3112         .clkdm_name     = "wkup_clkdm",
3113 };
3114
3115 DEFINE_STRUCT_CLK(usim_ick, gpio1_ick_parent_names, aes2_ick_ops);
3116
3117 static struct clk vpfe_fck;
3118
3119 static const char *vpfe_fck_parent_names[] = {
3120         "pclk_ck",
3121 };
3122
3123 static struct clk_hw_omap vpfe_fck_hw = {
3124         .hw = {
3125                 .clk = &vpfe_fck,
3126         },
3127         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3128         .enable_bit     = AM35XX_VPFE_FCLK_SHIFT,
3129 };
3130
3131 DEFINE_STRUCT_CLK(vpfe_fck, vpfe_fck_parent_names, aes1_ick_ops);
3132
3133 static struct clk vpfe_ick;
3134
3135 static struct clk_hw_omap vpfe_ick_hw = {
3136         .hw = {
3137                 .clk = &vpfe_ick,
3138         },
3139         .ops            = &clkhwops_am35xx_ipss_module_wait,
3140         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3141         .enable_bit     = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3142         .clkdm_name     = "core_l3_clkdm",
3143 };
3144
3145 DEFINE_STRUCT_CLK(vpfe_ick, emac_ick_parent_names, aes2_ick_ops);
3146
3147 static struct clk wdt1_fck;
3148
3149 DEFINE_STRUCT_CLK_HW_OMAP(wdt1_fck, "wkup_clkdm");
3150 DEFINE_STRUCT_CLK(wdt1_fck, gpt12_fck_parent_names, core_l4_ick_ops);
3151
3152 static struct clk wdt1_ick;
3153
3154 static struct clk_hw_omap wdt1_ick_hw = {
3155         .hw = {
3156                 .clk = &wdt1_ick,
3157         },
3158         .ops            = &clkhwops_iclk_wait,
3159         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3160         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
3161         .clkdm_name     = "wkup_clkdm",
3162 };
3163
3164 DEFINE_STRUCT_CLK(wdt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
3165
3166 static struct clk wdt2_fck;
3167
3168 static struct clk_hw_omap wdt2_fck_hw = {
3169         .hw = {
3170                 .clk = &wdt2_fck,
3171         },
3172         .ops            = &clkhwops_wait,
3173         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3174         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
3175         .clkdm_name     = "wkup_clkdm",
3176 };
3177
3178 DEFINE_STRUCT_CLK(wdt2_fck, gpio1_dbck_parent_names, aes2_ick_ops);
3179
3180 static struct clk wdt2_ick;
3181
3182 static struct clk_hw_omap wdt2_ick_hw = {
3183         .hw = {
3184                 .clk = &wdt2_ick,
3185         },
3186         .ops            = &clkhwops_iclk_wait,
3187         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3188         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
3189         .clkdm_name     = "wkup_clkdm",
3190 };
3191
3192 DEFINE_STRUCT_CLK(wdt2_ick, gpio1_ick_parent_names, aes2_ick_ops);
3193
3194 static struct clk wdt3_fck;
3195
3196 static struct clk_hw_omap wdt3_fck_hw = {
3197         .hw = {
3198                 .clk = &wdt3_fck,
3199         },
3200         .ops            = &clkhwops_wait,
3201         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
3202         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
3203         .clkdm_name     = "per_clkdm",
3204 };
3205
3206 DEFINE_STRUCT_CLK(wdt3_fck, gpio2_dbck_parent_names, aes2_ick_ops);
3207
3208 static struct clk wdt3_ick;
3209
3210 static struct clk_hw_omap wdt3_ick_hw = {
3211         .hw = {
3212                 .clk = &wdt3_ick,
3213         },
3214         .ops            = &clkhwops_iclk_wait,
3215         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
3216         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
3217         .clkdm_name     = "per_clkdm",
3218 };
3219
3220 DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
3221
3222 /*
3223  * clocks specific to omap3430es1
3224  */
3225 static struct omap_clk omap3430es1_clks[] = {
3226         CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck),
3227         CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck),
3228         CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick),
3229         CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck),
3230         CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck),
3231         CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck),
3232         CLK(NULL,       "fshostusb_fck", &fshostusb_fck),
3233         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1),
3234         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1),
3235         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es1),
3236         CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es1),
3237         CLK(NULL,       "fac_ick",      &fac_ick),
3238         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1),
3239         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick),
3240         CLK(NULL,       "dss1_alwon_fck",       &dss1_alwon_fck_3430es1),
3241         CLK("omapdss_dss",      "ick",          &dss_ick_3430es1),
3242         CLK(NULL,       "dss_ick",              &dss_ick_3430es1),
3243 };
3244
3245 /*
3246  * clocks specific to am35xx
3247  */
3248 static struct omap_clk am35xx_clks[] = {
3249         CLK(NULL,       "ipss_ick",     &ipss_ick),
3250         CLK(NULL,       "rmii_ck",      &rmii_ck),
3251         CLK(NULL,       "pclk_ck",      &pclk_ck),
3252         CLK(NULL,       "emac_ick",     &emac_ick),
3253         CLK(NULL,       "emac_fck",     &emac_fck),
3254         CLK("davinci_emac.0",   NULL,   &emac_ick),
3255         CLK("davinci_mdio.0",   NULL,   &emac_fck),
3256         CLK("vpfe-capture",     "master",       &vpfe_ick),
3257         CLK("vpfe-capture",     "slave",        &vpfe_fck),
3258         CLK(NULL,       "hsotgusb_ick",         &hsotgusb_ick_am35xx),
3259         CLK(NULL,       "hsotgusb_fck",         &hsotgusb_fck_am35xx),
3260         CLK(NULL,       "hecc_ck",      &hecc_ck),
3261         CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx),
3262         CLK(NULL,       "uart4_fck",    &uart4_fck_am35xx),
3263 };
3264
3265 /*
3266  * clocks specific to omap36xx
3267  */
3268 static struct omap_clk omap36xx_clks[] = {
3269         CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck),
3270         CLK(NULL,       "uart4_fck",    &uart4_fck),
3271 };
3272
3273 /*
3274  * clocks common to omap36xx omap34xx
3275  */
3276 static struct omap_clk omap34xx_omap36xx_clks[] = {
3277         CLK(NULL,       "aes1_ick",     &aes1_ick),
3278         CLK("omap_rng", "ick",          &rng_ick),
3279         CLK(NULL,       "sha11_ick",    &sha11_ick),
3280         CLK(NULL,       "des1_ick",     &des1_ick),
3281         CLK(NULL,       "cam_mclk",     &cam_mclk),
3282         CLK(NULL,       "cam_ick",      &cam_ick),
3283         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck),
3284         CLK(NULL,       "security_l3_ick", &security_l3_ick),
3285         CLK(NULL,       "pka_ick",      &pka_ick),
3286         CLK(NULL,       "icr_ick",      &icr_ick),
3287         CLK("omap-aes", "ick",  &aes2_ick),
3288         CLK("omap-sham",        "ick",  &sha12_ick),
3289         CLK(NULL,       "des2_ick",     &des2_ick),
3290         CLK(NULL,       "mspro_ick",    &mspro_ick),
3291         CLK(NULL,       "mailboxes_ick", &mailboxes_ick),
3292         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick),
3293         CLK(NULL,       "sr1_fck",      &sr1_fck),
3294         CLK(NULL,       "sr2_fck",      &sr2_fck),
3295         CLK(NULL,       "sr_l4_ick",    &sr_l4_ick),
3296         CLK(NULL,       "security_l4_ick2", &security_l4_ick2),
3297         CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick),
3298         CLK(NULL,       "dpll2_fck",    &dpll2_fck),
3299         CLK(NULL,       "iva2_ck",      &iva2_ck),
3300         CLK(NULL,       "modem_fck",    &modem_fck),
3301         CLK(NULL,       "sad2d_ick",    &sad2d_ick),
3302         CLK(NULL,       "mad2d_ick",    &mad2d_ick),
3303         CLK(NULL,       "mspro_fck",    &mspro_fck),
3304         CLK(NULL,       "dpll2_ck",     &dpll2_ck),
3305         CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck),
3306 };
3307
3308 /*
3309  * clocks common to omap36xx and omap3430es2plus
3310  */
3311 static struct omap_clk omap36xx_omap3430es2plus_clks[] = {
3312         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2),
3313         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2),
3314         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es2),
3315         CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es2),
3316         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2),
3317         CLK(NULL,       "usim_fck",     &usim_fck),
3318         CLK(NULL,       "usim_ick",     &usim_ick),
3319 };
3320
3321 /*
3322  * clocks common to am35xx omap36xx and omap3430es2plus
3323  */
3324 static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
3325         CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck),
3326         CLK(NULL,       "dpll5_ck",     &dpll5_ck),
3327         CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck),
3328         CLK(NULL,       "sgx_fck",      &sgx_fck),
3329         CLK(NULL,       "sgx_ick",      &sgx_ick),
3330         CLK(NULL,       "cpefuse_fck",  &cpefuse_fck),
3331         CLK(NULL,       "ts_fck",       &ts_fck),
3332         CLK(NULL,       "usbtll_fck",   &usbtll_fck),
3333         CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck),
3334         CLK("usbhs_tll",        "usbtll_fck",   &usbtll_fck),
3335         CLK(NULL,       "usbtll_ick",   &usbtll_ick),
3336         CLK("usbhs_omap",       "usbtll_ick",   &usbtll_ick),
3337         CLK("usbhs_tll",        "usbtll_ick",   &usbtll_ick),
3338         CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick),
3339         CLK(NULL,       "mmchs3_ick",   &mmchs3_ick),
3340         CLK(NULL,       "mmchs3_fck",   &mmchs3_fck),
3341         CLK(NULL,       "dss1_alwon_fck",       &dss1_alwon_fck_3430es2),
3342         CLK("omapdss_dss",      "ick",          &dss_ick_3430es2),
3343         CLK(NULL,       "dss_ick",              &dss_ick_3430es2),
3344         CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck),
3345         CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck),
3346         CLK(NULL,       "usbhost_ick",  &usbhost_ick),
3347         CLK("usbhs_omap",       "usbhost_ick",  &usbhost_ick),
3348 };
3349
3350 /*
3351  * common clocks
3352  */
3353 static struct omap_clk omap3xxx_clks[] = {
3354         CLK(NULL,       "apb_pclk",     &dummy_apb_pclk),
3355         CLK(NULL,       "omap_32k_fck", &omap_32k_fck),
3356         CLK(NULL,       "virt_12m_ck",  &virt_12m_ck),
3357         CLK(NULL,       "virt_13m_ck",  &virt_13m_ck),
3358         CLK(NULL,       "virt_19200000_ck", &virt_19200000_ck),
3359         CLK(NULL,       "virt_26000000_ck", &virt_26000000_ck),
3360         CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck),
3361         CLK(NULL,       "osc_sys_ck",   &osc_sys_ck),
3362         CLK("twl",      "fck",          &osc_sys_ck),
3363         CLK(NULL,       "sys_ck",       &sys_ck),
3364         CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck),
3365         CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck),
3366         CLK(NULL,       "sys_altclk",   &sys_altclk),
3367         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks),
3368         CLK(NULL,       "sys_clkout1",  &sys_clkout1),
3369         CLK(NULL,       "dpll1_ck",     &dpll1_ck),
3370         CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck),
3371         CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck),
3372         CLK(NULL,       "dpll3_ck",     &dpll3_ck),
3373         CLK(NULL,       "core_ck",      &core_ck),
3374         CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck),
3375         CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck),
3376         CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck),
3377         CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck),
3378         CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck),
3379         CLK(NULL,       "dpll4_ck",     &dpll4_ck),
3380         CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck),
3381         CLK(NULL,       "omap_96m_fck", &omap_96m_fck),
3382         CLK(NULL,       "cm_96m_fck",   &cm_96m_fck),
3383         CLK(NULL,       "omap_54m_fck", &omap_54m_fck),
3384         CLK(NULL,       "omap_48m_fck", &omap_48m_fck),
3385         CLK(NULL,       "omap_12m_fck", &omap_12m_fck),
3386         CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck),
3387         CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck),
3388         CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck),
3389         CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck),
3390         CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck),
3391         CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck),
3392         CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck),
3393         CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck),
3394         CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck),
3395         CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck),
3396         CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck),
3397         CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck),
3398         CLK(NULL,       "sys_clkout2",  &sys_clkout2),
3399         CLK(NULL,       "corex2_fck",   &corex2_fck),
3400         CLK(NULL,       "dpll1_fck",    &dpll1_fck),
3401         CLK(NULL,       "mpu_ck",       &mpu_ck),
3402         CLK(NULL,       "arm_fck",      &arm_fck),
3403         CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck),
3404         CLK(NULL,       "l3_ick",       &l3_ick),
3405         CLK(NULL,       "l4_ick",       &l4_ick),
3406         CLK(NULL,       "rm_ick",       &rm_ick),
3407         CLK(NULL,       "gpt10_fck",    &gpt10_fck),
3408         CLK(NULL,       "gpt11_fck",    &gpt11_fck),
3409         CLK(NULL,       "core_96m_fck", &core_96m_fck),
3410         CLK(NULL,       "mmchs2_fck",   &mmchs2_fck),
3411         CLK(NULL,       "mmchs1_fck",   &mmchs1_fck),
3412         CLK(NULL,       "i2c3_fck",     &i2c3_fck),
3413         CLK(NULL,       "i2c2_fck",     &i2c2_fck),
3414         CLK(NULL,       "i2c1_fck",     &i2c1_fck),
3415         CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck),
3416         CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck),
3417         CLK(NULL,       "core_48m_fck", &core_48m_fck),
3418         CLK(NULL,       "mcspi4_fck",   &mcspi4_fck),
3419         CLK(NULL,       "mcspi3_fck",   &mcspi3_fck),
3420         CLK(NULL,       "mcspi2_fck",   &mcspi2_fck),
3421         CLK(NULL,       "mcspi1_fck",   &mcspi1_fck),
3422         CLK(NULL,       "uart2_fck",    &uart2_fck),
3423         CLK(NULL,       "uart1_fck",    &uart1_fck),
3424         CLK(NULL,       "core_12m_fck", &core_12m_fck),
3425         CLK("omap_hdq.0",       "fck",  &hdq_fck),
3426         CLK(NULL,       "hdq_fck",      &hdq_fck),
3427         CLK(NULL,       "core_l3_ick",  &core_l3_ick),
3428         CLK(NULL,       "sdrc_ick",     &sdrc_ick),
3429         CLK(NULL,       "gpmc_fck",     &gpmc_fck),
3430         CLK(NULL,       "core_l4_ick",  &core_l4_ick),
3431         CLK("omap_hsmmc.1",     "ick",  &mmchs2_ick),
3432         CLK("omap_hsmmc.0",     "ick",  &mmchs1_ick),
3433         CLK(NULL,       "mmchs2_ick",   &mmchs2_ick),
3434         CLK(NULL,       "mmchs1_ick",   &mmchs1_ick),
3435         CLK("omap_hdq.0", "ick",        &hdq_ick),
3436         CLK(NULL,       "hdq_ick",      &hdq_ick),
3437         CLK("omap2_mcspi.4", "ick",     &mcspi4_ick),
3438         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick),
3439         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick),
3440         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick),
3441         CLK(NULL,       "mcspi4_ick",   &mcspi4_ick),
3442         CLK(NULL,       "mcspi3_ick",   &mcspi3_ick),
3443         CLK(NULL,       "mcspi2_ick",   &mcspi2_ick),
3444         CLK(NULL,       "mcspi1_ick",   &mcspi1_ick),
3445         CLK("omap_i2c.3", "ick",        &i2c3_ick),
3446         CLK("omap_i2c.2", "ick",        &i2c2_ick),
3447         CLK("omap_i2c.1", "ick",        &i2c1_ick),
3448         CLK(NULL,       "i2c3_ick",     &i2c3_ick),
3449         CLK(NULL,       "i2c2_ick",     &i2c2_ick),
3450         CLK(NULL,       "i2c1_ick",     &i2c1_ick),
3451         CLK(NULL,       "uart2_ick",    &uart2_ick),
3452         CLK(NULL,       "uart1_ick",    &uart1_ick),
3453         CLK(NULL,       "gpt11_ick",    &gpt11_ick),
3454         CLK(NULL,       "gpt10_ick",    &gpt10_ick),
3455         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick),
3456         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick),
3457         CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick),
3458         CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick),
3459         CLK(NULL,       "omapctrl_ick", &omapctrl_ick),
3460         CLK(NULL,       "dss_tv_fck",   &dss_tv_fck),
3461         CLK(NULL,       "dss_96m_fck",  &dss_96m_fck),
3462         CLK(NULL,       "dss2_alwon_fck",       &dss2_alwon_fck),
3463         CLK(NULL,       "utmi_p1_gfclk",        &dummy_ck),
3464         CLK(NULL,       "utmi_p2_gfclk",        &dummy_ck),
3465         CLK(NULL,       "xclk60mhsp1_ck",       &dummy_ck),
3466         CLK(NULL,       "xclk60mhsp2_ck",       &dummy_ck),
3467         CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &dummy_ck),
3468         CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &dummy_ck),
3469         CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck),
3470         CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck),
3471         CLK("usbhs_tll",        "usb_tll_hs_usb_ch0_clk",       &dummy_ck),
3472         CLK("usbhs_tll",        "usb_tll_hs_usb_ch1_clk",       &dummy_ck),
3473         CLK(NULL,       "init_60m_fclk",        &dummy_ck),
3474         CLK(NULL,       "gpt1_fck",     &gpt1_fck),
3475         CLK(NULL,       "aes2_ick",     &aes2_ick),
3476         CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck),
3477         CLK(NULL,       "gpio1_dbck",   &gpio1_dbck),
3478         CLK(NULL,       "sha12_ick",    &sha12_ick),
3479         CLK(NULL,       "wdt2_fck",             &wdt2_fck),
3480         CLK("omap_wdt", "ick",          &wdt2_ick),
3481         CLK(NULL,       "wdt2_ick",     &wdt2_ick),
3482         CLK(NULL,       "wdt1_ick",     &wdt1_ick),
3483         CLK(NULL,       "gpio1_ick",    &gpio1_ick),
3484         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick),
3485         CLK(NULL,       "gpt12_ick",    &gpt12_ick),
3486         CLK(NULL,       "gpt1_ick",     &gpt1_ick),
3487         CLK(NULL,       "per_96m_fck",  &per_96m_fck),
3488         CLK(NULL,       "per_48m_fck",  &per_48m_fck),
3489         CLK(NULL,       "uart3_fck",    &uart3_fck),
3490         CLK(NULL,       "gpt2_fck",     &gpt2_fck),
3491         CLK(NULL,       "gpt3_fck",     &gpt3_fck),
3492         CLK(NULL,       "gpt4_fck",     &gpt4_fck),
3493         CLK(NULL,       "gpt5_fck",     &gpt5_fck),
3494         CLK(NULL,       "gpt6_fck",     &gpt6_fck),
3495         CLK(NULL,       "gpt7_fck",     &gpt7_fck),
3496         CLK(NULL,       "gpt8_fck",     &gpt8_fck),
3497         CLK(NULL,       "gpt9_fck",     &gpt9_fck),
3498         CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck),
3499         CLK(NULL,       "gpio6_dbck",   &gpio6_dbck),
3500         CLK(NULL,       "gpio5_dbck",   &gpio5_dbck),
3501         CLK(NULL,       "gpio4_dbck",   &gpio4_dbck),
3502         CLK(NULL,       "gpio3_dbck",   &gpio3_dbck),
3503         CLK(NULL,       "gpio2_dbck",   &gpio2_dbck),
3504         CLK(NULL,       "wdt3_fck",     &wdt3_fck),
3505         CLK(NULL,       "per_l4_ick",   &per_l4_ick),
3506         CLK(NULL,       "gpio6_ick",    &gpio6_ick),
3507         CLK(NULL,       "gpio5_ick",    &gpio5_ick),
3508         CLK(NULL,       "gpio4_ick",    &gpio4_ick),
3509         CLK(NULL,       "gpio3_ick",    &gpio3_ick),
3510         CLK(NULL,       "gpio2_ick",    &gpio2_ick),
3511         CLK(NULL,       "wdt3_ick",     &wdt3_ick),
3512         CLK(NULL,       "uart3_ick",    &uart3_ick),
3513         CLK(NULL,       "uart4_ick",    &uart4_ick),
3514         CLK(NULL,       "gpt9_ick",     &gpt9_ick),
3515         CLK(NULL,       "gpt8_ick",     &gpt8_ick),
3516         CLK(NULL,       "gpt7_ick",     &gpt7_ick),
3517         CLK(NULL,       "gpt6_ick",     &gpt6_ick),
3518         CLK(NULL,       "gpt5_ick",     &gpt5_ick),
3519         CLK(NULL,       "gpt4_ick",     &gpt4_ick),
3520         CLK(NULL,       "gpt3_ick",     &gpt3_ick),
3521         CLK(NULL,       "gpt2_ick",     &gpt2_ick),
3522         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick),
3523         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick),
3524         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick),
3525         CLK(NULL,       "mcbsp4_ick",   &mcbsp2_ick),
3526         CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick),
3527         CLK(NULL,       "mcbsp2_ick",   &mcbsp4_ick),
3528         CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck),
3529         CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck),
3530         CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck),
3531         CLK("etb",      "emu_src_ck",   &emu_src_ck),
3532         CLK(NULL,       "emu_src_ck",   &emu_src_ck),
3533         CLK(NULL,       "pclk_fck",     &pclk_fck),
3534         CLK(NULL,       "pclkx2_fck",   &pclkx2_fck),
3535         CLK(NULL,       "atclk_fck",    &atclk_fck),
3536         CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck),
3537         CLK(NULL,       "traceclk_fck", &traceclk_fck),
3538         CLK(NULL,       "secure_32k_fck", &secure_32k_fck),
3539         CLK(NULL,       "gpt12_fck",    &gpt12_fck),
3540         CLK(NULL,       "wdt1_fck",     &wdt1_fck),
3541         CLK(NULL,       "timer_32k_ck", &omap_32k_fck),
3542         CLK(NULL,       "timer_sys_ck", &sys_ck),
3543         CLK(NULL,       "cpufreq_ck",   &dpll1_ck),
3544 };
3545
3546 static const char *enable_init_clks[] = {
3547         "sdrc_ick",
3548         "gpmc_fck",
3549         "omapctrl_ick",
3550 };
3551
3552 int __init omap3xxx_clk_init(void)
3553 {
3554         if (omap3_has_192mhz_clk())
3555                 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3556
3557         if (cpu_is_omap3630()) {
3558                 dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
3559                 dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
3560                 dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
3561                 dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
3562                 dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
3563                 dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
3564         }
3565
3566         /*
3567          * XXX This type of dynamic rewriting of the clock tree is
3568          * deprecated and should be revised soon.
3569          */
3570         if (cpu_is_omap3630())
3571                 dpll4_dd = dpll4_dd_3630;
3572         else
3573                 dpll4_dd = dpll4_dd_34xx;
3574
3575
3576         /*
3577          * 3505 must be tested before 3517, since 3517 returns true
3578          * for both AM3517 chips and AM3517 family chips, which
3579          * includes 3505.  Unfortunately there's no obvious family
3580          * test for 3517/3505 :-(
3581          */
3582         if (soc_is_am35xx()) {
3583                 cpu_mask = RATE_IN_34XX;
3584                 omap_clocks_register(am35xx_clks, ARRAY_SIZE(am35xx_clks));
3585                 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3586                                      ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3587                 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
3588         } else if (cpu_is_omap3630()) {
3589                 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3590                 omap_clocks_register(omap36xx_clks, ARRAY_SIZE(omap36xx_clks));
3591                 omap_clocks_register(omap36xx_omap3430es2plus_clks,
3592                                      ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
3593                 omap_clocks_register(omap34xx_omap36xx_clks,
3594                                      ARRAY_SIZE(omap34xx_omap36xx_clks));
3595                 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3596                                      ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3597                 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
3598         } else if (soc_is_am33xx()) {
3599                 cpu_mask = RATE_IN_AM33XX;
3600         } else if (cpu_is_ti814x()) {
3601                 cpu_mask = RATE_IN_TI814X;
3602         } else if (cpu_is_omap34xx()) {
3603                 if (omap_rev() == OMAP3430_REV_ES1_0) {
3604                         cpu_mask = RATE_IN_3430ES1;
3605                         omap_clocks_register(omap3430es1_clks,
3606                                              ARRAY_SIZE(omap3430es1_clks));
3607                         omap_clocks_register(omap34xx_omap36xx_clks,
3608                                              ARRAY_SIZE(omap34xx_omap36xx_clks));
3609                         omap_clocks_register(omap3xxx_clks,
3610                                              ARRAY_SIZE(omap3xxx_clks));
3611                 } else {
3612                         /*
3613                          * Assume that anything that we haven't matched yet
3614                          * has 3430ES2-type clocks.
3615                          */
3616                         cpu_mask = RATE_IN_3430ES2PLUS;
3617                         omap_clocks_register(omap34xx_omap36xx_clks,
3618                                              ARRAY_SIZE(omap34xx_omap36xx_clks));
3619                         omap_clocks_register(omap36xx_omap3430es2plus_clks,
3620                                              ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
3621                         omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3622                                              ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3623                         omap_clocks_register(omap3xxx_clks,
3624                                              ARRAY_SIZE(omap3xxx_clks));
3625                 }
3626         } else {
3627                 WARN(1, "clock: could not identify OMAP3 variant\n");
3628         }
3629
3630                 omap2_clk_disable_autoidle_all();
3631
3632         omap2_clk_enable_init_clocks(enable_init_clks,
3633                                      ARRAY_SIZE(enable_init_clks));
3634
3635         pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3636                 (clk_get_rate(&osc_sys_ck) / 1000000),
3637                 (clk_get_rate(&osc_sys_ck) / 100000) % 10,
3638                 (clk_get_rate(&core_ck) / 1000000),
3639                 (clk_get_rate(&arm_fck) / 1000000));
3640
3641         /*
3642          * Lock DPLL5 -- here only until other device init code can
3643          * handle this
3644          */
3645         if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
3646                 omap3_clk_lock_dpll5();
3647
3648         /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3649         sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3650         arm_fck_p = clk_get(NULL, "arm_fck");
3651
3652         return 0;
3653 }