arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts

   1 /*
   2  * ARM Ltd. Versatile Express
   3  *
   4  * CoreTile Express A15x2 A7x3
   5  * Cortex-A15_A7 MPCore (V2P-CA15_A7)
   6  *
   7  * HBI-0249A
   8  */
   9
  10 /dts-v1/;
  11
  12 /memreserve/ 0xff000000 0x01000000;
  13
  14 / {
  15         model = "V2P-CA15_CA7";
  16         arm,hbi = <0x249>;
  17         arm,vexpress,site = <0xf>;
  18         compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress", "arm,generic";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         chosen { };
  24
  25         aliases {
  26                 serial0 = &v2m_serial0;
  27                 serial1 = &v2m_serial1;
  28                 serial2 = &v2m_serial2;
  29                 serial3 = &v2m_serial3;
  30                 i2c0 = &v2m_i2c_dvi;
  31                 i2c1 = &v2m_i2c_pcie;
  32         };
  33
  34         clusters {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 cluster0: cluster@0 {
  39                         reg = <0>;
  40                         cores {
  41                                 #address-cells = <1>;
  42                                 #size-cells = <0>;
  43
  44                                 core0: core@0 {
  45                                         reg = <0>;
  46                                 };
  47
  48                                 core1: core@1 {
  49                                         reg = <1>;
  50                                 };
  51
  52                         };
  53                 };
  54
  55                 cluster1: cluster@1 {
  56                         reg = <1>;
  57                         cores {
  58                                 #address-cells = <1>;
  59                                 #size-cells = <0>;
  60
  61                                 core2: core@0 {
  62                                         reg = <0>;
  63                                 };
  64
  65                                 core3: core@1 {
  66                                         reg = <1>;
  67                                 };
  68
  69                                 core4: core@2 {
  70                                         reg = <2>;
  71                                 };
  72                         };
  73                 };
  74         };
  75
  76         cpus {
  77                 #address-cells = <1>;
  78                 #size-cells = <0>;
  79
  80                 cpu2: cpu@2 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a7";
  83                         reg = <0x100>;
  84                         cluster = <&cluster1>;
  85                         core = <&core2>;
  86                         clock-frequency = <800000000>;
  87                         cci-control-port = <&cci_control2>;
  88                 };
  89
  90                 cpu3: cpu@3 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a7";
  93                         reg = <0x101>;
  94                         cluster = <&cluster1>;
  95                         core = <&core3>;
  96                         clock-frequency = <800000000>;
  97                         cci-control-port = <&cci_control2>;
  98                 };
  99
 100                 cpu4: cpu@4 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a7";
 103                         reg = <0x102>;
 104                         cluster = <&cluster1>;
 105                         core = <&core4>;
 106                         clock-frequency = <800000000>;
 107                         cci-control-port = <&cci_control2>;
 108                 };
 109
 110                 cpu0: cpu@0 {
 111                         device_type = "cpu";
 112                         compatible = "arm,cortex-a15";
 113                         reg = <0>;
 114                         cluster = <&cluster0>;
 115                         core = <&core0>;
 116                         clock-frequency = <1000000000>;
 117                         cci-control-port = <&cci_control1>;
 118                 };
 119
 120                 cpu1: cpu@1 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a15";
 123                         reg = <1>;
 124                         cluster = <&cluster0>;
 125                         core = <&core1>;
 126                         clock-frequency = <1000000000>;
 127                         cci-control-port = <&cci_control1>;
 128                 };
 129         };
 130
 131         memory@80000000 {
 132                 device_type = "memory";
 133                 reg = <0 0x80000000 0 0x80000000>;
 134         };
 135
 136         wdt@2a490000 {
 137                 compatible = "arm,sp805", "arm,primecell";
 138                 reg = <0 0x2a490000 0 0x1000>;
 139                 interrupts = <0 98 4>;
 140                 clocks = <&oscclk6a>, <&oscclk6a>;
 141                 clock-names = "wdogclk", "apb_pclk";
 142         };
 143
 144         hdlcd@2b000000 {
 145                 compatible = "arm,hdlcd";
 146                 reg = <0 0x2b000000 0 0x1000>;
 147                 interrupts = <0 85 4>;
 148                 mode = "1024x768-16@60";
 149                 framebuffer = <0 0xff000000 0 0x01000000>;
 150                 clocks = <&oscclk5>;
 151                 clock-names = "pxlclk";
 152         };
 153
 154         memory-controller@2b0a0000 {
 155                 compatible = "arm,pl341", "arm,primecell";
 156                 reg = <0 0x2b0a0000 0 0x1000>;
 157                 clocks = <&oscclk6a>;
 158                 clock-names = "apb_pclk";
 159         };
 160
 161         gic: interrupt-controller@2c001000 {
 162                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 163                 #interrupt-cells = <3>;
 164                 #address-cells = <0>;
 165                 interrupt-controller;
 166                 reg = <0 0x2c001000 0 0x1000>,
 167                       <0 0x2c002000 0 0x1000>,
 168                       <0 0x2c004000 0 0x2000>,
 169                       <0 0x2c006000 0 0x2000>;
 170                 interrupts = <1 9 0xf04>;
 171
 172                 gic-cpuif@0 {
 173                         compatible = "arm,gic-cpuif";
 174                         cpuif-id = <0>;
 175                         cpu = <&cpu0>;
 176                 };
 177                 gic-cpuif@1 {
 178                         compatible = "arm,gic-cpuif";
 179                         cpuif-id = <1>;
 180                         cpu = <&cpu1>;
 181                 };
 182                 gic-cpuif@2 {
 183                         compatible = "arm,gic-cpuif";
 184                         cpuif-id = <2>;
 185                         cpu = <&cpu2>;
 186                 };
 187
 188                 gic-cpuif@3 {
 189                         compatible = "arm,gic-cpuif";
 190                         cpuif-id = <3>;
 191                         cpu = <&cpu3>;
 192                 };
 193
 194                 gic-cpuif@4 {
 195                         compatible = "arm,gic-cpuif";
 196                         cpuif-id = <4>;
 197                         cpu = <&cpu4>;
 198                 };
 199         };
 200
 201         cci@2c090000 {
 202                 compatible = "arm,cci-400";
 203                 #address-cells = <1>;
 204                 #size-cells = <1>;
 205                 reg = <0 0x2c090000 0 0x1000>;
 206                 ranges = <0x0 0x0 0x2c090000 0x10000>;
 207
 208                 cci_control1: slave-if@4000 {
 209                         compatible = "arm,cci-400-ctrl-if";
 210                         interface-type = "ace";
 211                         reg = <0x4000 0x1000>;
 212                 };
 213
 214                 cci_control2: slave-if@5000 {
 215                         compatible = "arm,cci-400-ctrl-if";
 216                         interface-type = "ace";
 217                         reg = <0x5000 0x1000>;
 218                 };
 219         };
 220
 221         cci-pmu@2c099000 {
 222                 compatible = "arm,cci-400-pmu";
 223                 reg = <0 0x2c099000 0 0x6000>;
 224                 interrupts = <0 101 4>,
 225                              <0 102 4>,
 226                              <0 103 4>,
 227                              <0 104 4>,
 228                              <0 105 4>;
 229         };
 230
 231         memory-controller@7ffd0000 {
 232                 compatible = "arm,pl354", "arm,primecell";
 233                 reg = <0 0x7ffd0000 0 0x1000>;
 234                 interrupts = <0 86 4>,
 235                              <0 87 4>;
 236                 clocks = <&oscclk6a>;
 237                 clock-names = "apb_pclk";
 238         };
 239
 240         dma@7ff00000 {
 241                 compatible = "arm,pl330", "arm,primecell";
 242                 reg = <0 0x7ff00000 0 0x1000>;
 243                 interrupts = <0 92 4>,
 244                              <0 88 4>,
 245                              <0 89 4>,
 246                              <0 90 4>,
 247                              <0 91 4>;
 248                 clocks = <&oscclk6a>;
 249                 clock-names = "apb_pclk";
 250         };
 251
 252         spc@7fff0000 {
 253                 compatible = "arm,vexpress-spc,v2p-ca15_a7","arm,vexpress-spc";
 254                 reg = <0 0x7fff0000 0 0x1000>;
 255                 interrupts = <0 95 4>;
 256         };
 257
 258         timer {
 259                 compatible = "arm,armv7-timer";
 260                 interrupts = <1 13 0xf08>,
 261                              <1 14 0xf08>,
 262                              <1 11 0xf08>,
 263                              <1 10 0xf08>;
 264         };
 265
 266         pmu_a15 {
 267                 compatible = "arm,cortex-a15-pmu";
 268                 cluster  = <&cluster0>;
 269                 interrupts = <0 68 4>,
 270                              <0 69 4>;
 271         };
 272
 273         pmu_a7 {
 274                 compatible = "arm,cortex-a7-pmu";
 275                 cluster  = <&cluster1>;
 276                 interrupts = <0 128 4>,
 277                              <0 129 4>,
 278                              <0 130 4>;
 279         };
 280
 281         oscclk6a: oscclk6a {
 282                 /* Reference 24MHz clock */
 283                 compatible = "fixed-clock";
 284                 #clock-cells = <0>;
 285                 clock-frequency = <24000000>;
 286                 clock-output-names = "oscclk6a";
 287         };
 288
 289         psci {
 290                 compatible      = "arm,psci";
 291                 method          = "smc";
 292                 cpu_suspend     = <0x80100001>;
 293                 cpu_off         = <0x80100002>;
 294                 cpu_on          = <0x80100003>;
 295                 migrate         = <0x80100004>;
 296         };
 297
 298         dcc {
 299                 compatible = "arm,vexpress,config-bus";
 300                 arm,vexpress,config-bridge = <&v2m_sysreg>;
 301
 302                 osc@0 {
 303                         /* A15 PLL 0 reference clock */
 304                         compatible = "arm,vexpress-osc";
 305                         arm,vexpress-sysreg,func = <1 0>;
 306                         freq-range = <17000000 50000000>;
 307                         #clock-cells = <0>;
 308                         clock-output-names = "oscclk0";
 309                 };
 310
 311                 osc@1 {
 312                         /* A15 PLL 1 reference clock */
 313                         compatible = "arm,vexpress-osc";
 314                         arm,vexpress-sysreg,func = <1 1>;
 315                         freq-range = <17000000 50000000>;
 316                         #clock-cells = <0>;
 317                         clock-output-names = "oscclk1";
 318                 };
 319
 320                 osc@2 {
 321                         /* A7 PLL 0 reference clock */
 322                         compatible = "arm,vexpress-osc";
 323                         arm,vexpress-sysreg,func = <1 2>;
 324                         freq-range = <17000000 50000000>;
 325                         #clock-cells = <0>;
 326                         clock-output-names = "oscclk2";
 327                 };
 328
 329                 osc@3 {
 330                         /* A7 PLL 1 reference clock */
 331                         compatible = "arm,vexpress-osc";
 332                         arm,vexpress-sysreg,func = <1 3>;
 333                         freq-range = <17000000 50000000>;
 334                         #clock-cells = <0>;
 335                         clock-output-names = "oscclk3";
 336                 };
 337
 338                 osc@4 {
 339                         /* External AXI master clock */
 340                         compatible = "arm,vexpress-osc";
 341                         arm,vexpress-sysreg,func = <1 4>;
 342                         freq-range = <20000000 40000000>;
 343                         #clock-cells = <0>;
 344                         clock-output-names = "oscclk4";
 345                 };
 346
 347                 oscclk5: osc@5 {
 348                         /* HDLCD PLL reference clock */
 349                         compatible = "arm,vexpress-osc";
 350                         arm,vexpress-sysreg,func = <1 5>;
 351                         freq-range = <23750000 165000000>;
 352                         #clock-cells = <0>;
 353                         clock-output-names = "oscclk5";
 354                 };
 355
 356                 smbclk: osc@6 {
 357                         /* Static memory controller clock */
 358                         compatible = "arm,vexpress-osc";
 359                         arm,vexpress-sysreg,func = <1 6>;
 360                         freq-range = <20000000 40000000>;
 361                         #clock-cells = <0>;
 362                         clock-output-names = "oscclk6";
 363                 };
 364
 365                 osc@7 {
 366                         /* SYS PLL reference clock */
 367                         compatible = "arm,vexpress-osc";
 368                         arm,vexpress-sysreg,func = <1 7>;
 369                         freq-range = <17000000 50000000>;
 370                         #clock-cells = <0>;
 371                         clock-output-names = "oscclk7";
 372                 };
 373
 374                 osc@8 {
 375                         /* DDR2 PLL reference clock */
 376                         compatible = "arm,vexpress-osc";
 377                         arm,vexpress-sysreg,func = <1 8>;
 378                         freq-range = <20000000 50000000>;
 379                         #clock-cells = <0>;
 380                         clock-output-names = "oscclk8";
 381                 };
 382
 383                 volt@0 {
 384                         /* A15 CPU core voltage */
 385                         compatible = "arm,vexpress-volt";
 386                         arm,vexpress-sysreg,func = <2 0>;
 387                         regulator-name = "A15 Vcore";
 388                         regulator-min-microvolt = <800000>;
 389                         regulator-max-microvolt = <1050000>;
 390                         regulator-always-on;
 391                         label = "A15 Vcore";
 392                 };
 393
 394                 volt@1 {
 395                         /* A7 CPU core voltage */
 396                         compatible = "arm,vexpress-volt";
 397                         arm,vexpress-sysreg,func = <2 1>;
 398                         regulator-name = "A7 Vcore";
 399                         regulator-min-microvolt = <800000>;
 400                         regulator-max-microvolt = <1050000>;
 401                         regulator-always-on;
 402                         label = "A7 Vcore";
 403                 };
 404
 405                 amp@0 {
 406                         /* Total current for the two A15 cores */
 407                         compatible = "arm,vexpress-amp";
 408                         arm,vexpress-sysreg,func = <3 0>;
 409                         label = "A15 Icore";
 410                 };
 411
 412                 amp@1 {
 413                         /* Total current for the three A7 cores */
 414                         compatible = "arm,vexpress-amp";
 415                         arm,vexpress-sysreg,func = <3 1>;
 416                         label = "A7 Icore";
 417                 };
 418
 419                 temp@0 {
 420                         /* DCC internal temperature */
 421                         compatible = "arm,vexpress-temp";
 422                         arm,vexpress-sysreg,func = <4 0>;
 423                         label = "DCC";
 424                 };
 425
 426                 power@0 {
 427                         /* Total power for the two A15 cores */
 428                         compatible = "arm,vexpress-power";
 429                         arm,vexpress-sysreg,func = <12 0>;
 430                         label = "A15 Pcore";
 431                 };
 432                 power@1 {
 433                         /* Total power for the three A7 cores */
 434                         compatible = "arm,vexpress-power";
 435                         arm,vexpress-sysreg,func = <12 1>;
 436                         label = "A7 Pcore";
 437                 };
 438
 439                 energy@0 {
 440                         /* Total energy for the two A15 cores */
 441                         compatible = "arm,vexpress-energy";
 442                         arm,vexpress-sysreg,func = <13 0>;
 443                         label = "A15 Jcore";
 444                 };
 445
 446                 energy@2 {
 447                         /* Total energy for the three A7 cores */
 448                         compatible = "arm,vexpress-energy";
 449                         arm,vexpress-sysreg,func = <13 2>;
 450                         label = "A7 Jcore";
 451                 };
 452         };
 453
 454         smb {
 455                 compatible = "simple-bus";
 456
 457                 #address-cells = <2>;
 458                 #size-cells = <1>;
 459                 ranges = <0 0 0 0x08000000 0x04000000>,
 460                          <1 0 0 0x14000000 0x04000000>,
 461                          <2 0 0 0x18000000 0x04000000>,
 462                          <3 0 0 0x1c000000 0x04000000>,
 463                          <4 0 0 0x0c000000 0x04000000>,
 464                          <5 0 0 0x10000000 0x04000000>;
 465
 466                 #interrupt-cells = <1>;
 467                 interrupt-map-mask = <0 0 63>;
 468                 interrupt-map = <0 0  0 &gic 0  0 4>,
 469                                 <0 0  1 &gic 0  1 4>,
 470                                 <0 0  2 &gic 0  2 4>,
 471                                 <0 0  3 &gic 0  3 4>,
 472                                 <0 0  4 &gic 0  4 4>,
 473                                 <0 0  5 &gic 0  5 4>,
 474                                 <0 0  6 &gic 0  6 4>,
 475                                 <0 0  7 &gic 0  7 4>,
 476                                 <0 0  8 &gic 0  8 4>,
 477                                 <0 0  9 &gic 0  9 4>,
 478                                 <0 0 10 &gic 0 10 4>,
 479                                 <0 0 11 &gic 0 11 4>,
 480                                 <0 0 12 &gic 0 12 4>,
 481                                 <0 0 13 &gic 0 13 4>,
 482                                 <0 0 14 &gic 0 14 4>,
 483                                 <0 0 15 &gic 0 15 4>,
 484                                 <0 0 16 &gic 0 16 4>,
 485                                 <0 0 17 &gic 0 17 4>,
 486                                 <0 0 18 &gic 0 18 4>,
 487                                 <0 0 19 &gic 0 19 4>,
 488                                 <0 0 20 &gic 0 20 4>,
 489                                 <0 0 21 &gic 0 21 4>,
 490                                 <0 0 22 &gic 0 22 4>,
 491                                 <0 0 23 &gic 0 23 4>,
 492                                 <0 0 24 &gic 0 24 4>,
 493                                 <0 0 25 &gic 0 25 4>,
 494                                 <0 0 26 &gic 0 26 4>,
 495                                 <0 0 27 &gic 0 27 4>,
 496                                 <0 0 28 &gic 0 28 4>,
 497                                 <0 0 29 &gic 0 29 4>,
 498                                 <0 0 30 &gic 0 30 4>,
 499                                 <0 0 31 &gic 0 31 4>,
 500                                 <0 0 32 &gic 0 32 4>,
 501                                 <0 0 33 &gic 0 33 4>,
 502                                 <0 0 34 &gic 0 34 4>,
 503                                 <0 0 35 &gic 0 35 4>,
 504                                 <0 0 36 &gic 0 36 4>,
 505                                 <0 0 37 &gic 0 37 4>,
 506                                 <0 0 38 &gic 0 38 4>,
 507                                 <0 0 39 &gic 0 39 4>,
 508                                 <0 0 40 &gic 0 40 4>,
 509                                 <0 0 41 &gic 0 41 4>,
 510                                 <0 0 42 &gic 0 42 4>;
 511
 512                 /include/ "vexpress-v2m-rs1.dtsi"
 513         };
 514 };