arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts

   1 /*
   2  * ARM Ltd. Versatile Express
   3  *
   4  * CoreTile Express A15x2 (version with Test Chip 1)
   5  * Cortex-A15 MPCore (V2P-CA15)
   6  *
   7  * HBI-0237A
   8  */
   9
  10 /dts-v1/;
  11
  12 /memreserve/ 0xbf000000 0x01000000;
  13
  14 / {
  15         model = "V2P-CA15";
  16         arm,hbi = <0x237>;
  17         arm,vexpress,site = <0xf>;
  18         compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         chosen { };
  24
  25         aliases {
  26                 serial0 = &v2m_serial0;
  27                 serial1 = &v2m_serial1;
  28                 serial2 = &v2m_serial2;
  29                 serial3 = &v2m_serial3;
  30                 i2c0 = &v2m_i2c_dvi;
  31                 i2c1 = &v2m_i2c_pcie;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a15";
  41                         reg = <0>;
  42                 };
  43
  44                 cpu@1 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a15";
  47                         reg = <1>;
  48                 };
  49         };
  50
  51         memory@80000000 {
  52                 device_type = "memory";
  53                 reg = <0 0x80000000 0 0x40000000>;
  54         };
  55
  56         hdlcd@2b000000 {
  57                 compatible = "arm,hdlcd";
  58                 reg = <0 0x2b000000 0 0x1000>;
  59                 interrupts = <0 85 4>;
  60                 clocks = <&oscclk5>;
  61                 clock-names = "pxlclk";
  62                 mode = "1024x768-16@60";
  63                 framebuffer = <0 0xff000000 0 0x01000000>;
  64         };
  65
  66         memory-controller@2b0a0000 {
  67                 compatible = "arm,pl341", "arm,primecell";
  68                 reg = <0 0x2b0a0000 0 0x1000>;
  69                 clocks = <&oscclk7>;
  70                 clock-names = "apb_pclk";
  71         };
  72
  73         wdt@2b060000 {
  74                 compatible = "arm,sp805", "arm,primecell";
  75                 status = "disabled";
  76                 reg = <0 0x2b060000 0 0x1000>;
  77                 interrupts = <0 98 4>;
  78                 clocks = <&oscclk7>;
  79                 clock-names = "apb_pclk";
  80         };
  81
  82         gic: interrupt-controller@2c001000 {
  83                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  84                 #interrupt-cells = <3>;
  85                 #address-cells = <0>;
  86                 interrupt-controller;
  87                 reg = <0 0x2c001000 0 0x1000>,
  88                       <0 0x2c002000 0 0x1000>,
  89                       <0 0x2c004000 0 0x2000>,
  90                       <0 0x2c006000 0 0x2000>;
  91                 interrupts = <1 9 0xf04>;
  92         };
  93
  94         memory-controller@7ffd0000 {
  95                 compatible = "arm,pl354", "arm,primecell";
  96                 reg = <0 0x7ffd0000 0 0x1000>;
  97                 interrupts = <0 86 4>,
  98                              <0 87 4>;
  99                 clocks = <&oscclk7>;
 100                 clock-names = "apb_pclk";
 101         };
 102
 103         dma@7ffb0000 {
 104                 compatible = "arm,pl330", "arm,primecell";
 105                 reg = <0 0x7ffb0000 0 0x1000>;
 106                 interrupts = <0 92 4>,
 107                              <0 88 4>,
 108                              <0 89 4>,
 109                              <0 90 4>,
 110                              <0 91 4>;
 111                 clocks = <&oscclk7>;
 112                 clock-names = "apb_pclk";
 113         };
 114
 115         timer {
 116                 compatible = "arm,armv7-timer";
 117                 interrupts = <1 13 0xf08>,
 118                              <1 14 0xf08>,
 119                              <1 11 0xf08>,
 120                              <1 10 0xf08>;
 121         };
 122
 123         pmu {
 124                 compatible = "arm,cortex-a15-pmu";
 125                 interrupts = <0 68 4>,
 126                              <0 69 4>;
 127         };
 128
 129         dcc {
 130                 compatible = "arm,vexpress,config-bus";
 131                 arm,vexpress,config-bridge = <&v2m_sysreg>;
 132
 133                 osc@0 {
 134                         /* CPU PLL reference clock */
 135                         compatible = "arm,vexpress-osc";
 136                         arm,vexpress-sysreg,func = <1 0>;
 137                         freq-range = <50000000 60000000>;
 138                         #clock-cells = <0>;
 139                         clock-output-names = "oscclk0";
 140                 };
 141
 142                 osc@4 {
 143                         /* Multiplexed AXI master clock */
 144                         compatible = "arm,vexpress-osc";
 145                         arm,vexpress-sysreg,func = <1 4>;
 146                         freq-range = <20000000 40000000>;
 147                         #clock-cells = <0>;
 148                         clock-output-names = "oscclk4";
 149                 };
 150
 151                 oscclk5: osc@5 {
 152                         /* HDLCD PLL reference clock */
 153                         compatible = "arm,vexpress-osc";
 154                         arm,vexpress-sysreg,func = <1 5>;
 155                         freq-range = <23750000 165000000>;
 156                         #clock-cells = <0>;
 157                         clock-output-names = "oscclk5";
 158                 };
 159
 160                 smbclk: osc@6 {
 161                         /* SMB clock */
 162                         compatible = "arm,vexpress-osc";
 163                         arm,vexpress-sysreg,func = <1 6>;
 164                         freq-range = <20000000 50000000>;
 165                         #clock-cells = <0>;
 166                         clock-output-names = "oscclk6";
 167                 };
 168
 169                 oscclk7: osc@7 {
 170                         /* SYS PLL reference clock */
 171                         compatible = "arm,vexpress-osc";
 172                         arm,vexpress-sysreg,func = <1 7>;
 173                         freq-range = <20000000 60000000>;
 174                         #clock-cells = <0>;
 175                         clock-output-names = "oscclk7";
 176                 };
 177
 178                 osc@8 {
 179                         /* DDR2 PLL reference clock */
 180                         compatible = "arm,vexpress-osc";
 181                         arm,vexpress-sysreg,func = <1 8>;
 182                         freq-range = <40000000 40000000>;
 183                         #clock-cells = <0>;
 184                         clock-output-names = "oscclk8";
 185                 };
 186
 187                 volt@0 {
 188                         /* CPU core voltage */
 189                         compatible = "arm,vexpress-volt";
 190                         arm,vexpress-sysreg,func = <2 0>;
 191                         regulator-name = "Cores";
 192                         regulator-min-microvolt = <800000>;
 193                         regulator-max-microvolt = <1050000>;
 194                         regulator-always-on;
 195                         label = "Cores";
 196                 };
 197
 198                 amp@0 {
 199                         /* Total current for the two cores */
 200                         compatible = "arm,vexpress-amp";
 201                         arm,vexpress-sysreg,func = <3 0>;
 202                         label = "Cores";
 203                 };
 204
 205                 temp@0 {
 206                         /* DCC internal temperature */
 207                         compatible = "arm,vexpress-temp";
 208                         arm,vexpress-sysreg,func = <4 0>;
 209                         label = "DCC";
 210                 };
 211
 212                 power@0 {
 213                         /* Total power */
 214                         compatible = "arm,vexpress-power";
 215                         arm,vexpress-sysreg,func = <12 0>;
 216                         label = "Cores";
 217                 };
 218
 219                 energy@0 {
 220                         /* Total energy */
 221                         compatible = "arm,vexpress-energy";
 222                         arm,vexpress-sysreg,func = <13 0>;
 223                         label = "Cores";
 224                 };
 225         };
 226
 227         smb {
 228                 compatible = "simple-bus";
 229
 230                 #address-cells = <2>;
 231                 #size-cells = <1>;
 232                 ranges = <0 0 0 0x08000000 0x04000000>,
 233                          <1 0 0 0x14000000 0x04000000>,
 234                          <2 0 0 0x18000000 0x04000000>,
 235                          <3 0 0 0x1c000000 0x04000000>,
 236                          <4 0 0 0x0c000000 0x04000000>,
 237                          <5 0 0 0x10000000 0x04000000>;
 238
 239                 #interrupt-cells = <1>;
 240                 interrupt-map-mask = <0 0 63>;
 241                 interrupt-map = <0 0  0 &gic 0  0 4>,
 242                                 <0 0  1 &gic 0  1 4>,
 243                                 <0 0  2 &gic 0  2 4>,
 244                                 <0 0  3 &gic 0  3 4>,
 245                                 <0 0  4 &gic 0  4 4>,
 246                                 <0 0  5 &gic 0  5 4>,
 247                                 <0 0  6 &gic 0  6 4>,
 248                                 <0 0  7 &gic 0  7 4>,
 249                                 <0 0  8 &gic 0  8 4>,
 250                                 <0 0  9 &gic 0  9 4>,
 251                                 <0 0 10 &gic 0 10 4>,
 252                                 <0 0 11 &gic 0 11 4>,
 253                                 <0 0 12 &gic 0 12 4>,
 254                                 <0 0 13 &gic 0 13 4>,
 255                                 <0 0 14 &gic 0 14 4>,
 256                                 <0 0 15 &gic 0 15 4>,
 257                                 <0 0 16 &gic 0 16 4>,
 258                                 <0 0 17 &gic 0 17 4>,
 259                                 <0 0 18 &gic 0 18 4>,
 260                                 <0 0 19 &gic 0 19 4>,
 261                                 <0 0 20 &gic 0 20 4>,
 262                                 <0 0 21 &gic 0 21 4>,
 263                                 <0 0 22 &gic 0 22 4>,
 264                                 <0 0 23 &gic 0 23 4>,
 265                                 <0 0 24 &gic 0 24 4>,
 266                                 <0 0 25 &gic 0 25 4>,
 267                                 <0 0 26 &gic 0 26 4>,
 268                                 <0 0 27 &gic 0 27 4>,
 269                                 <0 0 28 &gic 0 28 4>,
 270                                 <0 0 29 &gic 0 29 4>,
 271                                 <0 0 30 &gic 0 30 4>,
 272                                 <0 0 31 &gic 0 31 4>,
 273                                 <0 0 32 &gic 0 32 4>,
 274                                 <0 0 33 &gic 0 33 4>,
 275                                 <0 0 34 &gic 0 34 4>,
 276                                 <0 0 35 &gic 0 35 4>,
 277                                 <0 0 36 &gic 0 36 4>,
 278                                 <0 0 37 &gic 0 37 4>,
 279                                 <0 0 38 &gic 0 38 4>,
 280                                 <0 0 39 &gic 0 39 4>,
 281                                 <0 0 40 &gic 0 40 4>,
 282                                 <0 0 41 &gic 0 41 4>,
 283                                 <0 0 42 &gic 0 42 4>;
 284
 285                 /include/ "vexpress-v2m-rs1.dtsi"
 286         };
 287 };