arch/arm/boot/dts/sun4i-a10.dtsi

   1 /*
   2  * Copyright 2012 Stefan Roese
   3  * Stefan Roese <sr@denx.de>
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /include/ "skeleton.dtsi"
  14
  15 / {
  16         interrupt-parent = <&intc>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21                 cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a8";
  24                         reg = <0x0>;
  25                 };
  26         };
  27
  28         memory {
  29                 reg = <0x40000000 0x80000000>;
  30         };
  31
  32         clocks {
  33                 #address-cells = <1>;
  34                 #size-cells = <1>;
  35                 ranges;
  36
  37                 /*
  38                  * This is a dummy clock, to be used as placeholder on
  39                  * other mux clocks when a specific parent clock is not
  40                  * yet implemented. It should be dropped when the driver
  41                  * is complete.
  42                  */
  43                 dummy: dummy {
  44                         #clock-cells = <0>;
  45                         compatible = "fixed-clock";
  46                         clock-frequency = <0>;
  47                 };
  48
  49                 osc24M: osc24M@01c20050 {
  50                         #clock-cells = <0>;
  51                         compatible = "allwinner,sun4i-osc-clk";
  52                         reg = <0x01c20050 0x4>;
  53                         clock-frequency = <24000000>;
  54                 };
  55
  56                 osc32k: osc32k {
  57                         #clock-cells = <0>;
  58                         compatible = "fixed-clock";
  59                         clock-frequency = <32768>;
  60                 };
  61
  62                 pll1: pll1@01c20000 {
  63                         #clock-cells = <0>;
  64                         compatible = "allwinner,sun4i-pll1-clk";
  65                         reg = <0x01c20000 0x4>;
  66                         clocks = <&osc24M>;
  67                 };
  68
  69                 /* dummy is 200M */
  70                 cpu: cpu@01c20054 {
  71                         #clock-cells = <0>;
  72                         compatible = "allwinner,sun4i-cpu-clk";
  73                         reg = <0x01c20054 0x4>;
  74                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
  75                 };
  76
  77                 axi: axi@01c20054 {
  78                         #clock-cells = <0>;
  79                         compatible = "allwinner,sun4i-axi-clk";
  80                         reg = <0x01c20054 0x4>;
  81                         clocks = <&cpu>;
  82                 };
  83
  84                 axi_gates: axi_gates@01c2005c {
  85                         #clock-cells = <1>;
  86                         compatible = "allwinner,sun4i-axi-gates-clk";
  87                         reg = <0x01c2005c 0x4>;
  88                         clocks = <&axi>;
  89                         clock-output-names = "axi_dram";
  90                 };
  91
  92                 ahb: ahb@01c20054 {
  93                         #clock-cells = <0>;
  94                         compatible = "allwinner,sun4i-ahb-clk";
  95                         reg = <0x01c20054 0x4>;
  96                         clocks = <&axi>;
  97                 };
  98
  99                 ahb_gates: ahb_gates@01c20060 {
 100                         #clock-cells = <1>;
 101                         compatible = "allwinner,sun4i-ahb-gates-clk";
 102                         reg = <0x01c20060 0x8>;
 103                         clocks = <&ahb>;
 104                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 105                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
 106                                 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
 107                                 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
 108                                 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
 109                                 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
 110                                 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
 111                                 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
 112                                 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
 113                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 114                                 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
 115                 };
 116
 117                 apb0: apb0@01c20054 {
 118                         #clock-cells = <0>;
 119                         compatible = "allwinner,sun4i-apb0-clk";
 120                         reg = <0x01c20054 0x4>;
 121                         clocks = <&ahb>;
 122                 };
 123
 124                 apb0_gates: apb0_gates@01c20068 {
 125                         #clock-cells = <1>;
 126                         compatible = "allwinner,sun4i-apb0-gates-clk";
 127                         reg = <0x01c20068 0x4>;
 128                         clocks = <&apb0>;
 129                         clock-output-names = "apb0_codec", "apb0_spdif",
 130                                 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
 131                                 "apb0_ir1", "apb0_keypad";
 132                 };
 133
 134                 /* dummy is pll62 */
 135                 apb1_mux: apb1_mux@01c20058 {
 136                         #clock-cells = <0>;
 137                         compatible = "allwinner,sun4i-apb1-mux-clk";
 138                         reg = <0x01c20058 0x4>;
 139                         clocks = <&osc24M>, <&dummy>, <&osc32k>;
 140                 };
 141
 142                 apb1: apb1@01c20058 {
 143                         #clock-cells = <0>;
 144                         compatible = "allwinner,sun4i-apb1-clk";
 145                         reg = <0x01c20058 0x4>;
 146                         clocks = <&apb1_mux>;
 147                 };
 148
 149                 apb1_gates: apb1_gates@01c2006c {
 150                         #clock-cells = <1>;
 151                         compatible = "allwinner,sun4i-apb1-gates-clk";
 152                         reg = <0x01c2006c 0x4>;
 153                         clocks = <&apb1>;
 154                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 155                                 "apb1_i2c2", "apb1_can", "apb1_scr",
 156                                 "apb1_ps20", "apb1_ps21", "apb1_uart0",
 157                                 "apb1_uart1", "apb1_uart2", "apb1_uart3",
 158                                 "apb1_uart4", "apb1_uart5", "apb1_uart6",
 159                                 "apb1_uart7";
 160                 };
 161         };
 162
 163         soc@01c20000 {
 164                 compatible = "simple-bus";
 165                 #address-cells = <1>;
 166                 #size-cells = <1>;
 167                 reg = <0x01c20000 0x300000>;
 168                 ranges;
 169
 170                 intc: interrupt-controller@01c20400 {
 171                         compatible = "allwinner,sun4i-ic";
 172                         reg = <0x01c20400 0x400>;
 173                         interrupt-controller;
 174                         #interrupt-cells = <1>;
 175                 };
 176
 177                 pio: pinctrl@01c20800 {
 178                         compatible = "allwinner,sun4i-a10-pinctrl";
 179                         reg = <0x01c20800 0x400>;
 180                         clocks = <&apb0_gates 5>;
 181                         gpio-controller;
 182                         #address-cells = <1>;
 183                         #size-cells = <0>;
 184                         #gpio-cells = <3>;
 185
 186                         uart0_pins_a: uart0@0 {
 187                                 allwinner,pins = "PB22", "PB23";
 188                                 allwinner,function = "uart0";
 189                                 allwinner,drive = <0>;
 190                                 allwinner,pull = <0>;
 191                         };
 192
 193                         uart0_pins_b: uart0@1 {
 194                                 allwinner,pins = "PF2", "PF4";
 195                                 allwinner,function = "uart0";
 196                                 allwinner,drive = <0>;
 197                                 allwinner,pull = <0>;
 198                         };
 199
 200                         uart1_pins_a: uart1@0 {
 201                                 allwinner,pins = "PA10", "PA11";
 202                                 allwinner,function = "uart1";
 203                                 allwinner,drive = <0>;
 204                                 allwinner,pull = <0>;
 205                         };
 206                 };
 207
 208                 timer@01c20c00 {
 209                         compatible = "allwinner,sun4i-timer";
 210                         reg = <0x01c20c00 0x90>;
 211                         interrupts = <22>;
 212                         clocks = <&osc24M>;
 213                 };
 214
 215                 wdt: watchdog@01c20c90 {
 216                         compatible = "allwinner,sun4i-wdt";
 217                         reg = <0x01c20c90 0x10>;
 218                 };
 219
 220                 uart0: serial@01c28000 {
 221                         compatible = "snps,dw-apb-uart";
 222                         reg = <0x01c28000 0x400>;
 223                         interrupts = <1>;
 224                         reg-shift = <2>;
 225                         reg-io-width = <4>;
 226                         clocks = <&apb1_gates 16>;
 227                         status = "disabled";
 228                 };
 229
 230                 uart1: serial@01c28400 {
 231                         compatible = "snps,dw-apb-uart";
 232                         reg = <0x01c28400 0x400>;
 233                         interrupts = <2>;
 234                         reg-shift = <2>;
 235                         reg-io-width = <4>;
 236                         clocks = <&apb1_gates 17>;
 237                         status = "disabled";
 238                 };
 239
 240                 uart2: serial@01c28800 {
 241                         compatible = "snps,dw-apb-uart";
 242                         reg = <0x01c28800 0x400>;
 243                         interrupts = <3>;
 244                         reg-shift = <2>;
 245                         reg-io-width = <4>;
 246                         clocks = <&apb1_gates 18>;
 247                         status = "disabled";
 248                 };
 249
 250                 uart3: serial@01c28c00 {
 251                         compatible = "snps,dw-apb-uart";
 252                         reg = <0x01c28c00 0x400>;
 253                         interrupts = <4>;
 254                         reg-shift = <2>;
 255                         reg-io-width = <4>;
 256                         clocks = <&apb1_gates 19>;
 257                         status = "disabled";
 258                 };
 259
 260                 uart4: serial@01c29000 {
 261                         compatible = "snps,dw-apb-uart";
 262                         reg = <0x01c29000 0x400>;
 263                         interrupts = <17>;
 264                         reg-shift = <2>;
 265                         reg-io-width = <4>;
 266                         clocks = <&apb1_gates 20>;
 267                         status = "disabled";
 268                 };
 269
 270                 uart5: serial@01c29400 {
 271                         compatible = "snps,dw-apb-uart";
 272                         reg = <0x01c29400 0x400>;
 273                         interrupts = <18>;
 274                         reg-shift = <2>;
 275                         reg-io-width = <4>;
 276                         clocks = <&apb1_gates 21>;
 277                         status = "disabled";
 278                 };
 279
 280                 uart6: serial@01c29800 {
 281                         compatible = "snps,dw-apb-uart";
 282                         reg = <0x01c29800 0x400>;
 283                         interrupts = <19>;
 284                         reg-shift = <2>;
 285                         reg-io-width = <4>;
 286                         clocks = <&apb1_gates 22>;
 287                         status = "disabled";
 288                 };
 289
 290                 uart7: serial@01c29c00 {
 291                         compatible = "snps,dw-apb-uart";
 292                         reg = <0x01c29c00 0x400>;
 293                         interrupts = <20>;
 294                         reg-shift = <2>;
 295                         reg-io-width = <4>;
 296                         clocks = <&apb1_gates 23>;
 297                         status = "disabled";
 298                 };
 299         };
 300 };