arch/arm/boot/dts/rtsm_ve-motherboard.dtsi

   1 /*
   2  * ARM Ltd. Fast Models
   3  *
   4  * Versatile Express (VE) system model
   5  * Motherboard component
   6  *
   7  * VEMotherBoard.lisa
   8  */
   9
  10         motherboard {
  11                 compatible = "arm,vexpress,v2m-p1", "simple-bus";
  12                 arm,hbi = <0x190>;
  13                 arm,vexpress,site = <0>;
  14                 arm,v2m-memory-map = "rs1";
  15                 #address-cells = <2>; /* SMB chipselect number and offset */
  16                 #size-cells = <1>;
  17                 #interrupt-cells = <1>;
  18                 ranges;
  19
  20                 flash@0,00000000 {
  21                         compatible = "arm,vexpress-flash", "cfi-flash";
  22                         reg = <0 0x00000000 0x04000000>,
  23                               <4 0x00000000 0x04000000>;
  24                         bank-width = <4>;
  25                 };
  26
  27                 vram@2,00000000 {
  28                         compatible = "arm,vexpress-vram";
  29                         reg = <2 0x00000000 0x00800000>;
  30                 };
  31
  32                 ethernet@2,02000000 {
  33                         compatible = "smsc,lan91c111";
  34                         reg = <2 0x02000000 0x10000>;
  35                         interrupts = <15>;
  36                 };
  37
  38                 iofpga@3,00000000 {
  39                         compatible = "arm,amba-bus", "simple-bus";
  40                         #address-cells = <1>;
  41                         #size-cells = <1>;
  42                         ranges = <0 3 0 0x200000>;
  43
  44                         v2m_sysreg: sysreg@010000 {
  45                                 compatible = "arm,vexpress-sysreg";
  46                                 reg = <0x010000 0x1000>;
  47                                 gpio-controller;
  48                                 #gpio-cells = <2>;
  49                         };
  50
  51                         v2m_sysctl: sysctl@020000 {
  52                                 compatible = "arm,sp810", "arm,primecell";
  53                                 reg = <0x020000 0x1000>;
  54                                 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
  55                                 clock-names = "refclk", "timclk", "apb_pclk";
  56                                 #clock-cells = <1>;
  57                                 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
  58                         };
  59
  60                         aaci@040000 {
  61                                 compatible = "arm,pl041", "arm,primecell";
  62                                 reg = <0x040000 0x1000>;
  63                                 interrupts = <11>;
  64                                 clocks = <&smbclk>;
  65                                 clock-names = "apb_pclk";
  66                         };
  67
  68                         mmci@050000 {
  69                                 compatible = "arm,pl180", "arm,primecell";
  70                                 reg = <0x050000 0x1000>;
  71                                 interrupts = <9 10>;
  72                                 cd-gpios = <&v2m_sysreg 0 0>;
  73                                 wp-gpios = <&v2m_sysreg 1 0>;
  74                                 max-frequency = <12000000>;
  75                                 vmmc-supply = <&v2m_fixed_3v3>;
  76                                 clocks = <&v2m_clk24mhz>, <&smbclk>;
  77                                 clock-names = "mclk", "apb_pclk";
  78                         };
  79
  80                         kmi@060000 {
  81                                 compatible = "arm,pl050", "arm,primecell";
  82                                 reg = <0x060000 0x1000>;
  83                                 interrupts = <12>;
  84                                 clocks = <&v2m_clk24mhz>, <&smbclk>;
  85                                 clock-names = "KMIREFCLK", "apb_pclk";
  86                         };
  87
  88                         kmi@070000 {
  89                                 compatible = "arm,pl050", "arm,primecell";
  90                                 reg = <0x070000 0x1000>;
  91                                 interrupts = <13>;
  92                                 clocks = <&v2m_clk24mhz>, <&smbclk>;
  93                                 clock-names = "KMIREFCLK", "apb_pclk";
  94                         };
  95
  96                         v2m_serial0: uart@090000 {
  97                                 compatible = "arm,pl011", "arm,primecell";
  98                                 reg = <0x090000 0x1000>;
  99                                 interrupts = <5>;
 100                                 clocks = <&v2m_clk24mhz>, <&smbclk>;
 101                                 clock-names = "uartclk", "apb_pclk";
 102                         };
 103
 104                         v2m_serial1: uart@0a0000 {
 105                                 compatible = "arm,pl011", "arm,primecell";
 106                                 reg = <0x0a0000 0x1000>;
 107                                 interrupts = <6>;
 108                                 clocks = <&v2m_clk24mhz>, <&smbclk>;
 109                                 clock-names = "uartclk", "apb_pclk";
 110                         };
 111
 112                         v2m_serial2: uart@0b0000 {
 113                                 compatible = "arm,pl011", "arm,primecell";
 114                                 reg = <0x0b0000 0x1000>;
 115                                 interrupts = <7>;
 116                                 clocks = <&v2m_clk24mhz>, <&smbclk>;
 117                                 clock-names = "uartclk", "apb_pclk";
 118                         };
 119
 120                         v2m_serial3: uart@0c0000 {
 121                                 compatible = "arm,pl011", "arm,primecell";
 122                                 reg = <0x0c0000 0x1000>;
 123                                 interrupts = <8>;
 124                                 clocks = <&v2m_clk24mhz>, <&smbclk>;
 125                                 clock-names = "uartclk", "apb_pclk";
 126                         };
 127
 128                         wdt@0f0000 {
 129                                 compatible = "arm,sp805", "arm,primecell";
 130                                 reg = <0x0f0000 0x1000>;
 131                                 interrupts = <0>;
 132                                 clocks = <&v2m_refclk32khz>, <&smbclk>;
 133                                 clock-names = "wdogclk", "apb_pclk";
 134                         };
 135
 136                         v2m_timer01: timer@110000 {
 137                                 compatible = "arm,sp804", "arm,primecell";
 138                                 reg = <0x110000 0x1000>;
 139                                 interrupts = <2>;
 140                                 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
 141                                 clock-names = "timclken1", "timclken2", "apb_pclk";
 142                         };
 143
 144                         v2m_timer23: timer@120000 {
 145                                 compatible = "arm,sp804", "arm,primecell";
 146                                 reg = <0x120000 0x1000>;
 147                                 interrupts = <3>;
 148                                 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
 149                                 clock-names = "timclken1", "timclken2", "apb_pclk";
 150                         };
 151
 152                         rtc@170000 {
 153                                 compatible = "arm,pl031", "arm,primecell";
 154                                 reg = <0x170000 0x1000>;
 155                                 interrupts = <4>;
 156                                 clocks = <&smbclk>;
 157                                 clock-names = "apb_pclk";
 158                         };
 159
 160                         clcd@1f0000 {
 161                                 compatible = "arm,pl111", "arm,primecell";
 162                                 reg = <0x1f0000 0x1000>;
 163                                 interrupts = <14>;
 164                                 clocks = <&v2m_oscclk1>, <&smbclk>;
 165                                 clock-names = "v2m:oscclk1", "apb_pclk";
 166                                 mode = "VGA";
 167                                 use_dma = <0>;
 168                                 framebuffer = <0x18000000 0x00180000>;
 169                         };
 170
 171                         virtio_block@0130000 {
 172                                 compatible = "virtio,mmio";
 173                                 reg = <0x130000 0x200>;
 174                                 interrupts = <42>;
 175                         };
 176
 177                 };
 178
 179                 v2m_fixed_3v3: fixedregulator@0 {
 180                         compatible = "regulator-fixed";
 181                         regulator-name = "3V3";
 182                         regulator-min-microvolt = <3300000>;
 183                         regulator-max-microvolt = <3300000>;
 184                         regulator-always-on;
 185                 };
 186
 187                 v2m_clk24mhz: clk24mhz {
 188                         compatible = "fixed-clock";
 189                         #clock-cells = <0>;
 190                         clock-frequency = <24000000>;
 191                         clock-output-names = "v2m:clk24mhz";
 192                 };
 193
 194                 v2m_refclk1mhz: refclk1mhz {
 195                         compatible = "fixed-clock";
 196                         #clock-cells = <0>;
 197                         clock-frequency = <1000000>;
 198                         clock-output-names = "v2m:refclk1mhz";
 199                 };
 200
 201                 v2m_refclk32khz: refclk32khz {
 202                         compatible = "fixed-clock";
 203                         #clock-cells = <0>;
 204                         clock-frequency = <32768>;
 205                         clock-output-names = "v2m:refclk32khz";
 206                 };
 207
 208                 mcc {
 209                         compatible = "simple-bus";
 210                         arm,vexpress,config-bridge = <&v2m_sysreg>;
 211
 212                         v2m_oscclk1: osc@1 {
 213                                 /* CLCD clock */
 214                                 compatible = "arm,vexpress-osc";
 215                                 arm,vexpress-sysreg,func = <1 1>;
 216                                 freq-range = <23750000 63500000>;
 217                                 #clock-cells = <0>;
 218                                 clock-output-names = "v2m:oscclk1";
 219                         };
 220
 221                         muxfpga@0 {
 222                                 compatible = "arm,vexpress-muxfpga";
 223                                 arm,vexpress-sysreg,func = <7 0>;
 224                         };
 225
 226                         shutdown@0 {
 227                                 compatible = "arm,vexpress-shutdown";
 228                                 arm,vexpress-sysreg,func = <8 0>;
 229                         };
 230                 };
 231         };