arch/arm/boot/dts/rtsm_ve-cortex_a15x1.dts

   1 /*
   2  * ARM Ltd. Fast Models
   3  *
   4  * Versatile Express (VE) system model
   5  * ARMCortexA15x1CT
   6  *
   7  * RTSM_VE_Cortex_A15x1.lisa
   8  */
   9
  10 /dts-v1/;
  11
  12 / {
  13         model = "RTSM_VE_CortexA15x1";
  14         arm,vexpress,site = <0xf>;
  15         compatible = "arm,rtsm_ve,cortex_a15x1", "arm,vexpress";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         chosen { };
  21
  22         aliases {
  23                 serial0 = &v2m_serial0;
  24                 serial1 = &v2m_serial1;
  25                 serial2 = &v2m_serial2;
  26                 serial3 = &v2m_serial3;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a15";
  36                         reg = <0>;
  37                 };
  38         };
  39
  40         memory@80000000 {
  41                 device_type = "memory";
  42                 reg = <0 0x80000000 0 0x80000000>;
  43         };
  44
  45         gic: interrupt-controller@2c001000 {
  46                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  47                 #interrupt-cells = <3>;
  48                 #address-cells = <0>;
  49                 interrupt-controller;
  50                 reg = <0 0x2c001000 0 0x1000>,
  51                       <0 0x2c002000 0 0x1000>,
  52                       <0 0x2c004000 0 0x2000>,
  53                       <0 0x2c006000 0 0x2000>;
  54                 interrupts = <1 9 0xf04>;
  55         };
  56
  57         timer {
  58                 compatible = "arm,armv7-timer";
  59                 interrupts = <1 13 0xf08>,
  60                              <1 14 0xf08>,
  61                              <1 11 0xf08>,
  62                              <1 10 0xf08>;
  63         };
  64
  65         dcc {
  66                 compatible = "arm,vexpress,config-bus";
  67                 arm,vexpress,config-bridge = <&v2m_sysreg>;
  68
  69                 osc@0 {
  70                         /* ACLK clock to the AXI master port on the test chip */
  71                         compatible = "arm,vexpress-osc";
  72                         arm,vexpress-sysreg,func = <1 0>;
  73                         freq-range = <30000000 50000000>;
  74                         #clock-cells = <0>;
  75                         clock-output-names = "extsaxiclk";
  76                 };
  77
  78                 oscclk1: osc@1 {
  79                         /* Reference clock for the CLCD */
  80                         compatible = "arm,vexpress-osc";
  81                         arm,vexpress-sysreg,func = <1 1>;
  82                         freq-range = <10000000 80000000>;
  83                         #clock-cells = <0>;
  84                         clock-output-names = "clcdclk";
  85                 };
  86
  87                 smbclk: oscclk2: osc@2 {
  88                         /* Reference clock for the test chip internal PLLs */
  89                         compatible = "arm,vexpress-osc";
  90                         arm,vexpress-sysreg,func = <1 2>;
  91                         freq-range = <33000000 100000000>;
  92                         #clock-cells = <0>;
  93                         clock-output-names = "tcrefclk";
  94                 };
  95         };
  96
  97         smb {
  98                 compatible = "simple-bus";
  99
 100                 #address-cells = <2>;
 101                 #size-cells = <1>;
 102                 ranges = <0 0 0 0x08000000 0x04000000>,
 103                          <1 0 0 0x14000000 0x04000000>,
 104                          <2 0 0 0x18000000 0x04000000>,
 105                          <3 0 0 0x1c000000 0x04000000>,
 106                          <4 0 0 0x0c000000 0x04000000>,
 107                          <5 0 0 0x10000000 0x04000000>;
 108
 109                 #interrupt-cells = <1>;
 110                 interrupt-map-mask = <0 0 63>;
 111                 interrupt-map = <0 0  0 &gic 0  0 4>,
 112                                 <0 0  1 &gic 0  1 4>,
 113                                 <0 0  2 &gic 0  2 4>,
 114                                 <0 0  3 &gic 0  3 4>,
 115                                 <0 0  4 &gic 0  4 4>,
 116                                 <0 0  5 &gic 0  5 4>,
 117                                 <0 0  6 &gic 0  6 4>,
 118                                 <0 0  7 &gic 0  7 4>,
 119                                 <0 0  8 &gic 0  8 4>,
 120                                 <0 0  9 &gic 0  9 4>,
 121                                 <0 0 10 &gic 0 10 4>,
 122                                 <0 0 11 &gic 0 11 4>,
 123                                 <0 0 12 &gic 0 12 4>,
 124                                 <0 0 13 &gic 0 13 4>,
 125                                 <0 0 14 &gic 0 14 4>,
 126                                 <0 0 15 &gic 0 15 4>,
 127                                 <0 0 16 &gic 0 16 4>,
 128                                 <0 0 17 &gic 0 17 4>,
 129                                 <0 0 18 &gic 0 18 4>,
 130                                 <0 0 19 &gic 0 19 4>,
 131                                 <0 0 20 &gic 0 20 4>,
 132                                 <0 0 21 &gic 0 21 4>,
 133                                 <0 0 22 &gic 0 22 4>,
 134                                 <0 0 23 &gic 0 23 4>,
 135                                 <0 0 24 &gic 0 24 4>,
 136                                 <0 0 25 &gic 0 25 4>,
 137                                 <0 0 26 &gic 0 26 4>,
 138                                 <0 0 27 &gic 0 27 4>,
 139                                 <0 0 28 &gic 0 28 4>,
 140                                 <0 0 29 &gic 0 29 4>,
 141                                 <0 0 30 &gic 0 30 4>,
 142                                 <0 0 31 &gic 0 31 4>,
 143                                 <0 0 32 &gic 0 32 4>,
 144                                 <0 0 33 &gic 0 33 4>,
 145                                 <0 0 34 &gic 0 34 4>,
 146                                 <0 0 35 &gic 0 35 4>,
 147                                 <0 0 36 &gic 0 36 4>,
 148                                 <0 0 37 &gic 0 37 4>,
 149                                 <0 0 38 &gic 0 38 4>,
 150                                 <0 0 39 &gic 0 39 4>,
 151                                 <0 0 40 &gic 0 40 4>,
 152                                 <0 0 41 &gic 0 41 4>,
 153                                 <0 0 42 &gic 0 42 4>;
 154
 155                 /include/ "rtsm_ve-motherboard.dtsi"
 156         };
 157 };
 158
 159 /include/ "clcd-panels.dtsi"