arch/arm/boot/dts/rk3288.dtsi

   1 #include <dt-bindings/clock/rk_system_status.h>
   2 #include <dt-bindings/interrupt-controller/arm-gic.h>
   3 #include <dt-bindings/rkfb/rk_fb.h>
   4 #include <dt-bindings/rkmipi/mipi_dsi.h>
   5 #include <dt-bindings/suspend/rockchip-pm.h>
   6 #include <dt-bindings/sensor-dev.h>
   7
   8 #include "skeleton.dtsi"
   9 #include "rk3288-pinctrl.dtsi"
  10 #include "rk3288-clocks.dtsi"
  11
  12 / {
  13         compatible = "rockchip,rk3288";
  14         rockchip,sram = <&sram>;
  15         interrupt-parent = <&gic>;
  16
  17         aliases {
  18                 serial0 = &uart_bt;
  19                 serial1 = &uart_bb;
  20                 serial2 = &uart_dbg;
  21                 serial3 = &uart_gps;
  22                 serial4 = &uart_exp;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 lcdc0 = &lcdc0;
  30                 lcdc1 = &lcdc1;
  31                 spi0 = &spi0;
  32                 spi1 = &spi1;
  33                 spi2 = &spi2;
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 cpu@0 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <0x500>;
  44                 };
  45                 cpu@1 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a15";
  48                         reg = <0x501>;
  49                 };
  50                 cpu@2 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a15";
  53                         reg = <0x502>;
  54                 };
  55                 cpu@3 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a15";
  58                         reg = <0x503>;
  59                 };
  60         };
  61
  62         gic: interrupt-controller@ffc01000 {
  63                 compatible = "arm,cortex-a15-gic";
  64                 interrupt-controller;
  65                 #interrupt-cells = <3>;
  66                 #address-cells = <0>;
  67                 reg = <0xffc01000 0x1000>,
  68                       <0xffc02000 0x1000>;
  69         };
  70
  71         arm-pmu {
  72                 compatible = "arm,cortex-a12-pmu";
  73                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  74                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  75                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  76                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  77         };
  78
  79         cpu_axi_bus: cpu_axi_bus {
  80                 compatible = "rockchip,cpu_axi_bus";
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 ranges;
  84
  85                 qos {
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         ranges;
  89                         /* service core */
  90                         cpup {
  91                                 reg = <0xffa80000 0x20>;
  92                         };
  93                         cpum_r {
  94                                 reg = <0xffa80080 0x20>;
  95                         };
  96                         cpum_w {
  97                                 reg = <0xffa80100 0x20>;
  98                         };
  99                         /* service dmac */
 100                         bus_dmac {
 101                                 reg = <0xffa90000 0x20>;
 102                         };
 103                         host {
 104                                 reg = <0xffa90080 0x20>;
 105                         };
 106                         crypto {
 107                                 reg = <0xffa90100 0x20>;
 108                         };
 109                         ccp {
 110                                 reg = <0xffa90180 0x20>;
 111                         };
 112                         ccs {
 113                                 reg = <0xffa90200 0x20>;
 114                         };
 115                         /* service gpu */
 116                         gpu_r {
 117                                 reg = <0xffaa0000 0x20>;
 118                         };
 119                         gpu_w {
 120                                 reg = <0xffaa0080 0x20>;
 121                         };
 122                         /* service peri */
 123                         peri {
 124                                 reg = <0xffab0000 0x20>;
 125                         };
 126                         /* service vio */
 127                         vio1_vop {
 128                                 reg = <0xffad0000 0x20>;
 129                                 rockchip,priority = <2 2>;
 130                         };
 131                         vio1_isp_w0 {
 132                                 reg = <0xffad0100 0x20>;
 133                         };
 134                         vio1_isp_w1 {
 135                                 reg = <0xffad0180 0x20>;
 136                         };
 137                         vio0_vop {
 138                                 reg = <0xffad0400 0x20>;
 139                                 rockchip,priority = <2 2>;
 140                         };
 141                         vio0_vip {
 142                                 reg = <0xffad0480 0x20>;
 143                         };
 144                         vio0_iep {
 145                                 reg = <0xffad0500 0x20>;
 146                         };
 147                         vio2_rga_r {
 148                                 reg = <0xffad0800 0x20>;
 149                         };
 150                         vio2_rga_w {
 151                                 reg = <0xffad0880 0x20>;
 152                         };
 153                         vio1_isp_r {
 154                                 reg = <0xffad0900 0x20>;
 155                         };
 156                         /* service video */
 157                         video {
 158                                 reg = <0xffae0000 0x20>;
 159                         };
 160                         /* service hevc */
 161                         hevc_r {
 162                                 reg = <0xffaf0000 0x20>;
 163                         };
 164                         hevc_w {
 165                                 reg = <0xffaf0080 0x20>;
 166                         };
 167                 };
 168
 169                 msch {
 170                         #address-cells = <1>;
 171                         #size-cells = <1>;
 172                         ranges;
 173
 174                         msch@0 {
 175                                 reg = <0xffac0000 0x40>;
 176                                 rockchip,read-latency = <0x34>;
 177                         };
 178                         msch@1 {
 179                                 reg = <0xffac0080 0x40>;
 180                                 rockchip,read-latency = <0x34>;
 181                         };
 182                 };
 183         };
 184
 185         sram: sram@ff710000 {
 186                 compatible = "mmio-sram";
 187                 reg = <0xff710000 0x8000>; /* 32k */
 188                 map-exec;
 189         };
 190
 191         timer {
 192                 compatible = "arm,armv7-timer";
 193                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 194                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 195                 clock-frequency = <24000000>;
 196         };
 197
 198         timer@ff810000 {
 199                 compatible = "rockchip,timer";
 200                 reg = <0xff810000 0x20>;
 201                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 202                 rockchip,broadcast = <1>;
 203         };
 204
 205         watchdog: wdt@2004c000 {
 206                 compatible = "rockchip,watch dog";
 207                 reg = <0xff800000 0x100>;
 208                 clocks = <&pclk_pd_alive>;
 209                 clock-names = "pclk_wdt";
 210                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 211                 rockchip,irq = <1>;
 212                 rockchip,timeout = <60>;
 213                 rockchip,atboot = <1>;
 214                 rockchip,debug = <0>;
 215                 status = "disabled";
 216         };
 217
 218         amba {
 219                 #address-cells = <1>;
 220                 #size-cells = <1>;
 221                 compatible = "arm,amba-bus";
 222                 interrupt-parent = <&gic>;
 223                 ranges;
 224
 225                 pdma0: pdma@ffb20000 {
 226                         compatible = "arm,pl330", "arm,primecell";
 227                         reg = <0xffb20000 0x4000>;
 228                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 229                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 230                         #dma-cells = <1>;
 231                 };
 232
 233                 pdma1: pdma@ff250000 {
 234                         compatible = "arm,pl330", "arm,primecell";
 235                         reg = <0xff250000 0x4000>;
 236                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 237                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 238                         #dma-cells = <1>;
 239                 };
 240         };
 241
 242         nandc0: nandc@0xff400000 {
 243                 compatible = "rockchip,rk-nandc";
 244                 reg = <0xff400000 0x4000>;
 245                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 246                 nandc_id = <0>;
 247                 clocks = <&clk_nandc0>, <&clk_gates5 5>, <&clk_gates7 14>;
 248                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 249         };
 250
 251         nandc1: nandc@0xff410000 {
 252             compatible = "rockchip,rk-nandc";
 253                 reg = <0xff410000 0x4000>;
 254                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 255                 nandc_id = <1>;
 256                 clocks = <&clk_nandc1>, <&clk_gates5 6>, <&clk_gates7 15>;
 257                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 258         };
 259
 260         nandc0reg: nandc0@0xff400000 {
 261                 compatible = "rockchip,rk-nandc";
 262                 reg = <0xff400000 0x4000>;
 263         };
 264
 265         emmc: rksdmmc@ff0f0000 {
 266                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 267                 reg = <0xff0f0000 0x4000>;
 268                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 269                 #address-cells = <1>;
 270                 #size-cells = <0>;
 271                 //pinctrl-names = "default",,"suspend";
 272                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 273                 clocks = <&clk_emmc>, <&clk_gates8 6>;
 274                 clock-names = "clk_mmc", "hclk_mmc";
 275                 num-slots = <1>;
 276                 fifo-depth = <0x100>;
 277                 bus-width = <8>;
 278         };
 279
 280         sdmmc: rksdmmc@ff0c0000 {
 281                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 282                 reg = <0xff0c0000 0x4000>;
 283                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 284                 #address-cells = <1>;
 285                 #size-cells = <0>;
 286                 pinctrl-names = "default", "idle";
 287                 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 288                 pinctrl-1 = <&sdmmc0_gpio>;
 289                 cd-gpios = <&gpio6 GPIO_C6 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 290                 clocks = <&clk_sdmmc>, <&clk_gates8 3>;
 291                 clock-names = "clk_mmc", "hclk_mmc";
 292                 num-slots = <1>;
 293                 fifo-depth = <0x100>;
 294                 bus-width = <4>;
 295         };
 296
 297         sdio: rksdmmc@ff0d0000 {
 298                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 299                 reg = <0xff0d0000 0x4000>;
 300                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 301                 #address-cells = <1>;
 302                 #size-cells = <0>;
 303                 pinctrl-names = "default","idle";
 304                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwr &sdio0_bkpwr
 305                              &sdio0_intn &sdio0_bus4>;
 306                 pinctrl-1 = <&sdio0_gpio>;
 307                 clocks = <&clk_sdio0>, <&clk_gates8 4>;
 308                 clock-names = "clk_mmc", "hclk_mmc";
 309                 num-slots = <1>;
 310                 fifo-depth = <0x100>;
 311                 bus-width = <4>;
 312         };
 313
 314         sdio1: rksdmmc@ff0e0000 {
 315                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 316                 reg = <0xff0e0000 0x4000>;
 317                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 318                 #address-cells = <1>;
 319                 #size-cells = <0>;
 320                 //pinctrl-names = "default","suspend";
 321                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 322                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/
 323                 clocks = <&clk_sdio1>, <&clk_gates8 5>;
 324                 clock-names = "clk_mmc", "hclk_mmc";
 325                 num-slots = <1>;
 326                 fifo-depth = <0x100>;
 327                 bus-width = <4>;
 328                 status = "disabled";
 329         };
 330
 331         spi0: spi@ff110000 {
 332                 compatible = "rockchip,rockchip-spi";
 333                 reg = <0xff110000 0x1000>;
 334                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 335                 #address-cells = <1>;
 336                 #size-cells = <0>;
 337                 pinctrl-names = "default";
 338                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 339                 rockchip,spi-src-clk = <0>;
 340                 num-cs = <2>;
 341                 clocks =<&clk_spi0>, <&clk_gates6 4>;
 342                 clock-names = "spi","pclk_spi0";
 343                 //dmas = <&pdma1 11>, <&pdma1 12>;
 344                 //#dma-cells = <2>;
 345                 //dma-names = "tx", "rx";
 346                 status = "disabled";
 347         };
 348
 349         spi1: spi@ff120000 {
 350                 compatible = "rockchip,rockchip-spi";
 351                 reg = <0xff120000 0x1000>;
 352                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 353                 #address-cells = <1>;
 354                 #size-cells = <0>;
 355                 pinctrl-names = "default";
 356                 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0>;
 357                 rockchip,spi-src-clk = <1>;
 358                 num-cs = <1>;
 359                 clocks = <&clk_spi1>, <&clk_gates6 5>;
 360                 clock-names = "spi","pclk_spi1";
 361                 //dmas = <&pdma1 13>, <&pdma1 14>;
 362                 //#dma-cells = <2>;
 363                 //dma-names = "tx", "rx";
 364                 status = "disabled";
 365         };
 366
 367         spi2: spi@ff130000 {
 368                 compatible = "rockchip,rockchip-spi";
 369                 reg = <0xff130000 0x1000>;
 370                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 371                 #address-cells = <1>;
 372                 #size-cells = <0>;
 373                 pinctrl-names = "default";
 374                 pinctrl-0 = <&spi2_txd &spi2_rxd &spi2_clk &spi2_cs0 &spi2_cs1>;
 375                 rockchip,spi-src-clk = <2>;
 376                 num-cs = <2>;
 377                 clocks = <&clk_spi2>, <&clk_gates6 6>;
 378                 clock-names = "spi","pclk_spi2";
 379                 //dmas = <&pdma1 15>, <&pdma1 16>;
 380                 //#dma-cells = <2>;
 381                 //dma-names = "tx", "rx";
 382                 status = "disabled";
 383         };
 384
 385         uart_bt: serial@ff180000 {
 386                 compatible = "rockchip,serial";
 387                 reg = <0xff180000 0x100>;
 388                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 389                 clock-frequency = <24000000>;
 390                 clocks = <&clk_uart0>, <&clk_gates6 8>;
 391                 clock-names = "sclk_uart", "pclk_uart";
 392                 reg-shift = <2>;
 393                 reg-io-width = <4>;
 394                 dmas = <&pdma1 1>, <&pdma1 2>;
 395                 #dma-cells = <2>;
 396                 pinctrl-names = "default";
 397                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 398                 status = "disabled";
 399         };
 400
 401         uart_bb: serial@ff190000 {
 402                 compatible = "rockchip,serial";
 403                 reg = <0xff190000 0x100>;
 404                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 405                 clock-frequency = <24000000>;
 406                 clocks = <&clk_uart1>, <&clk_gates6 9>;
 407                 clock-names = "sclk_uart", "pclk_uart";
 408                 reg-shift = <2>;
 409                 reg-io-width = <4>;
 410                 dmas = <&pdma1 3>, <&pdma1 4>;
 411                 #dma-cells = <2>;
 412                 pinctrl-names = "default";
 413                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 414                 status = "disabled";
 415         };
 416
 417         uart_dbg: serial@ff690000 {
 418                 compatible = "rockchip,serial";
 419                 reg = <0xff690000 0x100>;
 420                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 421                 clock-frequency = <24000000>;
 422                 clocks = <&clk_uart2>, <&clk_gates11 9>;
 423                 clock-names = "sclk_uart", "pclk_uart";
 424                 reg-shift = <2>;
 425                 reg-io-width = <4>;
 426                 dmas = <&pdma0 4>, <&pdma0 5>;
 427                 #dma-cells = <2>;
 428                 pinctrl-names = "default";
 429                 pinctrl-0 = <&uart2_xfer>;
 430                 status = "disabled";
 431         };
 432
 433         uart_gps: serial@ff1b0000 {
 434                 compatible = "rockchip,serial";
 435                 reg = <0xff1b0000 0x100>;
 436                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 437                 clock-frequency = <24000000>;
 438                 clocks = <&clk_uart3>, <&clk_gates6 11>;
 439                 clock-names = "sclk_uart", "pclk_uart";
 440                 current-speed = <115200>;
 441                 reg-shift = <2>;
 442                 reg-io-width = <4>;
 443                 dmas = <&pdma1 7>, <&pdma1 8>;
 444                 #dma-cells = <2>;
 445                 pinctrl-names = "default";
 446                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 447                 status = "disabled";
 448         };
 449
 450         uart_exp: serial@ff1c0000 {
 451                 compatible = "rockchip,serial";
 452                 reg = <0xff1c0000 0x100>;
 453                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 454                 clock-frequency = <24000000>;
 455                 clocks = <&clk_uart4>, <&clk_gates6 12>;
 456                 clock-names = "sclk_uart", "pclk_uart";
 457                 reg-shift = <2>;
 458                 reg-io-width = <4>;
 459                 dmas = <&pdma1 9>, <&pdma1 10>;
 460                 #dma-cells = <2>;
 461                 pinctrl-names = "default";
 462                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 463                 status = "disabled";
 464         };
 465
 466         fiq-debugger {
 467                 compatible = "rockchip,fiq-debugger";
 468                 rockchip,serial-id = <2>;
 469                 rockchip,signal-irq = <106>;
 470                 rockchip,wake-irq = <0>;
 471                 status = "disabled";
 472         };
 473
 474         rockchip_clocks_init: clocks-init{
 475                 compatible = "rockchip,clocks-init";
 476                 rockchip,clocks-init-parent =
 477                         <&clk_core &clk_apll>,  <&aclk_bus_src &clk_gpll>,
 478                         <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
 479                         <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
 480                         <&usbphy_480m &otgphy2_480m>;
 481                 rockchip,clocks-init-rate =
 482                         <&clk_core 792000000>,  <&clk_gpll 297000000>,
 483                         /*<&clk_cpll 47000000>,*/       <&clk_npll 1250000000>,
 484                         <&aclk_bus_src 300000000>,      <&aclk_bus 300000000>,
 485                         <&hclk_bus 150000000>,  <&pclk_bus 75000000>,
 486                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 487                         <&hclk_peri 150000000>, <&pclk_peri 75000000>,
 488                         <&clk_gpu 200000000>,   <&aclk_vio0 300000000>,
 489                         <&aclk_vio1 300000000>, <&hclk_vio 75000000>,
 490                         <&pclk_pd_alive 100000000>,     <&pclk_pd_pmu 100000000>,
 491                         <&aclk_hevc 400000000>, <&hclk_hevc 200000000>,
 492                         <&clk_hevc_cabac 300000000>, <&clk_hevc_core 300000000>,
 493                         <&aclk_rga 300000000>, <&clk_rga 300000000>,
 494                         <&clk_vepu 300000000>, <&clk_vdpu 300000000>,
 495                         <&clk_edp 200000000>, <&clk_isp 200000000>,
 496                         <&clk_isp_jpe 400000000>, <&clk_tsp 80000000>,
 497                         <&clk_tspout 80000000>, <&clk_mac 125000000>;
 498                 rockchip,clocks-uboot-has-init =
 499                         <&aclk_vio0>;
 500         };
 501
 502         clocks-enable {
 503                 compatible = "rockchip,clocks-enable";
 504                 clocks =
 505                                 /*PD_CORE*/
 506                                 <&clk_gates0 2>, <&clk_core0>,
 507                                 <&clk_core1>, <&clk_core2>,
 508                                 <&clk_core3>, <&clk_l2ram>,
 509                                 <&aclk_core_m0>, <&aclk_core_mp>,
 510                                 <&atclk_core>, <&pclk_dbg_src>,
 511                                 <&clk_gates12 9>, <&clk_gates12 10>,
 512                                 <&clk_gates12 11>,
 513
 514                                 /*PD_BUS*/
 515                                 <&aclk_bus>, <&clk_gates0 3>,
 516                                 <&hclk_bus>, <&pclk_bus>,
 517                                 <&clk_gates13 8>, <&clk_crypto>,
 518                                 <&clk_gates0 7>,
 519
 520                                 /*TIMER*/
 521                                 <&clk_gates1 0>, <&clk_gates1 1>,
 522                                 <&clk_gates1 2>, <&clk_gates1 3>,
 523                                 <&clk_gates1 4>, <&clk_gates1 5>,
 524
 525                                 <&pclk_pd_alive>, <&pclk_pd_pmu>,
 526
 527                                 /*PD_PERI*/
 528                                 <&aclk_peri>, <&hclk_peri>,
 529                                 <&pclk_peri>,
 530
 531                                 /*JTAG*/
 532                                 /*<&clk_gates4 14>,*/
 533
 534                                 /*aclk_bus*/
 535                                 <&clk_gates10 5>,/*aclk_intmem0*/
 536                                 <&clk_gates10 6>,/*aclk_intmem1*/
 537                                 <&clk_gates10 7>,/*aclk_intmem2*/
 538                                 <&clk_gates10 12>,/*aclk_dma1*/
 539                                 <&clk_gates10 13>,/*aclk_strc_sys*/
 540                                 <&clk_gates10 4>,/*aclk_intmem*/
 541                                 <&clk_gates11 6>,/*aclk_crypto*/
 542                                 <&clk_gates11 8>,/*aclk_ccp*/
 543
 544                                 /*hclk_bus*/
 545                                 <&clk_gates11 7>,/*hclk_crypto*/
 546                                 <&clk_gates10 9>,/*hclk_rom*/
 547
 548                                 /*pclk_bus*/
 549                                 <&clk_gates10 1>,/*pclk_timer*/
 550                                 <&clk_gates10 9>,/*rom*/
 551                                 <&clk_gates10 13>,/*aclk strc*/
 552
 553                                 <&clk_gates12 8>,/*aclk strc*/
 554
 555                                 /*aclk_peri*/
 556                                 <&clk_gates6 2>,/*aclk_peri_axi_matrix*/
 557                                 <&clk_gates6 3>,/*aclk_dmac2*/
 558                                 <&clk_gates7 11>,/*aclk_peri_niu*/
 559                                 <&clk_gates8 12>,/*aclk_peri_mmu*/
 560
 561                                 /*hclk_peri*/
 562                                 <&clk_gates6 0>,/*hclk_peri_matrix*/
 563                                 <&clk_gates7 10>,/*hclk_peri_ahb_arbi*/
 564                                 <&clk_gates7 12>,/*hclk_emem_peri*/
 565                                 <&clk_gates7 13>,/*hclk_mem_peri*/
 566
 567                                 /*pclk_peri*/
 568                                 <&clk_gates6 1>,/*pclk_peri_axi_matrix*/
 569
 570                                 /*pclk_pd_alive*/
 571                                 <&clk_gates14 11>,/*pclk_grf*/
 572                                 <&clk_gates14 12>,/*pclk_alive_niu*/
 573
 574                                 /*pclk_pd_pmu*/
 575                                 <&clk_gates17 0>,/*pclk_pmu*/
 576                                 <&clk_gates17 1>,/*pclk_intmem1*/
 577                                 <&clk_gates17 2>,/*pclk_pmu_niu*/
 578                                 <&clk_gates17 3>,/*pclk_sgrf*/
 579
 580                                 /*hclk_vio*/
 581                                 <&clk_gates15 9>,/*hclk_vio_ahb_arbi*/
 582                                 <&clk_gates15 10>,/*hclk_vio_niu*/
 583                                 <&clk_gates16 10>,/*hclk_vio2_h2p*/
 584                                 <&clk_gates16 11>,/*pclk_vio2_h2p*/
 585
 586                                 /*aclk_vio0*/
 587                                 <&clk_gates15 11>,/*aclk_vio0_niu*/
 588
 589                                 /*aclk_vio1*/
 590                                 <&clk_gates15 12>,/*aclk_vio1_niu*/
 591
 592                                 /*HDMI*/
 593                                 //<&clk_gates5 12>,/*hdmi_hdcp_clk*/
 594
 595                                 /*UART*/
 596                                 <&clk_gates11 9>,/*pclk_uart2*/
 597
 598                                 /*480M*/
 599                                 <&usbphy_480m>;
 600         };
 601
 602         i2c0: i2c@ff650000 {
 603                 compatible = "rockchip,rk30-i2c";
 604                 reg = <0xff650000 0x1000>;
 605                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 606                 #address-cells = <1>;
 607                 #size-cells = <0>;
 608                 pinctrl-names = "default", "gpio";
 609                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 610                 pinctrl-1 = <&i2c0_gpio>;
 611                 gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 612                 clocks = <&clk_gates10 2>;
 613                 rockchip,check-idle = <1>;
 614                 status = "disabled";
 615         };
 616
 617         i2c1: i2c@ff140000 {
 618                 compatible = "rockchip,rk30-i2c";
 619                 reg = <0xff140000 0x1000>;
 620                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 621                 #address-cells = <1>;
 622                 #size-cells = <0>;
 623                 pinctrl-names = "default", "gpio";
 624                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 625                 pinctrl-1 = <&i2c1_gpio>;
 626                 gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 627                 clocks = <&clk_gates10 3>;
 628                 rockchip,check-idle = <1>;
 629                 status = "disabled";
 630         };
 631
 632         i2c2: i2c@ff660000 {
 633                 compatible = "rockchip,rk30-i2c";
 634                 reg = <0xff660000 0x1000>;
 635                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 636                 #address-cells = <1>;
 637                 #size-cells = <0>;
 638                 pinctrl-names = "default", "gpio";
 639                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 640                 pinctrl-1 = <&i2c2_gpio>;
 641                 gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 642                 clocks = <&clk_gates6 13>;
 643                 rockchip,check-idle = <1>;
 644                 status = "disabled";
 645         };
 646
 647         i2c3: i2c@ff150000 {
 648                 compatible = "rockchip,rk30-i2c";
 649                 reg = <0xff150000 0x1000>;
 650                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 651                 #address-cells = <1>;
 652                 #size-cells = <0>;
 653                 pinctrl-names = "default", "gpio";
 654                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 655                 pinctrl-1 = <&i2c3_gpio>;
 656                 gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
 657                 clocks = <&clk_gates6 14>;
 658                 rockchip,check-idle = <1>;
 659                 status = "disabled";
 660         };
 661
 662         i2c4: i2c@ff160000 {
 663                 compatible = "rockchip,rk30-i2c";
 664                 reg = <0xff160000 0x1000>;
 665                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 666                 #address-cells = <1>;
 667                 #size-cells = <0>;
 668                 pinctrl-names = "default", "gpio";
 669                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 670                 pinctrl-1 = <&i2c4_gpio>;
 671                 gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
 672                 clocks = <&clk_gates6 15>;
 673                 rockchip,check-idle = <1>;
 674                 status = "disabled";
 675         };
 676
 677         i2c5: i2c@ff170000 {
 678                 compatible = "rockchip,rk30-i2c";
 679                 reg = <0xff170000 0x1000>;
 680                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 681                 #address-cells = <1>;
 682                 #size-cells = <0>;
 683                 pinctrl-names = "default", "gpio";
 684                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 685                 pinctrl-1 = <&i2c5_gpio>;
 686                 gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
 687                 clocks = <&clk_gates7 0>;
 688                 rockchip,check-idle = <1>;
 689                 status = "disabled";
 690         };
 691
 692         fb: fb{
 693                 compatible = "rockchip,rk-fb";
 694                 rockchip,disp-mode = <DUAL>;
 695         };
 696
 697         rk_screen: rk_screen{
 698                         compatible = "rockchip,screen";
 699         };
 700
 701         dsihost0: mipi@ff960000{
 702                 compatible = "rockchip,rk32-dsi";
 703                 rockchip,prop = <0>;
 704                 reg = <0xff960000 0x4000>;
 705                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 706                 clocks = <&clk_gates5 15>, <&clk_gates16 4> , <&pd_mipidsi>;
 707                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
 708                 status = "disabled";
 709         };
 710
 711         dsihost1: mipi@ff964000{
 712                 compatible = "rockchip,rk32-dsi";
 713                 rockchip,prop = <1>;
 714                 reg = <0xff964000 0x4000>;
 715                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 716                 clocks = <&clk_gates5 15>, <&clk_gates16 5>, <&pd_mipidsi>;
 717                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
 718                 status = "disabled";
 719         };
 720
 721         lvds: lvds@ff96c000 {
 722                 compatible = "rockchip,rk32-lvds";
 723                 reg = <0xff96c000 0x4000>;
 724                 clocks = <&clk_gates16 7>;
 725                 clock-names = "pclk_lvds";
 726         };
 727
 728         edp: edp@ff970000 {
 729                 compatible = "rockchip,rk32-edp";
 730                 reg = <0xff970000 0x4000>;
 731                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 732                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates16 8>;
 733                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 734         };
 735
 736         hdmi: hdmi@ff980000 {
 737                 compatible = "rockchip,rk3288-hdmi";
 738                 reg = <0xff980000 0x20000>;
 739                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 740                 pinctrl-names = "default", "sleep";
 741                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 742                 pinctrl-1 = <&i2c5_gpio>;
 743                 clocks = <&clk_gates16 9>, <&clk_gates5 12>;
 744                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi";
 745                 status = "disabled";
 746         };
 747
 748         lcdc0: lcdc@ff930000 {
 749                 compatible = "rockchip,rk3288-lcdc";
 750                 rockchip,prop = <PRMRY>;
 751                 rockchip,pwr18 = <0>;
 752                 rockchip,iommu-enabled = <1>;
 753                 reg = <0xff930000 0x10000>;
 754                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 755                 pinctrl-names = "default", "gpio";
 756                 pinctrl-0 = <&lcdc0_lcdc>;
 757                 pinctrl-1 = <&lcdc0_gpio>;
 758                 status = "disabled";
 759                 clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>, <&pd_vop0>;
 760                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
 761         };
 762
 763         lcdc1: lcdc@ff940000 {
 764                 compatible = "rockchip,rk3288-lcdc";
 765                 rockchip,prop = <EXTEND>;
 766                 rochchip,pwr18 = <0>;
 767                 rockchip,iommu-enabled = <1>;
 768                 reg = <0xff940000 0x10000>;
 769                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 770                 status = "disabled";
 771                 clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>, <&pd_vop1>;
 772                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
 773         };
 774
 775         adc: adc@ff100000 {
 776                 compatible = "rockchip,saradc";
 777                 reg = <0xff100000 0x100>;
 778                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 779                 #io-channel-cells = <1>;
 780                 io-channel-ranges;
 781                 rockchip,adc-vref = <1800>;
 782                 clock-frequency = <1000000>;
 783                 clocks = <&clk_saradc>, <&clk_gates7 1>;
 784                 clock-names = "saradc", "pclk_saradc";
 785                 status = "disabled";
 786         };
 787
 788         rga@ff920000 {
 789                 compatible = "rockchip,rga";
 790                 reg = <0xff920000 0x1000>;
 791                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 792                 clocks = <&clk_gates15 1>, <&aclk_rga>, <&clk_rga>;
 793                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 794         };
 795
 796         i2s: rockchip-i2s@0xff890000 {
 797                 compatible = "rockchip-i2s";
 798                 reg = <0xff890000 0x10000>;
 799                 i2s-id = <0>;
 800                 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates10 8>;
 801                 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
 802                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 803                 dmas = <&pdma0 0>, <&pdma0 1>;
 804                 //#dma-cells = <2>;
 805                 dma-names = "tx", "rx";
 806                 pinctrl-names = "default", "sleep";
 807                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 808                 pinctrl-1 = <&i2s_gpio>;
 809         };
 810
 811         spdif: rockchip-spdif@0xff8b0000 {
 812                 compatible = "rockchip-spdif";
 813                 reg = <0xff8b0000 0x10000>;     //8channel
 814                 //reg = <ff880000 0x10000>;//2channel
 815                 clocks = <&clk_spdif>, <&clk_spdif_8ch>,<&clk_gates10 11>;
 816                 clock-names = "spdif_mclk","spdif_8ch_mclk","spdif_hclk";
 817                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 818                 dmas = <&pdma0 3>;
 819                 //dmas = <&pdma0 2>; //2channel
 820                 //#dma-cells = <1>;
 821                 dma-names = "tx";
 822                 pinctrl-names = "default";
 823                 pinctrl-0 = <&spdif_tx>;
 824         };
 825
 826         vop1pwm: pwm@ff9401a0 {
 827                 compatible = "rockchip,vop-pwm";
 828                 reg = <0xff9401a0 0x10>;
 829                 #pwm-cells = <2>;
 830                 pinctrl-names = "default";
 831                 pinctrl-0 = <&vop1_pwm_pin>;
 832                 clocks = <&clk_gates13 11>;
 833                 clock-names = "pclk_pwm";
 834                 status = "disabled";
 835         };
 836
 837         vop0pwm: pwm@ff9301a0 {
 838                 compatible = "rockchip,vop-pwm";
 839                 reg = <0xff9301a0 0x10>;
 840                 #pwm-cells = <2>;
 841                 pinctrl-names = "default";
 842                 pinctrl-0 = <&vop0_pwm_pin>;
 843                 clocks = <&clk_gates13 10>;
 844                 clock-names = "pclk_pwm";
 845                 status = "disabled";
 846         };
 847
 848         pwm0: pwm@ff680000 {
 849                 compatible = "rockchip,rk-pwm";
 850                 reg = <0xff680000 0x10>;
 851                 #pwm-cells = <2>;
 852                 pinctrl-names = "default";
 853                 pinctrl-0 = <&pwm0_pin>;
 854                 clocks = <&clk_gates11 11>;
 855                 clock-names = "pclk_pwm";
 856                 status = "disabled";
 857         };
 858
 859         pwm1: pwm@ff680010 {
 860                 compatible = "rockchip,rk-pwm";
 861                 reg = <0xff680010 0x10>;
 862                 #pwm-cells = <2>;
 863                 pinctrl-names = "default";
 864                 pinctrl-0 = <&pwm1_pin>;
 865                 clocks = <&clk_gates11 11>;
 866                 clock-names = "pclk_pwm";
 867                 status = "disabled";
 868         };
 869
 870         pwm2: pwm@ff680020 {
 871                 compatible = "rockchip,rk-pwm";
 872                 reg = <0xff680020 0x10>;
 873                 #pwm-cells = <2>;
 874                 pinctrl-names = "default";
 875                 pinctrl-0 = <&pwm2_pin>;
 876                 clocks = <&clk_gates11 11>;
 877                 clock-names = "pclk_pwm";
 878                 status = "disabled";
 879         };
 880
 881         pwm3: pwm@ff680030 {
 882                 compatible = "rockchip,rk-pwm";
 883                 reg = <0xff680030 0x10>;
 884                 #pwm-cells = <2>;
 885                 pinctrl-names = "default";
 886                 pinctrl-0 = <&pwm3_pin>;
 887                 clocks = <&clk_gates11 11>;
 888                 clock-names = "pclk_pwm";
 889                 status = "disabled";
 890         };
 891
 892         dvfs {
 893                 temp-limit-enable = <1>;
 894                 target-temp = <80>;
 895
 896                 vd_arm: vd_arm {
 897                         regulator_name = "vdd_arm";
 898                         suspend_volt = <1000>; //mV
 899                         pd_core {
 900                                 clk_core_dvfs_table: clk_core {
 901                                         operating-points = <
 902                                                 /* KHz    uV */
 903                                                 312000 1100000
 904                                                 504000 1100000
 905                                                 816000 1100000
 906                                                 1008000 1100000
 907                                                 >;
 908                                         temp-channel = <1>;
 909                                         normal-temp-limit = <
 910                                         /*delta-temp    delta-freq*/
 911                                                 3       96000
 912                                                 6       144000
 913                                                 9       192000
 914                                                 15      384000
 915                                                 >;
 916                                         performance-temp-limit = <
 917                                                 /*temp    freq*/
 918                                                 110     816000
 919                                                 >;
 920                                         status = "okay";
 921                                 };
 922                         };
 923                 };
 924
 925                 vd_logic: vd_logic {
 926                         regulator_name = "vdd_logic";
 927                         suspend_volt = <1000>; //mV
 928                         pd_ddr {
 929                                 clk_ddr_dvfs_table: clk_ddr {
 930                                         operating-points = <
 931                                                 /* KHz    uV */
 932                                                 200000 1200000
 933                                                 300000 1200000
 934                                                 400000 1200000
 935                                                 >;
 936                                         status = "disabled";
 937                                 };
 938                         };
 939
 940                         pd_vio {
 941                                 aclk_vio1_dvfs_table: aclk_vio1 {
 942                                         operating-points = <
 943                                                 /* KHz    uV */
 944                                                 100000 1100000
 945                                                 500000 1100000
 946                                                 >;
 947                                         status = "okay";
 948                                 };
 949                         };
 950                 };
 951
 952                 vd_gpu: vd_gpu {
 953                         regulator_name = "vdd_gpu";
 954                         suspend_volt = <1000>; //mV
 955                         pd_gpu {
 956                                 clk_gpu_dvfs_table: clk_gpu {
 957                                         operating-points = <
 958                                                 /* KHz    uV */
 959                                                 200000 1200000
 960                                                 300000 1200000
 961                                                 400000 1200000
 962                                                 >;
 963                                         status = "okay";
 964                                 };
 965                         };
 966                 };
 967         };
 968
 969         ion {
 970                 compatible = "rockchip,ion";
 971                 #address-cells = <1>;
 972                 #size-cells = <0>;
 973
 974                 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
 975                         compatible = "rockchip,ion-reserve";
 976                         rockchip,ion_heap = <1>;
 977                         reg = <0x00000000 0x20000000>; /* 512MB */
 978                 };
 979                 rockchip,ion-heap@3 { /* VMALLOC HEAP */
 980                         rockchip,ion_heap = <3>;
 981                 };
 982         };
 983
 984         vpu: vpu_service@ff9a0000 {
 985                 compatible = "vpu_service";
 986                 reg = <0xff9a0000 0x800>;
 987                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 988                 interrupt-names = "irq_enc", "irq_dec";
 989                 clocks = <&clk_vdpu>, <&hclk_vdpu>;
 990                 clock-names = "aclk_vcodec", "hclk_vcodec";
 991                 name = "vpu_service";
 992                 //status = "disabled";
 993         };
 994
 995         hevc: hevc_service@ff9c0000 {
 996                 compatible = "rockchip,hevc_service";
 997                 reg = <0xff9c0000 0x800>;
 998                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 999                 interrupt-names = "irq_dec";
1000                 clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1001                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1002                 name = "hevc_service";
1003                 //status = "disabled";
1004         };
1005
1006         iep: iep@ff900000 {
1007                 compatible = "rockchip,iep";
1008                 reg = <0xff900000 0x800>;
1009                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1010                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1011                 clock-names = "aclk_iep", "hclk_iep";
1012                 status = "okay";
1013         };
1014
1015         dwc_control_usb: dwc-control-usb@ff770284 {
1016                 compatible = "rockchip,rk3288-dwc-control-usb";
1017                 reg = <0xff770284 0x04>, <0xff770288 0x04>,
1018                       <0xff7702cc 0x04>, <0xff7702d4 0x04>,
1019                       <0xff770320 0x14>, <0xff770334 0x14>,
1020                       <0xff770348 0x10>, <0xff770358 0x08>,
1021                       <0xff770360 0x08>;
1022                 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
1023                             "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
1024                             "GRF_UOC0_BASE", "GRF_UOC1_BASE",
1025                             "GRF_UOC2_BASE", "GRF_UOC3_BASE",
1026                             "GRF_UOC4_BASE";
1027                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1028                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1029                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1030                 interrupt-names = "otg_id", "otg_bvalid",
1031                                   "otg_linestate", "host0_linestate",
1032                                   "host1_linestate";
1033                 clocks = <&clk_gates7 9>, <&usbphy_480m>,
1034                          <&otgphy1_480m>, <&otgphy2_480m>;
1035                 clock-names = "hclk_usb_peri", "usbphy_480m",
1036                               "usbphy1_480m", "usbphy2_480m";
1037
1038                 usb_bc {
1039                         compatible = "synopsys,phy";
1040                                         /* offset bit mask */
1041                         rk_usb,bvalid     = <0x288 14 1>;
1042                         rk_usb,iddig      = <0x288 17 1>;
1043                         rk_usb,dcdenb     = <0x328 14 1>;
1044                         rk_usb,vdatsrcenb = <0x328  7 1>;
1045                         rk_usb,vdatdetenb = <0x328  6 1>;
1046                         rk_usb,chrgsel    = <0x328  5 1>;
1047                         rk_usb,chgdet     = <0x2cc 23 1>;
1048                         rk_usb,fsvminus   = <0x2cc 25 1>;
1049                         rk_usb,fsvplus    = <0x2cc 24 1>;
1050                 };
1051         };
1052
1053         usb0: usb@ff580000 {
1054                 compatible = "rockchip,rk3288_usb20_otg";
1055                 reg = <0xff580000 0x40000>;
1056                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1057                 clocks = <&clk_gates13 4>, <&clk_gates7 4>;
1058                 clock-names = "clk_usbphy0", "hclk_usb0";
1059                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1060                 rockchip,usb-mode = <0>;
1061         };
1062
1063         usb1: usb@ff540000 {
1064                 compatible = "rockchip,rk3288_usb20_host";
1065                 reg = <0xff540000 0x40000>;
1066                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1067                 clocks = <&clk_gates13 6>, <&clk_gates7 7>,
1068                          <&usbphy_480m>;
1069                 clock-names = "clk_usbphy1", "hclk_usb1",
1070                               "usbphy_480m";
1071         };
1072
1073         usb2: usb@ff500000 {
1074                 compatible = "rockchip,rk3288_rk_ehci_host";
1075                 reg = <0xff500000 0x20000>;
1076                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1077                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1078                 clock-names = "clk_usbphy2", "hclk_usb2";
1079         };
1080
1081         usb3: usb@ff520000 {
1082                 compatible = "rockchip,rk3288_rk_ohci_host";
1083                 reg = <0xff520000 0x20000>;
1084                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1085                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1086                 clock-names = "clk_usbphy3", "hclk_usb3";
1087         };
1088
1089         hsic: hsic@ff5c0000 {
1090                 compatible = "rockchip,rk3288_rk_hsic_host";
1091                 reg = <0xff5c0000 0x40000>;
1092                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1093                 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1094                          <&hsicphy_12m>, <&usbphy_480m>,
1095                          <&otgphy1_480m>, <&otgphy2_480m>;
1096                 clock-names = "hsicphy_480m", "hclk_hsic",
1097                               "hsicphy_12m", "usbphy_480m",
1098                               "hsic_usbphy1", "hsic_usbphy2";
1099         };
1100
1101         gmac: eth@ff290000 {
1102                 compatible = "rockchip,gmac";
1103                 reg = <0xff290000 0x10000>;
1104                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1105                 interrupt-names = "macirq";
1106                 clocks = <&clk_mac>, <&clk_gates5 0>,
1107                          <&clk_gates5 1>, <&clk_gates5 2>,
1108                          <&clk_gates5 3>, <&clk_gates8 0>,
1109                          <&clk_gates8 1>;
1110                 clock-names = "clk_mac", "mac_clk_rx",
1111                               "mac_clk_tx", "clk_mac_ref",
1112                               "clk_mac_refout", "aclk_mac",
1113                               "pclk_mac";
1114                 //phy-mode = "rmii";
1115                 phy-mode = "rgmii";
1116                 pinctrl-names = "default";
1117                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
1118         };
1119
1120         gpu {
1121                 compatible = "arm,malit764",
1122                              "arm,malit76x",
1123                              "arm,malit7xx",
1124                              "arm,mali-midgard";
1125                 reg = <0xffa30000 0x10000>;
1126                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1127                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1128                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1129                 interrupt-names = "JOB", "MMU", "GPU";
1130         };
1131
1132         iep_mmu {
1133                 dbgname = "iep";
1134                 compatible = "iommu,iep_mmu";
1135                 reg = <0xff900800 0x100>;
1136                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1137                 interrupt-names = "iep_mmu";
1138         };
1139
1140         vip_mmu {
1141                 dbgname = "vip";
1142                 compatible = "iommu,vip_mmu";
1143                 reg = <0xff950800 0x100>;
1144                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1145                 interrupt-names = "vip_mmu";
1146         };
1147
1148         vopb_mmu {
1149                 dbgname = "vopb";
1150                 compatible = "iommu,vopb_mmu";
1151                 reg = <0xff930300 0x100>;
1152                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1153                 interrupt-names = "vopb_mmu";
1154         };
1155
1156         vopl_mmu {
1157                 dbgname = "vopl";
1158                 compatible = "iommu,vopl_mmu";
1159                 reg = <0xff940300 0x100>;
1160                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1161                 interrupt-names = "vopl_mmu";
1162         };
1163
1164         hevc_mmu {
1165                 dbgname = "hevc";
1166                 compatible = "iommu,hevc_mmu";
1167                 reg = <0xff9c0440 0x100>,
1168                       <0xff9c0480 0x100>;
1169                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1170                 interrupt-names = "hevc_mmu";
1171         };
1172
1173         vpu_mmu {
1174                 dbgname = "vpu";
1175                 compatible = "iommu,vpu_mmu";
1176                 reg = <0xff9a0800 0x100>;
1177                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1178                 interrupt-names = "vpu_mmu";
1179         };
1180
1181         isp_mmu {
1182                 dbgname = "isp_mmu";
1183                 compatible = "iommu,isp_mmu";
1184                 reg = <0xff914000 0x100>,
1185                       <0xff915000 0x100>;
1186                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1187                 interrupt-names = "isp_mmu";
1188         };
1189
1190         rockchip_suspend {
1191                 rockchip,ctrbits = <
1192                         (0
1193                          |RKPM_CTR_PWR_DMNS
1194                          |RKPM_CTR_GTCLKS
1195                          |RKPM_CTR_PLLS
1196                  //      |RKPM_CTR_GPIOS
1197                 //       |RKPM_CTR_SYSCLK_DIV
1198                 //       |RKPM_CTR_IDLEAUTO_MD
1199                 //       |RKPM_CTR_ARMOFF_LPMD
1200                          |RKPM_CTR_ARMOFF_LOGDP_LPMD
1201                         )
1202                         >;
1203                 rockchip,pmic-suspend_gpios = <
1204                         RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H)
1205                         >;
1206                 rockchip,pmic-resume_gpios = <
1207                         RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN)
1208                         >;
1209
1210         };
1211
1212         isp: isp@ff910000{
1213                 compatible = "rockchip,isp";
1214                 reg = <0xff910000 0x10000>;
1215                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1216                 clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, <&clk_isp_jpe>, <&clkin_isp>, <&clk_cif_out>, <&clk_gates5 15>, <&clk_cif_pll>, <&pd_isp>, <&clk_gates16 6>;
1217                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_mipi_24m", "clk_cif_pll", "pd_isp", "hclk_mipiphy1";
1218                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1219                 pinctrl-0 = <&isp_mipi>;
1220                 pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
1221                 pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
1222                 pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1223                 pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
1224                 pinctrl-5 = <&isp_mipi>;
1225                 pinctrl-6 = <&isp_mipi &isp_prelight>;
1226                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1227                 pinctrl-8 = <&isp_flash_trigger>;
1228                 rockchip,isp,mipiphy = <2>;
1229                 rockchip,isp,cifphy = <1>;
1230                 rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
1231                 rockchip,gpios = <&gpio7 GPIO_B5 GPIO_ACTIVE_HIGH>;
1232                 status = "okay";
1233         };
1234
1235         tsadc: tsadc@ff280000 {
1236                 compatible = "rockchip,tsadc";
1237                 reg = <0xff280000 0x100>;
1238                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1239                 #io-channel-cells = <1>;
1240                 io-channel-ranges;
1241                 clock-frequency = <10000>;
1242                 clocks = <&clk_tsadc>, <&clk_gates7 2>;
1243                 clock-names = "tsadc", "pclk_tsadc";
1244                 pinctrl-names = "default", "tsadc_int";
1245                 pinctrl-0 = <&tsadc_gpio>;
1246                 pinctrl-1 = <&tsadc_int>;
1247                 tsadc-ht-temp = <120>;
1248                 tsadc-ht-reset-cru = <1>;
1249                 tsadc-ht-pull-gpio = <0>;
1250                 status = "okay";
1251         };
1252
1253         lcdc_vdd_domain: lcdc-vdd-domain {
1254                 compatible = "rockchip,io_vol_domain";
1255                 pinctrl-names = "default", "1.8V", "3.3V";
1256                 pinctrl-0 = <&lcdc_vcc>;
1257                 pinctrl-1 = <&lcdc_vcc_18>;
1258                 pinctrl-2 = <&lcdc_vcc_33>;
1259         };
1260
1261         dpio_vdd_domain: dpio-vdd-domain {
1262                 compatible = "rockchip,io_vol_domain";
1263                 pinctrl-names = "default", "1.8V", "3.3V";
1264                 pinctrl-0 = <&dvp_vcc>;
1265                 pinctrl-1 = <&dvp_vcc_18>;
1266                 pinctrl-2 = <&dvp_vcc_33>;
1267         };
1268
1269         flash0_vdd_domain: flash0-vdd-domain {
1270                 compatible = "rockchip,io_vol_domain";
1271                 pinctrl-names = "default", "1.8V", "3.3V";
1272                 pinctrl-0 = <&flash0_vcc>;
1273                 pinctrl-1 = <&flash0_vcc_18>;
1274                 pinctrl-2 = <&flash0_vcc_33>;
1275         };
1276
1277         flash1_vdd_domain: flash1-vdd-domain {
1278                 compatible = "rockchip,io_vol_domain";
1279                 pinctrl-names = "default", "1.8V", "3.3V";
1280                 pinctrl-0 = <&flash1_vcc>;
1281                 pinctrl-1 = <&flash1_vcc_18>;
1282                 pinctrl-2 = <&flash1_vcc_33>;
1283         };
1284
1285         apio3_vdd_domain: apio3-vdd-domain {
1286                 compatible = "rockchip,io_vol_domain";
1287                 pinctrl-names = "default", "1.8V", "3.3V";
1288                 pinctrl-0 = <&wifi_vcc>;
1289                 pinctrl-1 = <&wifi_vcc_18>;
1290                 pinctrl-2 = <&wifi_vcc_33>;
1291         };
1292
1293         apio5_vdd_domain: apio5-vdd-domain {
1294                 compatible = "rockchip,io_vol_domain";
1295                 pinctrl-names = "default", "1.8V", "3.3V";
1296                 pinctrl-0 = <&bb_vcc>;
1297                 pinctrl-1 = <&bb_vcc_18>;
1298                 pinctrl-2 = <&bb_vcc_33>;
1299         };
1300
1301         apio4_vdd_domain: apio4-vdd-domain {
1302                 compatible = "rockchip,io_vol_domain";
1303                 pinctrl-names = "default", "1.8V", "3.3V";
1304                 pinctrl-0 = <&audio_vcc>;
1305                 pinctrl-1 = <&audio_vcc_18>;
1306                 pinctrl-2 = <&audio_vcc_33>;
1307         };
1308
1309         apio1_vdd_domain: apio0-vdd-domain {
1310                 compatible = "rockchip,io_vol_domain";
1311                 pinctrl-names = "default", "1.8V", "3.3V";
1312                 pinctrl-0 = <&gpio30_vcc>;
1313                 pinctrl-1 = <&gpio30_vcc_18>;
1314                 pinctrl-2 = <&gpio30_vcc_33>;
1315         };
1316
1317         apio2_vdd_domain: apio2-vdd-domain {
1318                 compatible = "rockchip,io_vol_domain";
1319                 pinctrl-names = "default", "1.8V", "3.3V";
1320                 pinctrl-0 = <&gpio1830_vcc>;
1321                 pinctrl-1 = <&gpio1830_vcc_18>;
1322                 pinctrl-2 = <&gpio1830_vcc_33>;
1323         };
1324
1325         sdmmc0_vdd_domain: sdmmc0-vdd-domain {
1326                 compatible = "rockchip,io_vol_domain";
1327                 pinctrl-names = "default", "1.8V", "3.3V";
1328                 pinctrl-0 = <&sdcard_vcc>;
1329                 pinctrl-1 = <&sdcard_vcc_18>;
1330                 pinctrl-2 = <&sdcard_vcc_33>;
1331         };
1332 };