arch/arm/boot/dts/rk3288.dtsi

   1 #include <dt-bindings/clock/rk_system_status.h>
   2 #include <dt-bindings/interrupt-controller/arm-gic.h>
   3 #include <dt-bindings/rkfb/rk_fb.h>
   4 #include <dt-bindings/rkmipi/mipi_dsi.h>
   5 #include <dt-bindings/suspend/rockchip-pm.h>
   6 #include <dt-bindings/sensor-dev.h>
   7
   8 #include "skeleton.dtsi"
   9 #include "rk3288-pinctrl.dtsi"
  10 #include "rk3288-clocks.dtsi"
  11
  12 / {
  13         compatible = "rockchip,rk3288";
  14         rockchip,sram = <&sram>;
  15         interrupt-parent = <&gic>;
  16
  17         aliases {
  18                 serial0 = &uart_bt;
  19                 serial1 = &uart_bb;
  20                 serial2 = &uart_dbg;
  21                 serial3 = &uart_gps;
  22                 serial4 = &uart_exp;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 lcdc0 = &lcdc0;
  30                 lcdc1 = &lcdc1;
  31                 spi0 = &spi0;
  32                 spi1 = &spi1;
  33                 spi2 = &spi2;
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 cpu@0 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <0x500>;
  44                 };
  45                 cpu@1 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a15";
  48                         reg = <0x501>;
  49                 };
  50                 cpu@2 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a15";
  53                         reg = <0x502>;
  54                 };
  55                 cpu@3 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a15";
  58                         reg = <0x503>;
  59                 };
  60         };
  61
  62         gic: interrupt-controller@ffc01000 {
  63                 compatible = "arm,cortex-a15-gic";
  64                 interrupt-controller;
  65                 #interrupt-cells = <3>;
  66                 #address-cells = <0>;
  67                 reg = <0xffc01000 0x1000>,
  68                       <0xffc02000 0x1000>;
  69         };
  70
  71         arm-pmu {
  72                 compatible = "arm,cortex-a12-pmu";
  73                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  74                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  75                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  76                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  77         };
  78
  79         cpu_axi_bus: cpu_axi_bus {
  80                 compatible = "rockchip,cpu_axi_bus";
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 ranges;
  84
  85                 qos {
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         ranges;
  89                         /* service core */
  90                         cpup {
  91                                 reg = <0xffa80000 0x20>;
  92                         };
  93                         cpum_r {
  94                                 reg = <0xffa80080 0x20>;
  95                         };
  96                         cpum_w {
  97                                 reg = <0xffa80100 0x20>;
  98                         };
  99                         /* service dmac */
 100                         bus_dmac {
 101                                 reg = <0xffa90000 0x20>;
 102                         };
 103                         host {
 104                                 reg = <0xffa90080 0x20>;
 105                         };
 106                         crypto {
 107                                 reg = <0xffa90100 0x20>;
 108                         };
 109                         ccp {
 110                                 reg = <0xffa90180 0x20>;
 111                         };
 112                         ccs {
 113                                 reg = <0xffa90200 0x20>;
 114                         };
 115                         /* service gpu */
 116                         gpu_r {
 117                                 reg = <0xffaa0000 0x20>;
 118                         };
 119                         gpu_w {
 120                                 reg = <0xffaa0080 0x20>;
 121                         };
 122                         /* service peri */
 123                         peri {
 124                                 reg = <0xffab0000 0x20>;
 125                         };
 126                         /* service vio */
 127                         vio1_vop {
 128                                 reg = <0xffad0000 0x20>;
 129                                 rockchip,priority = <2 2>;
 130                         };
 131                         vio1_isp_w0 {
 132                                 reg = <0xffad0100 0x20>;
 133                                 rockchip,priority = <2 2>;
 134                         };
 135                         vio1_isp_w1 {
 136                                 reg = <0xffad0180 0x20>;
 137                         };
 138                         vio0_vop {
 139                                 reg = <0xffad0400 0x20>;
 140                                 rockchip,priority = <2 2>;
 141                         };
 142                         vio0_vip {
 143                                 reg = <0xffad0480 0x20>;
 144                         };
 145                         vio0_iep {
 146                                 reg = <0xffad0500 0x20>;
 147                         };
 148                         vio2_rga_r {
 149                                 reg = <0xffad0800 0x20>;
 150                         };
 151                         vio2_rga_w {
 152                                 reg = <0xffad0880 0x20>;
 153                         };
 154                         vio1_isp_r {
 155                                 reg = <0xffad0900 0x20>;
 156                         };
 157                         /* service video */
 158                         video {
 159                                 reg = <0xffae0000 0x20>;
 160                         };
 161                         /* service hevc */
 162                         hevc_r {
 163                                 reg = <0xffaf0000 0x20>;
 164                         };
 165                         hevc_w {
 166                                 reg = <0xffaf0080 0x20>;
 167                         };
 168                 };
 169
 170                 msch {
 171                         #address-cells = <1>;
 172                         #size-cells = <1>;
 173                         ranges;
 174
 175                         msch@0 {
 176                                 reg = <0xffac0000 0x40>;
 177                                 rockchip,read-latency = <0x34>;
 178                         };
 179                         msch@1 {
 180                                 reg = <0xffac0080 0x40>;
 181                                 rockchip,read-latency = <0x34>;
 182                         };
 183                 };
 184         };
 185
 186         sram: sram@ff710000 {
 187                 compatible = "mmio-sram";
 188                 reg = <0xff710000 0x8000>; /* 32k */
 189                 map-exec;
 190         };
 191
 192         timer {
 193                 compatible = "arm,armv7-timer";
 194                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 195                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 196                 clock-frequency = <24000000>;
 197         };
 198
 199         timer@ff810000 {
 200                 compatible = "rockchip,timer";
 201                 reg = <0xff810000 0x20>;
 202                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 203                 rockchip,broadcast = <1>;
 204         };
 205
 206         watchdog: wdt@2004c000 {
 207                 compatible = "rockchip,watch dog";
 208                 reg = <0xff800000 0x100>;
 209                 clocks = <&pclk_pd_alive>;
 210                 clock-names = "pclk_wdt";
 211                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 212                 rockchip,irq = <1>;
 213                 rockchip,timeout = <60>;
 214                 rockchip,atboot = <1>;
 215                 rockchip,debug = <0>;
 216                 status = "disabled";
 217         };
 218
 219         amba {
 220                 #address-cells = <1>;
 221                 #size-cells = <1>;
 222                 compatible = "arm,amba-bus";
 223                 interrupt-parent = <&gic>;
 224                 ranges;
 225
 226                 pdma0: pdma@ffb20000 {
 227                         compatible = "arm,pl330", "arm,primecell";
 228                         reg = <0xffb20000 0x4000>;
 229                         clocks = <&clk_gates10 12>;
 230                         clock-names = "apb_pclk";
 231                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 232                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 233                         #dma-cells = <1>;
 234                 };
 235
 236                 pdma1: pdma@ff250000 {
 237                         compatible = "arm,pl330", "arm,primecell";
 238                         reg = <0xff250000 0x4000>;
 239                         clocks = <&clk_gates6 3>;
 240                         clock-names = "apb_pclk";
 241                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 242                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 243                         #dma-cells = <1>;
 244                 };
 245         };
 246
 247         reset: reset@ff7601b8{
 248                 compatible = "rockchip,reset";
 249                 reg = <0xff7601b8 0x30>;
 250                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 251                 #reset-cells = <1>;
 252         };
 253
 254         nandc0: nandc@0xff400000 {
 255                 compatible = "rockchip,rk-nandc";
 256                 reg = <0xff400000 0x4000>;
 257                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 258                 nandc_id = <0>;
 259                 clocks = <&clk_nandc0>, <&clk_gates5 5>, <&clk_gates7 14>;
 260                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 261         };
 262
 263         nandc1: nandc@0xff410000 {
 264             compatible = "rockchip,rk-nandc";
 265                 reg = <0xff410000 0x4000>;
 266                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 267                 nandc_id = <1>;
 268                 clocks = <&clk_nandc1>, <&clk_gates5 6>, <&clk_gates7 15>;
 269                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 270         };
 271
 272         nandc0reg: nandc0@0xff400000 {
 273                 compatible = "rockchip,rk-nandc";
 274                 reg = <0xff400000 0x4000>;
 275         };
 276
 277         emmc: rksdmmc@ff0f0000 {
 278                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 279                 reg = <0xff0f0000 0x4000>;
 280                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 281                 #address-cells = <1>;
 282                 #size-cells = <0>;
 283                 //pinctrl-names = "default",,"suspend";
 284                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 285                 clocks = <&clk_emmc>, <&clk_gates8 6>;
 286                 clock-names = "clk_mmc", "hclk_mmc";
 287                 num-slots = <1>;
 288                 fifo-depth = <0x100>;
 289                 bus-width = <8>;
 290         };
 291
 292         sdmmc: rksdmmc@ff0c0000 {
 293                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 294                 reg = <0xff0c0000 0x4000>;
 295                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 296                 #address-cells = <1>;
 297                 #size-cells = <0>;
 298                 pinctrl-names = "default", "idle";
 299                 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 300                 pinctrl-1 = <&sdmmc0_gpio>;
 301                 cd-gpios = <&gpio6 GPIO_C6 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 302                 clocks = <&clk_sdmmc>, <&clk_gates8 3>;
 303                 clock-names = "clk_mmc", "hclk_mmc";
 304                 num-slots = <1>;
 305                 fifo-depth = <0x100>;
 306                 bus-width = <4>;
 307         };
 308
 309         sdio: rksdmmc@ff0d0000 {
 310                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 311                 reg = <0xff0d0000 0x4000>;
 312                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 313                 #address-cells = <1>;
 314                 #size-cells = <0>;
 315                 pinctrl-names = "default","idle";
 316                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwr &sdio0_bkpwr
 317                              &sdio0_intn &sdio0_bus4>;
 318                 pinctrl-1 = <&sdio0_gpio>;
 319                 clocks = <&clk_sdio0>, <&clk_gates8 4>;
 320                 clock-names = "clk_mmc", "hclk_mmc";
 321                 num-slots = <1>;
 322                 fifo-depth = <0x100>;
 323                 bus-width = <4>;
 324         };
 325
 326         sdio1: rksdmmc@ff0e0000 {
 327                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 328                 reg = <0xff0e0000 0x4000>;
 329                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 330                 #address-cells = <1>;
 331                 #size-cells = <0>;
 332                 //pinctrl-names = "default","suspend";
 333                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 334                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/
 335                 clocks = <&clk_sdio1>, <&clk_gates8 5>;
 336                 clock-names = "clk_mmc", "hclk_mmc";
 337                 num-slots = <1>;
 338                 fifo-depth = <0x100>;
 339                 bus-width = <4>;
 340                 status = "disabled";
 341         };
 342
 343         spi0: spi@ff110000 {
 344                 compatible = "rockchip,rockchip-spi";
 345                 reg = <0xff110000 0x1000>;
 346                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 347                 #address-cells = <1>;
 348                 #size-cells = <0>;
 349                 pinctrl-names = "default";
 350                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 351                 rockchip,spi-src-clk = <0>;
 352                 num-cs = <2>;
 353                 clocks =<&clk_spi0>, <&clk_gates6 4>;
 354                 clock-names = "spi","pclk_spi0";
 355                 dmas = <&pdma1 11>, <&pdma1 12>;
 356                 #dma-cells = <2>;
 357                 dma-names = "tx", "rx";
 358                 status = "disabled";
 359         };
 360
 361         spi1: spi@ff120000 {
 362                 compatible = "rockchip,rockchip-spi";
 363                 reg = <0xff120000 0x1000>;
 364                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 365                 #address-cells = <1>;
 366                 #size-cells = <0>;
 367                 pinctrl-names = "default";
 368                 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0>;
 369                 rockchip,spi-src-clk = <1>;
 370                 num-cs = <1>;
 371                 clocks = <&clk_spi1>, <&clk_gates6 5>;
 372                 clock-names = "spi","pclk_spi1";
 373                 dmas = <&pdma1 13>, <&pdma1 14>;
 374                 #dma-cells = <2>;
 375                 dma-names = "tx", "rx";
 376                 status = "disabled";
 377         };
 378
 379         spi2: spi@ff130000 {
 380                 compatible = "rockchip,rockchip-spi";
 381                 reg = <0xff130000 0x1000>;
 382                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 383                 #address-cells = <1>;
 384                 #size-cells = <0>;
 385                 pinctrl-names = "default";
 386                 pinctrl-0 = <&spi2_txd &spi2_rxd &spi2_clk &spi2_cs0 &spi2_cs1>;
 387                 rockchip,spi-src-clk = <2>;
 388                 num-cs = <2>;
 389                 clocks = <&clk_spi2>, <&clk_gates6 6>;
 390                 clock-names = "spi","pclk_spi2";
 391                 dmas = <&pdma1 15>, <&pdma1 16>;
 392                 #dma-cells = <2>;
 393                 dma-names = "tx", "rx";
 394                 status = "disabled";
 395         };
 396
 397         uart_bt: serial@ff180000 {
 398                 compatible = "rockchip,serial";
 399                 reg = <0xff180000 0x100>;
 400                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 401                 clock-frequency = <24000000>;
 402                 clocks = <&clk_uart0>, <&clk_gates6 8>;
 403                 clock-names = "sclk_uart", "pclk_uart";
 404                 reg-shift = <2>;
 405                 reg-io-width = <4>;
 406                 dmas = <&pdma1 1>, <&pdma1 2>;
 407                 #dma-cells = <2>;
 408                 pinctrl-names = "default";
 409                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 410                 status = "disabled";
 411         };
 412
 413         uart_bb: serial@ff190000 {
 414                 compatible = "rockchip,serial";
 415                 reg = <0xff190000 0x100>;
 416                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 417                 clock-frequency = <24000000>;
 418                 clocks = <&clk_uart1>, <&clk_gates6 9>;
 419                 clock-names = "sclk_uart", "pclk_uart";
 420                 reg-shift = <2>;
 421                 reg-io-width = <4>;
 422                 dmas = <&pdma1 3>, <&pdma1 4>;
 423                 #dma-cells = <2>;
 424                 pinctrl-names = "default";
 425                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 426                 status = "disabled";
 427         };
 428
 429         uart_dbg: serial@ff690000 {
 430                 compatible = "rockchip,serial";
 431                 reg = <0xff690000 0x100>;
 432                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 433                 clock-frequency = <24000000>;
 434                 clocks = <&clk_uart2>, <&clk_gates11 9>;
 435                 clock-names = "sclk_uart", "pclk_uart";
 436                 reg-shift = <2>;
 437                 reg-io-width = <4>;
 438                 dmas = <&pdma0 4>, <&pdma0 5>;
 439                 #dma-cells = <2>;
 440                 pinctrl-names = "default";
 441                 pinctrl-0 = <&uart2_xfer>;
 442                 status = "disabled";
 443         };
 444
 445         uart_gps: serial@ff1b0000 {
 446                 compatible = "rockchip,serial";
 447                 reg = <0xff1b0000 0x100>;
 448                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 449                 clock-frequency = <24000000>;
 450                 clocks = <&clk_uart3>, <&clk_gates6 11>;
 451                 clock-names = "sclk_uart", "pclk_uart";
 452                 current-speed = <115200>;
 453                 reg-shift = <2>;
 454                 reg-io-width = <4>;
 455                 dmas = <&pdma1 7>, <&pdma1 8>;
 456                 #dma-cells = <2>;
 457                 pinctrl-names = "default";
 458                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 459                 status = "disabled";
 460         };
 461
 462         uart_exp: serial@ff1c0000 {
 463                 compatible = "rockchip,serial";
 464                 reg = <0xff1c0000 0x100>;
 465                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 466                 clock-frequency = <24000000>;
 467                 clocks = <&clk_uart4>, <&clk_gates6 12>;
 468                 clock-names = "sclk_uart", "pclk_uart";
 469                 reg-shift = <2>;
 470                 reg-io-width = <4>;
 471                 dmas = <&pdma1 9>, <&pdma1 10>;
 472                 #dma-cells = <2>;
 473                 pinctrl-names = "default";
 474                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 475                 status = "disabled";
 476         };
 477
 478         fiq-debugger {
 479                 compatible = "rockchip,fiq-debugger";
 480                 rockchip,serial-id = <2>;
 481                 rockchip,signal-irq = <106>;
 482                 rockchip,wake-irq = <0>;
 483                 status = "disabled";
 484         };
 485
 486         rockchip_clocks_init: clocks-init{
 487                 compatible = "rockchip,clocks-init";
 488                 rockchip,clocks-init-parent =
 489                         <&clk_core &clk_apll>,  <&aclk_bus_src &clk_gpll>,
 490                         <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
 491                         <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
 492                         <&usbphy_480m &otgphy2_480m>;
 493                 rockchip,clocks-init-rate =
 494                         <&clk_core 792000000>,  <&clk_gpll 297000000>,
 495                         /*<&clk_cpll 47000000>,*/       <&clk_npll 1250000000>,
 496                         <&aclk_bus_src 300000000>,      <&aclk_bus 300000000>,
 497                         <&hclk_bus 150000000>,  <&pclk_bus 75000000>,
 498                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 499                         <&hclk_peri 150000000>, <&pclk_peri 75000000>,
 500                         <&clk_gpu 200000000>,   <&aclk_vio0 300000000>,
 501                         <&aclk_vio1 300000000>, <&hclk_vio 75000000>,
 502                         <&pclk_pd_alive 100000000>,     <&pclk_pd_pmu 100000000>,
 503                         <&aclk_hevc 400000000>, <&hclk_hevc 200000000>,
 504                         <&clk_hevc_cabac 300000000>, <&clk_hevc_core 300000000>,
 505                         <&aclk_rga 300000000>, <&clk_rga 300000000>,
 506                         <&clk_vepu 300000000>, <&clk_vdpu 300000000>,
 507                         <&clk_edp 200000000>, <&clk_isp 200000000>,
 508                         <&clk_isp_jpe 400000000>, <&clk_tsp 80000000>,
 509                         <&clk_tspout 80000000>, <&clk_mac 125000000>;
 510                 rockchip,clocks-uboot-has-init =
 511                         <&aclk_vio0>;
 512         };
 513
 514         clocks-enable {
 515                 compatible = "rockchip,clocks-enable";
 516                 clocks =
 517                                 /*PLL*/
 518                                 <&clk_dpll>, <&clk_gpll>,
 519
 520                                 /*PD_CORE*/
 521                                 <&clk_gates0 2>, <&clk_core0>,
 522                                 <&clk_core1>, <&clk_core2>,
 523                                 <&clk_core3>, <&clk_l2ram>,
 524                                 <&aclk_core_m0>, <&aclk_core_mp>,
 525                                 <&atclk_core>, <&pclk_dbg_src>,
 526                                 <&clk_gates12 9>, <&clk_gates12 10>,
 527                                 <&clk_gates12 11>,
 528
 529                                 /*PD_BUS*/
 530                                 <&aclk_bus>, <&clk_gates0 3>,
 531                                 <&hclk_bus>, <&pclk_bus>,
 532                                 <&clk_gates13 8>,
 533                                 <&clk_gates0 7>,
 534
 535                                 /*TIMER*/
 536                                 <&clk_gates1 0>, <&clk_gates1 1>,
 537                                 <&clk_gates1 2>, <&clk_gates1 3>,
 538                                 <&clk_gates1 4>, <&clk_gates1 5>,
 539
 540                                 <&pclk_pd_alive>, <&pclk_pd_pmu>,
 541
 542                                 /*PD_PERI*/
 543                                 <&aclk_peri>, <&hclk_peri>,
 544                                 <&pclk_peri>,
 545
 546                                 /*JTAG*/
 547                                 /*<&clk_gates4 14>,*/
 548
 549                                 /*aclk_bus*/
 550                                 <&clk_gates10 5>,/*aclk_intmem0*/
 551                                 <&clk_gates10 6>,/*aclk_intmem1*/
 552                                 <&clk_gates10 7>,/*aclk_intmem2*/
 553                                 /*<&clk_gates10 12>,*//*aclk_dma1*/
 554                                 <&clk_gates10 13>,/*aclk_strc_sys*/
 555                                 <&clk_gates10 4>,/*aclk_intmem*/
 556
 557                                 /*hclk_bus*/
 558                                 <&clk_gates10 9>,/*hclk_rom*/
 559
 560                                 /*pclk_bus*/
 561                                 <&clk_gates10 1>,/*pclk_timer*/
 562                                 <&clk_gates10 9>,/*rom*/
 563                                 <&clk_gates10 13>,/*aclk strc*/
 564
 565                                 <&clk_gates12 8>,/*aclk strc*/
 566
 567                                 /*aclk_peri*/
 568                                 <&clk_gates6 2>,/*aclk_peri_axi_matrix*/
 569                                 /*<&clk_gates6 3>,*//*aclk_dmac2*/
 570                                 <&clk_gates7 11>,/*aclk_peri_niu*/
 571                                 <&clk_gates8 12>,/*aclk_peri_mmu*/
 572
 573                                 /*hclk_peri*/
 574                                 <&clk_gates6 0>,/*hclk_peri_matrix*/
 575                                 <&clk_gates7 10>,/*hclk_peri_ahb_arbi*/
 576                                 <&clk_gates7 12>,/*hclk_emem_peri*/
 577                                 <&clk_gates7 13>,/*hclk_mem_peri*/
 578
 579                                 /*pclk_peri*/
 580                                 <&clk_gates6 1>,/*pclk_peri_axi_matrix*/
 581
 582                                 /*pclk_pd_alive*/
 583                                 <&clk_gates14 11>,/*pclk_grf*/
 584                                 <&clk_gates14 12>,/*pclk_alive_niu*/
 585
 586                                 /*pclk_pd_pmu*/
 587                                 <&clk_gates17 0>,/*pclk_pmu*/
 588                                 <&clk_gates17 1>,/*pclk_intmem1*/
 589                                 <&clk_gates17 2>,/*pclk_pmu_niu*/
 590                                 <&clk_gates17 3>,/*pclk_sgrf*/
 591
 592                                 /*UART*/
 593                                 <&clk_gates11 9>,/*pclk_uart2*/
 594
 595                                 /*480M*/
 596                                 <&usbphy_480m>;
 597         };
 598
 599         i2c0: i2c@ff650000 {
 600                 compatible = "rockchip,rk30-i2c";
 601                 reg = <0xff650000 0x1000>;
 602                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 603                 #address-cells = <1>;
 604                 #size-cells = <0>;
 605                 pinctrl-names = "default", "gpio";
 606                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 607                 pinctrl-1 = <&i2c0_gpio>;
 608                 gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 609                 clocks = <&clk_gates10 2>;
 610                 rockchip,check-idle = <1>;
 611                 status = "disabled";
 612         };
 613
 614         i2c1: i2c@ff140000 {
 615                 compatible = "rockchip,rk30-i2c";
 616                 reg = <0xff140000 0x1000>;
 617                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 618                 #address-cells = <1>;
 619                 #size-cells = <0>;
 620                 pinctrl-names = "default", "gpio";
 621                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 622                 pinctrl-1 = <&i2c1_gpio>;
 623                 gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 624                 clocks = <&clk_gates6 13>;
 625                 rockchip,check-idle = <1>;
 626                 status = "disabled";
 627         };
 628
 629         i2c2: i2c@ff660000 {
 630                 compatible = "rockchip,rk30-i2c";
 631                 reg = <0xff660000 0x1000>;
 632                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 633                 #address-cells = <1>;
 634                 #size-cells = <0>;
 635                 pinctrl-names = "default", "gpio";
 636                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 637                 pinctrl-1 = <&i2c2_gpio>;
 638                 gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 639                 clocks = <&clk_gates10 3>;
 640                 rockchip,check-idle = <1>;
 641                 status = "disabled";
 642         };
 643
 644         i2c3: i2c@ff150000 {
 645                 compatible = "rockchip,rk30-i2c";
 646                 reg = <0xff150000 0x1000>;
 647                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 648                 #address-cells = <1>;
 649                 #size-cells = <0>;
 650                 pinctrl-names = "default", "gpio";
 651                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 652                 pinctrl-1 = <&i2c3_gpio>;
 653                 gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
 654                 clocks = <&clk_gates6 14>;
 655                 rockchip,check-idle = <1>;
 656                 status = "disabled";
 657         };
 658
 659         i2c4: i2c@ff160000 {
 660                 compatible = "rockchip,rk30-i2c";
 661                 reg = <0xff160000 0x1000>;
 662                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 663                 #address-cells = <1>;
 664                 #size-cells = <0>;
 665                 pinctrl-names = "default", "gpio";
 666                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 667                 pinctrl-1 = <&i2c4_gpio>;
 668                 gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
 669                 clocks = <&clk_gates6 15>;
 670                 rockchip,check-idle = <1>;
 671                 status = "disabled";
 672         };
 673
 674         i2c5: i2c@ff170000 {
 675                 compatible = "rockchip,rk30-i2c";
 676                 reg = <0xff170000 0x1000>;
 677                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 678                 #address-cells = <1>;
 679                 #size-cells = <0>;
 680                 pinctrl-names = "default", "gpio";
 681                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 682                 pinctrl-1 = <&i2c5_gpio>;
 683                 gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
 684                 clocks = <&clk_gates7 0>;
 685                 rockchip,check-idle = <1>;
 686                 status = "disabled";
 687         };
 688
 689         fb: fb{
 690                 compatible = "rockchip,rk-fb";
 691                 rockchip,disp-mode = <DUAL>;
 692         };
 693
 694         rk_screen: rk_screen{
 695                         compatible = "rockchip,screen";
 696         };
 697
 698         dsihost0: mipi@ff960000{
 699                 compatible = "rockchip,rk32-dsi";
 700                 rockchip,prop = <0>;
 701                 reg = <0xff960000 0x4000>;
 702                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 703                 clocks = <&clk_gates5 15>, <&clk_gates16 4> , <&pd_mipidsi>;
 704                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
 705                 status = "disabled";
 706         };
 707
 708         dsihost1: mipi@ff964000{
 709                 compatible = "rockchip,rk32-dsi";
 710                 rockchip,prop = <1>;
 711                 reg = <0xff964000 0x4000>;
 712                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 713                 clocks = <&clk_gates5 15>, <&clk_gates16 5>, <&pd_mipidsi>;
 714                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
 715                 status = "disabled";
 716         };
 717
 718         lvds: lvds@ff96c000 {
 719                 compatible = "rockchip,rk32-lvds";
 720                 reg = <0xff96c000 0x4000>;
 721                 clocks = <&clk_gates16 7>;
 722                 clock-names = "pclk_lvds";
 723         };
 724
 725         edp: edp@ff970000 {
 726                 compatible = "rockchip,rk32-edp";
 727                 reg = <0xff970000 0x4000>;
 728                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 729                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates16 8>;
 730                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 731         };
 732
 733         hdmi: hdmi@ff980000 {
 734                 compatible = "rockchip,rk3288-hdmi";
 735                 reg = <0xff980000 0x20000>;
 736                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 737                 pinctrl-names = "default", "sleep";
 738                 pinctrl-0 = <&i2c5_sda &i2c5_scl &hdmi_cec>;
 739                 pinctrl-1 = <&i2c5_gpio>;
 740                 clocks = <&clk_gates16 9>, <&clk_gates5 12>, <&clk_gates5 11>;
 741                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 742                 rockchip,hdmi_video_source = <DISPLAY_SOURCE_LCDC0>;
 743                 rockchip,hdmi_audio_source = <0>;
 744                 rockchip,hdcp_enable = <0>;
 745                 rockchip,cec_enable = <0>;
 746                 status = "disabled";
 747         };
 748
 749         lcdc0: lcdc@ff930000 {
 750                 compatible = "rockchip,rk3288-lcdc";
 751                 rockchip,prop = <PRMRY>;
 752                 rockchip,pwr18 = <0>;
 753                 rockchip,iommu-enabled = <0>;
 754                 reg = <0xff930000 0x10000>;
 755                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 756                 pinctrl-names = "default", "gpio";
 757                 pinctrl-0 = <&lcdc0_lcdc>;
 758                 pinctrl-1 = <&lcdc0_gpio>;
 759                 status = "disabled";
 760                 clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>, <&pd_vop0>;
 761                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
 762         };
 763
 764         lcdc1: lcdc@ff940000 {
 765                 compatible = "rockchip,rk3288-lcdc";
 766                 rockchip,prop = <EXTEND>;
 767                 rockchip,pwr18 = <0>;
 768                 rockchip,iommu-enabled = <0>;
 769                 reg = <0xff940000 0x10000>;
 770                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 771                 status = "disabled";
 772                 clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>, <&pd_vop1>;
 773                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
 774         };
 775
 776         adc: adc@ff100000 {
 777                 compatible = "rockchip,saradc";
 778                 reg = <0xff100000 0x100>;
 779                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 780                 #io-channel-cells = <1>;
 781                 io-channel-ranges;
 782                 rockchip,adc-vref = <1800>;
 783                 clock-frequency = <1000000>;
 784                 clocks = <&clk_saradc>, <&clk_gates7 1>;
 785                 clock-names = "saradc", "pclk_saradc";
 786                 status = "disabled";
 787         };
 788
 789         rga@ff920000 {
 790                 compatible = "rockchip,rk3288-rga2";
 791                 reg = <0xff920000 0x1000>;
 792                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 793                 clocks = <&clk_gates15 1>, <&aclk_rga>, <&clk_rga>;
 794                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 795         };
 796
 797         i2s: rockchip-i2s@0xff890000 {
 798                 compatible = "rockchip-i2s";
 799                 reg = <0xff890000 0x10000>;
 800                 i2s-id = <0>;
 801                 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates10 8>;
 802                 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
 803                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 804                 dmas = <&pdma0 0>, <&pdma0 1>;
 805                 //#dma-cells = <2>;
 806                 dma-names = "tx", "rx";
 807                 pinctrl-names = "default", "sleep";
 808                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 809                 pinctrl-1 = <&i2s_gpio>;
 810         };
 811
 812         spdif: rockchip-spdif@0xff8b0000 {
 813                 compatible = "rockchip-spdif";
 814                 reg = <0xff8b0000 0x10000>;     //8channel
 815                 //reg = <ff880000 0x10000>;//2channel
 816                 clocks = <&clk_spdif>, <&clk_spdif_8ch>,<&clk_gates10 11>;
 817                 clock-names = "spdif_mclk","spdif_8ch_mclk","spdif_hclk";
 818                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 819                 dmas = <&pdma0 3>;
 820                 //dmas = <&pdma0 2>; //2channel
 821                 //#dma-cells = <1>;
 822                 dma-names = "tx";
 823                 pinctrl-names = "default";
 824                 pinctrl-0 = <&spdif_tx>;
 825         };
 826
 827         vop1pwm: pwm@ff9401a0 {
 828                 compatible = "rockchip,vop-pwm";
 829                 reg = <0xff9401a0 0x10>;
 830                 #pwm-cells = <2>;
 831                 pinctrl-names = "default";
 832                 pinctrl-0 = <&vop1_pwm_pin>;
 833                 clocks = <&clk_gates13 11>, <&clk_gates15 7>, <&clk_gates15 8>;
 834                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 835                 status = "disabled";
 836         };
 837
 838         vop0pwm: pwm@ff9301a0 {
 839                 compatible = "rockchip,vop-pwm";
 840                 reg = <0xff9301a0 0x10>;
 841                 #pwm-cells = <2>;
 842                 pinctrl-names = "default";
 843                 pinctrl-0 = <&vop0_pwm_pin>;
 844                 clocks = <&clk_gates13 10>, <&clk_gates15 5>, <&clk_gates15 6>;
 845                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 846                 status = "disabled";
 847         };
 848
 849         pwm0: pwm@ff680000 {
 850                 compatible = "rockchip,rk-pwm";
 851                 reg = <0xff680000 0x10>;
 852                 #pwm-cells = <2>;
 853                 pinctrl-names = "default";
 854                 pinctrl-0 = <&pwm0_pin>;
 855                 clocks = <&clk_gates11 11>;
 856                 clock-names = "pclk_pwm";
 857                 status = "disabled";
 858         };
 859
 860         pwm1: pwm@ff680010 {
 861                 compatible = "rockchip,rk-pwm";
 862                 reg = <0xff680010 0x10>;
 863                 #pwm-cells = <2>;
 864                 pinctrl-names = "default";
 865                 pinctrl-0 = <&pwm1_pin>;
 866                 clocks = <&clk_gates11 11>;
 867                 clock-names = "pclk_pwm";
 868                 status = "disabled";
 869         };
 870
 871         pwm2: pwm@ff680020 {
 872                 compatible = "rockchip,rk-pwm";
 873                 reg = <0xff680020 0x10>;
 874                 #pwm-cells = <2>;
 875                 pinctrl-names = "default";
 876                 pinctrl-0 = <&pwm2_pin>;
 877                 clocks = <&clk_gates11 11>;
 878                 clock-names = "pclk_pwm";
 879                 status = "disabled";
 880         };
 881
 882         pwm3: pwm@ff680030 {
 883                 compatible = "rockchip,rk-pwm";
 884                 reg = <0xff680030 0x10>;
 885                 #pwm-cells = <2>;
 886                 pinctrl-names = "default";
 887                 pinctrl-0 = <&pwm3_pin>;
 888                 clocks = <&clk_gates11 11>;
 889                 clock-names = "pclk_pwm";
 890                 status = "disabled";
 891         };
 892
 893         dvfs {
 894
 895                 vd_arm: vd_arm {
 896                         regulator_name = "vdd_arm";
 897                         suspend_volt = <1000>; //mV
 898                         pd_core {
 899                                 clk_core_dvfs_table: clk_core {
 900                                         operating-points = <
 901                                                 /* KHz    uV */
 902                                                 312000 1100000
 903                                                 504000 1100000
 904                                                 816000 1100000
 905                                                 1008000 1100000
 906                                                 >;
 907                                         channel = <0>;
 908                                         temp-limit-enable = <1>;
 909                                         target-temp = <80>;
 910                                         normal-temp-limit = <
 911                                         /*delta-temp    delta-freq*/
 912                                                 3       96000
 913                                                 6       144000
 914                                                 9       192000
 915                                                 15      384000
 916                                                 >;
 917                                         performance-temp-limit = <
 918                                                 /*temp    freq*/
 919                                                 100     816000
 920                                                 >;
 921                                         status = "okay";
 922                                         regu-mode-table = <
 923                                                 /*freq     mode*/
 924                                                 1008000    4
 925                                                 0          3
 926                                         >;
 927                                         regu-mode-en = <0>;
 928                                 };
 929                         };
 930                 };
 931
 932                 vd_logic: vd_logic {
 933                         regulator_name = "vdd_logic";
 934                         suspend_volt = <1000>; //mV
 935                         pd_ddr {
 936                                 clk_ddr_dvfs_table: clk_ddr {
 937                                         operating-points = <
 938                                                 /* KHz    uV */
 939                                                 200000 1200000
 940                                                 300000 1200000
 941                                                 400000 1200000
 942                                                 >;
 943                                         channel = <2>;
 944                                         status = "disabled";
 945                                 };
 946                         };
 947
 948                         pd_vio {
 949                                 aclk_vio1_dvfs_table: aclk_vio1 {
 950                                         operating-points = <
 951                                                 /* KHz    uV */
 952                                                 100000 1100000
 953                                                 500000 1100000
 954                                                 >;
 955                                         status = "okay";
 956                                 };
 957                         };
 958                 };
 959
 960                 vd_gpu: vd_gpu {
 961                         regulator_name = "vdd_gpu";
 962                         suspend_volt = <1000>; //mV
 963                         pd_gpu {
 964                                 clk_gpu_dvfs_table: clk_gpu {
 965                                         operating-points = <
 966                                                 /* KHz    uV */
 967                                                 200000 1200000
 968                                                 300000 1200000
 969                                                 400000 1200000
 970                                                 >;
 971                                         channel = <1>;
 972                                         status = "okay";
 973                                         regu-mode-table = <
 974                                                 /*freq     mode*/
 975                                                 200000     4
 976                                                 0          3
 977                                         >;
 978                                         regu-mode-en = <0>;
 979                                 };
 980                         };
 981                 };
 982         };
 983
 984         ion {
 985                 compatible = "rockchip,ion";
 986                 #address-cells = <1>;
 987                 #size-cells = <0>;
 988
 989                 ion_drm: rockchip,ion-heap@5 {
 990                         compatible = "rockchip,ion-heap";
 991                         rockchip,ion_heap = <5>;
 992                         reg = <0x00000000 0x00000000>;
 993                 };
 994                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
 995                         compatible = "rockchip,ion-heap";
 996                         rockchip,ion_heap = <4>;
 997                         reg = <0x00000000 0x28000000>; /* 640MB */
 998                 };
 999                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
1000                         compatible = "rockchip,ion-heap";
1001                         rockchip,ion_heap = <0>;
1002                 };
1003         };
1004
1005         vpu: vpu_service@ff9a0000 {
1006                 compatible = "vpu_service";
1007                 iommu_enabled = <0>;
1008                 reg = <0xff9a0000 0x800>;
1009                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1010                 interrupt-names = "irq_enc", "irq_dec";
1011                 clocks = <&clk_vdpu>, <&hclk_vdpu>;
1012                 clock-names = "aclk_vcodec", "hclk_vcodec";
1013                 name = "vpu_service";
1014                 dev_mode = <0>;
1015                 //status = "disabled";
1016         };
1017
1018         hevc: hevc_service@ff9c0000 {
1019                 compatible = "rockchip,hevc_service";
1020                 iommu_enabled = <0>;
1021                 reg = <0xff9c0000 0x800>;
1022                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1023                 interrupt-names = "irq_dec";
1024                 clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1025                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1026                 dev_mode = <1>;
1027                 name = "hevc_service";
1028                 //status = "disabled";
1029         };
1030
1031         iep: iep@ff900000 {
1032                 compatible = "rockchip,iep";
1033                 iommu_enabled = <0>;
1034                 reg = <0xff900000 0x800>;
1035                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1036                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1037                 clock-names = "aclk_iep", "hclk_iep";
1038                 status = "okay";
1039         };
1040
1041         dwc_control_usb: dwc-control-usb@ff770284 {
1042                 compatible = "rockchip,rk3288-dwc-control-usb";
1043                 reg = <0xff770284 0x04>, <0xff770288 0x04>,
1044                       <0xff7702cc 0x04>, <0xff7702d4 0x04>,
1045                       <0xff770320 0x14>, <0xff770334 0x14>,
1046                       <0xff770348 0x10>, <0xff770358 0x08>,
1047                       <0xff770360 0x08>;
1048                 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
1049                             "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
1050                             "GRF_UOC0_BASE", "GRF_UOC1_BASE",
1051                             "GRF_UOC2_BASE", "GRF_UOC3_BASE",
1052                             "GRF_UOC4_BASE";
1053                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1054                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1055                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1056                 interrupt-names = "otg_id", "otg_bvalid",
1057                                   "otg_linestate", "host0_linestate",
1058                                   "host1_linestate";
1059                 clocks = <&clk_gates7 9>, <&usbphy_480m>,
1060                          <&otgphy1_480m>, <&otgphy2_480m>;
1061                 clock-names = "hclk_usb_peri", "usbphy_480m",
1062                               "usbphy1_480m", "usbphy2_480m";
1063
1064                 usb_bc {
1065                         compatible = "synopsys,phy";
1066                                         /* offset bit mask */
1067                         rk_usb,bvalid     = <0x288 14 1>;
1068                         rk_usb,iddig      = <0x288 17 1>;
1069                         rk_usb,dcdenb     = <0x328 14 1>;
1070                         rk_usb,vdatsrcenb = <0x328  7 1>;
1071                         rk_usb,vdatdetenb = <0x328  6 1>;
1072                         rk_usb,chrgsel    = <0x328  5 1>;
1073                         rk_usb,chgdet     = <0x2cc 23 1>;
1074                         rk_usb,fsvminus   = <0x2cc 25 1>;
1075                         rk_usb,fsvplus    = <0x2cc 24 1>;
1076                 };
1077         };
1078
1079         usb0: usb@ff580000 {
1080                 compatible = "rockchip,rk3288_usb20_otg";
1081                 reg = <0xff580000 0x40000>;
1082                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1083                 clocks = <&clk_gates13 4>, <&clk_gates7 4>;
1084                 clock-names = "clk_usbphy0", "hclk_usb0";
1085                 resets = <&reset RK3288_SOFT_RST_USBOTG_H>, <&reset RK3288_SOFT_RST_USBOTGPHY>,
1086                                 <&reset RK3288_SOFT_RST_USBOTGC>;
1087                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1088                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1089                 rockchip,usb-mode = <0>;
1090         };
1091
1092         usb1: usb@ff540000 {
1093                 compatible = "rockchip,rk3288_usb20_host";
1094                 reg = <0xff540000 0x40000>;
1095                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1096                 clocks = <&clk_gates13 6>, <&clk_gates7 7>,
1097                          <&usbphy_480m>;
1098                 clock-names = "clk_usbphy1", "hclk_usb1",
1099                               "usbphy_480m";
1100                 resets = <&reset RK3288_SOFT_RST_USBHOST1_H>, <&reset RK3288_SOFT_RST_USBHOST1PHY>,
1101                                 <&reset RK3288_SOFT_RST_USBHOST1C>;
1102                 reset-names = "host1_ahb", "host1_phy", "host1_controller";
1103         };
1104
1105         usb2: usb@ff500000 {
1106                 compatible = "rockchip,rk3288_rk_ehci_host";
1107                 reg = <0xff500000 0x20000>;
1108                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1109                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1110                 clock-names = "clk_usbphy2", "hclk_usb2";
1111                 resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1112                                 <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1113                 reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1114         };
1115
1116         usb3: usb@ff520000 {
1117                 compatible = "rockchip,rk3288_rk_ohci_host";
1118                 reg = <0xff520000 0x20000>;
1119                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1120                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1121                 clock-names = "clk_usbphy3", "hclk_usb3";
1122                 status = "disabled";
1123         };
1124
1125         hsic: hsic@ff5c0000 {
1126                 compatible = "rockchip,rk3288_rk_hsic_host";
1127                 reg = <0xff5c0000 0x40000>;
1128                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1129                 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1130                          <&hsicphy_12m>, <&usbphy_480m>,
1131                          <&otgphy1_480m>, <&otgphy2_480m>;
1132                 clock-names = "hsicphy_480m", "hclk_hsic",
1133                               "hsicphy_12m", "usbphy_480m",
1134                               "hsic_usbphy1", "hsic_usbphy2";
1135                 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1136                                 <&reset RK3288_SOFT_RST_HSICPHY>;
1137                 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1138         };
1139
1140         gmac: eth@ff290000 {
1141                 compatible = "rockchip,rk3288-gmac";
1142                 reg = <0xff290000 0x10000>;
1143                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1144                 interrupt-names = "macirq";
1145                 clocks = <&clk_mac>, <&clk_gates5 0>,
1146                          <&clk_gates5 1>, <&clk_gates5 2>,
1147                          <&clk_gates5 3>, <&clk_gates8 0>,
1148                          <&clk_gates8 1>;
1149                 clock-names = "clk_mac", "mac_clk_rx",
1150                               "mac_clk_tx", "clk_mac_ref",
1151                               "clk_mac_refout", "aclk_mac",
1152                               "pclk_mac";
1153                 phy-mode = "rgmii";
1154                 pinctrl-names = "default";
1155                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
1156         };
1157
1158         gpu {
1159                 compatible = "arm,malit764",
1160                              "arm,malit76x",
1161                              "arm,malit7xx",
1162                              "arm,mali-midgard";
1163                 reg = <0xffa30000 0x10000>;
1164                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1165                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1166                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1167                 interrupt-names = "JOB", "MMU", "GPU";
1168         };
1169
1170         iep_mmu {
1171                 dbgname = "iep";
1172                 compatible = "rockchip,iep_mmu";
1173                 reg = <0xff900800 0x100>;
1174                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1175                 interrupt-names = "iep_mmu";
1176         };
1177
1178         vip_mmu {
1179                 dbgname = "vip";
1180                 compatible = "rockchip,vip_mmu";
1181                 reg = <0xff950800 0x100>;
1182                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1183                 interrupt-names = "vip_mmu";
1184         };
1185
1186         vopb_mmu {
1187                 dbgname = "vopb";
1188                 compatible = "rockchip,vopb_mmu";
1189                 reg = <0xff930300 0x100>;
1190                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1191                 interrupt-names = "vopb_mmu";
1192         };
1193
1194         vopl_mmu {
1195                 dbgname = "vopl";
1196                 compatible = "rockchip,vopl_mmu";
1197                 reg = <0xff940300 0x100>;
1198                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1199                 interrupt-names = "vopl_mmu";
1200         };
1201
1202         hevc_mmu {
1203                 dbgname = "hevc";
1204                 compatible = "rockchip,hevc_mmu";
1205                 reg = <0xff9c0440 0x40>,
1206                       <0xff9c0480 0x40>;
1207                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1208                 interrupt-names = "hevc_mmu";
1209         };
1210
1211         vpu_mmu {
1212                 dbgname = "vpu";
1213                 compatible = "rockchip,vpu_mmu";
1214                 reg = <0xff9a0800 0x100>;
1215                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1216                 interrupt-names = "vpu_mmu";
1217         };
1218
1219         isp_mmu {
1220                 dbgname = "isp_mmu";
1221                 compatible = "rockchip,isp_mmu";
1222                 reg = <0xff914000 0x100>,
1223                       <0xff915000 0x100>;
1224                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1225                 interrupt-names = "isp_mmu";
1226         };
1227
1228         rockchip_suspend {
1229                 rockchip,ctrbits = <
1230                         (0
1231                          |RKPM_CTR_PWR_DMNS
1232                          |RKPM_CTR_GTCLKS
1233                          |RKPM_CTR_PLLS
1234                  //      |RKPM_CTR_GPIOS
1235                 //       |RKPM_CTR_SYSCLK_DIV
1236                 //       |RKPM_CTR_IDLEAUTO_MD
1237                 //       |RKPM_CTR_ARMOFF_LPMD
1238                          |RKPM_CTR_ARMOFF_LOGDP_LPMD
1239                         )
1240                         >;
1241                 rockchip,pmic-suspend_gpios = <
1242                         RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H)
1243                         >;
1244                 rockchip,pmic-resume_gpios = <
1245                         RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN)
1246                         >;
1247
1248         };
1249
1250         isp: isp@ff910000{
1251                 compatible = "rockchip,isp";
1252                 reg = <0xff910000 0x10000>;
1253                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1254                 clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, <&clk_isp_jpe>, <&clkin_isp>, <&clk_cif_out>, <&clk_gates5 15>, <&clk_cif_pll>, <&pd_isp>, <&clk_gates16 6>;
1255                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_mipi_24m", "clk_cif_pll", "pd_isp", "hclk_mipiphy1";
1256                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1257                 pinctrl-0 = <&isp_mipi>;
1258                 pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
1259                 pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
1260                 pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1261                 pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
1262                 pinctrl-5 = <&isp_mipi>;
1263                 pinctrl-6 = <&isp_mipi &isp_prelight>;
1264                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1265                 pinctrl-8 = <&isp_flash_trigger>;
1266                 rockchip,isp,mipiphy = <2>;
1267                 rockchip,isp,cifphy = <1>;
1268                 rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
1269                 rockchip,gpios = <&gpio7 GPIO_B5 GPIO_ACTIVE_HIGH>;
1270                 rockchip,isp,iommu_enable = <1>;
1271                 status = "okay";
1272         };
1273         cif: cif@ff950000 {
1274              compatible = "rockchip,cif";
1275              reg = <0xff950000 0x10000>;
1276              interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1277              clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&clkin_cif>,<&clk_gates16 0>,<&clk_cif_out>;
1278              clock-names = "pd_cif0", "aclk_cif0","hclk_cif0","cif0_in","g_pclkin_cif","cif0_out";
1279              pinctrl-names = "cif_pin_all";
1280              pinctrl-0 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d10d11>;
1281              status = "okay";
1282              };
1283
1284         tsadc: tsadc@ff280000 {
1285                 compatible = "rockchip,tsadc";
1286                 reg = <0xff280000 0x100>;
1287                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1288                 #io-channel-cells = <1>;
1289                 io-channel-ranges;
1290                 clock-frequency = <10000>;
1291                 clocks = <&clk_tsadc>, <&clk_gates7 2>;
1292                 clock-names = "tsadc", "pclk_tsadc";
1293                 pinctrl-names = "default", "tsadc_int";
1294                 pinctrl-0 = <&tsadc_gpio>;
1295                 pinctrl-1 = <&tsadc_int>;
1296                 tsadc-ht-temp = <120>;
1297                 tsadc-ht-reset-cru = <1>;
1298                 tsadc-ht-pull-gpio = <0>;
1299                 status = "okay";
1300         };
1301
1302         lcdc_vdd_domain: lcdc-vdd-domain {
1303                 compatible = "rockchip,io_vol_domain";
1304                 pinctrl-names = "default", "1.8V", "3.3V";
1305                 pinctrl-0 = <&lcdc_vcc>;
1306                 pinctrl-1 = <&lcdc_vcc_18>;
1307                 pinctrl-2 = <&lcdc_vcc_33>;
1308         };
1309
1310         dpio_vdd_domain: dpio-vdd-domain {
1311                 compatible = "rockchip,io_vol_domain";
1312                 pinctrl-names = "default", "1.8V", "3.3V";
1313                 pinctrl-0 = <&dvp_vcc>;
1314                 pinctrl-1 = <&dvp_vcc_18>;
1315                 pinctrl-2 = <&dvp_vcc_33>;
1316         };
1317
1318         flash0_vdd_domain: flash0-vdd-domain {
1319                 compatible = "rockchip,io_vol_domain";
1320                 pinctrl-names = "default", "1.8V", "3.3V";
1321                 pinctrl-0 = <&flash0_vcc>;
1322                 pinctrl-1 = <&flash0_vcc_18>;
1323                 pinctrl-2 = <&flash0_vcc_33>;
1324         };
1325
1326         flash1_vdd_domain: flash1-vdd-domain {
1327                 compatible = "rockchip,io_vol_domain";
1328                 pinctrl-names = "default", "1.8V", "3.3V";
1329                 pinctrl-0 = <&flash1_vcc>;
1330                 pinctrl-1 = <&flash1_vcc_18>;
1331                 pinctrl-2 = <&flash1_vcc_33>;
1332         };
1333
1334         apio3_vdd_domain: apio3-vdd-domain {
1335                 compatible = "rockchip,io_vol_domain";
1336                 pinctrl-names = "default", "1.8V", "3.3V";
1337                 pinctrl-0 = <&wifi_vcc>;
1338                 pinctrl-1 = <&wifi_vcc_18>;
1339                 pinctrl-2 = <&wifi_vcc_33>;
1340         };
1341
1342         apio5_vdd_domain: apio5-vdd-domain {
1343                 compatible = "rockchip,io_vol_domain";
1344                 pinctrl-names = "default", "1.8V", "3.3V";
1345                 pinctrl-0 = <&bb_vcc>;
1346                 pinctrl-1 = <&bb_vcc_18>;
1347                 pinctrl-2 = <&bb_vcc_33>;
1348         };
1349
1350         apio4_vdd_domain: apio4-vdd-domain {
1351                 compatible = "rockchip,io_vol_domain";
1352                 pinctrl-names = "default", "1.8V", "3.3V";
1353                 pinctrl-0 = <&audio_vcc>;
1354                 pinctrl-1 = <&audio_vcc_18>;
1355                 pinctrl-2 = <&audio_vcc_33>;
1356         };
1357
1358         apio1_vdd_domain: apio0-vdd-domain {
1359                 compatible = "rockchip,io_vol_domain";
1360                 pinctrl-names = "default", "1.8V", "3.3V";
1361                 pinctrl-0 = <&gpio30_vcc>;
1362                 pinctrl-1 = <&gpio30_vcc_18>;
1363                 pinctrl-2 = <&gpio30_vcc_33>;
1364         };
1365
1366         apio2_vdd_domain: apio2-vdd-domain {
1367                 compatible = "rockchip,io_vol_domain";
1368                 pinctrl-names = "default", "1.8V", "3.3V";
1369                 pinctrl-0 = <&gpio1830_vcc>;
1370                 pinctrl-1 = <&gpio1830_vcc_18>;
1371                 pinctrl-2 = <&gpio1830_vcc_33>;
1372         };
1373
1374         sdmmc0_vdd_domain: sdmmc0-vdd-domain {
1375                 compatible = "rockchip,io_vol_domain";
1376                 pinctrl-names = "default", "1.8V", "3.3V";
1377                 pinctrl-0 = <&sdcard_vcc>;
1378                 pinctrl-1 = <&sdcard_vcc_18>;
1379                 pinctrl-2 = <&sdcard_vcc_33>;
1380         };
1381
1382         chosen {
1383                 bootargs = "vmalloc=496M";
1384         };
1385 };