arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip_boot-mode.h>
  49 #include "skeleton.dtsi"
  50
  51 / {
  52         compatible = "rockchip,rk3288";
  53
  54         interrupt-parent = <&gic>;
  55
  56         aliases {
  57                 i2c0 = &i2c0;
  58                 i2c1 = &i2c1;
  59                 i2c2 = &i2c2;
  60                 i2c3 = &i2c3;
  61                 i2c4 = &i2c4;
  62                 i2c5 = &i2c5;
  63                 mshc0 = &emmc;
  64                 mshc1 = &sdmmc;
  65                 mshc2 = &sdio0;
  66                 mshc3 = &sdio1;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72                 spi0 = &spi0;
  73                 spi1 = &spi1;
  74                 spi2 = &spi2;
  75         };
  76
  77         arm-pmu {
  78                 compatible = "arm,cortex-a12-pmu";
  79                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  83                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  84         };
  85
  86         cpus {
  87                 #address-cells = <1>;
  88                 #size-cells = <0>;
  89                 enable-method = "rockchip,rk3066-smp";
  90                 rockchip,pmu = <&pmu>;
  91
  92                 cpu0: cpu@500 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a12";
  95                         reg = <0x500>;
  96                         resets = <&cru SRST_CORE0>;
  97                         operating-points = <
  98                                 /* KHz    uV */
  99                                 1608000 1350000
 100                                 1512000 1300000
 101                                 1416000 1200000
 102                                 1200000 1100000
 103                                 1008000 1050000
 104                                  816000 1000000
 105                                  696000  950000
 106                                  600000  900000
 107                                  408000  900000
 108                                  312000  900000
 109                                  216000  900000
 110                                  126000  900000
 111                         >;
 112                         #cooling-cells = <2>; /* min followed by max */
 113                         clock-latency = <40000>;
 114                         clocks = <&cru ARMCLK>;
 115                 };
 116                 cpu1: cpu@501 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a12";
 119                         reg = <0x501>;
 120                         resets = <&cru SRST_CORE1>;
 121                 };
 122                 cpu2: cpu@502 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a12";
 125                         reg = <0x502>;
 126                         resets = <&cru SRST_CORE2>;
 127                 };
 128                 cpu3: cpu@503 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a12";
 131                         reg = <0x503>;
 132                         resets = <&cru SRST_CORE3>;
 133                 };
 134         };
 135
 136         amba {
 137                 compatible = "arm,amba-bus";
 138                 #address-cells = <1>;
 139                 #size-cells = <1>;
 140                 ranges;
 141
 142                 dmac_peri: dma-controller@ff250000 {
 143                         compatible = "arm,pl330", "arm,primecell";
 144                         reg = <0xff250000 0x4000>;
 145                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 146                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 147                         #dma-cells = <1>;
 148                         arm,pl330-broken-no-flushp;
 149                         peripherals-req-type-burst;
 150                         clocks = <&cru ACLK_DMAC2>;
 151                         clock-names = "apb_pclk";
 152                 };
 153
 154                 dmac_bus_ns: dma-controller@ff600000 {
 155                         compatible = "arm,pl330", "arm,primecell";
 156                         reg = <0xff600000 0x4000>;
 157                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 158                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 159                         #dma-cells = <1>;
 160                         arm,pl330-broken-no-flushp;
 161                         peripherals-req-type-burst;
 162                         clocks = <&cru ACLK_DMAC1>;
 163                         clock-names = "apb_pclk";
 164                         status = "disabled";
 165                 };
 166
 167                 dmac_bus_s: dma-controller@ffb20000 {
 168                         compatible = "arm,pl330", "arm,primecell";
 169                         reg = <0xffb20000 0x4000>;
 170                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 171                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 172                         #dma-cells = <1>;
 173                         arm,pl330-broken-no-flushp;
 174                         peripherals-req-type-burst;
 175                         clocks = <&cru ACLK_DMAC1>;
 176                         clock-names = "apb_pclk";
 177                 };
 178         };
 179
 180         reserved-memory {
 181                 #address-cells = <1>;
 182                 #size-cells = <1>;
 183                 ranges;
 184
 185                 /*
 186                  * The rk3288 cannot use the memory area above 0xfe000000
 187                  * for dma operations for some reason. While there is
 188                  * probably a better solution available somewhere, we
 189                  * haven't found it yet and while devices with 2GB of ram
 190                  * are not affected, this issue prevents 4GB from booting.
 191                  * So to make these devices at least bootable, block
 192                  * this area for the time being until the real solution
 193                  * is found.
 194                  */
 195                 dma-unusable@fe000000 {
 196                         reg = <0xfe000000 0x1000000>;
 197                 };
 198         };
 199
 200         xin24m: oscillator {
 201                 compatible = "fixed-clock";
 202                 clock-frequency = <24000000>;
 203                 clock-output-names = "xin24m";
 204                 #clock-cells = <0>;
 205         };
 206
 207         timer {
 208                 compatible = "arm,armv7-timer";
 209                 arm,cpu-registers-not-fw-configured;
 210                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 211                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 212                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 213                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 214                 clock-frequency = <24000000>;
 215         };
 216
 217         timer: timer@ff810000 {
 218                 compatible = "rockchip,rk3288-timer";
 219                 reg = <0xff810000 0x20>;
 220                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 221                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 222                 clock-names = "timer", "pclk";
 223         };
 224
 225         display-subsystem {
 226                 compatible = "rockchip,display-subsystem";
 227                 ports = <&vopl_out>, <&vopb_out>;
 228         };
 229
 230         sdmmc: dwmmc@ff0c0000 {
 231                 compatible = "rockchip,rk3288-dw-mshc";
 232                 clock-freq-min-max = <400000 150000000>;
 233                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 234                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 235                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 236                 fifo-depth = <0x100>;
 237                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 238                 reg = <0xff0c0000 0x4000>;
 239                 status = "disabled";
 240         };
 241
 242         sdio0: dwmmc@ff0d0000 {
 243                 compatible = "rockchip,rk3288-dw-mshc";
 244                 clock-freq-min-max = <400000 150000000>;
 245                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 246                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 247                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 248                 fifo-depth = <0x100>;
 249                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 250                 reg = <0xff0d0000 0x4000>;
 251                 status = "disabled";
 252         };
 253
 254         sdio1: dwmmc@ff0e0000 {
 255                 compatible = "rockchip,rk3288-dw-mshc";
 256                 clock-freq-min-max = <400000 150000000>;
 257                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 258                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 259                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 260                 fifo-depth = <0x100>;
 261                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 262                 reg = <0xff0e0000 0x4000>;
 263                 status = "disabled";
 264         };
 265
 266         emmc: dwmmc@ff0f0000 {
 267                 compatible = "rockchip,rk3288-dw-mshc";
 268                 clock-freq-min-max = <400000 150000000>;
 269                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 270                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 271                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 272                 fifo-depth = <0x100>;
 273                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 274                 reg = <0xff0f0000 0x4000>;
 275                 status = "disabled";
 276                 supports-emmc;
 277         };
 278
 279         saradc: saradc@ff100000 {
 280                 compatible = "rockchip,saradc";
 281                 reg = <0xff100000 0x100>;
 282                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 283                 #io-channel-cells = <1>;
 284                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 285                 clock-names = "saradc", "apb_pclk";
 286                 resets = <&cru SRST_SARADC>;
 287                 reset-names = "saradc-apb";
 288                 status = "disabled";
 289         };
 290
 291         spi0: spi@ff110000 {
 292                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 293                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 294                 clock-names = "spiclk", "apb_pclk";
 295                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 296                 dma-names = "tx", "rx";
 297                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 298                 pinctrl-names = "default";
 299                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 300                 reg = <0xff110000 0x1000>;
 301                 #address-cells = <1>;
 302                 #size-cells = <0>;
 303                 status = "disabled";
 304         };
 305
 306         spi1: spi@ff120000 {
 307                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 308                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 309                 clock-names = "spiclk", "apb_pclk";
 310                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 311                 dma-names = "tx", "rx";
 312                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 313                 pinctrl-names = "default";
 314                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 315                 reg = <0xff120000 0x1000>;
 316                 #address-cells = <1>;
 317                 #size-cells = <0>;
 318                 status = "disabled";
 319         };
 320
 321         spi2: spi@ff130000 {
 322                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 323                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 324                 clock-names = "spiclk", "apb_pclk";
 325                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 326                 dma-names = "tx", "rx";
 327                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 328                 pinctrl-names = "default";
 329                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 330                 reg = <0xff130000 0x1000>;
 331                 #address-cells = <1>;
 332                 #size-cells = <0>;
 333                 status = "disabled";
 334         };
 335
 336         i2c1: i2c@ff140000 {
 337                 compatible = "rockchip,rk3288-i2c";
 338                 reg = <0xff140000 0x1000>;
 339                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 340                 #address-cells = <1>;
 341                 #size-cells = <0>;
 342                 clock-names = "i2c";
 343                 clocks = <&cru PCLK_I2C1>;
 344                 pinctrl-names = "default";
 345                 pinctrl-0 = <&i2c1_xfer>;
 346                 status = "disabled";
 347         };
 348
 349         i2c3: i2c@ff150000 {
 350                 compatible = "rockchip,rk3288-i2c";
 351                 reg = <0xff150000 0x1000>;
 352                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 353                 #address-cells = <1>;
 354                 #size-cells = <0>;
 355                 clock-names = "i2c";
 356                 clocks = <&cru PCLK_I2C3>;
 357                 pinctrl-names = "default";
 358                 pinctrl-0 = <&i2c3_xfer>;
 359                 status = "disabled";
 360         };
 361
 362         i2c4: i2c@ff160000 {
 363                 compatible = "rockchip,rk3288-i2c";
 364                 reg = <0xff160000 0x1000>;
 365                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 366                 #address-cells = <1>;
 367                 #size-cells = <0>;
 368                 clock-names = "i2c";
 369                 clocks = <&cru PCLK_I2C4>;
 370                 pinctrl-names = "default";
 371                 pinctrl-0 = <&i2c4_xfer>;
 372                 status = "disabled";
 373         };
 374
 375         i2c5: i2c@ff170000 {
 376                 compatible = "rockchip,rk3288-i2c";
 377                 reg = <0xff170000 0x1000>;
 378                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 379                 #address-cells = <1>;
 380                 #size-cells = <0>;
 381                 clock-names = "i2c";
 382                 clocks = <&cru PCLK_I2C5>;
 383                 pinctrl-names = "default";
 384                 pinctrl-0 = <&i2c5_xfer>;
 385                 status = "disabled";
 386         };
 387
 388         uart0: serial@ff180000 {
 389                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 390                 reg = <0xff180000 0x100>;
 391                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 392                 reg-shift = <2>;
 393                 reg-io-width = <4>;
 394                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 395                 clock-names = "baudclk", "apb_pclk";
 396                 pinctrl-names = "default";
 397                 pinctrl-0 = <&uart0_xfer>;
 398                 status = "disabled";
 399         };
 400
 401         uart1: serial@ff190000 {
 402                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 403                 reg = <0xff190000 0x100>;
 404                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 405                 reg-shift = <2>;
 406                 reg-io-width = <4>;
 407                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 408                 clock-names = "baudclk", "apb_pclk";
 409                 pinctrl-names = "default";
 410                 pinctrl-0 = <&uart1_xfer>;
 411                 status = "disabled";
 412         };
 413
 414         uart2: serial@ff690000 {
 415                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 416                 reg = <0xff690000 0x100>;
 417                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 418                 reg-shift = <2>;
 419                 reg-io-width = <4>;
 420                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 421                 clock-names = "baudclk", "apb_pclk";
 422                 pinctrl-names = "default";
 423                 pinctrl-0 = <&uart2_xfer>;
 424                 status = "disabled";
 425         };
 426
 427         uart3: serial@ff1b0000 {
 428                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 429                 reg = <0xff1b0000 0x100>;
 430                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 431                 reg-shift = <2>;
 432                 reg-io-width = <4>;
 433                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 434                 clock-names = "baudclk", "apb_pclk";
 435                 pinctrl-names = "default";
 436                 pinctrl-0 = <&uart3_xfer>;
 437                 status = "disabled";
 438         };
 439
 440         uart4: serial@ff1c0000 {
 441                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 442                 reg = <0xff1c0000 0x100>;
 443                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 444                 reg-shift = <2>;
 445                 reg-io-width = <4>;
 446                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 447                 clock-names = "baudclk", "apb_pclk";
 448                 pinctrl-names = "default";
 449                 pinctrl-0 = <&uart4_xfer>;
 450                 status = "disabled";
 451         };
 452
 453         thermal-zones {
 454                 reserve_thermal: reserve_thermal {
 455                         polling-delay-passive = <1000>; /* milliseconds */
 456                         polling-delay = <5000>; /* milliseconds */
 457
 458                         thermal-sensors = <&tsadc 0>;
 459                 };
 460
 461                 cpu_thermal: cpu_thermal {
 462                         polling-delay-passive = <100>; /* milliseconds */
 463                         polling-delay = <5000>; /* milliseconds */
 464
 465                         thermal-sensors = <&tsadc 1>;
 466
 467                         trips {
 468                                 cpu_alert0: cpu_alert0 {
 469                                         temperature = <70000>; /* millicelsius */
 470                                         hysteresis = <2000>; /* millicelsius */
 471                                         type = "passive";
 472                                 };
 473                                 cpu_alert1: cpu_alert1 {
 474                                         temperature = <75000>; /* millicelsius */
 475                                         hysteresis = <2000>; /* millicelsius */
 476                                         type = "passive";
 477                                 };
 478                                 cpu_crit: cpu_crit {
 479                                         temperature = <90000>; /* millicelsius */
 480                                         hysteresis = <2000>; /* millicelsius */
 481                                         type = "critical";
 482                                 };
 483                         };
 484
 485                         cooling-maps {
 486                                 map0 {
 487                                         trip = <&cpu_alert0>;
 488                                         cooling-device =
 489                                                 <&cpu0 THERMAL_NO_LIMIT 6>;
 490                                 };
 491                                 map1 {
 492                                         trip = <&cpu_alert1>;
 493                                         cooling-device =
 494                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 495                                 };
 496                         };
 497                 };
 498
 499                 gpu_thermal: gpu_thermal {
 500                         polling-delay-passive = <100>; /* milliseconds */
 501                         polling-delay = <5000>; /* milliseconds */
 502
 503                         thermal-sensors = <&tsadc 2>;
 504
 505                         trips {
 506                                 gpu_alert0: gpu_alert0 {
 507                                         temperature = <70000>; /* millicelsius */
 508                                         hysteresis = <2000>; /* millicelsius */
 509                                         type = "passive";
 510                                 };
 511                                 gpu_crit: gpu_crit {
 512                                         temperature = <90000>; /* millicelsius */
 513                                         hysteresis = <2000>; /* millicelsius */
 514                                         type = "critical";
 515                                 };
 516                         };
 517
 518                         cooling-maps {
 519                                 map0 {
 520                                         trip = <&gpu_alert0>;
 521                                         cooling-device =
 522                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 523                                 };
 524                         };
 525                 };
 526         };
 527
 528         tsadc: tsadc@ff280000 {
 529                 compatible = "rockchip,rk3288-tsadc";
 530                 reg = <0xff280000 0x100>;
 531                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 532                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 533                 clock-names = "tsadc", "apb_pclk";
 534                 resets = <&cru SRST_TSADC>;
 535                 reset-names = "tsadc-apb";
 536                 pinctrl-names = "init", "default", "sleep";
 537                 pinctrl-0 = <&otp_gpio>;
 538                 pinctrl-1 = <&otp_out>;
 539                 pinctrl-2 = <&otp_gpio>;
 540                 #thermal-sensor-cells = <1>;
 541                 rockchip,hw-tshut-temp = <95000>;
 542                 status = "disabled";
 543         };
 544
 545         gmac: ethernet@ff290000 {
 546                 compatible = "rockchip,rk3288-gmac";
 547                 reg = <0xff290000 0x10000>;
 548                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 549                 interrupt-names = "macirq";
 550                 rockchip,grf = <&grf>;
 551                 clocks = <&cru SCLK_MAC>,
 552                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 553                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 554                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 555                 clock-names = "stmmaceth",
 556                         "mac_clk_rx", "mac_clk_tx",
 557                         "clk_mac_ref", "clk_mac_refout",
 558                         "aclk_mac", "pclk_mac";
 559                 resets = <&cru SRST_MAC>;
 560                 reset-names = "stmmaceth";
 561                 max-speed = <100>;
 562                 status = "disabled";
 563         };
 564
 565         usb_host0_ehci: usb@ff500000 {
 566                 compatible = "generic-ehci";
 567                 reg = <0xff500000 0x100>;
 568                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 569                 clocks = <&cru HCLK_USBHOST0>;
 570                 clock-names = "usbhost";
 571                 phys = <&usbphy1>;
 572                 phy-names = "usb";
 573                 status = "disabled";
 574         };
 575
 576         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 577
 578         usb_host1: usb@ff540000 {
 579                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 580                                 "snps,dwc2";
 581                 reg = <0xff540000 0x40000>;
 582                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 583                 clocks = <&cru HCLK_USBHOST1>;
 584                 clock-names = "otg";
 585                 dr_mode = "host";
 586                 phys = <&usbphy2>;
 587                 phy-names = "usb2-phy";
 588                 status = "disabled";
 589         };
 590
 591         usb_otg: usb@ff580000 {
 592                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 593                                 "snps,dwc2";
 594                 reg = <0xff580000 0x40000>;
 595                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 596                 clocks = <&cru HCLK_OTG0>;
 597                 clock-names = "otg";
 598                 dr_mode = "otg";
 599                 g-np-tx-fifo-size = <16>;
 600                 g-rx-fifo-size = <275>;
 601                 g-tx-fifo-size = <256 128 128 64 64 32>;
 602                 g-use-dma;
 603                 phys = <&usbphy0>;
 604                 phy-names = "usb2-phy";
 605                 status = "disabled";
 606         };
 607
 608         usb_hsic: usb@ff5c0000 {
 609                 compatible = "generic-ehci";
 610                 reg = <0xff5c0000 0x100>;
 611                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 612                 clocks = <&cru HCLK_HSIC>;
 613                 clock-names = "usbhost";
 614                 status = "disabled";
 615         };
 616
 617         i2c0: i2c@ff650000 {
 618                 compatible = "rockchip,rk3288-i2c";
 619                 reg = <0xff650000 0x1000>;
 620                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 621                 #address-cells = <1>;
 622                 #size-cells = <0>;
 623                 clock-names = "i2c";
 624                 clocks = <&cru PCLK_I2C0>;
 625                 pinctrl-names = "default";
 626                 pinctrl-0 = <&i2c0_xfer>;
 627                 status = "disabled";
 628         };
 629
 630         i2c2: i2c@ff660000 {
 631                 compatible = "rockchip,rk3288-i2c";
 632                 reg = <0xff660000 0x1000>;
 633                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 634                 #address-cells = <1>;
 635                 #size-cells = <0>;
 636                 clock-names = "i2c";
 637                 clocks = <&cru PCLK_I2C2>;
 638                 pinctrl-names = "default";
 639                 pinctrl-0 = <&i2c2_xfer>;
 640                 status = "disabled";
 641         };
 642
 643         pwm0: pwm@ff680000 {
 644                 compatible = "rockchip,rk3288-pwm";
 645                 reg = <0xff680000 0x10>;
 646                 #pwm-cells = <3>;
 647                 pinctrl-names = "default";
 648                 pinctrl-0 = <&pwm0_pin>;
 649                 clocks = <&cru PCLK_PWM>;
 650                 clock-names = "pwm";
 651                 status = "disabled";
 652         };
 653
 654         pwm1: pwm@ff680010 {
 655                 compatible = "rockchip,rk3288-pwm";
 656                 reg = <0xff680010 0x10>;
 657                 #pwm-cells = <3>;
 658                 pinctrl-names = "default";
 659                 pinctrl-0 = <&pwm1_pin>;
 660                 clocks = <&cru PCLK_PWM>;
 661                 clock-names = "pwm";
 662                 status = "disabled";
 663         };
 664
 665         pwm2: pwm@ff680020 {
 666                 compatible = "rockchip,rk3288-pwm";
 667                 reg = <0xff680020 0x10>;
 668                 #pwm-cells = <3>;
 669                 pinctrl-names = "default";
 670                 pinctrl-0 = <&pwm2_pin>;
 671                 clocks = <&cru PCLK_PWM>;
 672                 clock-names = "pwm";
 673                 status = "disabled";
 674         };
 675
 676         pwm3: pwm@ff680030 {
 677                 compatible = "rockchip,rk3288-pwm";
 678                 reg = <0xff680030 0x10>;
 679                 #pwm-cells = <2>;
 680                 pinctrl-names = "default";
 681                 pinctrl-0 = <&pwm3_pin>;
 682                 clocks = <&cru PCLK_PWM>;
 683                 clock-names = "pwm";
 684                 status = "disabled";
 685         };
 686
 687         bus_intmem@ff700000 {
 688                 compatible = "mmio-sram";
 689                 reg = <0xff700000 0x18000>;
 690                 #address-cells = <1>;
 691                 #size-cells = <1>;
 692                 ranges = <0 0xff700000 0x18000>;
 693                 smp-sram@0 {
 694                         compatible = "rockchip,rk3066-smp-sram";
 695                         reg = <0x00 0x10>;
 696                 };
 697         };
 698
 699         sram@ff720000 {
 700                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 701                 reg = <0xff720000 0x1000>;
 702         };
 703
 704         qos_gpu_r: qos@ffaa0000 {
 705                 compatible = "syscon";
 706                 reg = <0xffaa0000 0x20>;
 707         };
 708
 709         qos_gpu_w: qos@ffaa0080 {
 710                 compatible = "syscon";
 711                 reg = <0xffaa0080 0x20>;
 712         };
 713
 714         qos_vio1_vop: qos@ffad0000 {
 715                 compatible = "syscon";
 716                 reg = <0xffad0000 0x20>;
 717         };
 718
 719         qos_vio1_isp_w0: qos@ffad0100 {
 720                 compatible = "syscon";
 721                 reg = <0xffad0100 0x20>;
 722         };
 723
 724         qos_vio1_isp_w1: qos@ffad0180 {
 725                 compatible = "syscon";
 726                 reg = <0xffad0180 0x20>;
 727         };
 728
 729         qos_vio0_vop: qos@ffad0400 {
 730                 compatible = "syscon";
 731                 reg = <0xffad0400 0x20>;
 732         };
 733
 734         qos_vio0_vip: qos@ffad0480 {
 735                 compatible = "syscon";
 736                 reg = <0xffad0480 0x20>;
 737         };
 738
 739         qos_vio0_iep: qos@ffad0500 {
 740                 compatible = "syscon";
 741                 reg = <0xffad0500 0x20>;
 742         };
 743
 744         qos_vio2_rga_r: qos@ffad0800 {
 745                 compatible = "syscon";
 746                 reg = <0xffad0800 0x20>;
 747         };
 748
 749         qos_vio2_rga_w: qos@ffad0880 {
 750                 compatible = "syscon";
 751                 reg = <0xffad0880 0x20>;
 752         };
 753
 754         qos_vio1_isp_r: qos@ffad0900 {
 755                 compatible = "syscon";
 756                 reg = <0xffad0900 0x20>;
 757         };
 758
 759         qos_video: qos@ffae0000 {
 760                 compatible = "syscon";
 761                 reg = <0xffae0000 0x20>;
 762         };
 763
 764         qos_hevc_r: qos@ffaf0000 {
 765                 compatible = "syscon";
 766                 reg = <0xffaf0000 0x20>;
 767         };
 768
 769         qos_hevc_w: qos@ffaf0080 {
 770                 compatible = "syscon";
 771                 reg = <0xffaf0080 0x20>;
 772         };
 773
 774         pmu: power-management@ff730000 {
 775                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 776                 reg = <0xff730000 0x100>;
 777
 778                 power: power-controller {
 779                         compatible = "rockchip,rk3288-power-controller";
 780                         #power-domain-cells = <1>;
 781                         #address-cells = <1>;
 782                         #size-cells = <0>;
 783
 784                         /*
 785                          * Note: Although SCLK_* are the working clocks
 786                          * of device without including on the NOC, needed for
 787                          * synchronous reset.
 788                          *
 789                          * The clocks on the which NOC:
 790                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 791                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 792                          * ACLK_RGA is on ACLK_RGA_NIU.
 793                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 794                          *
 795                          * Which clock are device clocks:
 796                          *      clocks          devices
 797                          *      *_IEP           IEP:Image Enhancement Processor
 798                          *      *_ISP           ISP:Image Signal Processing
 799                          *      *_VIP           VIP:Video Input Processor
 800                          *      *_VOP*          VOP:Visual Output Processor
 801                          *      *_RGA           RGA
 802                          *      *_EDP*          EDP
 803                          *      *_LVDS_*        LVDS
 804                          *      *_HDMI          HDMI
 805                          *      *_MIPI_*        MIPI
 806                          */
 807                         pd_vio@RK3288_PD_VIO {
 808                                 reg = <RK3288_PD_VIO>;
 809                                 clocks = <&cru ACLK_IEP>,
 810                                          <&cru ACLK_ISP>,
 811                                          <&cru ACLK_RGA>,
 812                                          <&cru ACLK_VIP>,
 813                                          <&cru ACLK_VOP0>,
 814                                          <&cru ACLK_VOP1>,
 815                                          <&cru DCLK_VOP0>,
 816                                          <&cru DCLK_VOP1>,
 817                                          <&cru HCLK_IEP>,
 818                                          <&cru HCLK_ISP>,
 819                                          <&cru HCLK_RGA>,
 820                                          <&cru HCLK_VIP>,
 821                                          <&cru HCLK_VOP0>,
 822                                          <&cru HCLK_VOP1>,
 823                                          <&cru PCLK_EDP_CTRL>,
 824                                          <&cru PCLK_HDMI_CTRL>,
 825                                          <&cru PCLK_LVDS_PHY>,
 826                                          <&cru PCLK_MIPI_CSI>,
 827                                          <&cru PCLK_MIPI_DSI0>,
 828                                          <&cru PCLK_MIPI_DSI1>,
 829                                          <&cru SCLK_EDP_24M>,
 830                                          <&cru SCLK_EDP>,
 831                                          <&cru SCLK_ISP_JPE>,
 832                                          <&cru SCLK_ISP>,
 833                                          <&cru SCLK_RGA>;
 834                                 pm_qos = <&qos_vio0_iep>,
 835                                          <&qos_vio1_vop>,
 836                                          <&qos_vio1_isp_w0>,
 837                                          <&qos_vio1_isp_w1>,
 838                                          <&qos_vio0_vop>,
 839                                          <&qos_vio0_vip>,
 840                                          <&qos_vio2_rga_r>,
 841                                          <&qos_vio2_rga_w>,
 842                                          <&qos_vio1_isp_r>;
 843                         };
 844
 845                         /*
 846                          * Note: The following 3 are HEVC(H.265) clocks,
 847                          * and on the ACLK_HEVC_NIU (NOC).
 848                          */
 849                         pd_hevc@RK3288_PD_HEVC {
 850                                 reg = <RK3288_PD_HEVC>;
 851                                 clocks = <&cru ACLK_HEVC>,
 852                                          <&cru SCLK_HEVC_CABAC>,
 853                                          <&cru SCLK_HEVC_CORE>;
 854                                 pm_qos = <&qos_hevc_r>,
 855                                          <&qos_hevc_w>;
 856                         };
 857
 858                         /*
 859                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 860                          * (video endecoder & decoder) clocks that on the
 861                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 862                          */
 863                         pd_video@RK3288_PD_VIDEO {
 864                                 reg = <RK3288_PD_VIDEO>;
 865                                 clocks = <&cru ACLK_VCODEC>,
 866                                          <&cru HCLK_VCODEC>;
 867                                 pm_qos = <&qos_video>;
 868                         };
 869
 870                         /*
 871                          * Note: ACLK_GPU is the GPU clock,
 872                          * and on the ACLK_GPU_NIU (NOC).
 873                          */
 874                         pd_gpu@RK3288_PD_GPU {
 875                                 reg = <RK3288_PD_GPU>;
 876                                 clocks = <&cru ACLK_GPU>;
 877                                 pm_qos = <&qos_gpu_r>,
 878                                          <&qos_gpu_w>;
 879                         };
 880                 };
 881
 882                 reboot-mode {
 883                         compatible = "syscon-reboot-mode";
 884                         offset = <0x94>;
 885                         mode-normal = <BOOT_NORMAL>;
 886                         mode-recovery = <BOOT_RECOVERY>;
 887                         mode-bootloader = <BOOT_FASTBOOT>;
 888                         mode-loader = <BOOT_LOADER>;
 889                         mode-ums = <BOOT_UMS>;
 890                 };
 891         };
 892
 893         sgrf: syscon@ff740000 {
 894                 compatible = "rockchip,rk3288-sgrf", "syscon";
 895                 reg = <0xff740000 0x1000>;
 896         };
 897
 898         cru: clock-controller@ff760000 {
 899                 compatible = "rockchip,rk3288-cru";
 900                 reg = <0xff760000 0x1000>;
 901                 rockchip,grf = <&grf>;
 902                 #clock-cells = <1>;
 903                 #reset-cells = <1>;
 904                 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
 905                                   <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 906                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 907                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 908                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 909                                   <&cru PCLK_PERI>;
 910                 assigned-clock-rates = <0>, <0>,
 911                                        <594000000>, <400000000>,
 912                                        <500000000>, <300000000>,
 913                                        <150000000>, <75000000>,
 914                                        <300000000>, <150000000>,
 915                                        <75000000>;
 916                 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
 917         };
 918
 919         grf: syscon@ff770000 {
 920                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 921                 reg = <0xff770000 0x1000>;
 922
 923                 edp_phy: edp-phy {
 924                         compatible = "rockchip,rk3288-dp-phy";
 925                         clocks = <&cru SCLK_EDP_24M>;
 926                         clock-names = "24m";
 927                         #phy-cells = <0>;
 928                         status = "disabled";
 929                 };
 930
 931                 io_domains: io-domains {
 932                         compatible = "rockchip,rk3288-io-voltage-domain";
 933                         status = "disabled";
 934                 };
 935
 936                 usbphy: usbphy {
 937                         compatible = "rockchip,rk3288-usb-phy";
 938                         #address-cells = <1>;
 939                         #size-cells = <0>;
 940                         status = "disabled";
 941
 942                         usbphy0: usb-phy@320 {
 943                                 #phy-cells = <0>;
 944                                 reg = <0x320>;
 945                                 clocks = <&cru SCLK_OTGPHY0>;
 946                                 clock-names = "phyclk";
 947                                 #clock-cells = <0>;
 948                                 resets = <&cru SRST_USBOTG_PHY>;
 949                                 reset-names = "phy-reset";
 950                         };
 951
 952                         usbphy1: usb-phy@334 {
 953                                 #phy-cells = <0>;
 954                                 reg = <0x334>;
 955                                 clocks = <&cru SCLK_OTGPHY1>;
 956                                 clock-names = "phyclk";
 957                                 #clock-cells = <0>;
 958                         };
 959
 960                         usbphy2: usb-phy@348 {
 961                                 #phy-cells = <0>;
 962                                 reg = <0x348>;
 963                                 clocks = <&cru SCLK_OTGPHY2>;
 964                                 clock-names = "phyclk";
 965                                 #clock-cells = <0>;
 966                                 resets = <&cru SRST_USBHOST1_PHY>;
 967                                 reset-names = "phy-reset";
 968                         };
 969                 };
 970         };
 971
 972         wdt: watchdog@ff800000 {
 973                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 974                 reg = <0xff800000 0x100>;
 975                 clocks = <&cru PCLK_WDT>;
 976                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 977                 status = "disabled";
 978         };
 979
 980         spdif: sound@ff88b0000 {
 981                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 982                 reg = <0xff8b0000 0x10000>;
 983                 #sound-dai-cells = <0>;
 984                 clock-names = "hclk", "mclk";
 985                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 986                 dmas = <&dmac_bus_s 3>;
 987                 dma-names = "tx";
 988                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 989                 pinctrl-names = "default";
 990                 pinctrl-0 = <&spdif_tx>;
 991                 rockchip,grf = <&grf>;
 992                 status = "disabled";
 993         };
 994
 995         i2s: i2s@ff890000 {
 996                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 997                 reg = <0xff890000 0x10000>;
 998                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 999                 #address-cells = <1>;
1000                 #size-cells = <0>;
1001                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
1002                 dma-names = "tx", "rx";
1003                 clock-names = "i2s_hclk", "i2s_clk";
1004                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
1005                 pinctrl-names = "default";
1006                 pinctrl-0 = <&i2s0_bus>;
1007                 status = "disabled";
1008         };
1009
1010         vopb: vop@ff930000 {
1011                 compatible = "rockchip,rk3288-vop";
1012                 reg = <0xff930000 0x19c>;
1013                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1014                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1015                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1016                 power-domains = <&power RK3288_PD_VIO>;
1017                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1018                 reset-names = "axi", "ahb", "dclk";
1019                 iommus = <&vopb_mmu>;
1020                 status = "disabled";
1021
1022                 vopb_out: port {
1023                         #address-cells = <1>;
1024                         #size-cells = <0>;
1025
1026                         vopb_out_hdmi: endpoint@0 {
1027                                 reg = <0>;
1028                                 remote-endpoint = <&hdmi_in_vopb>;
1029                         };
1030
1031                         vopb_out_edp: endpoint@1 {
1032                                 reg = <1>;
1033                                 remote-endpoint = <&edp_in_vopb>;
1034                         };
1035
1036                         vopb_out_mipi: endpoint@2 {
1037                                 reg = <2>;
1038                                 remote-endpoint = <&mipi_in_vopb>;
1039                         };
1040
1041                         vopb_out_lvds: endpoint@3 {
1042                                 reg = <3>;
1043                                 remote-endpoint = <&lvds_in_vopb>;
1044                         };
1045                 };
1046         };
1047
1048         vopb_mmu: iommu@ff930300 {
1049                 compatible = "rockchip,iommu";
1050                 reg = <0xff930300 0x100>;
1051                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1052                 interrupt-names = "vopb_mmu";
1053                 power-domains = <&power RK3288_PD_VIO>;
1054                 #iommu-cells = <0>;
1055                 status = "disabled";
1056         };
1057
1058         vopl: vop@ff940000 {
1059                 compatible = "rockchip,rk3288-vop";
1060                 reg = <0xff940000 0x19c>;
1061                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1062                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1063                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1064                 power-domains = <&power RK3288_PD_VIO>;
1065                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1066                 reset-names = "axi", "ahb", "dclk";
1067                 iommus = <&vopl_mmu>;
1068                 status = "disabled";
1069
1070                 vopl_out: port {
1071                         #address-cells = <1>;
1072                         #size-cells = <0>;
1073
1074                         vopl_out_hdmi: endpoint@0 {
1075                                 reg = <0>;
1076                                 remote-endpoint = <&hdmi_in_vopl>;
1077                         };
1078
1079                         vopl_out_edp: endpoint@1 {
1080                                 reg = <1>;
1081                                 remote-endpoint = <&edp_in_vopl>;
1082                         };
1083
1084                         vopl_out_mipi: endpoint@2 {
1085                                 reg = <2>;
1086                                 remote-endpoint = <&mipi_in_vopl>;
1087                         };
1088
1089                         vopl_out_lvds: endpoint@3 {
1090                                 reg = <3>;
1091                                 remote-endpoint = <&lvds_in_vopl>;
1092                         };
1093
1094                 };
1095         };
1096
1097         vopl_mmu: iommu@ff940300 {
1098                 compatible = "rockchip,iommu";
1099                 reg = <0xff940300 0x100>;
1100                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1101                 interrupt-names = "vopl_mmu";
1102                 power-domains = <&power RK3288_PD_VIO>;
1103                 #iommu-cells = <0>;
1104                 status = "disabled";
1105         };
1106
1107         mipi_dsi: mipi@ff960000 {
1108                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1109                 reg = <0xff960000 0x4000>;
1110                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1111                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1112                 clock-names = "ref", "pclk";
1113                 rockchip,grf = <&grf>;
1114                 #address-cells = <1>;
1115                 #size-cells = <0>;
1116                 status = "disabled";
1117
1118                 ports {
1119                         #address-cells = <1>;
1120                         #size-cells = <0>;
1121                         reg = <1>;
1122
1123                         mipi_in: port {
1124                                 #address-cells = <1>;
1125                                 #size-cells = <0>;
1126                                 mipi_in_vopb: endpoint@0 {
1127                                         reg = <0>;
1128                                         remote-endpoint = <&vopb_out_mipi>;
1129                                 };
1130                                 mipi_in_vopl: endpoint@1 {
1131                                         reg = <1>;
1132                                         remote-endpoint = <&vopl_out_mipi>;
1133                                 };
1134                         };
1135                 };
1136         };
1137
1138         edp: dp@ff970000 {
1139                 compatible = "rockchip,rk3288-dp";
1140                 reg = <0xff970000 0x4000>;
1141                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1142                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1143                 clock-names = "dp", "pclk";
1144                 phys = <&edp_phy>;
1145                 phy-names = "dp";
1146                 resets = <&cru SRST_EDP>;
1147                 reset-names = "dp";
1148                 rockchip,grf = <&grf>;
1149                 status = "disabled";
1150
1151                 ports {
1152                         #address-cells = <1>;
1153                         #size-cells = <0>;
1154                         edp_in: port@0 {
1155                                 reg = <0>;
1156                                 #address-cells = <1>;
1157                                 #size-cells = <0>;
1158                                 edp_in_vopb: endpoint@0 {
1159                                         reg = <0>;
1160                                         remote-endpoint = <&vopb_out_edp>;
1161                                 };
1162                                 edp_in_vopl: endpoint@1 {
1163                                         reg = <1>;
1164                                         remote-endpoint = <&vopl_out_edp>;
1165                                 };
1166                         };
1167                 };
1168         };
1169
1170         lvds: lvds@ff96c000 {
1171                 compatible = "rockchip,rk3288-lvds";
1172                 reg = <0xff96c000 0x4000>;
1173                 clocks = <&cru PCLK_LVDS_PHY>;
1174                 clock-names = "pclk_lvds";
1175                 pinctrl-names = "default";
1176                 pinctrl-0 = <&lcdc0_ctl>;
1177                 power-domains = <&power RK3288_PD_VIO>;
1178                 rockchip,grf = <&grf>;
1179                 status = "disabled";
1180
1181                 ports {
1182                         #address-cells = <1>;
1183                         #size-cells = <0>;
1184
1185                         lvds_in: port@0 {
1186                                 reg = <0>;
1187
1188                                 #address-cells = <1>;
1189                                 #size-cells = <0>;
1190
1191                                 lvds_in_vopb: endpoint@0 {
1192                                         reg = <0>;
1193                                         remote-endpoint = <&vopb_out_lvds>;
1194                                 };
1195                                 lvds_in_vopl: endpoint@1 {
1196                                         reg = <1>;
1197                                         remote-endpoint = <&vopl_out_lvds>;
1198                                 };
1199                         };
1200                 };
1201         };
1202
1203         hdmi: hdmi@ff980000 {
1204                 compatible = "rockchip,rk3288-dw-hdmi";
1205                 reg = <0xff980000 0x20000>;
1206                 reg-io-width = <4>;
1207                 rockchip,grf = <&grf>;
1208                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1209                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1210                 clock-names = "iahb", "isfr";
1211                 power-domains = <&power RK3288_PD_VIO>;
1212                 status = "disabled";
1213
1214                 ports {
1215                         hdmi_in: port {
1216                                 #address-cells = <1>;
1217                                 #size-cells = <0>;
1218                                 hdmi_in_vopb: endpoint@0 {
1219                                         reg = <0>;
1220                                         remote-endpoint = <&vopb_out_hdmi>;
1221                                 };
1222                                 hdmi_in_vopl: endpoint@1 {
1223                                         reg = <1>;
1224                                         remote-endpoint = <&vopl_out_hdmi>;
1225                                 };
1226                         };
1227                 };
1228         };
1229
1230         gpu: gpu@ffa30000 {
1231                 compatible = "arm,malit764",
1232                              "arm,malit76x",
1233                              "arm,malit7xx",
1234                              "arm,mali-midgard";
1235                 reg = <0xffa30000 0x10000>;
1236                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1237                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1238                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1239                 interrupt-names = "JOB", "MMU", "GPU";
1240                 clocks = <&cru ACLK_GPU>;
1241                 clock-names = "clk_mali";
1242                 operating-points = <
1243                         /* KHz uV */
1244                         600000 1250000
1245                         /* 500000 1200000 - See crosbug.com/p/33857 */
1246                         400000 1100000
1247                         300000 1000000
1248                         200000 950000
1249                         100000 950000
1250                 >;
1251                 #cooling-cells = <2>; /* min followed by max */
1252                 power-domains = <&power RK3288_PD_GPU>;
1253                 status = "disabled";
1254         };
1255
1256         vpu: video-codec@ff9a0000 {
1257                 compatible = "rockchip,rk3288-vpu";
1258                 reg = <0xff9a0000 0x800>;
1259                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1260                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1261                 interrupt-names = "vepu", "vdpu";
1262                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1263                 clock-names = "aclk", "hclk";
1264                 power-domains = <&power RK3288_PD_VIDEO>;
1265                 iommus = <&vpu_mmu>;
1266                 assigned-clocks = <&cru ACLK_VCODEC>;
1267                 assigned-clock-rates = <400000000>;
1268                 status = "disabled";
1269         };
1270
1271         vpu_service: vpu-service@ff9a0000 {
1272                 compatible = "rockchip,vpu_service";
1273                 reg = <0xff9a0000 0x800>;
1274                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1275                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1276                 interrupt-names = "irq_enc", "irq_dec";
1277                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1278                 clock-names = "aclk_vcodec", "hclk_vcodec";
1279                 power-domains = <&power RK3288_PD_VIDEO>;
1280                 rockchip,grf = <&grf>;
1281                 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1282                 reset-names = "video_a", "video_h";
1283                 iommus = <&vpu_mmu>;
1284                 iommu_enabled = <1>;
1285                 dev_mode = <0>;
1286                 status = "disabled";
1287         };
1288
1289         vpu_mmu: iommu@ff9a0800 {
1290                 compatible = "rockchip,iommu";
1291                 reg = <0xff9a0800 0x100>;
1292                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1293                 interrupt-names = "vpu_mmu";
1294                 power-domains = <&power RK3288_PD_VIDEO>;
1295                 #iommu-cells = <0>;
1296         };
1297
1298         hevc_service: hevc-service@ff9c0000 {
1299                 compatible = "rockchip,hevc_service";
1300                 reg = <0xff9c0000 0x400>;
1301                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1302                 interrupt-names = "irq_dec";
1303                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1304                         <&cru SCLK_HEVC_CORE>,
1305                         <&cru SCLK_HEVC_CABAC>;
1306                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1307                         "clk_cabac";
1308                 /*
1309                  * The 4K hevc would also work well with 500/125/300/300,
1310                  * no more err irq and reset request.
1311                  */
1312                 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1313                                   <&cru SCLK_HEVC_CORE>,
1314                                   <&cru SCLK_HEVC_CABAC>;
1315                 assigned-clock-rates = <400000000>, <100000000>,
1316                                        <300000000>, <300000000>;
1317
1318                 resets = <&cru SRST_HEVC>;
1319                 reset-names = "video";
1320                 power-domains = <&power RK3288_PD_HEVC>;
1321                 rockchip,grf = <&grf>;
1322                 dev_mode = <1>;
1323                 iommus = <&hevc_mmu>;
1324                 iommu_enabled = <1>;
1325                 status = "disabled";
1326         };
1327
1328         hevc_mmu: iommu@ff9c0440 {
1329                 compatible = "rockchip,iommu";
1330                 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1331                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1332                 interrupt-names = "hevc_mmu";
1333                 power-domains = <&power RK3288_PD_HEVC>;
1334                 #iommu-cells = <0>;
1335         };
1336
1337         gic: interrupt-controller@ffc01000 {
1338                 compatible = "arm,gic-400";
1339                 interrupt-controller;
1340                 #interrupt-cells = <3>;
1341                 #address-cells = <0>;
1342
1343                 reg = <0xffc01000 0x1000>,
1344                       <0xffc02000 0x1000>,
1345                       <0xffc04000 0x2000>,
1346                       <0xffc06000 0x2000>;
1347                 interrupts = <GIC_PPI 9 0xf04>;
1348         };
1349
1350         efuse: efuse@ffb40000 {
1351                 compatible = "rockchip,rockchip-efuse";
1352                 reg = <0xffb40000 0x20>;
1353                 #address-cells = <1>;
1354                 #size-cells = <1>;
1355                 clocks = <&cru PCLK_EFUSE256>;
1356                 clock-names = "pclk_efuse";
1357
1358                 cpu_leakage: cpu_leakage@17 {
1359                         reg = <0x17 0x1>;
1360                 };
1361         };
1362
1363         cif_isp0: cif_isp@ff910000 {
1364                 compatible = "rockchip,rk3288-cif-isp";
1365                 rockchip,grf = <&grf>;
1366                 reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
1367                 reg-names = "register", "csihost-register";
1368                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1369                         <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1370                         <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1371                         <&cru SCLK_MIPIDSI_24M>;
1372                 clock-names = "aclk_isp", "hclk_isp",
1373                         "sclk_isp", "sclk_isp_jpe",
1374                         "pclk_mipi_csi", "pclk_isp_in",
1375                         "sclk_mipidsi_24m";
1376                 resets = <&cru SRST_ISP>;
1377                 reset-names = "rst_isp";
1378                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1379                 interrupt-names = "cif_isp10_irq";
1380                 status = "disabled";
1381         };
1382
1383         pinctrl: pinctrl {
1384                 compatible = "rockchip,rk3288-pinctrl";
1385                 rockchip,grf = <&grf>;
1386                 rockchip,pmu = <&pmu>;
1387                 #address-cells = <1>;
1388                 #size-cells = <1>;
1389                 ranges;
1390
1391                 gpio0: gpio0@ff750000 {
1392                         compatible = "rockchip,gpio-bank";
1393                         reg =   <0xff750000 0x100>;
1394                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1395                         clocks = <&cru PCLK_GPIO0>;
1396
1397                         gpio-controller;
1398                         #gpio-cells = <2>;
1399
1400                         interrupt-controller;
1401                         #interrupt-cells = <2>;
1402                 };
1403
1404                 gpio1: gpio1@ff780000 {
1405                         compatible = "rockchip,gpio-bank";
1406                         reg = <0xff780000 0x100>;
1407                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1408                         clocks = <&cru PCLK_GPIO1>;
1409
1410                         gpio-controller;
1411                         #gpio-cells = <2>;
1412
1413                         interrupt-controller;
1414                         #interrupt-cells = <2>;
1415                 };
1416
1417                 gpio2: gpio2@ff790000 {
1418                         compatible = "rockchip,gpio-bank";
1419                         reg = <0xff790000 0x100>;
1420                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1421                         clocks = <&cru PCLK_GPIO2>;
1422
1423                         gpio-controller;
1424                         #gpio-cells = <2>;
1425
1426                         interrupt-controller;
1427                         #interrupt-cells = <2>;
1428                 };
1429
1430                 gpio3: gpio3@ff7a0000 {
1431                         compatible = "rockchip,gpio-bank";
1432                         reg = <0xff7a0000 0x100>;
1433                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1434                         clocks = <&cru PCLK_GPIO3>;
1435
1436                         gpio-controller;
1437                         #gpio-cells = <2>;
1438
1439                         interrupt-controller;
1440                         #interrupt-cells = <2>;
1441                 };
1442
1443                 gpio4: gpio4@ff7b0000 {
1444                         compatible = "rockchip,gpio-bank";
1445                         reg = <0xff7b0000 0x100>;
1446                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1447                         clocks = <&cru PCLK_GPIO4>;
1448
1449                         gpio-controller;
1450                         #gpio-cells = <2>;
1451
1452                         interrupt-controller;
1453                         #interrupt-cells = <2>;
1454                 };
1455
1456                 gpio5: gpio5@ff7c0000 {
1457                         compatible = "rockchip,gpio-bank";
1458                         reg = <0xff7c0000 0x100>;
1459                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1460                         clocks = <&cru PCLK_GPIO5>;
1461
1462                         gpio-controller;
1463                         #gpio-cells = <2>;
1464
1465                         interrupt-controller;
1466                         #interrupt-cells = <2>;
1467                 };
1468
1469                 gpio6: gpio6@ff7d0000 {
1470                         compatible = "rockchip,gpio-bank";
1471                         reg = <0xff7d0000 0x100>;
1472                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1473                         clocks = <&cru PCLK_GPIO6>;
1474
1475                         gpio-controller;
1476                         #gpio-cells = <2>;
1477
1478                         interrupt-controller;
1479                         #interrupt-cells = <2>;
1480                 };
1481
1482                 gpio7: gpio7@ff7e0000 {
1483                         compatible = "rockchip,gpio-bank";
1484                         reg = <0xff7e0000 0x100>;
1485                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1486                         clocks = <&cru PCLK_GPIO7>;
1487
1488                         gpio-controller;
1489                         #gpio-cells = <2>;
1490
1491                         interrupt-controller;
1492                         #interrupt-cells = <2>;
1493                 };
1494
1495                 gpio8: gpio8@ff7f0000 {
1496                         compatible = "rockchip,gpio-bank";
1497                         reg = <0xff7f0000 0x100>;
1498                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1499                         clocks = <&cru PCLK_GPIO8>;
1500
1501                         gpio-controller;
1502                         #gpio-cells = <2>;
1503
1504                         interrupt-controller;
1505                         #interrupt-cells = <2>;
1506                 };
1507
1508                 hdmi {
1509                         hdmi_ddc: hdmi-ddc {
1510                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1511                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1512                         };
1513                 };
1514
1515                 pcfg_pull_up: pcfg-pull-up {
1516                         bias-pull-up;
1517                 };
1518
1519                 pcfg_pull_down: pcfg-pull-down {
1520                         bias-pull-down;
1521                 };
1522
1523                 pcfg_pull_none: pcfg-pull-none {
1524                         bias-disable;
1525                 };
1526
1527                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1528                         bias-disable;
1529                         drive-strength = <12>;
1530                 };
1531
1532                 sleep {
1533                         global_pwroff: global-pwroff {
1534                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1535                         };
1536
1537                         ddrio_pwroff: ddrio-pwroff {
1538                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1539                         };
1540
1541                         ddr0_retention: ddr0-retention {
1542                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1543                         };
1544
1545                         ddr1_retention: ddr1-retention {
1546                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1547                         };
1548                 };
1549
1550                 edp {
1551                         edp_hpd: edp-hpd {
1552                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1553                         };
1554                 };
1555
1556                 i2c0 {
1557                         i2c0_xfer: i2c0-xfer {
1558                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1559                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1560                         };
1561                 };
1562
1563                 i2c1 {
1564                         i2c1_xfer: i2c1-xfer {
1565                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1566                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1567                         };
1568                 };
1569
1570                 i2c2 {
1571                         i2c2_xfer: i2c2-xfer {
1572                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1573                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1574                         };
1575                 };
1576
1577                 i2c3 {
1578                         i2c3_xfer: i2c3-xfer {
1579                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1580                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1581                         };
1582                 };
1583
1584                 i2c4 {
1585                         i2c4_xfer: i2c4-xfer {
1586                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1587                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1588                         };
1589                 };
1590
1591                 i2c5 {
1592                         i2c5_xfer: i2c5-xfer {
1593                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1594                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1595                         };
1596                 };
1597
1598                 i2s0 {
1599                         i2s0_bus: i2s0-bus {
1600                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1601                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1602                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1603                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1604                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1605                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1606                         };
1607                 };
1608
1609                 lcdc0 {
1610                         lcdc0_ctl: lcdc0-ctl {
1611                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1612                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1613                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1614                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1615                         };
1616                 };
1617
1618                 sdmmc {
1619                         sdmmc_clk: sdmmc-clk {
1620                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1621                         };
1622
1623                         sdmmc_cmd: sdmmc-cmd {
1624                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1625                         };
1626
1627                         sdmmc_cd: sdmcc-cd {
1628                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1629                         };
1630
1631                         sdmmc_bus1: sdmmc-bus1 {
1632                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1633                         };
1634
1635                         sdmmc_bus4: sdmmc-bus4 {
1636                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1637                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1638                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1639                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1640                         };
1641                 };
1642
1643                 sdio0 {
1644                         sdio0_bus1: sdio0-bus1 {
1645                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1646                         };
1647
1648                         sdio0_bus4: sdio0-bus4 {
1649                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1650                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1651                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1652                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1653                         };
1654
1655                         sdio0_cmd: sdio0-cmd {
1656                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1657                         };
1658
1659                         sdio0_clk: sdio0-clk {
1660                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1661                         };
1662
1663                         sdio0_cd: sdio0-cd {
1664                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1665                         };
1666
1667                         sdio0_wp: sdio0-wp {
1668                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1669                         };
1670
1671                         sdio0_pwr: sdio0-pwr {
1672                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1673                         };
1674
1675                         sdio0_bkpwr: sdio0-bkpwr {
1676                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1677                         };
1678
1679                         sdio0_int: sdio0-int {
1680                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1681                         };
1682                 };
1683
1684                 sdio1 {
1685                         sdio1_bus1: sdio1-bus1 {
1686                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1687                         };
1688
1689                         sdio1_bus4: sdio1-bus4 {
1690                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1691                                                 <3 25 4 &pcfg_pull_up>,
1692                                                 <3 26 4 &pcfg_pull_up>,
1693                                                 <3 27 4 &pcfg_pull_up>;
1694                         };
1695
1696                         sdio1_cd: sdio1-cd {
1697                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1698                         };
1699
1700                         sdio1_wp: sdio1-wp {
1701                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1702                         };
1703
1704                         sdio1_bkpwr: sdio1-bkpwr {
1705                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1706                         };
1707
1708                         sdio1_int: sdio1-int {
1709                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1710                         };
1711
1712                         sdio1_cmd: sdio1-cmd {
1713                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1714                         };
1715
1716                         sdio1_clk: sdio1-clk {
1717                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1718                         };
1719
1720                         sdio1_pwr: sdio1-pwr {
1721                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1722                         };
1723                 };
1724
1725                 emmc {
1726                         emmc_clk: emmc-clk {
1727                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1728                         };
1729
1730                         emmc_cmd: emmc-cmd {
1731                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1732                         };
1733
1734                         emmc_pwr: emmc-pwr {
1735                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1736                         };
1737
1738                         emmc_bus1: emmc-bus1 {
1739                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1740                         };
1741
1742                         emmc_bus4: emmc-bus4 {
1743                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1744                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1745                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1746                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1747                         };
1748
1749                         emmc_bus8: emmc-bus8 {
1750                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1751                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1752                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1753                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1754                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1755                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1756                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1757                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1758                         };
1759                 };
1760
1761                 spi0 {
1762                         spi0_clk: spi0-clk {
1763                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1764                         };
1765                         spi0_cs0: spi0-cs0 {
1766                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1767                         };
1768                         spi0_tx: spi0-tx {
1769                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1770                         };
1771                         spi0_rx: spi0-rx {
1772                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1773                         };
1774                         spi0_cs1: spi0-cs1 {
1775                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1776                         };
1777                 };
1778                 spi1 {
1779                         spi1_clk: spi1-clk {
1780                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1781                         };
1782                         spi1_cs0: spi1-cs0 {
1783                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1784                         };
1785                         spi1_rx: spi1-rx {
1786                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1787                         };
1788                         spi1_tx: spi1-tx {
1789                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1790                         };
1791                 };
1792
1793                 spi2 {
1794                         spi2_cs1: spi2-cs1 {
1795                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1796                         };
1797                         spi2_clk: spi2-clk {
1798                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1799                         };
1800                         spi2_cs0: spi2-cs0 {
1801                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1802                         };
1803                         spi2_rx: spi2-rx {
1804                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1805                         };
1806                         spi2_tx: spi2-tx {
1807                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1808                         };
1809                 };
1810
1811                 uart0 {
1812                         uart0_xfer: uart0-xfer {
1813                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1814                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1815                         };
1816
1817                         uart0_cts: uart0-cts {
1818                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1819                         };
1820
1821                         uart0_rts: uart0-rts {
1822                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1823                         };
1824                 };
1825
1826                 uart1 {
1827                         uart1_xfer: uart1-xfer {
1828                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1829                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1830                         };
1831
1832                         uart1_cts: uart1-cts {
1833                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1834                         };
1835
1836                         uart1_rts: uart1-rts {
1837                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1838                         };
1839                 };
1840
1841                 uart2 {
1842                         uart2_xfer: uart2-xfer {
1843                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1844                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1845                         };
1846                         /* no rts / cts for uart2 */
1847                 };
1848
1849                 uart3 {
1850                         uart3_xfer: uart3-xfer {
1851                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1852                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1853                         };
1854
1855                         uart3_cts: uart3-cts {
1856                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1857                         };
1858
1859                         uart3_rts: uart3-rts {
1860                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1861                         };
1862                 };
1863
1864                 uart4 {
1865                         uart4_xfer: uart4-xfer {
1866                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1867                                                 <5 13 3 &pcfg_pull_none>;
1868                         };
1869
1870                         uart4_cts: uart4-cts {
1871                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1872                         };
1873
1874                         uart4_rts: uart4-rts {
1875                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1876                         };
1877                 };
1878
1879                 tsadc {
1880                         otp_gpio: otp-gpio {
1881                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1882                         };
1883
1884                         otp_out: otp-out {
1885                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1886                         };
1887                 };
1888
1889                 pwm0 {
1890                         pwm0_pin: pwm0-pin {
1891                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1892                         };
1893                 };
1894
1895                 pwm1 {
1896                         pwm1_pin: pwm1-pin {
1897                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1898                         };
1899                 };
1900
1901                 pwm2 {
1902                         pwm2_pin: pwm2-pin {
1903                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1904                         };
1905                 };
1906
1907                 pwm3 {
1908                         pwm3_pin: pwm3-pin {
1909                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1910                         };
1911                 };
1912
1913                 gmac {
1914                         rgmii_pins: rgmii-pins {
1915                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1916                                                 <3 31 3 &pcfg_pull_none>,
1917                                                 <3 26 3 &pcfg_pull_none>,
1918                                                 <3 27 3 &pcfg_pull_none>,
1919                                                 <3 28 3 &pcfg_pull_none_12ma>,
1920                                                 <3 29 3 &pcfg_pull_none_12ma>,
1921                                                 <3 24 3 &pcfg_pull_none_12ma>,
1922                                                 <3 25 3 &pcfg_pull_none_12ma>,
1923                                                 <4 0 3 &pcfg_pull_none>,
1924                                                 <4 5 3 &pcfg_pull_none>,
1925                                                 <4 6 3 &pcfg_pull_none>,
1926                                                 <4 9 3 &pcfg_pull_none_12ma>,
1927                                                 <4 4 3 &pcfg_pull_none_12ma>,
1928                                                 <4 1 3 &pcfg_pull_none>,
1929                                                 <4 3 3 &pcfg_pull_none>;
1930                         };
1931
1932                         rmii_pins: rmii-pins {
1933                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1934                                                 <3 31 3 &pcfg_pull_none>,
1935                                                 <3 28 3 &pcfg_pull_none>,
1936                                                 <3 29 3 &pcfg_pull_none>,
1937                                                 <4 0 3 &pcfg_pull_none>,
1938                                                 <4 5 3 &pcfg_pull_none>,
1939                                                 <4 4 3 &pcfg_pull_none>,
1940                                                 <4 1 3 &pcfg_pull_none>,
1941                                                 <4 2 3 &pcfg_pull_none>,
1942                                                 <4 3 3 &pcfg_pull_none>;
1943                         };
1944                 };
1945
1946                 spdif {
1947                         spdif_tx: spdif-tx {
1948                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1949                         };
1950                 };
1951
1952                 cif {
1953                         cif_dvp_d2d9: cif-dvp-d2d9 {
1954                                 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
1955                                                 <2 1 RK_FUNC_1 &pcfg_pull_none>,
1956                                                 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1957                                                 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1958                                                 <2 4 RK_FUNC_1 &pcfg_pull_none>,
1959                                                 <2 5 RK_FUNC_1 &pcfg_pull_none>,
1960                                                 <2 6 RK_FUNC_1 &pcfg_pull_none>,
1961                                                 <2 7 RK_FUNC_1 &pcfg_pull_none>,
1962                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>,
1963                                                 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1964                                                 <2 11 RK_FUNC_1 &pcfg_pull_none>;
1965                         };
1966                 };
1967         };
1968 };