arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip_boot-mode.h>
  49 #include "skeleton.dtsi"
  50
  51 / {
  52         compatible = "rockchip,rk3288";
  53
  54         interrupt-parent = <&gic>;
  55
  56         aliases {
  57                 i2c0 = &i2c0;
  58                 i2c1 = &i2c1;
  59                 i2c2 = &i2c2;
  60                 i2c3 = &i2c3;
  61                 i2c4 = &i2c4;
  62                 i2c5 = &i2c5;
  63                 mshc0 = &emmc;
  64                 mshc1 = &sdmmc;
  65                 mshc2 = &sdio0;
  66                 mshc3 = &sdio1;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72                 spi0 = &spi0;
  73                 spi1 = &spi1;
  74                 spi2 = &spi2;
  75         };
  76
  77         arm-pmu {
  78                 compatible = "arm,cortex-a12-pmu";
  79                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  83                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  84         };
  85
  86         cpus {
  87                 #address-cells = <1>;
  88                 #size-cells = <0>;
  89                 enable-method = "rockchip,rk3066-smp";
  90                 rockchip,pmu = <&pmu>;
  91
  92                 cpu0: cpu@500 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a12";
  95                         reg = <0x500>;
  96                         resets = <&cru SRST_CORE0>;
  97                         operating-points = <
  98                                 /* KHz    uV */
  99                                 1608000 1350000
 100                                 1512000 1300000
 101                                 1416000 1200000
 102                                 1200000 1100000
 103                                 1008000 1050000
 104                                  816000 1000000
 105                                  696000  950000
 106                                  600000  900000
 107                                  408000  900000
 108                                  312000  900000
 109                                  216000  900000
 110                                  126000  900000
 111                         >;
 112                         #cooling-cells = <2>; /* min followed by max */
 113                         clock-latency = <40000>;
 114                         clocks = <&cru ARMCLK>;
 115                 };
 116                 cpu1: cpu@501 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a12";
 119                         reg = <0x501>;
 120                         resets = <&cru SRST_CORE1>;
 121                 };
 122                 cpu2: cpu@502 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a12";
 125                         reg = <0x502>;
 126                         resets = <&cru SRST_CORE2>;
 127                 };
 128                 cpu3: cpu@503 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a12";
 131                         reg = <0x503>;
 132                         resets = <&cru SRST_CORE3>;
 133                 };
 134         };
 135
 136         amba {
 137                 compatible = "arm,amba-bus";
 138                 #address-cells = <1>;
 139                 #size-cells = <1>;
 140                 ranges;
 141
 142                 dmac_peri: dma-controller@ff250000 {
 143                         compatible = "arm,pl330", "arm,primecell";
 144                         reg = <0xff250000 0x4000>;
 145                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 146                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 147                         #dma-cells = <1>;
 148                         arm,pl330-broken-no-flushp;
 149                         peripherals-req-type-burst;
 150                         clocks = <&cru ACLK_DMAC2>;
 151                         clock-names = "apb_pclk";
 152                 };
 153
 154                 dmac_bus_ns: dma-controller@ff600000 {
 155                         compatible = "arm,pl330", "arm,primecell";
 156                         reg = <0xff600000 0x4000>;
 157                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 158                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 159                         #dma-cells = <1>;
 160                         arm,pl330-broken-no-flushp;
 161                         peripherals-req-type-burst;
 162                         clocks = <&cru ACLK_DMAC1>;
 163                         clock-names = "apb_pclk";
 164                         status = "disabled";
 165                 };
 166
 167                 dmac_bus_s: dma-controller@ffb20000 {
 168                         compatible = "arm,pl330", "arm,primecell";
 169                         reg = <0xffb20000 0x4000>;
 170                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 171                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 172                         #dma-cells = <1>;
 173                         arm,pl330-broken-no-flushp;
 174                         peripherals-req-type-burst;
 175                         clocks = <&cru ACLK_DMAC1>;
 176                         clock-names = "apb_pclk";
 177                 };
 178         };
 179
 180         reserved-memory {
 181                 #address-cells = <1>;
 182                 #size-cells = <1>;
 183                 ranges;
 184
 185                 /*
 186                  * The rk3288 cannot use the memory area above 0xfe000000
 187                  * for dma operations for some reason. While there is
 188                  * probably a better solution available somewhere, we
 189                  * haven't found it yet and while devices with 2GB of ram
 190                  * are not affected, this issue prevents 4GB from booting.
 191                  * So to make these devices at least bootable, block
 192                  * this area for the time being until the real solution
 193                  * is found.
 194                  */
 195                 dma-unusable@fe000000 {
 196                         reg = <0xfe000000 0x1000000>;
 197                 };
 198         };
 199
 200         xin24m: oscillator {
 201                 compatible = "fixed-clock";
 202                 clock-frequency = <24000000>;
 203                 clock-output-names = "xin24m";
 204                 #clock-cells = <0>;
 205         };
 206
 207         edp_phy: edp-phy {
 208                 compatible = "rockchip,rk3288-dp-phy";
 209                 clocks = <&cru SCLK_EDP_24M>;
 210                 clock-names = "24m";
 211                 rockchip,grf = <&grf>;
 212                 #phy-cells = <0>;
 213                 status = "disabled";
 214         };
 215
 216         timer {
 217                 compatible = "arm,armv7-timer";
 218                 arm,cpu-registers-not-fw-configured;
 219                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 220                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 221                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 222                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 223                 clock-frequency = <24000000>;
 224         };
 225
 226         timer: timer@ff810000 {
 227                 compatible = "rockchip,rk3288-timer";
 228                 reg = <0xff810000 0x20>;
 229                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 230                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 231                 clock-names = "timer", "pclk";
 232         };
 233
 234         display-subsystem {
 235                 compatible = "rockchip,display-subsystem";
 236                 ports = <&vopl_out>, <&vopb_out>;
 237         };
 238
 239         sdmmc: dwmmc@ff0c0000 {
 240                 compatible = "rockchip,rk3288-dw-mshc";
 241                 clock-freq-min-max = <400000 150000000>;
 242                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 243                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 244                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 245                 fifo-depth = <0x100>;
 246                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 247                 reg = <0xff0c0000 0x4000>;
 248                 status = "disabled";
 249         };
 250
 251         sdio0: dwmmc@ff0d0000 {
 252                 compatible = "rockchip,rk3288-dw-mshc";
 253                 clock-freq-min-max = <400000 150000000>;
 254                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 255                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 256                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 257                 fifo-depth = <0x100>;
 258                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 259                 reg = <0xff0d0000 0x4000>;
 260                 status = "disabled";
 261         };
 262
 263         sdio1: dwmmc@ff0e0000 {
 264                 compatible = "rockchip,rk3288-dw-mshc";
 265                 clock-freq-min-max = <400000 150000000>;
 266                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 267                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 268                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 269                 fifo-depth = <0x100>;
 270                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 271                 reg = <0xff0e0000 0x4000>;
 272                 status = "disabled";
 273         };
 274
 275         emmc: dwmmc@ff0f0000 {
 276                 compatible = "rockchip,rk3288-dw-mshc";
 277                 clock-freq-min-max = <400000 150000000>;
 278                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 279                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 280                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 281                 fifo-depth = <0x100>;
 282                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 283                 reg = <0xff0f0000 0x4000>;
 284                 status = "disabled";
 285                 supports-emmc;
 286         };
 287
 288         saradc: saradc@ff100000 {
 289                 compatible = "rockchip,saradc";
 290                 reg = <0xff100000 0x100>;
 291                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 292                 #io-channel-cells = <1>;
 293                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 294                 clock-names = "saradc", "apb_pclk";
 295                 status = "disabled";
 296         };
 297
 298         spi0: spi@ff110000 {
 299                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 300                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 301                 clock-names = "spiclk", "apb_pclk";
 302                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 303                 dma-names = "tx", "rx";
 304                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 305                 pinctrl-names = "default";
 306                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 307                 reg = <0xff110000 0x1000>;
 308                 #address-cells = <1>;
 309                 #size-cells = <0>;
 310                 status = "disabled";
 311         };
 312
 313         spi1: spi@ff120000 {
 314                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 315                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 316                 clock-names = "spiclk", "apb_pclk";
 317                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 318                 dma-names = "tx", "rx";
 319                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 320                 pinctrl-names = "default";
 321                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 322                 reg = <0xff120000 0x1000>;
 323                 #address-cells = <1>;
 324                 #size-cells = <0>;
 325                 status = "disabled";
 326         };
 327
 328         spi2: spi@ff130000 {
 329                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 330                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 331                 clock-names = "spiclk", "apb_pclk";
 332                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 333                 dma-names = "tx", "rx";
 334                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 335                 pinctrl-names = "default";
 336                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 337                 reg = <0xff130000 0x1000>;
 338                 #address-cells = <1>;
 339                 #size-cells = <0>;
 340                 status = "disabled";
 341         };
 342
 343         i2c1: i2c@ff140000 {
 344                 compatible = "rockchip,rk3288-i2c";
 345                 reg = <0xff140000 0x1000>;
 346                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 347                 #address-cells = <1>;
 348                 #size-cells = <0>;
 349                 clock-names = "i2c";
 350                 clocks = <&cru PCLK_I2C1>;
 351                 pinctrl-names = "default";
 352                 pinctrl-0 = <&i2c1_xfer>;
 353                 status = "disabled";
 354         };
 355
 356         i2c3: i2c@ff150000 {
 357                 compatible = "rockchip,rk3288-i2c";
 358                 reg = <0xff150000 0x1000>;
 359                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 360                 #address-cells = <1>;
 361                 #size-cells = <0>;
 362                 clock-names = "i2c";
 363                 clocks = <&cru PCLK_I2C3>;
 364                 pinctrl-names = "default";
 365                 pinctrl-0 = <&i2c3_xfer>;
 366                 status = "disabled";
 367         };
 368
 369         i2c4: i2c@ff160000 {
 370                 compatible = "rockchip,rk3288-i2c";
 371                 reg = <0xff160000 0x1000>;
 372                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 373                 #address-cells = <1>;
 374                 #size-cells = <0>;
 375                 clock-names = "i2c";
 376                 clocks = <&cru PCLK_I2C4>;
 377                 pinctrl-names = "default";
 378                 pinctrl-0 = <&i2c4_xfer>;
 379                 status = "disabled";
 380         };
 381
 382         i2c5: i2c@ff170000 {
 383                 compatible = "rockchip,rk3288-i2c";
 384                 reg = <0xff170000 0x1000>;
 385                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 386                 #address-cells = <1>;
 387                 #size-cells = <0>;
 388                 clock-names = "i2c";
 389                 clocks = <&cru PCLK_I2C5>;
 390                 pinctrl-names = "default";
 391                 pinctrl-0 = <&i2c5_xfer>;
 392                 status = "disabled";
 393         };
 394
 395         uart0: serial@ff180000 {
 396                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 397                 reg = <0xff180000 0x100>;
 398                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 399                 reg-shift = <2>;
 400                 reg-io-width = <4>;
 401                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 402                 clock-names = "baudclk", "apb_pclk";
 403                 pinctrl-names = "default";
 404                 pinctrl-0 = <&uart0_xfer>;
 405                 status = "disabled";
 406         };
 407
 408         uart1: serial@ff190000 {
 409                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 410                 reg = <0xff190000 0x100>;
 411                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 412                 reg-shift = <2>;
 413                 reg-io-width = <4>;
 414                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 415                 clock-names = "baudclk", "apb_pclk";
 416                 pinctrl-names = "default";
 417                 pinctrl-0 = <&uart1_xfer>;
 418                 status = "disabled";
 419         };
 420
 421         uart2: serial@ff690000 {
 422                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 423                 reg = <0xff690000 0x100>;
 424                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 425                 reg-shift = <2>;
 426                 reg-io-width = <4>;
 427                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 428                 clock-names = "baudclk", "apb_pclk";
 429                 pinctrl-names = "default";
 430                 pinctrl-0 = <&uart2_xfer>;
 431                 status = "disabled";
 432         };
 433
 434         uart3: serial@ff1b0000 {
 435                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 436                 reg = <0xff1b0000 0x100>;
 437                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 438                 reg-shift = <2>;
 439                 reg-io-width = <4>;
 440                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 441                 clock-names = "baudclk", "apb_pclk";
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&uart3_xfer>;
 444                 status = "disabled";
 445         };
 446
 447         uart4: serial@ff1c0000 {
 448                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 449                 reg = <0xff1c0000 0x100>;
 450                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 451                 reg-shift = <2>;
 452                 reg-io-width = <4>;
 453                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 454                 clock-names = "baudclk", "apb_pclk";
 455                 pinctrl-names = "default";
 456                 pinctrl-0 = <&uart4_xfer>;
 457                 status = "disabled";
 458         };
 459
 460         thermal-zones {
 461                 #include "rk3288-thermal.dtsi"
 462         };
 463
 464         tsadc: tsadc@ff280000 {
 465                 compatible = "rockchip,rk3288-tsadc";
 466                 reg = <0xff280000 0x100>;
 467                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 468                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 469                 clock-names = "tsadc", "apb_pclk";
 470                 resets = <&cru SRST_TSADC>;
 471                 reset-names = "tsadc-apb";
 472                 pinctrl-names = "init", "default", "sleep";
 473                 pinctrl-0 = <&otp_gpio>;
 474                 pinctrl-1 = <&otp_out>;
 475                 pinctrl-2 = <&otp_gpio>;
 476                 #thermal-sensor-cells = <1>;
 477                 rockchip,hw-tshut-temp = <95000>;
 478                 status = "disabled";
 479         };
 480
 481         gmac: ethernet@ff290000 {
 482                 compatible = "rockchip,rk3288-gmac";
 483                 reg = <0xff290000 0x10000>;
 484                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 485                 interrupt-names = "macirq";
 486                 rockchip,grf = <&grf>;
 487                 clocks = <&cru SCLK_MAC>,
 488                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 489                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 490                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 491                 clock-names = "stmmaceth",
 492                         "mac_clk_rx", "mac_clk_tx",
 493                         "clk_mac_ref", "clk_mac_refout",
 494                         "aclk_mac", "pclk_mac";
 495                 resets = <&cru SRST_MAC>;
 496                 reset-names = "stmmaceth";
 497                 max-speed = <100>;
 498                 status = "disabled";
 499         };
 500
 501         usb_host0_ehci: usb@ff500000 {
 502                 compatible = "generic-ehci";
 503                 reg = <0xff500000 0x100>;
 504                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 505                 clocks = <&cru HCLK_USBHOST0>;
 506                 clock-names = "usbhost";
 507                 phys = <&usbphy1>;
 508                 phy-names = "usb";
 509                 status = "disabled";
 510         };
 511
 512         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 513
 514         usb_host1: usb@ff540000 {
 515                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 516                                 "snps,dwc2";
 517                 reg = <0xff540000 0x40000>;
 518                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 519                 clocks = <&cru HCLK_USBHOST1>;
 520                 clock-names = "otg";
 521                 dr_mode = "host";
 522                 phys = <&usbphy2>;
 523                 phy-names = "usb2-phy";
 524                 status = "disabled";
 525         };
 526
 527         usb_otg: usb@ff580000 {
 528                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 529                                 "snps,dwc2";
 530                 reg = <0xff580000 0x40000>;
 531                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 532                 clocks = <&cru HCLK_OTG0>;
 533                 clock-names = "otg";
 534                 dr_mode = "otg";
 535                 g-np-tx-fifo-size = <16>;
 536                 g-rx-fifo-size = <275>;
 537                 g-tx-fifo-size = <256 128 128 64 64 32>;
 538                 g-use-dma;
 539                 phys = <&usbphy0>;
 540                 phy-names = "usb2-phy";
 541                 status = "disabled";
 542         };
 543
 544         usb_hsic: usb@ff5c0000 {
 545                 compatible = "generic-ehci";
 546                 reg = <0xff5c0000 0x100>;
 547                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 548                 clocks = <&cru HCLK_HSIC>;
 549                 clock-names = "usbhost";
 550                 status = "disabled";
 551         };
 552
 553         i2c0: i2c@ff650000 {
 554                 compatible = "rockchip,rk3288-i2c";
 555                 reg = <0xff650000 0x1000>;
 556                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 557                 #address-cells = <1>;
 558                 #size-cells = <0>;
 559                 clock-names = "i2c";
 560                 clocks = <&cru PCLK_I2C0>;
 561                 pinctrl-names = "default";
 562                 pinctrl-0 = <&i2c0_xfer>;
 563                 status = "disabled";
 564         };
 565
 566         i2c2: i2c@ff660000 {
 567                 compatible = "rockchip,rk3288-i2c";
 568                 reg = <0xff660000 0x1000>;
 569                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 570                 #address-cells = <1>;
 571                 #size-cells = <0>;
 572                 clock-names = "i2c";
 573                 clocks = <&cru PCLK_I2C2>;
 574                 pinctrl-names = "default";
 575                 pinctrl-0 = <&i2c2_xfer>;
 576                 status = "disabled";
 577         };
 578
 579         pwm0: pwm@ff680000 {
 580                 compatible = "rockchip,rk3288-pwm";
 581                 reg = <0xff680000 0x10>;
 582                 #pwm-cells = <3>;
 583                 pinctrl-names = "default";
 584                 pinctrl-0 = <&pwm0_pin>;
 585                 clocks = <&cru PCLK_PWM>;
 586                 clock-names = "pwm";
 587                 status = "disabled";
 588         };
 589
 590         pwm1: pwm@ff680010 {
 591                 compatible = "rockchip,rk3288-pwm";
 592                 reg = <0xff680010 0x10>;
 593                 #pwm-cells = <3>;
 594                 pinctrl-names = "default";
 595                 pinctrl-0 = <&pwm1_pin>;
 596                 clocks = <&cru PCLK_PWM>;
 597                 clock-names = "pwm";
 598                 status = "disabled";
 599         };
 600
 601         pwm2: pwm@ff680020 {
 602                 compatible = "rockchip,rk3288-pwm";
 603                 reg = <0xff680020 0x10>;
 604                 #pwm-cells = <3>;
 605                 pinctrl-names = "default";
 606                 pinctrl-0 = <&pwm2_pin>;
 607                 clocks = <&cru PCLK_PWM>;
 608                 clock-names = "pwm";
 609                 status = "disabled";
 610         };
 611
 612         pwm3: pwm@ff680030 {
 613                 compatible = "rockchip,rk3288-pwm";
 614                 reg = <0xff680030 0x10>;
 615                 #pwm-cells = <2>;
 616                 pinctrl-names = "default";
 617                 pinctrl-0 = <&pwm3_pin>;
 618                 clocks = <&cru PCLK_PWM>;
 619                 clock-names = "pwm";
 620                 status = "disabled";
 621         };
 622
 623         bus_intmem@ff700000 {
 624                 compatible = "mmio-sram";
 625                 reg = <0xff700000 0x18000>;
 626                 #address-cells = <1>;
 627                 #size-cells = <1>;
 628                 ranges = <0 0xff700000 0x18000>;
 629                 smp-sram@0 {
 630                         compatible = "rockchip,rk3066-smp-sram";
 631                         reg = <0x00 0x10>;
 632                 };
 633         };
 634
 635         sram@ff720000 {
 636                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 637                 reg = <0xff720000 0x1000>;
 638         };
 639
 640         qos_gpu_r: qos@ffaa0000 {
 641                 compatible = "syscon";
 642                 reg = <0xffaa0000 0x20>;
 643         };
 644
 645         qos_gpu_w: qos@ffaa0080 {
 646                 compatible = "syscon";
 647                 reg = <0xffaa0080 0x20>;
 648         };
 649
 650         qos_vio1_vop: qos@ffad0000 {
 651                 compatible = "syscon";
 652                 reg = <0xffad0000 0x20>;
 653         };
 654
 655         qos_vio1_isp_w0: qos@ffad0100 {
 656                 compatible = "syscon";
 657                 reg = <0xffad0100 0x20>;
 658         };
 659
 660         qos_vio1_isp_w1: qos@ffad0180 {
 661                 compatible = "syscon";
 662                 reg = <0xffad0180 0x20>;
 663         };
 664
 665         qos_vio0_vop: qos@ffad0400 {
 666                 compatible = "syscon";
 667                 reg = <0xffad0400 0x20>;
 668         };
 669
 670         qos_vio0_vip: qos@ffad0480 {
 671                 compatible = "syscon";
 672                 reg = <0xffad0480 0x20>;
 673         };
 674
 675         qos_vio0_iep: qos@ffad0500 {
 676                 compatible = "syscon";
 677                 reg = <0xffad0500 0x20>;
 678         };
 679
 680         qos_vio2_rga_r: qos@ffad0800 {
 681                 compatible = "syscon";
 682                 reg = <0xffad0800 0x20>;
 683         };
 684
 685         qos_vio2_rga_w: qos@ffad0880 {
 686                 compatible = "syscon";
 687                 reg = <0xffad0880 0x20>;
 688         };
 689
 690         qos_vio1_isp_r: qos@ffad0900 {
 691                 compatible = "syscon";
 692                 reg = <0xffad0900 0x20>;
 693         };
 694
 695         qos_video: qos@ffae0000 {
 696                 compatible = "syscon";
 697                 reg = <0xffae0000 0x20>;
 698         };
 699
 700         qos_hevc_r: qos@ffaf0000 {
 701                 compatible = "syscon";
 702                 reg = <0xffaf0000 0x20>;
 703         };
 704
 705         qos_hevc_w: qos@ffaf0080 {
 706                 compatible = "syscon";
 707                 reg = <0xffaf0080 0x20>;
 708         };
 709
 710         pmu: power-management@ff730000 {
 711                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 712                 reg = <0xff730000 0x100>;
 713
 714                 power: power-controller {
 715                         compatible = "rockchip,rk3288-power-controller";
 716                         #power-domain-cells = <1>;
 717                         #address-cells = <1>;
 718                         #size-cells = <0>;
 719
 720                         /*
 721                          * Note: Although SCLK_* are the working clocks
 722                          * of device without including on the NOC, needed for
 723                          * synchronous reset.
 724                          *
 725                          * The clocks on the which NOC:
 726                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 727                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 728                          * ACLK_RGA is on ACLK_RGA_NIU.
 729                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 730                          *
 731                          * Which clock are device clocks:
 732                          *      clocks          devices
 733                          *      *_IEP           IEP:Image Enhancement Processor
 734                          *      *_ISP           ISP:Image Signal Processing
 735                          *      *_VIP           VIP:Video Input Processor
 736                          *      *_VOP*          VOP:Visual Output Processor
 737                          *      *_RGA           RGA
 738                          *      *_EDP*          EDP
 739                          *      *_LVDS_*        LVDS
 740                          *      *_HDMI          HDMI
 741                          *      *_MIPI_*        MIPI
 742                          */
 743                         pd_vio {
 744                                 reg = <RK3288_PD_VIO>;
 745                                 clocks = <&cru ACLK_IEP>,
 746                                          <&cru ACLK_ISP>,
 747                                          <&cru ACLK_RGA>,
 748                                          <&cru ACLK_VIP>,
 749                                          <&cru ACLK_VOP0>,
 750                                          <&cru ACLK_VOP1>,
 751                                          <&cru DCLK_VOP0>,
 752                                          <&cru DCLK_VOP1>,
 753                                          <&cru HCLK_IEP>,
 754                                          <&cru HCLK_ISP>,
 755                                          <&cru HCLK_RGA>,
 756                                          <&cru HCLK_VIP>,
 757                                          <&cru HCLK_VOP0>,
 758                                          <&cru HCLK_VOP1>,
 759                                          <&cru PCLK_EDP_CTRL>,
 760                                          <&cru PCLK_HDMI_CTRL>,
 761                                          <&cru PCLK_LVDS_PHY>,
 762                                          <&cru PCLK_MIPI_CSI>,
 763                                          <&cru PCLK_MIPI_DSI0>,
 764                                          <&cru PCLK_MIPI_DSI1>,
 765                                          <&cru SCLK_EDP_24M>,
 766                                          <&cru SCLK_EDP>,
 767                                          <&cru SCLK_ISP_JPE>,
 768                                          <&cru SCLK_ISP>,
 769                                          <&cru SCLK_RGA>;
 770                                 pm_qos = <&qos_vio0_iep>,
 771                                          <&qos_vio1_vop>,
 772                                          <&qos_vio1_isp_w0>,
 773                                          <&qos_vio1_isp_w1>,
 774                                          <&qos_vio0_vop>,
 775                                          <&qos_vio0_vip>,
 776                                          <&qos_vio2_rga_r>,
 777                                          <&qos_vio2_rga_w>,
 778                                          <&qos_vio1_isp_r>;
 779                         };
 780
 781                         /*
 782                          * Note: The following 3 are HEVC(H.265) clocks,
 783                          * and on the ACLK_HEVC_NIU (NOC).
 784                          */
 785                         pd_hevc {
 786                                 reg = <RK3288_PD_HEVC>;
 787                                 clocks = <&cru ACLK_HEVC>,
 788                                          <&cru SCLK_HEVC_CABAC>,
 789                                          <&cru SCLK_HEVC_CORE>;
 790                                 pm_qos = <&qos_hevc_r>,
 791                                          <&qos_hevc_w>;
 792                         };
 793
 794                         /*
 795                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 796                          * (video endecoder & decoder) clocks that on the
 797                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 798                          */
 799                         pd_video {
 800                                 reg = <RK3288_PD_VIDEO>;
 801                                 clocks = <&cru ACLK_VCODEC>,
 802                                          <&cru HCLK_VCODEC>;
 803                                 pm_qos = <&qos_video>;
 804                         };
 805
 806                         /*
 807                          * Note: ACLK_GPU is the GPU clock,
 808                          * and on the ACLK_GPU_NIU (NOC).
 809                          */
 810                         pd_gpu {
 811                                 reg = <RK3288_PD_GPU>;
 812                                 clocks = <&cru ACLK_GPU>;
 813                                 pm_qos = <&qos_gpu_r>,
 814                                          <&qos_gpu_w>;
 815                         };
 816                 };
 817
 818                 reboot-mode {
 819                         compatible = "syscon-reboot-mode";
 820                         offset = <0x94>;
 821                         mode-normal = <BOOT_NORMAL>;
 822                         mode-recovery = <BOOT_RECOVERY>;
 823                         mode-bootloader = <BOOT_FASTBOOT>;
 824                         mode-loader = <BOOT_LOADER>;
 825                         mode-ums = <BOOT_UMS>;
 826                 };
 827         };
 828
 829         sgrf: syscon@ff740000 {
 830                 compatible = "rockchip,rk3288-sgrf", "syscon";
 831                 reg = <0xff740000 0x1000>;
 832         };
 833
 834         cru: clock-controller@ff760000 {
 835                 compatible = "rockchip,rk3288-cru";
 836                 reg = <0xff760000 0x1000>;
 837                 rockchip,grf = <&grf>;
 838                 #clock-cells = <1>;
 839                 #reset-cells = <1>;
 840                 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
 841                                   <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 842                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 843                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 844                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 845                                   <&cru PCLK_PERI>;
 846                 assigned-clock-rates = <0>, <0>,
 847                                        <594000000>, <400000000>,
 848                                        <500000000>, <300000000>,
 849                                        <150000000>, <75000000>,
 850                                        <300000000>, <150000000>,
 851                                        <75000000>;
 852                 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
 853         };
 854
 855         grf: syscon@ff770000 {
 856                 compatible = "rockchip,rk3288-grf", "syscon";
 857                 reg = <0xff770000 0x1000>;
 858         };
 859
 860         wdt: watchdog@ff800000 {
 861                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 862                 reg = <0xff800000 0x100>;
 863                 clocks = <&cru PCLK_WDT>;
 864                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 865                 status = "disabled";
 866         };
 867
 868         spdif: sound@ff88b0000 {
 869                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 870                 reg = <0xff8b0000 0x10000>;
 871                 #sound-dai-cells = <0>;
 872                 clock-names = "hclk", "mclk";
 873                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 874                 dmas = <&dmac_bus_s 3>;
 875                 dma-names = "tx";
 876                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 877                 pinctrl-names = "default";
 878                 pinctrl-0 = <&spdif_tx>;
 879                 rockchip,grf = <&grf>;
 880                 status = "disabled";
 881         };
 882
 883         i2s: i2s@ff890000 {
 884                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 885                 reg = <0xff890000 0x10000>;
 886                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 887                 #address-cells = <1>;
 888                 #size-cells = <0>;
 889                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 890                 dma-names = "tx", "rx";
 891                 clock-names = "i2s_hclk", "i2s_clk";
 892                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 893                 pinctrl-names = "default";
 894                 pinctrl-0 = <&i2s0_bus>;
 895                 status = "disabled";
 896         };
 897
 898         vopb: vop@ff930000 {
 899                 compatible = "rockchip,rk3288-vop";
 900                 reg = <0xff930000 0x19c>;
 901                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 902                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 903                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 904                 power-domains = <&power RK3288_PD_VIO>;
 905                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 906                 reset-names = "axi", "ahb", "dclk";
 907                 iommus = <&vopb_mmu>;
 908                 status = "disabled";
 909
 910                 vopb_out: port {
 911                         #address-cells = <1>;
 912                         #size-cells = <0>;
 913
 914                         vopb_out_hdmi: endpoint@0 {
 915                                 reg = <0>;
 916                                 remote-endpoint = <&hdmi_in_vopb>;
 917                         };
 918
 919                         vopb_out_edp: endpoint@1 {
 920                                 reg = <1>;
 921                                 remote-endpoint = <&edp_in_vopb>;
 922                         };
 923
 924                         vopb_out_mipi: endpoint@2 {
 925                                 reg = <2>;
 926                                 remote-endpoint = <&mipi_in_vopb>;
 927                         };
 928
 929                         vopb_out_lvds: endpoint@3 {
 930                                 reg = <3>;
 931                                 remote-endpoint = <&lvds_in_vopb>;
 932                         };
 933                 };
 934         };
 935
 936         vopb_mmu: iommu@ff930300 {
 937                 compatible = "rockchip,iommu";
 938                 reg = <0xff930300 0x100>;
 939                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 940                 interrupt-names = "vopb_mmu";
 941                 power-domains = <&power RK3288_PD_VIO>;
 942                 #iommu-cells = <0>;
 943                 status = "disabled";
 944         };
 945
 946         vopl: vop@ff940000 {
 947                 compatible = "rockchip,rk3288-vop";
 948                 reg = <0xff940000 0x19c>;
 949                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 950                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 951                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 952                 power-domains = <&power RK3288_PD_VIO>;
 953                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 954                 reset-names = "axi", "ahb", "dclk";
 955                 iommus = <&vopl_mmu>;
 956                 status = "disabled";
 957
 958                 vopl_out: port {
 959                         #address-cells = <1>;
 960                         #size-cells = <0>;
 961
 962                         vopl_out_hdmi: endpoint@0 {
 963                                 reg = <0>;
 964                                 remote-endpoint = <&hdmi_in_vopl>;
 965                         };
 966
 967                         vopl_out_edp: endpoint@1 {
 968                                 reg = <1>;
 969                                 remote-endpoint = <&edp_in_vopl>;
 970                         };
 971
 972                         vopl_out_mipi: endpoint@2 {
 973                                 reg = <2>;
 974                                 remote-endpoint = <&mipi_in_vopl>;
 975                         };
 976
 977                         vopl_out_lvds: endpoint@3 {
 978                                 reg = <3>;
 979                                 remote-endpoint = <&lvds_in_vopl>;
 980                         };
 981
 982                 };
 983         };
 984
 985         vopl_mmu: iommu@ff940300 {
 986                 compatible = "rockchip,iommu";
 987                 reg = <0xff940300 0x100>;
 988                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 989                 interrupt-names = "vopl_mmu";
 990                 power-domains = <&power RK3288_PD_VIO>;
 991                 #iommu-cells = <0>;
 992                 status = "disabled";
 993         };
 994
 995         mipi_dsi: mipi@ff960000 {
 996                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
 997                 reg = <0xff960000 0x4000>;
 998                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 999                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1000                 clock-names = "ref", "pclk";
1001                 rockchip,grf = <&grf>;
1002                 #address-cells = <1>;
1003                 #size-cells = <0>;
1004                 status = "disabled";
1005
1006                 ports {
1007                         #address-cells = <1>;
1008                         #size-cells = <0>;
1009                         reg = <1>;
1010
1011                         mipi_in: port {
1012                                 #address-cells = <1>;
1013                                 #size-cells = <0>;
1014                                 mipi_in_vopb: endpoint@0 {
1015                                         reg = <0>;
1016                                         remote-endpoint = <&vopb_out_mipi>;
1017                                 };
1018                                 mipi_in_vopl: endpoint@1 {
1019                                         reg = <1>;
1020                                         remote-endpoint = <&vopl_out_mipi>;
1021                                 };
1022                         };
1023                 };
1024         };
1025
1026         edp: dp@ff970000 {
1027                 compatible = "rockchip,rk3288-dp";
1028                 reg = <0xff970000 0x4000>;
1029                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1030                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1031                 clock-names = "dp", "pclk";
1032                 phys = <&edp_phy>;
1033                 phy-names = "dp";
1034                 resets = <&cru SRST_EDP>;
1035                 reset-names = "dp";
1036                 rockchip,grf = <&grf>;
1037                 status = "disabled";
1038
1039                 ports {
1040                         #address-cells = <1>;
1041                         #size-cells = <0>;
1042                         edp_in: port@0 {
1043                                 reg = <0>;
1044                                 #address-cells = <1>;
1045                                 #size-cells = <0>;
1046                                 edp_in_vopb: endpoint@0 {
1047                                         reg = <0>;
1048                                         remote-endpoint = <&vopb_out_edp>;
1049                                 };
1050                                 edp_in_vopl: endpoint@1 {
1051                                         reg = <1>;
1052                                         remote-endpoint = <&vopl_out_edp>;
1053                                 };
1054                         };
1055                 };
1056         };
1057
1058         lvds: lvds@ff96c000 {
1059                 compatible = "rockchip,rk3288-lvds";
1060                 reg = <0xff96c000 0x4000>;
1061                 clocks = <&cru PCLK_LVDS_PHY>;
1062                 clock-names = "pclk_lvds";
1063                 pinctrl-names = "default";
1064                 pinctrl-0 = <&lcdc0_ctl>;
1065                 power-domains = <&power RK3288_PD_VIO>;
1066                 rockchip,grf = <&grf>;
1067                 status = "disabled";
1068
1069                 ports {
1070                         #address-cells = <1>;
1071                         #size-cells = <0>;
1072
1073                         lvds_in: port@0 {
1074                                 reg = <0>;
1075
1076                                 #address-cells = <1>;
1077                                 #size-cells = <0>;
1078
1079                                 lvds_in_vopb: endpoint@0 {
1080                                         reg = <0>;
1081                                         remote-endpoint = <&vopb_out_lvds>;
1082                                 };
1083                                 lvds_in_vopl: endpoint@1 {
1084                                         reg = <1>;
1085                                         remote-endpoint = <&vopl_out_lvds>;
1086                                 };
1087                         };
1088                 };
1089         };
1090
1091         hdmi: hdmi@ff980000 {
1092                 compatible = "rockchip,rk3288-dw-hdmi";
1093                 reg = <0xff980000 0x20000>;
1094                 reg-io-width = <4>;
1095                 rockchip,grf = <&grf>;
1096                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1097                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1098                 clock-names = "iahb", "isfr";
1099                 power-domains = <&power RK3288_PD_VIO>;
1100                 status = "disabled";
1101
1102                 ports {
1103                         hdmi_in: port {
1104                                 #address-cells = <1>;
1105                                 #size-cells = <0>;
1106                                 hdmi_in_vopb: endpoint@0 {
1107                                         reg = <0>;
1108                                         remote-endpoint = <&vopb_out_hdmi>;
1109                                 };
1110                                 hdmi_in_vopl: endpoint@1 {
1111                                         reg = <1>;
1112                                         remote-endpoint = <&vopl_out_hdmi>;
1113                                 };
1114                         };
1115                 };
1116         };
1117
1118         gpu: gpu@ffa30000 {
1119                 compatible = "arm,malit764",
1120                              "arm,malit76x",
1121                              "arm,malit7xx",
1122                              "arm,mali-midgard";
1123                 reg = <0xffa30000 0x10000>;
1124                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1125                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1126                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1127                 interrupt-names = "JOB", "MMU", "GPU";
1128                 clocks = <&cru ACLK_GPU>;
1129                 clock-names = "clk_mali";
1130                 operating-points = <
1131                         /* KHz uV */
1132                         600000 1250000
1133                         /* 500000 1200000 - See crosbug.com/p/33857 */
1134                         400000 1100000
1135                         300000 1000000
1136                         200000 950000
1137                         100000 950000
1138                 >;
1139                 #cooling-cells = <2>; /* min followed by max */
1140                 power-domains = <&power RK3288_PD_GPU>;
1141                 status = "disabled";
1142         };
1143
1144         vpu: video-codec@ff9a0000 {
1145                 compatible = "rockchip,rk3288-vpu";
1146                 reg = <0xff9a0000 0x800>;
1147                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1148                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1149                 interrupt-names = "vepu", "vdpu";
1150                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1151                 clock-names = "aclk", "hclk";
1152                 power-domains = <&power RK3288_PD_VIDEO>;
1153                 iommus = <&vpu_mmu>;
1154                 assigned-clocks = <&cru ACLK_VCODEC>;
1155                 assigned-clock-rates = <400000000>;
1156                 status = "disabled";
1157         };
1158
1159         vpu_service: vpu-service@ff9a0000 {
1160                 compatible = "rockchip,vpu_service";
1161                 reg = <0xff9a0000 0x800>;
1162                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1163                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1164                 interrupt-names = "irq_enc", "irq_dec";
1165                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1166                 clock-names = "aclk_vcodec", "hclk_vcodec";
1167                 power-domains = <&power RK3288_PD_VIDEO>;
1168                 rockchip,grf = <&grf>;
1169                 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1170                 reset-names = "video_a", "video_h";
1171                 iommus = <&vpu_mmu>;
1172                 iommu_enabled = <1>;
1173                 dev_mode = <0>;
1174                 status = "disabled";
1175         };
1176
1177         vpu_mmu: iommu@ff9a0800 {
1178                 compatible = "rockchip,iommu";
1179                 reg = <0xff9a0800 0x100>;
1180                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1181                 interrupt-names = "vpu_mmu";
1182                 power-domains = <&power RK3288_PD_VIDEO>;
1183                 #iommu-cells = <0>;
1184         };
1185
1186         hevc_service: hevc-service@ff9c0000 {
1187                 compatible = "rockchip,hevc_service";
1188                 reg = <0xff9c0000 0x400>;
1189                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1190                 interrupt-names = "irq_dec";
1191                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1192                         <&cru SCLK_HEVC_CORE>,
1193                         <&cru SCLK_HEVC_CABAC>;
1194                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1195                         "clk_cabac";
1196                 resets = <&cru SRST_HEVC>;
1197                 reset-names = "video";
1198                 power-domains = <&power RK3288_PD_HEVC>;
1199                 rockchip,grf = <&grf>;
1200                 dev_mode = <1>;
1201                 iommus = <&hevc_mmu>;
1202                 iommu_enabled = <1>;
1203                 status = "disabled";
1204         };
1205
1206         hevc_mmu: iommu@ff9c0440 {
1207                 compatible = "rockchip,iommu";
1208                 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1209                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1210                 interrupt-names = "hevc_mmu";
1211                 power-domains = <&power RK3288_PD_HEVC>;
1212                 #iommu-cells = <0>;
1213         };
1214
1215         gic: interrupt-controller@ffc01000 {
1216                 compatible = "arm,gic-400";
1217                 interrupt-controller;
1218                 #interrupt-cells = <3>;
1219                 #address-cells = <0>;
1220
1221                 reg = <0xffc01000 0x1000>,
1222                       <0xffc02000 0x1000>,
1223                       <0xffc04000 0x2000>,
1224                       <0xffc06000 0x2000>;
1225                 interrupts = <GIC_PPI 9 0xf04>;
1226         };
1227
1228         efuse: efuse@ffb40000 {
1229                 compatible = "rockchip,rockchip-efuse";
1230                 reg = <0xffb40000 0x20>;
1231                 #address-cells = <1>;
1232                 #size-cells = <1>;
1233                 clocks = <&cru PCLK_EFUSE256>;
1234                 clock-names = "pclk_efuse";
1235
1236                 cpu_leakage: cpu_leakage@17 {
1237                         reg = <0x17 0x1>;
1238                 };
1239         };
1240
1241         usbphy: phy {
1242                 compatible = "rockchip,rk3288-usb-phy";
1243                 rockchip,grf = <&grf>;
1244                 #address-cells = <1>;
1245                 #size-cells = <0>;
1246                 status = "disabled";
1247
1248                 usbphy0: usb-phy0 {
1249                         #phy-cells = <0>;
1250                         reg = <0x320>;
1251                         clocks = <&cru SCLK_OTGPHY0>;
1252                         clock-names = "phyclk";
1253                 };
1254
1255                 usbphy1: usb-phy1 {
1256                         #phy-cells = <0>;
1257                         reg = <0x334>;
1258                         clocks = <&cru SCLK_OTGPHY1>;
1259                         clock-names = "phyclk";
1260                 };
1261
1262                 usbphy2: usb-phy2 {
1263                         #phy-cells = <0>;
1264                         reg = <0x348>;
1265                         clocks = <&cru SCLK_OTGPHY2>;
1266                         clock-names = "phyclk";
1267                 };
1268         };
1269
1270         pinctrl: pinctrl {
1271                 compatible = "rockchip,rk3288-pinctrl";
1272                 rockchip,grf = <&grf>;
1273                 rockchip,pmu = <&pmu>;
1274                 #address-cells = <1>;
1275                 #size-cells = <1>;
1276                 ranges;
1277
1278                 gpio0: gpio0@ff750000 {
1279                         compatible = "rockchip,gpio-bank";
1280                         reg =   <0xff750000 0x100>;
1281                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1282                         clocks = <&cru PCLK_GPIO0>;
1283
1284                         gpio-controller;
1285                         #gpio-cells = <2>;
1286
1287                         interrupt-controller;
1288                         #interrupt-cells = <2>;
1289                 };
1290
1291                 gpio1: gpio1@ff780000 {
1292                         compatible = "rockchip,gpio-bank";
1293                         reg = <0xff780000 0x100>;
1294                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1295                         clocks = <&cru PCLK_GPIO1>;
1296
1297                         gpio-controller;
1298                         #gpio-cells = <2>;
1299
1300                         interrupt-controller;
1301                         #interrupt-cells = <2>;
1302                 };
1303
1304                 gpio2: gpio2@ff790000 {
1305                         compatible = "rockchip,gpio-bank";
1306                         reg = <0xff790000 0x100>;
1307                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1308                         clocks = <&cru PCLK_GPIO2>;
1309
1310                         gpio-controller;
1311                         #gpio-cells = <2>;
1312
1313                         interrupt-controller;
1314                         #interrupt-cells = <2>;
1315                 };
1316
1317                 gpio3: gpio3@ff7a0000 {
1318                         compatible = "rockchip,gpio-bank";
1319                         reg = <0xff7a0000 0x100>;
1320                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1321                         clocks = <&cru PCLK_GPIO3>;
1322
1323                         gpio-controller;
1324                         #gpio-cells = <2>;
1325
1326                         interrupt-controller;
1327                         #interrupt-cells = <2>;
1328                 };
1329
1330                 gpio4: gpio4@ff7b0000 {
1331                         compatible = "rockchip,gpio-bank";
1332                         reg = <0xff7b0000 0x100>;
1333                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1334                         clocks = <&cru PCLK_GPIO4>;
1335
1336                         gpio-controller;
1337                         #gpio-cells = <2>;
1338
1339                         interrupt-controller;
1340                         #interrupt-cells = <2>;
1341                 };
1342
1343                 gpio5: gpio5@ff7c0000 {
1344                         compatible = "rockchip,gpio-bank";
1345                         reg = <0xff7c0000 0x100>;
1346                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1347                         clocks = <&cru PCLK_GPIO5>;
1348
1349                         gpio-controller;
1350                         #gpio-cells = <2>;
1351
1352                         interrupt-controller;
1353                         #interrupt-cells = <2>;
1354                 };
1355
1356                 gpio6: gpio6@ff7d0000 {
1357                         compatible = "rockchip,gpio-bank";
1358                         reg = <0xff7d0000 0x100>;
1359                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1360                         clocks = <&cru PCLK_GPIO6>;
1361
1362                         gpio-controller;
1363                         #gpio-cells = <2>;
1364
1365                         interrupt-controller;
1366                         #interrupt-cells = <2>;
1367                 };
1368
1369                 gpio7: gpio7@ff7e0000 {
1370                         compatible = "rockchip,gpio-bank";
1371                         reg = <0xff7e0000 0x100>;
1372                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1373                         clocks = <&cru PCLK_GPIO7>;
1374
1375                         gpio-controller;
1376                         #gpio-cells = <2>;
1377
1378                         interrupt-controller;
1379                         #interrupt-cells = <2>;
1380                 };
1381
1382                 gpio8: gpio8@ff7f0000 {
1383                         compatible = "rockchip,gpio-bank";
1384                         reg = <0xff7f0000 0x100>;
1385                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1386                         clocks = <&cru PCLK_GPIO8>;
1387
1388                         gpio-controller;
1389                         #gpio-cells = <2>;
1390
1391                         interrupt-controller;
1392                         #interrupt-cells = <2>;
1393                 };
1394
1395                 hdmi {
1396                         hdmi_ddc: hdmi-ddc {
1397                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1398                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1399                         };
1400                 };
1401
1402                 pcfg_pull_up: pcfg-pull-up {
1403                         bias-pull-up;
1404                 };
1405
1406                 pcfg_pull_down: pcfg-pull-down {
1407                         bias-pull-down;
1408                 };
1409
1410                 pcfg_pull_none: pcfg-pull-none {
1411                         bias-disable;
1412                 };
1413
1414                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1415                         bias-disable;
1416                         drive-strength = <12>;
1417                 };
1418
1419                 sleep {
1420                         global_pwroff: global-pwroff {
1421                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1422                         };
1423
1424                         ddrio_pwroff: ddrio-pwroff {
1425                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1426                         };
1427
1428                         ddr0_retention: ddr0-retention {
1429                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1430                         };
1431
1432                         ddr1_retention: ddr1-retention {
1433                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1434                         };
1435                 };
1436
1437                 edp {
1438                         edp_hpd: edp-hpd {
1439                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1440                         };
1441                 };
1442
1443                 i2c0 {
1444                         i2c0_xfer: i2c0-xfer {
1445                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1446                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1447                         };
1448                 };
1449
1450                 i2c1 {
1451                         i2c1_xfer: i2c1-xfer {
1452                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1453                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1454                         };
1455                 };
1456
1457                 i2c2 {
1458                         i2c2_xfer: i2c2-xfer {
1459                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1460                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1461                         };
1462                 };
1463
1464                 i2c3 {
1465                         i2c3_xfer: i2c3-xfer {
1466                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1467                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1468                         };
1469                 };
1470
1471                 i2c4 {
1472                         i2c4_xfer: i2c4-xfer {
1473                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1474                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1475                         };
1476                 };
1477
1478                 i2c5 {
1479                         i2c5_xfer: i2c5-xfer {
1480                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1481                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1482                         };
1483                 };
1484
1485                 i2s0 {
1486                         i2s0_bus: i2s0-bus {
1487                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1488                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1489                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1490                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1491                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1492                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1493                         };
1494                 };
1495
1496                 lcdc0 {
1497                         lcdc0_ctl: lcdc0-ctl {
1498                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1499                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1500                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1501                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1502                         };
1503                 };
1504
1505                 sdmmc {
1506                         sdmmc_clk: sdmmc-clk {
1507                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1508                         };
1509
1510                         sdmmc_cmd: sdmmc-cmd {
1511                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1512                         };
1513
1514                         sdmmc_cd: sdmcc-cd {
1515                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1516                         };
1517
1518                         sdmmc_bus1: sdmmc-bus1 {
1519                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1520                         };
1521
1522                         sdmmc_bus4: sdmmc-bus4 {
1523                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1524                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1525                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1526                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1527                         };
1528                 };
1529
1530                 sdio0 {
1531                         sdio0_bus1: sdio0-bus1 {
1532                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1533                         };
1534
1535                         sdio0_bus4: sdio0-bus4 {
1536                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1537                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1538                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1539                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1540                         };
1541
1542                         sdio0_cmd: sdio0-cmd {
1543                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1544                         };
1545
1546                         sdio0_clk: sdio0-clk {
1547                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1548                         };
1549
1550                         sdio0_cd: sdio0-cd {
1551                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1552                         };
1553
1554                         sdio0_wp: sdio0-wp {
1555                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1556                         };
1557
1558                         sdio0_pwr: sdio0-pwr {
1559                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1560                         };
1561
1562                         sdio0_bkpwr: sdio0-bkpwr {
1563                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1564                         };
1565
1566                         sdio0_int: sdio0-int {
1567                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1568                         };
1569                 };
1570
1571                 sdio1 {
1572                         sdio1_bus1: sdio1-bus1 {
1573                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1574                         };
1575
1576                         sdio1_bus4: sdio1-bus4 {
1577                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1578                                                 <3 25 4 &pcfg_pull_up>,
1579                                                 <3 26 4 &pcfg_pull_up>,
1580                                                 <3 27 4 &pcfg_pull_up>;
1581                         };
1582
1583                         sdio1_cd: sdio1-cd {
1584                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1585                         };
1586
1587                         sdio1_wp: sdio1-wp {
1588                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1589                         };
1590
1591                         sdio1_bkpwr: sdio1-bkpwr {
1592                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1593                         };
1594
1595                         sdio1_int: sdio1-int {
1596                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1597                         };
1598
1599                         sdio1_cmd: sdio1-cmd {
1600                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1601                         };
1602
1603                         sdio1_clk: sdio1-clk {
1604                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1605                         };
1606
1607                         sdio1_pwr: sdio1-pwr {
1608                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1609                         };
1610                 };
1611
1612                 emmc {
1613                         emmc_clk: emmc-clk {
1614                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1615                         };
1616
1617                         emmc_cmd: emmc-cmd {
1618                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1619                         };
1620
1621                         emmc_pwr: emmc-pwr {
1622                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1623                         };
1624
1625                         emmc_bus1: emmc-bus1 {
1626                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1627                         };
1628
1629                         emmc_bus4: emmc-bus4 {
1630                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1631                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1632                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1633                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1634                         };
1635
1636                         emmc_bus8: emmc-bus8 {
1637                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1638                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1639                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1640                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1641                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1642                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1643                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1644                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1645                         };
1646                 };
1647
1648                 spi0 {
1649                         spi0_clk: spi0-clk {
1650                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1651                         };
1652                         spi0_cs0: spi0-cs0 {
1653                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1654                         };
1655                         spi0_tx: spi0-tx {
1656                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1657                         };
1658                         spi0_rx: spi0-rx {
1659                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1660                         };
1661                         spi0_cs1: spi0-cs1 {
1662                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1663                         };
1664                 };
1665                 spi1 {
1666                         spi1_clk: spi1-clk {
1667                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1668                         };
1669                         spi1_cs0: spi1-cs0 {
1670                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1671                         };
1672                         spi1_rx: spi1-rx {
1673                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1674                         };
1675                         spi1_tx: spi1-tx {
1676                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1677                         };
1678                 };
1679
1680                 spi2 {
1681                         spi2_cs1: spi2-cs1 {
1682                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1683                         };
1684                         spi2_clk: spi2-clk {
1685                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1686                         };
1687                         spi2_cs0: spi2-cs0 {
1688                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1689                         };
1690                         spi2_rx: spi2-rx {
1691                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1692                         };
1693                         spi2_tx: spi2-tx {
1694                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1695                         };
1696                 };
1697
1698                 uart0 {
1699                         uart0_xfer: uart0-xfer {
1700                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1701                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1702                         };
1703
1704                         uart0_cts: uart0-cts {
1705                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1706                         };
1707
1708                         uart0_rts: uart0-rts {
1709                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1710                         };
1711                 };
1712
1713                 uart1 {
1714                         uart1_xfer: uart1-xfer {
1715                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1716                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1717                         };
1718
1719                         uart1_cts: uart1-cts {
1720                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1721                         };
1722
1723                         uart1_rts: uart1-rts {
1724                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1725                         };
1726                 };
1727
1728                 uart2 {
1729                         uart2_xfer: uart2-xfer {
1730                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1731                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1732                         };
1733                         /* no rts / cts for uart2 */
1734                 };
1735
1736                 uart3 {
1737                         uart3_xfer: uart3-xfer {
1738                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1739                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1740                         };
1741
1742                         uart3_cts: uart3-cts {
1743                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1744                         };
1745
1746                         uart3_rts: uart3-rts {
1747                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1748                         };
1749                 };
1750
1751                 uart4 {
1752                         uart4_xfer: uart4-xfer {
1753                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1754                                                 <5 13 3 &pcfg_pull_none>;
1755                         };
1756
1757                         uart4_cts: uart4-cts {
1758                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1759                         };
1760
1761                         uart4_rts: uart4-rts {
1762                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1763                         };
1764                 };
1765
1766                 tsadc {
1767                         otp_gpio: otp-gpio {
1768                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1769                         };
1770
1771                         otp_out: otp-out {
1772                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1773                         };
1774                 };
1775
1776                 pwm0 {
1777                         pwm0_pin: pwm0-pin {
1778                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1779                         };
1780                 };
1781
1782                 pwm1 {
1783                         pwm1_pin: pwm1-pin {
1784                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1785                         };
1786                 };
1787
1788                 pwm2 {
1789                         pwm2_pin: pwm2-pin {
1790                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1791                         };
1792                 };
1793
1794                 pwm3 {
1795                         pwm3_pin: pwm3-pin {
1796                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1797                         };
1798                 };
1799
1800                 gmac {
1801                         rgmii_pins: rgmii-pins {
1802                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1803                                                 <3 31 3 &pcfg_pull_none>,
1804                                                 <3 26 3 &pcfg_pull_none>,
1805                                                 <3 27 3 &pcfg_pull_none>,
1806                                                 <3 28 3 &pcfg_pull_none_12ma>,
1807                                                 <3 29 3 &pcfg_pull_none_12ma>,
1808                                                 <3 24 3 &pcfg_pull_none_12ma>,
1809                                                 <3 25 3 &pcfg_pull_none_12ma>,
1810                                                 <4 0 3 &pcfg_pull_none>,
1811                                                 <4 5 3 &pcfg_pull_none>,
1812                                                 <4 6 3 &pcfg_pull_none>,
1813                                                 <4 9 3 &pcfg_pull_none_12ma>,
1814                                                 <4 4 3 &pcfg_pull_none_12ma>,
1815                                                 <4 1 3 &pcfg_pull_none>,
1816                                                 <4 3 3 &pcfg_pull_none>;
1817                         };
1818
1819                         rmii_pins: rmii-pins {
1820                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1821                                                 <3 31 3 &pcfg_pull_none>,
1822                                                 <3 28 3 &pcfg_pull_none>,
1823                                                 <3 29 3 &pcfg_pull_none>,
1824                                                 <4 0 3 &pcfg_pull_none>,
1825                                                 <4 5 3 &pcfg_pull_none>,
1826                                                 <4 4 3 &pcfg_pull_none>,
1827                                                 <4 1 3 &pcfg_pull_none>,
1828                                                 <4 2 3 &pcfg_pull_none>,
1829                                                 <4 3 3 &pcfg_pull_none>;
1830                         };
1831                 };
1832
1833                 spdif {
1834                         spdif_tx: spdif-tx {
1835                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1836                         };
1837                 };
1838         };
1839 };