2 * Google Veyron (and derivatives) board device tree source
4 * Copyright 2015 Google, Inc
6 * This file is dual-licensed: you can use it either under the terms
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8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
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45 #include <dt-bindings/clock/rockchip,rk808.h>
46 #include <dt-bindings/input/input.h>
47 #include "rk3288.dtsi"
51 device_type = "memory";
52 reg = <0x0 0x80000000>;
55 gpio_keys: gpio-keys {
56 compatible = "gpio-keys";
60 pinctrl-names = "default";
61 pinctrl-0 = <&pwr_key_l>;
64 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
65 linux,code = <KEY_POWER>;
66 debounce-interval = <100>;
72 compatible = "gpio-restart";
73 gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
74 pinctrl-names = "default";
75 pinctrl-0 = <&ap_warm_reset_h>;
79 emmc_pwrseq: emmc-pwrseq {
80 compatible = "mmc-pwrseq-emmc";
81 pinctrl-0 = <&emmc_reset>;
82 pinctrl-names = "default";
83 reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
86 io_domains: io-domains {
87 compatible = "rockchip,rk3288-io-voltage-domain";
88 rockchip,grf = <&grf>;
90 bb-supply = <&vcc33_io>;
91 dvp-supply = <&vcc_18>;
92 flash0-supply = <&vcc18_flashio>;
93 gpio1830-supply = <&vcc33_io>;
94 gpio30-supply = <&vcc33_io>;
95 lcdc-supply = <&vcc33_lcd>;
96 wifi-supply = <&vcc18_wl>;
99 sdio_pwrseq: sdio-pwrseq {
100 compatible = "mmc-pwrseq-simple";
101 clocks = <&rk808 RK808_CLKOUT1>;
102 clock-names = "ext_clock";
103 pinctrl-names = "default";
104 pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>;
107 * On the module itself this is one of these (depending
108 * on the actual card populated):
109 * - SDIO_RESET_L_WL_REG_ON
110 * - PDN (power down when low)
112 reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
116 compatible = "regulator-fixed";
117 regulator-name = "vcc_5v";
120 regulator-min-microvolt = <5000000>;
121 regulator-max-microvolt = <5000000>;
124 vcc33_sys: vcc33-sys {
125 compatible = "regulator-fixed";
126 regulator-name = "vcc33_sys";
129 regulator-min-microvolt = <3300000>;
130 regulator-max-microvolt = <3300000>;
133 vcc50_hdmi: vcc50-hdmi {
134 compatible = "regulator-fixed";
135 regulator-name = "vcc50_hdmi";
138 vin-supply = <&vcc_5v>;
143 cpu0-supply = <&vdd_cpu>;
151 rockchip,default-sample-phase = <158>;
154 mmc-pwrseq = <&emmc_pwrseq>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
162 ddc-i2c-bus = <&i2c5>;
169 clock-frequency = <400000>;
170 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
171 i2c-scl-rising-time-ns = <100>; /* 45ns measured */
174 compatible = "rockchip,rk808";
176 clock-output-names = "xin32k", "wifibt_32kin";
177 interrupt-parent = <&gpio0>;
178 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
179 pinctrl-names = "default";
180 pinctrl-0 = <&pmic_int_l>;
181 rockchip,system-power-controller;
185 vcc1-supply = <&vcc33_sys>;
186 vcc2-supply = <&vcc33_sys>;
187 vcc3-supply = <&vcc33_sys>;
188 vcc4-supply = <&vcc33_sys>;
189 vcc6-supply = <&vcc_5v>;
190 vcc7-supply = <&vcc33_sys>;
191 vcc8-supply = <&vcc33_sys>;
192 vcc12-supply = <&vcc_18>;
193 vddio-supply = <&vcc33_io>;
197 regulator-name = "vdd_arm";
200 regulator-min-microvolt = <750000>;
201 regulator-max-microvolt = <1450000>;
202 regulator-ramp-delay = <6001>;
203 regulator-state-mem {
204 regulator-off-in-suspend;
209 regulator-name = "vdd_gpu";
212 regulator-min-microvolt = <800000>;
213 regulator-max-microvolt = <1250000>;
214 regulator-ramp-delay = <6001>;
215 regulator-state-mem {
216 regulator-on-in-suspend;
217 regulator-suspend-microvolt = <1000000>;
221 vcc135_ddr: DCDC_REG3 {
222 regulator-name = "vcc135_ddr";
225 regulator-state-mem {
226 regulator-on-in-suspend;
231 * vcc_18 has several aliases. (vcc18_flashio and
232 * vcc18_wl). We'll add those aliases here just to
233 * make it easier to follow the schematic. The signals
234 * are actually hooked together and only separated for
235 * power measurement purposes).
237 vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
238 regulator-name = "vcc_18";
241 regulator-min-microvolt = <1800000>;
242 regulator-max-microvolt = <1800000>;
243 regulator-state-mem {
244 regulator-on-in-suspend;
245 regulator-suspend-microvolt = <1800000>;
250 * Note that both vcc33_io and vcc33_pmuio are always
251 * powered together. To simplify the logic in the dts
252 * we just refer to vcc33_io every time something is
253 * powered from vcc33_pmuio. In fact, on later boards
254 * (such as danger) they're the same net.
257 regulator-name = "vcc33_io";
260 regulator-min-microvolt = <3300000>;
261 regulator-max-microvolt = <3300000>;
262 regulator-state-mem {
263 regulator-on-in-suspend;
264 regulator-suspend-microvolt = <3300000>;
269 regulator-name = "vdd_10";
272 regulator-min-microvolt = <1000000>;
273 regulator-max-microvolt = <1000000>;
274 regulator-state-mem {
275 regulator-on-in-suspend;
276 regulator-suspend-microvolt = <1000000>;
280 vdd10_lcd_pwren_h: LDO_REG7 {
281 regulator-name = "vdd10_lcd_pwren_h";
284 regulator-min-microvolt = <2500000>;
285 regulator-max-microvolt = <2500000>;
286 regulator-state-mem {
287 regulator-off-in-suspend;
291 vcc33_lcd: SWITCH_REG1 {
292 regulator-name = "vcc33_lcd";
295 regulator-state-mem {
296 regulator-off-in-suspend;
306 clock-frequency = <400000>;
307 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
308 i2c-scl-rising-time-ns = <100>; /* 40ns measured */
311 compatible = "infineon,slb9645tt";
313 powered-while-suspended;
320 /* 100kHz since 4.7k resistors don't rise fast enough */
321 clock-frequency = <100000>;
322 i2c-scl-falling-time-ns = <50>; /* 10ns measured */
323 i2c-scl-rising-time-ns = <800>; /* 600ns measured */
329 clock-frequency = <400000>;
330 i2c-scl-falling-time-ns = <50>; /* 11ns measured */
331 i2c-scl-rising-time-ns = <300>; /* 225ns measured */
337 clock-frequency = <100000>;
338 i2c-scl-falling-time-ns = <300>;
339 i2c-scl-rising-time-ns = <1000>;
352 keep-power-in-suspend;
353 mmc-pwrseq = <&sdio_pwrseq>;
356 pinctrl-names = "default";
357 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
362 vmmc-supply = <&vcc33_sys>;
363 vqmmc-supply = <&vcc18_wl>;
369 rx-sample-delay-ns = <12>;
375 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
376 rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
382 /* We need to go faster than 24MHz, so adjust clock parents / rates */
383 assigned-clocks = <&cru SCLK_UART0>;
384 assigned-clock-rates = <48000000>;
386 /* Pins don't include flow control by default; add that in */
387 pinctrl-names = "default";
388 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
406 needs-reset-on-resume;
416 assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
417 assigned-clock-parents = <&cru SCLK_OTGPHY0>;
434 pinctrl-names = "default", "sleep";
436 /* Common for sleep and wake, but no owners */
440 /* Common for sleep and wake, but no owners */
444 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
446 drive-strength = <8>;
449 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
451 drive-strength = <8>;
454 pcfg_output_high: pcfg-output-high {
458 pcfg_output_low: pcfg-output-low {
463 pwr_key_l: pwr-key-l {
464 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
469 emmc_reset: emmc-reset {
470 rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
474 * We run eMMC at max speed; bump up drive strength.
475 * We also have external pulls, so disable the internal ones.
478 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
482 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
485 emmc_bus8: emmc-bus8 {
486 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
487 <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
488 <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
489 <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
490 <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
491 <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
492 <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
493 <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
498 pmic_int_l: pmic-int-l {
499 rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
504 ap_warm_reset_h: ap-warm-reset-h {
505 rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
510 rec_mode_l: rec-mode-l {
511 rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
516 wifi_enable_h: wifienable-h {
517 rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
520 /* NOTE: mislabelled on schematic; should be bt_enable_h */
521 bt_enable_l: bt-enable-l {
522 rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
526 * We run sdio0 at max speed; bump up drive strength.
527 * We also have external pulls, so disable the internal ones.
529 sdio0_bus4: sdio0-bus4 {
530 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
531 <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
532 <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
533 <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
536 sdio0_cmd: sdio0-cmd {
537 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
540 sdio0_clk: sdio0-clk {
541 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
546 tpm_int_h: tpm-int-h {
547 rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
553 rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;