arch/arm/boot/dts/rk3228.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/rkfb/rk_fb.h>
   3
   4 #include "skeleton.dtsi"
   5 #include "rk3228-clocks.dtsi"
   6
   7 / {
   8         compatible = "rockchip,rk3228";
   9         interrupt-parent = <&gic>;
  10
  11         aliases {
  12                 serial2 = &uart_dbg;
  13         };
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a7";
  22                         reg = <0xf00>;
  23                 };
  24                 cpu@1 {
  25                         device_type = "cpu";
  26                         compatible = "arm,cortex-a7";
  27                         reg = <0xf01>;
  28                 };
  29                 cpu@2 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a7";
  32                         reg = <0xf02>;
  33                 };
  34                 cpu@3 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a7";
  37                         reg = <0xf03>;
  38                 };
  39         };
  40
  41         gic: interrupt-controller@32010000 {
  42                 compatible = "arm,cortex-a15-gic";
  43                 interrupt-controller;
  44                 #interrupt-cells = <3>;
  45                 #address-cells = <0>;
  46                 reg = <0x32011000 0x1000>,
  47                       <0x32012000 0x1000>;
  48         };
  49
  50         arm-pmu {
  51                 compatible = "arm,cortex-a7-pmu";
  52                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  53                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
  54                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
  55                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  56         };
  57
  58         reset: reset@110e0110{
  59                 compatible = "rockchip,reset";
  60                 reg = <0x110e0110 0x20>;
  61                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
  62                 #reset-cells = <1>;
  63         };
  64
  65         timer {
  66                 compatible = "arm,armv7-timer";
  67                 interrupts = <GIC_PPI 13
  68                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  69                              <GIC_PPI 14
  70                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  71                 clock-frequency = <24000000>;
  72         };
  73
  74         uart_dbg: serial@11030000 {
  75                 compatible = "rockchip,serial";
  76                 reg = <0x11030000 0x100>;
  77                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  78                 clock-frequency = <24000000>;
  79                 clocks = <&xin24m>, <&xin24m>;
  80                 clock-names = "sclk_uart", "pclk_uart";
  81                 reg-shift = <2>;
  82                 reg-io-width = <4>;
  83                 status = "disabled";
  84         };
  85
  86         fiq-debugger {
  87                 compatible = "rockchip,fiq-debugger";
  88                 rockchip,serial-id = <2>;
  89                 rockchip,signal-irq = <159>;
  90                 rockchip,wake-irq = <0>;
  91                 rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
  92                 rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
  93                 status = "disabled";
  94         };
  95
  96         rockchip_clocks_init: clocks-init{
  97                 compatible = "rockchip,clocks-init";
  98                 rockchip,clocks-init-parent =
  99                         <&clk_i2s0_pll &clk_cpll>, <&clk_i2s1_pll &clk_cpll>,
 100                         <&clk_i2s2_pll &clk_cpll>, <&clk_spdif_pll &clk_cpll>,
 101                         <&clk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
 102                         <&aclk_bus &clk_cpll>, <&aclk_peri &clk_cpll>,
 103                         <&clk_sdmmc0 &clk_cpll>, <&clk_emmc &clk_cpll>,
 104                         <&clk_sdio &clk_cpll>, <&aclk_vpu &clk_cpll>,
 105                         <&hdmi_phy_clk &hdmiphy_out>, <&usb480m &usb480m_phy>;
 106                 rockchip,clocks-init-rate =
 107                         <&clk_gpll 600000000>, <&clk_core 700000000>,
 108                         <&clk_cpll 500000000>, <&aclk_bus 250000000>,
 109                         <&hclk_bus 125000000>, <&pclk_bus 62500000>,
 110                         <&aclk_peri 250000000>, <&hclk_peri 125000000>,
 111                         <&pclk_peri 62500000>, <&clk_mac 125000000>,
 112                         <&aclk_iep 250000000>, <&hclk_vio 125000000>,
 113                         <&aclk_rga 250000000>, <&clk_gpu 250000000>,
 114                         <&aclk_vpu 25000000>, <&clk_vdec_core 250000000>,
 115                         <&clk_vdec_cabac 250000000>;
 116 /*
 117                 rockchip,clocks-uboot-has-init =
 118                         <&aclk_vio0>;
 119 */
 120         };
 121
 122         rockchip_clocks_enable: clocks-enable {
 123                 compatible = "rockchip,clocks-enable";
 124                 clocks =
 125                         /*PLL*/
 126                         <&clk_apll>,
 127                         <&clk_dpll>,
 128                         <&clk_gpll>,
 129                         <&clk_cpll>,
 130
 131                         /*PD_CORE*/
 132                         <&clk_core>,
 133                         <&pclk_dbg>,
 134                         <&aclk_core>,
 135                         <&clk_gates4 2>,
 136
 137                         /*PD_BUS*/
 138                         <&aclk_bus>,
 139                         <&hclk_bus>,
 140                         <&pclk_bus>,
 141                         <&clk_gates8 0>,/*aclk_intmem*/
 142                         <&clk_gates8 1>,/*clk_intmem_mbist*/
 143                         <&clk_gates8 2>,/*aclk_dmac_bus*/
 144                         <&clk_gates10 1>,/*g_aclk_bus*/
 145                         <&clk_gates13 9>,/*aclk_gic400*/
 146                         <&clk_gates8 3>,/*hclk_rom*/
 147                         <&clk_gates8 4>,/*pclk_ddrupctl*/
 148                         <&clk_gates8 6>,/*pclk_ddrmon*/
 149                         <&clk_gates9 4>,/*pclk_timer0*/
 150                         <&clk_gates9 5>,/*pclk_stimer*/
 151                         <&clk_gates10 0>,/*pclk_grf*/
 152                         <&clk_gates10 4>,/*pclk_cru*/
 153                         <&clk_gates10 6>,/*pclk_sgrf*/
 154                         <&clk_gates10 3>,/*pclk_ddrphy*/
 155                         <&clk_gates10 9>,/*pclk_phy_noc*/
 156
 157                         /*PD_PERI*/
 158                         <&aclk_peri>,
 159                         <&hclk_peri>,
 160                         <&pclk_peri>,
 161                         <&clk_gates12 0>,/*aclk_peri_noc*/
 162                         <&clk_gates12 1>,/*hclk_peri_noc*/
 163                         <&clk_gates12 2>,/*pclk_peri_noc*/
 164
 165                         <&clk_gates6 5>, /* g_clk_timer0 */
 166                         <&clk_gates6 6>, /* g_clk_timer1 */
 167
 168                         <&clk_gates7 14>, /* g_aclk_gpu */
 169                         <&clk_gates7 15>, /* g_aclk_gpu_noc */
 170
 171                         <&clk_gates1 3>;/*clk_jtag*/
 172         };
 173
 174         amba {
 175                 #address-cells = <1>;
 176                 #size-cells = <1>;
 177                 compatible = "arm,amba-bus";
 178                 interrupt-parent = <&gic>;
 179                 ranges;
 180
 181                 pdma: pdma@110f0000 {
 182                         compatible = "arm,pl330", "arm,primecell";
 183                         reg = <0x110f0000 0x4000>;
 184                         clocks = <&clk_gates8 2>;
 185                         clock-names = "apb_pclk";
 186                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 187                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 188                         #dma-cells = <1>;
 189                 };
 190         };
 191
 192         i2s0: i2s0@100c0000 {
 193                 compatible = "rockchip-i2s";
 194                 reg = <0x100c0000 0x1000>;
 195                 i2s-id = <0>;
 196                 clocks = <&clk_i2s0>, <&clk_gates8 7>;
 197                 clock-names = "i2s_clk", "i2s_hclk";
 198                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 199                 dmas = <&pdma 11>, <&pdma 12>;
 200                 #dma-cells = <2>;
 201                 dma-names = "tx", "rx";
 202         };
 203
 204         i2s1: i2s1@100b0000 {
 205                 compatible = "rockchip-i2s";
 206                 reg = <0x100b0000 0x1000>;
 207                 i2s-id = <1>;
 208                 clocks = <&clk_i2s1>, <&clk_i2s1_out>, <&clk_gates8 8>;
 209                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 210                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 211                 dmas = <&pdma 14>, <&pdma 15>;
 212                 #dma-cells = <2>;
 213                 dma-names = "tx", "rx";
 214                 status = "disabled";
 215         };
 216
 217         i2s2: i2s2@100e0000 {
 218                 compatible = "rockchip-i2s";
 219                 reg = <0x100e0000 0x1000>;
 220                 i2s-id = <2>;
 221                 clocks = <&clk_i2s2>, <&clk_gates8 9>;
 222                 clock-names = "i2s_clk", "i2s_hclk";
 223                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 224                 dmas = <&pdma 0>, <&pdma 1>;
 225                 #dma-cells = <2>;
 226                 dma-names = "tx", "rx";
 227                 status = "disabled";
 228         };
 229
 230         spdif: spdif@100d0000 {
 231                 compatible = "rockchip-spdif";
 232                 reg = <0x100d0000 0x1000>;
 233                 clocks = <&clk_spdif>, <&clk_gates8 10>;
 234                 clock-names = "spdif_mclk", "spdif_hclk";
 235                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 236                 dmas = <&pdma 10>;
 237                 #dma-cells = <1>;
 238                 dma-names = "tx";
 239                 status = "disabled";
 240         };
 241
 242         gpu {
 243                 compatible = "arm,mali400";
 244                 reg = <0x20001000 0x200>,
 245                       <0x20000000 0x100>,
 246                       <0x20003000 0x100>,
 247                       <0x20008000 0x1100>,
 248                       <0x20004000 0x100>,
 249                       <0x2000A000 0x1100>,
 250                       <0x20005000 0x100>;
 251
 252                 reg-names = "Mali_L2",
 253                             "Mali_GP",
 254                             "Mali_GP_MMU",
 255                             "Mali_PP0",
 256                             "Mali_PP0_MMU",
 257                             "Mali_PP1",
 258                             "Mali_PP1_MMU";
 259
 260                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 261                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 263                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 264                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 265                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 266
 267                 interrupt-names = "Mali_GP_IRQ",
 268                                   "Mali_GP_MMU_IRQ",
 269                                   "Mali_PP0_IRQ",
 270                                   "Mali_PP0_MMU_IRQ",
 271                                   "Mali_PP1_IRQ",
 272                                   "Mali_PP1_MMU_IRQ";
 273         };
 274
 275         fb: fb {
 276                 compatible = "rockchip,rk-fb";
 277                 rockchip,disp-mode = <NO_DUAL>;
 278         };
 279
 280         rk_screen: rk_screen {
 281                 compatible = "rockchip,screen";
 282         };
 283
 284         vop: vop@20050000 {
 285                 compatible = "rockchip,rk3228-lcdc";
 286
 287                 rockchip,cabc_mode = <0>;
 288                 rockchip,pwr18 = <0>;
 289                 rockchip,iommu-enabled = <1>;
 290                 reg = <0x20050000 0x300>;
 291                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 292                 clocks = <&aclk_vop>, <&dclk_vop0>, <&hclk_vio>;
 293                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 294         };
 295
 296         vop_mmu {
 297                 dbgname = "vop";
 298                 compatible = "rockchip,vop_mmu";
 299                 reg = <0x20053f00 0x100>;
 300                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 301                 interrupt-names = "vop_mmu";
 302         };
 303
 304         hevc_mmu {
 305                 dbgname = "hevc";
 306                 compatible = "rockchip,hevc_mmu";
 307                 reg = <0x20034440 0x40>,
 308                       <0x20034480 0x40>;
 309                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 310                 interrupt-names = "hevc_mmu";
 311         };
 312
 313         vpu_mmu {
 314                 dbgname = "vpu";
 315                 compatible = "rockchip,vpu_mmu";
 316                 reg = <0x20026800 0x100>;
 317                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 318                 interrupt-names = "vpu_mmu";
 319         };
 320
 321         iep_mmu {
 322                 dbgname = "iep";
 323                 compatible = "rockchip,iep_mmu";
 324                 reg = <0x20078800 0x100>;
 325                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 326                 interrupt-names = "iep_mmu";
 327         };
 328
 329         hdmi: hdmi@200a0000 {
 330                 compatible = "rockchip,rk3228-hdmi";
 331                 reg = <0x200a0000 0x20000>,
 332                       <0x12030000 0x10000>;
 333                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 334                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 335                 clocks = <&clk_gates14 6>, <&clk_gates3 7>, <&clk_hdmi_cec>;
 336                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 337                 rockchip,hdmi_audio_source = <0>;
 338                 rockchip,hdcp_enable = <0>;
 339                 rockchip,cec_enable = <0>;
 340                 status = "disabled";
 341         };
 342
 343         hdmi_hdcp2: hdmi_hdcp2@20090000 {
 344                 compatible = "rockchip,rk3228-hdmi-hdcp2";
 345                 reg = <0x20090000 0x10000>;
 346                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 347                 clocks = <&aclk_hdcp>,
 348                          <&clk_gates14 12>,
 349                          <&clk_gates14 11>,
 350                          <&clk_hdcp>;
 351                 clock-names = "aclk_hdcp2",
 352                               "hclk_hdcp2_mmu",
 353                               "pclk_hdcp2",
 354                               "hdcp2_clk_hdmi";
 355                 status = "disabled";
 356         };
 357
 358         tve: tve {
 359                 compatible = "rockchip,rk3228-tve";
 360                 reg = <0x20053e00 0x100>,
 361                       <0x12020000 0x10000>;
 362                 clocks = <&clk_gates10 8>;
 363                 clock-names = "pclk_vdac";
 364                 status = "disabled";
 365         };
 366
 367         emmc: rksdmmc@30020000 {
 368                 compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
 369                 reg = <0x30020000 0x10000>;
 370                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 371                 #address-cells = <1>;
 372                 #size-cells = <0>;
 373                 clocks = <&clk_emmc>, <&clk_gates7 0>;
 374                 clock-names = "clk_mmc", "hclk_mmc";
 375                 num-slots = <1>;
 376                 fifo-depth = <0x100>;
 377                 bus-width = <8>;
 378                 cru_regsbase = <0x124>;
 379                 cru_reset_offset = <3>;
 380         };
 381
 382         sdmmc: rksdmmc@30000000 {
 383                 compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
 384                 reg = <0x30000000 0x10000>;
 385                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 386                 #address-cells = <1>;
 387                 #size-cells = <0>;
 388                 clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
 389                 clock-names = "clk_mmc", "hclk_mmc";
 390                 num-slots = <1>;
 391                 fifo-depth = <0x100>;
 392                 bus-width = <4>;
 393                 cru_regsbase = <0x124>;
 394                 cru_reset_offset = <1>;
 395         };
 396
 397         sdio: rksdmmc@30010000 {
 398                 compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
 399                 reg = <0x30010000 0x10000>;
 400                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 401                 #address-cells = <1>;
 402                 #size-cells = <0>;
 403                 clocks = <&clk_sdio>, <&clk_gates5 11>;
 404                 clock-names = "clk_mmc", "hclk_mmc";
 405                 num-slots = <1>;
 406                 fifo-depth = <0x100>;
 407                 bus-width = <4>;
 408                 cru_regsbase = <0x124>;
 409                 cru_reset_offset = <2>;
 410         };
 411  };