arch/arm/boot/dts/rk3188.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/gpio/gpio.h>
   3 #include <dt-bindings/pinctrl/rockchip.h>
   4
   5 #include "skeleton.dtsi"
   6
   7 / {
   8         compatible = "rockchip,rk3188";
   9         interrupt-parent = <&gic>;
  10
  11         cpus {
  12                 #address-cells = <1>;
  13                 #size-cells = <0>;
  14
  15                 cpu@0 {
  16                         device_type = "cpu";
  17                         compatible = "arm,cortex-a9";
  18                         reg = <0>;
  19                 };
  20                 cpu@1 {
  21                         device_type = "cpu";
  22                         compatible = "arm,cortex-a9";
  23                         reg = <1>;
  24                 };
  25                 cpu@2 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a9";
  28                         reg = <2>;
  29                 };
  30                 cpu@3 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a9";
  33                         reg = <3>;
  34                 };
  35         };
  36
  37         twd-wdt@1013c620 {
  38                 compatible = "arm,cortex-a9-twd-wdt";
  39                 reg = <0x1013c620 0x20>;
  40                 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  41         };
  42
  43         gic: interrupt-controller@1013d000 {
  44                 compatible = "arm,cortex-a9-gic";
  45                 interrupt-controller;
  46                 #interrupt-cells = <3>;
  47                 reg = <0x1013d000 0x1000>,
  48                       <0x1013c100 0x0100>;
  49         };
  50
  51         L2: cache-controller@10138000 {
  52                 compatible = "arm,pl310-cache";
  53                 reg = <0x10138000 0x1000>;
  54                 cache-unified;
  55                 cache-level = <2>;
  56                 arm,tag-latency = <1 1 1>;
  57                 arm,data-latency = <2 3 1>;
  58                 prefetch-ctrl = <0x70000003>;
  59                 /* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
  60                 power-ctrl = <0x3>;
  61 /*
  62                 (0x1 << 0) |    // Full line of write zero behavior Enabled
  63                 (0x1 << 25) |   // Round-robin replacement
  64                 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
  65                 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
  66                 (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
  67 */
  68                 aux-ctrl = <0x72000001 (~0x72000001)>;
  69         };
  70
  71         cpu_axi_bus: cpu_axi_bus@10128000 {
  72                 compatible = "rockchip,cpu_axi_bus";
  73                 reg = <0x10128000 0x8000>;
  74                 qos {
  75                         dmac {
  76                                 offset = <0x1000>;
  77                                 priority = <0 0>;
  78                         };
  79                         cpu0 {
  80                                 offset = <0x2000>;
  81                                 priority = <0 0>;
  82                         };
  83                         cpu1r {
  84                                 offset = <0x2080>;
  85                                 priority = <0 0>;
  86                         };
  87                         cpu1w {
  88                                 offset = <0x2100>;
  89                                 priority = <0 0>;
  90                         };
  91                         peri {
  92                                 offset = <0x4000>;
  93                                 priority = <2 2>;
  94                         };
  95                         gpu {
  96                                 offset = <0x5000>;
  97                                 priority = <2 1>;
  98                         };
  99                         vpu {
 100                                 offset = <0x6000>;
 101                         };
 102                         vop0 {
 103                                 offset = <0x7000>;
 104                                 priority = <3 3>;
 105                         };
 106                         cif0 {
 107                                 offset = <0x7080>;
 108                         };
 109                         ipp {
 110                                 offset = <0x7100>;
 111                         };
 112                         vop1 {
 113                                 offset = <0x7180>;
 114                                 priority = <3 3>;
 115                         };
 116                         cif1 {
 117                                 offset = <0x7200>;
 118                         };
 119                         rga {
 120                                 offset = <0x7280>;
 121                         };
 122                 };
 123         };
 124
 125         bootrom@10120000 {
 126                 compatible = "rockchip,bootrom";
 127                 reg = <0x10120000 0x4000>;
 128         };
 129
 130         bootram@10080000 {
 131                 compatible = "rockchip,bootram";
 132                 reg = <0x10080000 0x20>; /* 32 bytes */
 133         };
 134
 135         sram@10080020 {
 136                 compatible = "mmio-sram";
 137                 reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
 138                 map-exec;
 139         };
 140
 141         pmu@20004000 {
 142                 compatible = "rockchip,pmu";
 143                 reg = <0x20004000 0x4000>;
 144         };
 145
 146         timer@200380a0 {
 147                 compatible = "rockchip,timer";
 148                 reg = <0x200380a0 0x20>;
 149                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 150         };
 151
 152         timer@20038000 {
 153                 compatible = "rockchip,timer";
 154                 reg = <0x20038000 0x20>;
 155                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 156         };
 157
 158         timer@20038020 {
 159                 compatible = "rockchip,timer";
 160                 reg = <0x20038020 0x20>;
 161                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 162         };
 163
 164         timer@20038060 {
 165                 compatible = "rockchip,timer";
 166                 reg = <0x20038060 0x20>;
 167                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 168         };
 169
 170         timer@20038080 {
 171                 compatible = "rockchip,timer";
 172                 reg = <0x20038080 0x20>;
 173                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 174         };
 175
 176         pinctrl@20008000 {
 177                         compatible = "rockchip,rk3188-pinctrl";
 178                         reg = <0x20008000 0xa0>,
 179                               <0x20008164 0x1a0>;
 180                         reg-names = "base", "pull";
 181                         #address-cells = <1>;
 182                         #size-cells = <1>;
 183                         ranges;
 184
 185                         gpio0: gpio0@0x2000a000 {
 186                                 compatible = "rockchip,rk3188-gpio-bank0";
 187                                 reg = <0x2000a000 0x100>,
 188                                       <0x20004064 0x8>;
 189                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 190                                 /*clocks = <&clk_gates8 9>;*/
 191
 192                                 gpio-controller;
 193                                 #gpio-cells = <2>;
 194
 195                                 interrupt-controller;
 196                                 #interrupt-cells = <2>;
 197                         };
 198
 199                         gpio1: gpio1@0x2003c000 {
 200                                 compatible = "rockchip,gpio-bank";
 201                                 reg = <0x2003c000 0x100>;
 202                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 203                                 /*clocks = <&clk_gates8 10>;*/
 204
 205                                 gpio-controller;
 206                                 #gpio-cells = <2>;
 207
 208                                 interrupt-controller;
 209                                 #interrupt-cells = <2>;
 210                         };
 211
 212                         gpio2: gpio2@2003e000 {
 213                                 compatible = "rockchip,gpio-bank";
 214                                 reg = <0x2003e000 0x100>;
 215                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 216                                 /*clocks = <&clk_gates8 11>;*/
 217
 218                                 gpio-controller;
 219                                 #gpio-cells = <2>;
 220
 221                                 interrupt-controller;
 222                                 #interrupt-cells = <2>;
 223                         };
 224
 225                         gpio3: gpio3@20080000 {
 226                                 compatible = "rockchip,gpio-bank";
 227                                 reg = <0x20080000 0x100>;
 228                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 229                                 /*clocks = <&clk_gates8 12>;*/
 230
 231                                 gpio-controller;
 232                                 #gpio-cells = <2>;
 233
 234                                 interrupt-controller;
 235                                 #interrupt-cells = <2>;
 236                         };
 237
 238                         pcfg_pull_up: pcfg_pull_up {
 239                                 bias-pull-up;
 240                         };
 241
 242                         pcfg_pull_down: pcfg_pull_down {
 243                                 bias-pull-down;
 244                         };
 245
 246                         pcfg_pull_none: pcfg_pull_none {
 247                                 bias-disable;
 248                         };
 249
 250                         uart0 {
 251                                 uart0_xfer: uart0-xfer {
 252                                         rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_none>,
 253                                                         <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
 254                                 };
 255
 256                                 uart0_cts: uart0-cts {
 257                                         rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
 258                                 };
 259
 260                                 uart0_rts: uart0-rts {
 261                                         rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
 262                                 };
 263                         };
 264
 265                         uart1 {
 266                                 uart1_xfer: uart1-xfer {
 267                                         rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_none>,
 268                                                         <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
 269                                 };
 270
 271                                 uart1_cts: uart1-cts {
 272                                         rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
 273                                 };
 274
 275                                 uart1_rts: uart1-rts {
 276                                         rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
 277                                 };
 278                         };
 279
 280                         uart2 {
 281                                 uart2_xfer: uart2-xfer {
 282                                         rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_none>,
 283                                                         <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
 284                                 };
 285                                 /* no rts / cts for uart2 */
 286                         };
 287
 288                         uart3 {
 289                                 uart3_xfer: uart3-xfer {
 290                                         rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_none>,
 291                                                         <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
 292                                 };
 293
 294                                 uart3_cts: uart3-cts {
 295                                         rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
 296                                 };
 297
 298                                 uart3_rts: uart3-rts {
 299                                         rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
 300                                 };
 301                         };
 302
 303                         sd0 {
 304                                 sd0_clk: sd0-clk {
 305                                         rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
 306                                 };
 307
 308                                 sd0_cmd: sd0-cmd {
 309                                         rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
 310                                 };
 311
 312                                 sd0_cd: sd0-cd {
 313                                         rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
 314                                 };
 315
 316                                 sd0_wp: sd0-wp {
 317                                         rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
 318                                 };
 319
 320                                 sd0_pwr: sd0-pwr {
 321                                         rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
 322                                 };
 323
 324                                 sd0_bus1: sd0-bus-width1 {
 325                                         rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
 326                                 };
 327
 328                                 sd0_bus4: sd0-bus-width4 {
 329                                         rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
 330                                                         <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
 331                                                         <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
 332                                                         <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
 333                                 };
 334                         };
 335
 336                         sd1 {
 337                                 sd1_clk: sd1-clk {
 338                                         rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
 339                                 };
 340
 341                                 sd1_cmd: sd1-cmd {
 342                                         rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
 343                                 };
 344
 345                                 sd1_cd: sd1-cd {
 346                                         rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
 347                                 };
 348
 349                                 sd1_wp: sd1-wp {
 350                                         rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
 351                                 };
 352
 353                                 sd1_bus1: sd1-bus-width1 {
 354                                         rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
 355                                 };
 356
 357                                 sd1_bus4: sd1-bus-width4 {
 358                                         rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
 359                                                         <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
 360                                                         <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
 361                                                         <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
 362                                 };
 363                         };
 364                 };
 365
 366
 367         uart0: serial@10124000 {
 368                 compatible = "rockchip,serial";
 369                 reg = <0x10124000 0x100>;
 370                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 371                 clock-frequency = <24000000>;
 372                 reg-shift = <2>;
 373                 reg-io-width = <4>;
 374                 id = <0>;
 375                 status = "disabled";
 376         };
 377
 378         uart1: serial@10126000 {
 379                 compatible = "rockchip,serial";
 380                 reg = <0x10126000 0x100>;
 381                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 382                 clock-frequency = <24000000>;
 383                 reg-shift = <2>;
 384                 reg-io-width = <4>;
 385                 id = <1>;
 386                 status = "disabled";
 387         };
 388
 389         uart2: serial@20064000 {
 390                 compatible = "rockchip,serial";
 391                 reg = <0x20064000 0x100>;
 392                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 393                 clock-frequency = <24000000>;
 394                 current-speed = <115200>;
 395                 reg-shift = <2>;
 396                 reg-io-width = <4>;
 397                 id = <2>;
 398                 status = "disabled";
 399         };
 400
 401         uart3: serial@20068000 {
 402                 compatible = "rockchip,serial";
 403                 reg = <0x20068000 0x100>;
 404                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 405                 clock-frequency = <24000000>;
 406                 reg-shift = <2>;
 407                 reg-io-width = <4>;
 408                 id = <3>;
 409                 status = "disabled";
 410         };
 411 };