arch/arm/boot/dts/rk3188.dtsi

   1 #include <dt-bindings/clock/ddr.h>
   2 #include <dt-bindings/rkfb/rk_fb.h>
   3 #include <dt-bindings/suspend/rockchip-pm.h>
   4 #include <dt-bindings/sensor-dev.h>
   5
   6 #include "skeleton.dtsi"
   7 #include "rk3188-pinctrl.dtsi"
   8 #include "rk3188-clocks.dtsi"
   9
  10 / {
  11         compatible = "rockchip,rk3188";
  12         interrupt-parent = <&gic>;
  13         rockchip,sram = <&sram>;
  14
  15         aliases {
  16                 serial0 = &uart0;
  17                 serial1 = &uart1;
  18                 serial2 = &uart2;
  19                 serial3 = &uart3;
  20                 i2c0 = &i2c0;
  21                 i2c1 = &i2c1;
  22                 i2c2 = &i2c2;
  23                 i2c3 = &i2c3;
  24                 i2c4 = &i2c4;
  25                 lcdc0 = &lcdc0;
  26                 lcdc1 = &lcdc1;
  27                 spi0 = &spi0;
  28                 spi1 = &spi1;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 cpu@0 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a9";
  38                         reg = <0>;
  39                 };
  40                 cpu@1 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a9";
  43                         reg = <1>;
  44                 };
  45                 cpu@2 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a9";
  48                         reg = <2>;
  49                 };
  50                 cpu@3 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a9";
  53                         reg = <3>;
  54                 };
  55         };
  56
  57         twd-wdt@1013c620 {
  58                 compatible = "arm,cortex-a9-twd-wdt";
  59                 reg = <0x1013c620 0x20>;
  60                 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  61         };
  62
  63         gic: interrupt-controller@1013d000 {
  64                 compatible = "arm,cortex-a9-gic";
  65                 interrupt-controller;
  66                 #interrupt-cells = <3>;
  67                 reg = <0x1013d000 0x1000>,
  68                       <0x1013c100 0x0100>;
  69         };
  70
  71         L2: cache-controller@10138000 {
  72                 compatible = "rockchip,pl310-cache", "arm,pl310-cache";
  73                 reg = <0x10138000 0x1000>;
  74                 cache-unified;
  75                 cache-level = <2>;
  76                 arm,tag-latency = <1 1 1>;
  77                 arm,data-latency = <3 1 2>;
  78                 rockchip,prefetch-ctrl = <0x70000003>;
  79                 /* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
  80                 rockchip,power-ctrl = <0x3>;
  81 /*
  82                 (0x1 << 0) |    // Full line of write zero behavior Enabled
  83                 (0x1 << 25) |   // Round-robin replacement
  84                 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
  85                 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
  86                 (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
  87 */
  88                 rockchip,aux-ctrl = <0x72000001 (~0x72000001)>;
  89         };
  90
  91         cpu_axi_bus: cpu_axi_bus {
  92                 compatible = "rockchip,cpu_axi_bus";
  93                 #address-cells = <1>;
  94                 #size-cells = <1>;
  95                 ranges;
  96                 qos {
  97                         #address-cells = <1>;
  98                         #size-cells = <1>;
  99                         ranges;
 100                         dmac {
 101                                 reg = <0x10129000 0x20>;
 102                                 rockchip,priority = <0 0>;
 103                         };
 104                         cpu0 {
 105                                 reg = <0x1012a000 0x20>;
 106                                 rockchip,priority = <0 0>;
 107                         };
 108                         cpu1_r {
 109                                 reg = <0x1012a080 0x20>;
 110                                 rockchip,priority = <0 0>;
 111                         };
 112                         cpu1_w {
 113                                 reg = <0x1012a100 0x20>;
 114                                 rockchip,priority = <0 0>;
 115                         };
 116                         peri {
 117                                 reg = <0x1012c000 0x20>;
 118                                 rockchip,priority = <2 2>;
 119                         };
 120                         gpu {
 121                                 reg = <0x1012d000 0x20>;
 122                                 rockchip,priority = <2 1>;
 123                         };
 124                         vpu {
 125                                 reg = <0x1012e000 0x20>;
 126                         };
 127                         vop0 {
 128                                 reg = <0x1012f000 0x20>;
 129                                 rockchip,priority = <3 3>;
 130                         };
 131                         cif0 {
 132                                 reg = <0x1012f080 0x20>;
 133                         };
 134                         ipp {
 135                                 reg = <0x1012f100 0x20>;
 136                         };
 137                         vop1 {
 138                                 reg = <0x1012f180 0x20>;
 139                                 rockchip,priority = <3 3>;
 140                         };
 141                         cif1 {
 142                                 reg = <0x1012f200 0x20>;
 143                         };
 144                         rga {
 145                                 reg = <0x1012f280 0x20>;
 146                         };
 147                 };
 148                 msch {
 149                         #address-cells = <1>;
 150                         #size-cells = <1>;
 151                         ranges;
 152                         msch {
 153                                 reg = <0x10128000 0x18>;
 154                                 rockchip,read-latency = <0x3f>;
 155                         };
 156                 };
 157         };
 158
 159         bootrom@10120000 {
 160                 compatible = "rockchip,bootrom";
 161                 reg = <0x10120000 0x4000>;
 162         };
 163
 164         bootram@10080000 {
 165                 compatible = "rockchip,bootram";
 166                 reg = <0x10080000 0x20>; /* 32 bytes */
 167         };
 168
 169         sram: sram@10080020 {
 170                 compatible = "mmio-sram";
 171                 reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
 172                 map-exec;
 173         };
 174
 175         pmu@20004000 {
 176                 compatible = "rockchip,pmu";
 177                 reg = <0x20004000 0x4000>;
 178         };
 179
 180         timer@20038000 {
 181                 compatible = "rockchip,timer";
 182                 reg = <0x20038000 0x20>;
 183                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 184                 rockchip,percpu = <0>;
 185         };
 186
 187         timer@20038020 {
 188                 compatible = "rockchip,timer";
 189                 reg = <0x20038020 0x20>;
 190                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 191                 rockchip,percpu = <1>;
 192         };
 193
 194         timer@20038040 {
 195                 compatible = "rockchip,timer";
 196                 reg = <0x20038040 0x20>;
 197                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 198                 rockchip,percpu = <2>;
 199         };
 200
 201         timer@20038060 {
 202                 compatible = "rockchip,timer";
 203                 reg = <0x20038060 0x20>;
 204                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 205                 rockchip,percpu = <3>;
 206         };
 207
 208         timer@20038080 {
 209                 compatible = "rockchip,timer";
 210                 reg = <0x20038080 0x20>;
 211                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 212                 rockchip,broadcast = <1>;
 213         };
 214
 215         timer@200380a0 {
 216                 compatible = "rockchip,timer";
 217                 reg = <0x200380a0 0x20>;
 218                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 219                 rockchip,clocksource = <1>;
 220         };
 221
 222         watchdog:wdt@2004c000 {
 223                 compatible = "rockchip,watch dog";
 224                 reg = <0x2004c000 0x100>;
 225                 clocks = <&clk_gates7 15>;
 226                 clock-names = "pclk_wdt";
 227                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 228                 rockchip,irq = <1>;
 229                 rockchip,timeout = <5>;
 230                 rockchip,atboot = <1>;
 231                 rockchip,debug = <0>;
 232                 status = "disabled";
 233         };
 234
 235         amba {
 236                 #address-cells = <1>;
 237                 #size-cells = <1>;
 238                 compatible = "arm,amba-bus";
 239                 interrupt-parent = <&gic>;
 240                 ranges;
 241
 242                 pdma0: pdma@20018000 {
 243                         compatible = "arm,pl330", "arm,primecell";
 244                         reg = <0x20018000 0x4000>;
 245                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 246                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 247                         #dma-cells = <1>;
 248
 249                 };
 250
 251                 pdma1: pdma@20078000 {
 252                         compatible = "arm,pl330", "arm,primecell";
 253                         reg = <0x20078000 0x4000>;
 254                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 255                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 256                         #dma-cells = <1>;
 257
 258                 };
 259         };
 260
 261         emmc: rksdmmc@1021C000 {
 262                 compatible = "rockchip,rk_mmc";
 263                 reg = <0x1021C000 0x4000>;
 264                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;/*irq=57*/
 265                 #address-cells = <1>;
 266                 #size-cells = <0>;
 267                 //pinctrl-names = "default",,"suspend";
 268                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 269                 clocks = <&clk_gates2 14>;
 270                 num-slots = <1>;
 271
 272                 fifo-depth = <0x80>;
 273                 bus-width = <4>;
 274         };
 275
 276         sdmmc: rksdmmc@10214000 {
 277                 compatible = "rockchip,rk_mmc";
 278                 reg = <0x10214000 0x4000>;
 279                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; /*irq=55*/
 280                 #address-cells = <1>;
 281                 #size-cells = <0>;
 282                 pinctrl-names = "default","suspend";
 283                 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 284                 pinctrl-1 = <&sd0_cd_gpio>; //for int gpio?
 285                 clocks = <&clk_gates2 11>;
 286                 num-slots = <1>;
 287
 288                 fifo-depth = <0x100>;
 289                 bus-width = <4>;
 290         };
 291
 292         sdio: rksdmmc@10218000 {
 293                 compatible = "rockchip,rk_mmc";
 294                 reg = <0x10218000 0x4000>;
 295                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 296                 #address-cells = <1>;
 297                 #size-cells = <0>;
 298                 pinctrl-names = "default","suspend";
 299                 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 300                 clocks = <&clk_gates2 13>;
 301                 num-slots = <1>;
 302
 303                 fifo-depth = <0x100>;
 304                 bus-width = <4>;
 305         };
 306
 307         uart0: serial@10124000 {
 308                 compatible = "rockchip,serial";
 309                 reg = <0x10124000 0x100>;
 310                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 311                 clock-frequency = <24000000>;
 312                 clocks = <&clk_uart0>, <&clk_gates8 0>;
 313                 clock-names = "sclk_uart", "pclk_uart";
 314                 reg-shift = <2>;
 315                 reg-io-width = <4>;
 316                 dmas = <&pdma0 0>, <&pdma0 1>;
 317                 #dma-cells = <2>;
 318                 pinctrl-names = "default";
 319                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 320                 status = "disabled";
 321         };
 322
 323         uart1: serial@10126000 {
 324                 compatible = "rockchip,serial";
 325                 reg = <0x10126000 0x100>;
 326                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 327                 clock-frequency = <24000000>;
 328                 clocks = <&clk_uart1>, <&clk_gates8 1>;
 329                 clock-names = "sclk_uart", "pclk_uart";
 330                 reg-shift = <2>;
 331                 reg-io-width = <4>;
 332                 dmas = <&pdma0 2>, <&pdma0 3>;
 333                 #dma-cells = <2>;
 334                 pinctrl-names = "default";
 335                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 336                 status = "disabled";
 337         };
 338
 339         uart2: serial@20064000 {
 340                 compatible = "rockchip,serial";
 341                 reg = <0x20064000 0x100>;
 342                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 343                 clock-frequency = <24000000>;
 344                 clocks = <&clk_uart2>, <&clk_gates8 2>;
 345                 clock-names = "sclk_uart", "pclk_uart";
 346                 current-speed = <115200>;
 347                 reg-shift = <2>;
 348                 reg-io-width = <4>;
 349                 pinctrl-names = "default";
 350                 pinctrl-0 = <&uart2_xfer>;
 351                 status = "disabled";
 352         };
 353
 354         uart3: serial@20068000 {
 355                 compatible = "rockchip,serial";
 356                 reg = <0x20068000 0x100>;
 357                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 358                 clock-frequency = <24000000>;
 359                 clocks = <&clk_uart3>, <&clk_gates8 3>;
 360                 clock-names = "sclk_uart", "pclk_uart";
 361                 reg-shift = <2>;
 362                 reg-io-width = <4>;
 363                 dmas = <&pdma1 8>, <&pdma1 9>;
 364                 #dma-cells = <2>;
 365                 pinctrl-names = "default";
 366                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 367                 status = "disabled";
 368         };
 369
 370         fiq-debugger {
 371                 compatible = "rockchip,fiq-debugger";
 372                 rockchip,serial-id = <2>;
 373                 rockchip,signal-irq = <112>;
 374                 rockchip,wake-irq = <0>;
 375                 status = "disabled";
 376         };
 377
 378         spi0: spi@20070000 {
 379                 compatible = "rockchip,rockchip-spi";
 380                 reg = <0x20070000 0x1000>;
 381                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 382                 #address-cells = <1>;
 383                 #size-cells = <0>;
 384                 pinctrl-names = "default";
 385                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 386                 rockchip,spi-src-clk = <0>;
 387                 num-cs = <2>;
 388                 clocks =<&clk_spi0>, <&clk_gates7 12>;
 389                 clock-names = "spi","pclk_spi0";
 390                 dmas = <&pdma1 10>, <&pdma1 11>;
 391                 #dma-cells = <2>;
 392                 dma-names = "tx", "rx";
 393                 status = "disabled";
 394         };
 395
 396         spi1: spi@20074000 {
 397                 compatible = "rockchip,rockchip-spi";
 398                 reg = <0x20074000 0x1000>;
 399                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 400                 #address-cells = <1>;
 401                 #size-cells = <0>;
 402                 pinctrl-names = "default";
 403                 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0 &spi1_cs1>;
 404                 rockchip,spi-src-clk = <1>;
 405                 num-cs = <2>;
 406                 clocks = <&clk_spi1>, <&clk_gates7 13>;
 407                 clock-names = "spi","pclk_spi1";
 408                 dmas = <&pdma1 12>, <&pdma1 13>;
 409                 #dma-cells = <2>;
 410                 dma-names = "tx", "rx";
 411                 status = "disabled";
 412         };
 413
 414         i2c0: i2c@2002d000 {
 415                 compatible = "rockchip,rk30-i2c";
 416                 reg = <0x2002d000 0x1000>;
 417                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 418                 #address-cells = <1>;
 419                 #size-cells = <0>;
 420                 pinctrl-names = "default", "gpio";
 421                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 422                 pinctrl-1 = <&i2c0_gpio>;
 423                 gpios = <&gpio1 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D1 GPIO_ACTIVE_LOW>;
 424                 clocks = <&clk_gates8 4>;
 425                 rockchip,check-idle = <1>;
 426                 status = "disabled";
 427         };
 428
 429         i2c1: i2c@2002f000 {
 430                 compatible = "rockchip,rk30-i2c";
 431                 reg = <0x2002f000 0x1000>;
 432                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 433                 #address-cells = <1>;
 434                 #size-cells = <0>;
 435                 pinctrl-names = "default", "gpio";
 436                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 437                 pinctrl-1 = <&i2c1_gpio>;
 438                 gpios = <&gpio1 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D3 GPIO_ACTIVE_LOW>;
 439                 clocks = <&clk_gates8 5>;
 440                 rockchip,check-idle = <1>;
 441                 status = "disabled";
 442         };
 443
 444         i2c2: i2c@20056000 {
 445                 compatible = "rockchip,rk30-i2c";
 446                 reg = <0x20056000 0x1000>;
 447                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 448                 #address-cells = <1>;
 449                 #size-cells = <0>;
 450                 pinctrl-names = "default", "gpio";
 451                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 452                 pinctrl-1 = <&i2c2_gpio>;
 453                 gpios = <&gpio1 GPIO_D4 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D5 GPIO_ACTIVE_LOW>;
 454                 clocks = <&clk_gates8 6>;
 455                 rockchip,check-idle = <1>;
 456                 status = "disabled";
 457         };
 458
 459         i2c3: i2c@2005a000 {
 460                 compatible = "rockchip,rk30-i2c";
 461                 reg = <0x2005a000 0x1000>;
 462                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 463                 #address-cells = <1>;
 464                 #size-cells = <0>;
 465                 pinctrl-names = "default", "gpio";
 466                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 467                 pinctrl-1 = <&i2c3_gpio>;
 468                 gpios = <&gpio3 GPIO_B6 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_B7 GPIO_ACTIVE_LOW>;
 469                 clocks = <&clk_gates8 7>;
 470                 rockchip,check-idle = <1>;
 471                 status = "disabled";
 472         };
 473
 474         i2c4: i2c@2005e000 {
 475                 compatible = "rockchip,rk30-i2c";
 476                 reg = <0x2005e000 0x1000>;
 477                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 478                 #address-cells = <1>;
 479                 #size-cells = <0>;
 480                 pinctrl-names = "default", "gpio";
 481                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 482                 pinctrl-1 = <&i2c4_gpio>;
 483                 gpios = <&gpio1 GPIO_D6 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D7 GPIO_ACTIVE_LOW>;
 484                 clocks = <&clk_gates8 8>;
 485                 rockchip,check-idle = <1>;
 486                 status = "disabled";
 487         };
 488
 489         clocks-init{
 490                 compatible = "rockchip,clocks-init";
 491                 rockchip,clocks-init-parent =
 492                         <&clk_core &clk_apll>,  <&aclk_cpu &clk_gpll>,
 493                         <&aclk_peri &clk_gpll>, <&clk_i2s_pll_mux &clk_cpll>,
 494                         <&clk_uart_pll_mux &clk_gpll>;
 495                 rockchip,clocks-init-rate =
 496                         <&clk_core 792000000>,  <&clk_gpll 768000000>,
 497                         <&clk_cpll 594000000>,  <&aclk_cpu 192000000>,
 498                         <&hclk_cpu 96000000>,   <&pclk_cpu 48000000>,
 499                         <&pclk_ahb2apb 48000000>,       <&aclk_peri 192000000>,
 500                         <&hclk_peri 96000000>,  <&pclk_peri 48000000>,
 501                         <&clk_gpu 200000000>, <&aclk_lcdc0 300000000>,
 502                         <&aclk_lcdc1 300000000>;
 503         };
 504         rockchip_suspend {
 505                 //compatible = "rockchip,rkpm_suspend";
 506                 // define value is in dt-bindint/suspend/rockchip-pm.h
 507                 rockchip,ctrbits = <
 508                                                 (
 509                                                 RKPM_CTR_PWR_DMNS
 510                                                 |RKPM_CTR_GTCLKS
 511                                                 |RKPM_CTR_PLLS
 512                                                 |RKPM_CTR_SYSCLK_DIV
 513                                                 )
 514                                         >;
 515               rockchip,pmic-gpios=<
 516                                                 RKPM_PINGPIO_BITS_OUTPUT(GPIO0_A0,RKPM_GPIO_OUT_L)
 517                                                 RKPM_PINGPIO_BITS_INTPUT(GPIO0_A1,RKPM_GPIO_PULL_UP)
 518                                                 >;
 519
 520         };
 521         fb: fb{
 522                 compatible = "rockchip,rk-fb";
 523                 rockchip,disp-mode = <DUAL>;
 524         };
 525
 526         rk_screen: rk_screen{
 527                 compatible = "rockchip,screen";
 528         };
 529
 530         nandc: nandc {
 531                 compatible = "rockchip,rk-nandc";
 532                 reg = <0x10050000 0x4000>;
 533                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 534         };
 535
 536         lcdc0:lcdc@1010c000 {
 537                 compatible = "rockchip,rk3188-lcdc";
 538                 rockchip,prop = <PRMRY>;
 539                 rochchip,pwr18 = <0>;
 540                 reg = <0x1010c000 0x1000>;
 541                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 542                 status = "disabled";
 543         };
 544
 545         lcdc1:lcdc@1010e000 {
 546                 compatible = "rockchip,rk3188-lcdc";
 547                 rockchip,prop = <EXTEND>;
 548                 rockchip,pwr18 = <0>;
 549                 reg = <0x1010e000 0x1000>;
 550                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 551                 pinctrl-names = "default", "gpio";
 552                 pinctrl-0 = <&lcdc1_lcdc>;
 553                 pinctrl-1 = <&lcdc1_gpio>;
 554                 status = "disabled";
 555         };
 556
 557         rga@10114000 {
 558                 compatible = "rockchip,rga";
 559                 reg = <0x10114000 0x1000>;
 560                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 561                 clocks = <&clk_gates6 10>, <&clk_gates6 11>;
 562                 clock-names = "hclk_rga", "aclk_rga";
 563         };
 564
 565         adc: adc@2006c000 {
 566                 compatible = "rockchip,saradc";
 567                 reg = <0x2006c000 0x100>;
 568                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 569                 #io-channel-cells = <1>;
 570                 io-channel-ranges;
 571                 rockchip,adc-vref = <1800>;
 572                 clock-frequency = <1000000>;
 573                 clocks = <&clk_saradc>, <&clk_gates7 14>;
 574                 clock-names = "saradc", "pclk_saradc";
 575                 status = "disabled";
 576         };
 577
 578         spdif: rockchip-spdif@0x1011e000 {
 579                 compatible = "rockchip-spdif";
 580                 reg = <0x1011e000 0x2000>;
 581                 clocks = <&clk_spdif>;
 582                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 583                 dmas = <&pdma0 8>;
 584                 dma-names = "tx";
 585                 pinctrl-names = "default";
 586                 pinctrl-0 = <&spdif_tx>;
 587         };
 588
 589         i2s0: rockchip-i2s@0x1011a000 {
 590                 compatible = "rockchip-i2s";
 591                 reg = <0x1011a000 0x2000>;
 592                 i2s-id = <0>;
 593                 clocks = <&clk_i2s>;
 594                 clock-names = "i2s_clk";
 595                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 596                 dmas = <&pdma0 6>,
 597                         <&pdma0 7>;
 598                 dma-names = "tx", "rx";
 599                 pinctrl-names = "default", "sleep";
 600                 pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo>;
 601                 pinctrl-1 = <&i2s0_gpio>;
 602         };
 603
 604         pwm0: pwm@20030000{
 605                 compatible = "rockchip,pwm";
 606                 reg = <0x20030000 0x10>;
 607                 #pwm-cells = <2>;
 608                 pinctrl-names = "default";
 609                 pinctrl-0 = <&pwm0_pin>;
 610                 clocks = <&clk_gates7 10>;
 611                 clock-names = "pclk_pwm";
 612                 status = "disabled";
 613
 614         };
 615
 616         pwm1: pwm@20030010{
 617                 compatible = "rockchip,pwm";
 618                 reg = <0x20030010 0x10>; /*0x20030000*/
 619                 #pwm-cells = <2>;
 620                 pinctrl-names = "default";
 621                 pinctrl-0 = <&pwm1_pin>;
 622                 clocks = <&clk_gates7 10>;
 623                 clock-names = "pclk_pwm";
 624                 status = "disabled";
 625
 626         };
 627         pwm2: pwm@20050020{
 628                 compatible = "rockchip,pwm";
 629                 reg = <0x20050020 0x10>; /*0x20030000*/
 630                 #pwm-cells = <2>;
 631                 pinctrl-names = "default";
 632                 clock-names = "pclk_pwm";
 633                 clocks = <&clk_gates7 11>;
 634                 pinctrl-0 = <&pwm2_pin>;
 635                 status = "disabled";
 636
 637         };
 638
 639         pwm3: pwm@20050030{
 640                 compatible = "rockchip,pwm";
 641                 reg = <0x20050030 0x10>; /*0x20030000*/
 642                 #pwm-cells = <2>;
 643                 pinctrl-names = "default";
 644                 pinctrl-0 = <&pwm3_pin>;
 645                 clocks = <&clk_gates7 11>;
 646                 clock-names = "pclk_pwm";
 647                 status = "disabled";
 648
 649         };
 650         dvfs {
 651                 vd_arm:
 652                 vd_arm {
 653                         regulator_name="vdd_arm";
 654                         suspend_volt=<1000>; //mV
 655                         pd_a9 {
 656                                 clk_core_dvfs_table:
 657                                 clk_core {
 658                                         operating-points = <
 659                                                 /* KHz    uV */
 660                                                 312000 900000
 661                                                 504000 950000
 662                                                 816000 1000000
 663                                                 1008000 1100000
 664                                                 1200000 1200000
 665                                                 1416000 1300000
 666                                                 1608000 1350000
 667                                                 >;
 668                                         status = "okay";
 669                                 };
 670                         };
 671                 };
 672
 673                 vd_logic:
 674                 vd_logic {
 675                         regulator_name="vdd_logic";
 676                         suspend_volt=<1000>; //mV
 677
 678                         pd_gpu {
 679                                 clk_gpu_dvfs_table:
 680                                 clk_gpu {
 681                                         operating-points = <
 682                                                 /* KHz    uV */
 683                                                 200000 1200000
 684                                                 300000 1200000
 685                                                 400000 1200000
 686                                                 >;
 687                                         status = "okay";
 688                                 };
 689                         };
 690
 691                         pd_ddr {
 692                                 clk_ddr_dvfs_table:
 693                                 clk_ddr {
 694                                         operating-points = <
 695                                                 /* KHz    uV */
 696                                                 200000 1200000
 697                                                 300000 1200000
 698                                                 400000 1200000
 699                                                 >;
 700                                         status = "disable";
 701                                 };
 702                         };
 703                 };
 704         };
 705         ion{
 706                 compatible = "rockchip,ion";
 707                 #address-cells = <1>;
 708                 #size-cells = <0>;
 709                 rockchip,ion-heap@1 { /* CMA HEAP */
 710                         compatible = "rockchip,ion-reserve";
 711                         reg = <1>;
 712                         memory-reservation = <0x00000000 0x10000000>; /* 256MB */
 713                 };
 714                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 715                         reg = <3>;
 716                 };
 717         };
 718
 719         dwc_control_usb: dwc-control-usb@200080ac {
 720                 compatible = "rockchip,rk3188-dwc-control-usb";
 721                 reg = <0x200080ac 0x4>,
 722                       <0x2000810c 0x10>,
 723                       <0x2000811c 0x10>,
 724                       <0x2000812c 0x8>,
 725                       <0x20008138 0x8>;
 726                 reg-names = "GRF_SOC_STATUS0",
 727                     "GRF_UOC0_BASE",
 728                     "GRF_UOC1_BASE",
 729                     "GRF_UOC2_BASE",
 730                     "GRF_UOC3_BASE";
 731                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 732                 interrupt-names = "otg_bvalid";
 733                 gpios = <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D5 GPIO_ACTIVE_LOW>;
 734                 clocks = <&clk_gates4 5>;
 735                 clock-names = "hclk_usb_peri";
 736                 rockchip,remote_wakeup;
 737                 rockchip,usb_irq_wakeup;
 738
 739                 usb_bc{
 740                         compatible = "rockchip,ctrl";
 741                         rk_usb,bvalid   = <0xac 10 1>;
 742                         rk_usb,iddig    = <0xac 13 1>;
 743                         rk_usb,line     = <0xac 11 2>;
 744                         rk_usb,softctrl = <0x114 2 1>;
 745                         rk_usb,opmode   = <0x118 1 2>;
 746                         rk_usb,xcvrsel  = <0x118 3 2>;
 747                         rk_usb,termsel  = <0x118 5 1>;
 748                 };
 749         };
 750
 751
 752         usb0: usb@10180000 {
 753                 compatible = "rockchip,rk3188_usb20_otg";
 754                 reg = <0x10180000 0x40000>;
 755                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 756                 clocks = <&clk_gates1 5>, <&clk_gates5 13>;
 757                 clock-names = "clk_usbphy0", "hclk_usb0";
 758                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
 759                 rockchip,usb-mode = <0>;
 760         };
 761
 762         usb1: usb@101c0000 {
 763                 compatible = "rockchip,rk3188_usb20_host";
 764                 reg = <0x101c0000 0x40000>;
 765                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 766                 clocks = <&clk_gates1 6>, <&clk_gates7 3>;
 767                 clock-names = "clk_usbphy1", "hclk_usb1";
 768         };
 769
 770         hsic: hsic@10240000 {
 771                 compatible = "rockchip,rk3188_rk_hsic_host";
 772                 reg = <0x10240000 0x40000>;
 773                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 774                 clocks = <&clk_hsicphy480m>, <&clk_gates7 4>,
 775                  <&clk_hsicphy12m>, <&otgphy1_480m>;
 776                 clock-names = "hsicphy_480m", "hclk_hsic",
 777                       "hsicphy_12m", "hsic_usbphy1";
 778         };
 779
 780         vmac@10204000 {
 781                 compatible = "rockchip,vmac";
 782                 reg = <0x10204000 0x4000>;
 783                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 784                 pinctrl-names = "default", "gpio";
 785                 pinctrl-0 = <&rmii_clkoutpin &rmii_txpins &rmii_rxpins &rmii_mdpins>;
 786                 pinctrl-1 = <&rmii_clkinpin &rmii_txpins &rmii_rxpins &rmii_mdpins>;
 787         };
 788
 789         ap0_vcc_domain: ap0-vcc-domain {
 790                         compatible = "rockchip,io_vol_domain";
 791                         pinctrl-names = "default", "1.8V", "3.3V";
 792                         pinctrl-0 = <&ap0_vcc >;
 793                         pinctrl-1 = <&ap0_vcc_18>;
 794                         pinctrl-2 = <&ap0_vcc_33>;
 795         };
 796         ap1_vcc_domain: ap1-vcc-domain{
 797                         compatible = "rockchip,io_vol_domain";
 798                         pinctrl-names = "default", "1.8V", "3.3V";
 799                         pinctrl-0 = <&ap1_vcc >;
 800                         pinctrl-1 = <&ap1_vcc_18>;
 801                         pinctrl-2 = <&ap1_vcc_33>;
 802         };
 803         cif_vcc_domain: cif-vcc-domain{
 804                         compatible = "rockchip,io_vol_domain";
 805                         pinctrl-names = "default", "1.8V", "3.3V";
 806                         pinctrl-0 = <&cif_vcc>;
 807                         pinctrl-1 = <&cif_vcc_18>;
 808                         pinctrl-2 = <&cif_vcc_33>;
 809         };
 810         flash_vcc_domain: flash-vcc-domain{
 811                         compatible = "rockchip,io_vol_domain";
 812                         pinctrl-names = "default", "1.8V", "3.3V";
 813                         pinctrl-0 = <&flash_vcc>;
 814                         pinctrl-1 = <&flash_vcc_18>;
 815                         pinctrl-2 = <&flash_vcc_33>;
 816         };
 817         vccio0_vcc_domain: vccio0-vcc-domain{
 818                         compatible = "rockchip,io_vol_domain";
 819                         pinctrl-names = "default", "1.8V", "3.3V";
 820                         pinctrl-0 = <&vccio0_vcc>;
 821                         pinctrl-1 = <&vccio0_vcc_18>;
 822                         pinctrl-2 = <&vccio0_vcc_33>;
 823         };
 824         vccio1_vcc_domain: vccio1-vcc-domain{
 825                         compatible = "rockchip,io_vol_domain";
 826                         pinctrl-names = "default", "1.8V", "3.3V";
 827                         pinctrl-0 = <&vccio1_vcc>;
 828                         pinctrl-1 = <&vccio1_vcc_18>;
 829                         pinctrl-2 = <&vccio1_vcc_33>;
 830         };
 831         lcdc0_vcc_domain: lcdc0-vcc-domain{
 832                         compatible = "rockchip,io_vol_domain";
 833                         pinctrl-names = "default", "1.8V", "3.3V";
 834                         pinctrl-0 = <&lcdc0_vcc>;
 835                         pinctrl-1 = <&lcdc0_vcc_18>;
 836                         pinctrl-2 = <&lcdc0_vcc_33>;
 837         };
 838         lcdc1_vcc_domain: lcdc1-vcc-domain{
 839                         compatible = "rockchip,io_vol_domain";
 840                         pinctrl-names = "default", "1.8V", "3.3V";
 841                         pinctrl-0 = <&lcdc1_vcc>;
 842                         pinctrl-1 = <&lcdc1_vcc_18>;
 843                         pinctrl-2 = <&lcdc1_vcc_33>;
 844         };
 845
 846 };