arch/arm/boot/dts/rk3188.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/gpio/gpio.h>
   3 #include <dt-bindings/pinctrl/rockchip.h>
   4 #include <dt-bindings/pinctrl/rockchip-rk3188.h>
   5
   6 #include "skeleton.dtsi"
   7
   8 / {
   9         compatible = "rockchip,rk3188";
  10         interrupt-parent = <&gic>;
  11
  12         cpus {
  13                 #address-cells = <1>;
  14                 #size-cells = <0>;
  15
  16                 cpu@0 {
  17                         device_type = "cpu";
  18                         compatible = "arm,cortex-a9";
  19                         reg = <0>;
  20                 };
  21                 cpu@1 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a9";
  24                         reg = <1>;
  25                 };
  26                 cpu@2 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a9";
  29                         reg = <2>;
  30                 };
  31                 cpu@3 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a9";
  34                         reg = <3>;
  35                 };
  36         };
  37
  38         twd-wdt@1013c620 {
  39                 compatible = "arm,cortex-a9-twd-wdt";
  40                 reg = <0x1013c620 0x20>;
  41                 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  42         };
  43
  44         gic: interrupt-controller@1013d000 {
  45                 compatible = "arm,cortex-a9-gic";
  46                 interrupt-controller;
  47                 #interrupt-cells = <3>;
  48                 reg = <0x1013d000 0x1000>,
  49                       <0x1013c100 0x0100>;
  50         };
  51
  52         L2: cache-controller@10138000 {
  53                 compatible = "arm,pl310-cache";
  54                 reg = <0x10138000 0x1000>;
  55                 cache-unified;
  56                 cache-level = <2>;
  57                 arm,tag-latency = <1 1 1>;
  58                 arm,data-latency = <2 3 1>;
  59                 prefetch-ctrl = <0x70000003>;
  60                 /* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
  61                 power-ctrl = <0x3>;
  62 /*
  63                 (0x1 << 0) |    // Full line of write zero behavior Enabled
  64                 (0x1 << 25) |   // Round-robin replacement
  65                 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
  66                 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
  67                 (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
  68 */
  69                 aux-ctrl = <0x72000001 (~0x72000001)>;
  70         };
  71
  72         cpu_axi_bus: cpu_axi_bus@10128000 {
  73                 compatible = "rockchip,cpu_axi_bus";
  74                 reg = <0x10128000 0x8000>;
  75                 qos {
  76                         dmac {
  77                                 offset = <0x1000>;
  78                                 priority = <0 0>;
  79                         };
  80                         cpu0 {
  81                                 offset = <0x2000>;
  82                                 priority = <0 0>;
  83                         };
  84                         cpu1r {
  85                                 offset = <0x2080>;
  86                                 priority = <0 0>;
  87                         };
  88                         cpu1w {
  89                                 offset = <0x2100>;
  90                                 priority = <0 0>;
  91                         };
  92                         peri {
  93                                 offset = <0x4000>;
  94                                 priority = <2 2>;
  95                         };
  96                         gpu {
  97                                 offset = <0x5000>;
  98                                 priority = <2 1>;
  99                         };
 100                         vpu {
 101                                 offset = <0x6000>;
 102                         };
 103                         vop0 {
 104                                 offset = <0x7000>;
 105                                 priority = <3 3>;
 106                         };
 107                         cif0 {
 108                                 offset = <0x7080>;
 109                         };
 110                         ipp {
 111                                 offset = <0x7100>;
 112                         };
 113                         vop1 {
 114                                 offset = <0x7180>;
 115                                 priority = <3 3>;
 116                         };
 117                         cif1 {
 118                                 offset = <0x7200>;
 119                         };
 120                         rga {
 121                                 offset = <0x7280>;
 122                         };
 123                 };
 124         };
 125
 126         bootrom@10120000 {
 127                 compatible = "rockchip,bootrom";
 128                 reg = <0x10120000 0x4000>;
 129         };
 130
 131         bootram@10080000 {
 132                 compatible = "rockchip,bootram";
 133                 reg = <0x10080000 0x20>; /* 32 bytes */
 134         };
 135
 136         sram@10080020 {
 137                 compatible = "mmio-sram";
 138                 reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
 139                 map-exec;
 140         };
 141
 142         pmu@20004000 {
 143                 compatible = "rockchip,pmu";
 144                 reg = <0x20004000 0x4000>;
 145         };
 146
 147         timer@200380a0 {
 148                 compatible = "rockchip,timer";
 149                 reg = <0x200380a0 0x20>;
 150                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 151         };
 152
 153         timer@20038000 {
 154                 compatible = "rockchip,timer";
 155                 reg = <0x20038000 0x20>;
 156                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 157         };
 158
 159         timer@20038020 {
 160                 compatible = "rockchip,timer";
 161                 reg = <0x20038020 0x20>;
 162                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 163         };
 164
 165         timer@20038060 {
 166                 compatible = "rockchip,timer";
 167                 reg = <0x20038060 0x20>;
 168                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 169         };
 170
 171         timer@20038080 {
 172                 compatible = "rockchip,timer";
 173                 reg = <0x20038080 0x20>;
 174                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 175         };
 176
 177         pinctrl@20008000 {
 178                 compatible = "rockchip,rk3188-pinctrl";
 179                 reg = <0x20008000 0xa0>,
 180                       <0x20008164 0x1a0>;
 181                 reg-names = "base", "pull";
 182                 #address-cells = <1>;
 183                 #size-cells = <1>;
 184                 ranges;
 185
 186                 gpio0: gpio0@0x2000a000 {
 187                         compatible = "rockchip,rk3188-gpio-bank0";
 188                         reg = <0x2000a000 0x100>,
 189                               <0x20004064 0x8>;
 190                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 191                         /*clocks = <&clk_gates8 9>;*/
 192
 193                         gpio-controller;
 194                         #gpio-cells = <2>;
 195
 196                         interrupt-controller;
 197                         #interrupt-cells = <2>;
 198                 };
 199
 200                 gpio1: gpio1@0x2003c000 {
 201                         compatible = "rockchip,gpio-bank";
 202                         reg = <0x2003c000 0x100>;
 203                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 204                         /*clocks = <&clk_gates8 10>;*/
 205
 206                         gpio-controller;
 207                         #gpio-cells = <2>;
 208
 209                         interrupt-controller;
 210                         #interrupt-cells = <2>;
 211                 };
 212
 213                 gpio2: gpio2@2003e000 {
 214                         compatible = "rockchip,gpio-bank";
 215                         reg = <0x2003e000 0x100>;
 216                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 217                         /*clocks = <&clk_gates8 11>;*/
 218
 219                         gpio-controller;
 220                         #gpio-cells = <2>;
 221
 222                         interrupt-controller;
 223                         #interrupt-cells = <2>;
 224                 };
 225
 226                 gpio3: gpio3@20080000 {
 227                         compatible = "rockchip,gpio-bank";
 228                         reg = <0x20080000 0x100>;
 229                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 230                         /*clocks = <&clk_gates8 12>;*/
 231
 232                         gpio-controller;
 233                         #gpio-cells = <2>;
 234
 235                         interrupt-controller;
 236                         #interrupt-cells = <2>;
 237                 };
 238
 239                 pcfg_pull_up: pcfg_pull_up {
 240                         bias-pull-up;
 241                 };
 242
 243                 pcfg_pull_down: pcfg_pull_down {
 244                         bias-pull-down;
 245                 };
 246
 247                 pcfg_pull_none: pcfg_pull_none {
 248                         bias-disable;
 249                 };
 250
 251                 uart0 {
 252                         uart0_xfer: uart0-xfer {
 253                                 rockchip,pins = <UART0_SIN &pcfg_pull_none>,
 254                                                 <UART0_SOUT &pcfg_pull_none>;
 255                         };
 256
 257                         uart0_cts: uart0-cts {
 258                                 rockchip,pins = <UART0_CTSN &pcfg_pull_none>;
 259                         };
 260
 261                         uart0_rts: uart0-rts {
 262                                 rockchip,pins = <UART0_RTSN &pcfg_pull_none>;
 263                         };
 264                 };
 265
 266                 uart1 {
 267                         uart1_xfer: uart1-xfer {
 268                                 rockchip,pins = <UART1_SIN &pcfg_pull_none>,
 269                                                 <UART1_SOUT &pcfg_pull_none>;
 270                         };
 271
 272                         uart1_cts: uart1-cts {
 273                                 rockchip,pins = <UART1_CTSN &pcfg_pull_none>;
 274                         };
 275
 276                         uart1_rts: uart1-rts {
 277                                 rockchip,pins = <UART1_RTSN &pcfg_pull_none>;
 278                         };
 279                 };
 280
 281                 uart2 {
 282                         uart2_xfer: uart2-xfer {
 283                                 rockchip,pins = <UART2_SIN &pcfg_pull_none>,
 284                                                 <UART2_SOUT &pcfg_pull_none>;
 285                         };
 286                         /* no rts / cts for uart2 */
 287                 };
 288
 289                 uart3 {
 290                         uart3_xfer: uart3-xfer {
 291                                 rockchip,pins = <UART3_SIN &pcfg_pull_none>,
 292                                                 <UART3_SOUT &pcfg_pull_none>;
 293                         };
 294
 295                         uart3_cts: uart3-cts {
 296                                 rockchip,pins = <UART3_CTSN &pcfg_pull_none>;
 297                         };
 298
 299                         uart3_rts: uart3-rts {
 300                                 rockchip,pins = <UART3_RTSN &pcfg_pull_none>;
 301                         };
 302                 };
 303
 304                 sd0 {
 305                         sd0_clk: sd0-clk {
 306                                 rockchip,pins = <MMC0_CLKOUT &pcfg_pull_none>;
 307                         };
 308
 309                         sd0_cmd: sd0-cmd {
 310                                 rockchip,pins = <MMC0_CMD &pcfg_pull_none>;
 311                         };
 312
 313                         sd0_cd: sd0-cd {
 314                                 rockchip,pins = <MMC0_DETN &pcfg_pull_none>;
 315                         };
 316
 317                         sd0_wp: sd0-wp {
 318                                 rockchip,pins = <MMC0_WRPRT &pcfg_pull_none>;
 319                         };
 320
 321                         sd0_pwr: sd0-pwr {
 322                                 rockchip,pins = <MMC0_PWREN &pcfg_pull_none>;
 323                         };
 324
 325                         sd0_bus1: sd0-bus-width1 {
 326                                 rockchip,pins = <MMC0_D0 &pcfg_pull_none>;
 327                         };
 328
 329                         sd0_bus4: sd0-bus-width4 {
 330                                 rockchip,pins = <MMC0_D0 &pcfg_pull_none>,
 331                                                 <MMC0_D1 &pcfg_pull_none>,
 332                                                 <MMC0_D2 &pcfg_pull_none>,
 333                                                 <MMC0_D3 &pcfg_pull_none>;
 334                         };
 335                 };
 336
 337
 338                 sd1 {
 339                         sd1_clk: sd1-clk {
 340                                 rockchip,pins = <MMC1_CLKOUT &pcfg_pull_none>;
 341                         };
 342
 343                         sd1_cmd: sd1-cmd {
 344                                 rockchip,pins = <MMC1_CMD &pcfg_pull_none>;
 345                         };
 346
 347                         sd1_cd: sd1-cd {
 348                                 rockchip,pins = <MMC1_DETN &pcfg_pull_none>;
 349                         };
 350
 351                         sd1_wp: sd1-wp {
 352                                 rockchip,pins = <MMC1_WRPRT &pcfg_pull_none>;
 353                         };
 354
 355                         sd1_bus1: sd1-bus-width1 {
 356                                 rockchip,pins = <MMC1_D0 &pcfg_pull_none>;
 357                         };
 358
 359                         sd1_bus4: sd1-bus-width4 {
 360                                 rockchip,pins = <MMC1_D0 &pcfg_pull_none>,
 361                                                 <MMC1_D1 &pcfg_pull_none>,
 362                                                 <MMC1_D2 &pcfg_pull_none>,
 363                                                 <MMC1_D3 &pcfg_pull_none>;
 364                         };
 365                 };
 366         };
 367
 368
 369         uart0: serial@10124000 {
 370                 compatible = "rockchip,serial";
 371                 reg = <0x10124000 0x100>;
 372                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 373                 clock-frequency = <24000000>;
 374                 reg-shift = <2>;
 375                 reg-io-width = <4>;
 376                 id = <0>;
 377                 pinctrl-names = "default";
 378                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 379                 status = "disabled";
 380         };
 381
 382         uart1: serial@10126000 {
 383                 compatible = "rockchip,serial";
 384                 reg = <0x10126000 0x100>;
 385                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 386                 clock-frequency = <24000000>;
 387                 reg-shift = <2>;
 388                 reg-io-width = <4>;
 389                 id = <1>;
 390                 pinctrl-names = "default";
 391                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 392                 status = "disabled";
 393         };
 394
 395         uart2: serial@20064000 {
 396                 compatible = "rockchip,serial";
 397                 reg = <0x20064000 0x100>;
 398                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 399                 clock-frequency = <24000000>;
 400                 current-speed = <115200>;
 401                 reg-shift = <2>;
 402                 reg-io-width = <4>;
 403                 id = <2>;
 404                 pinctrl-names = "default";
 405                 pinctrl-0 = <&uart2_xfer>;
 406                 status = "disabled";
 407         };
 408
 409         uart3: serial@20068000 {
 410                 compatible = "rockchip,serial";
 411                 reg = <0x20068000 0x100>;
 412                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 413                 clock-frequency = <24000000>;
 414                 reg-shift = <2>;
 415                 reg-io-width = <4>;
 416                 id = <3>;
 417                 pinctrl-names = "default";
 418                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 419                 status = "disabled";
 420         };
 421
 422         fiq-debugger {
 423                 compatible = "rockchip,fiq-debugger";
 424                 serial-id = <2>;
 425                 signal-irq = <112>;
 426                 wake-irq = <0>;
 427                 status = "disabled";
 428         };
 429
 430 };