arch/arm/boot/dts/rk3188.dtsi

   1
   2 #include "skeleton.dtsi"
   3 #include "rk3188-pinctrl.dtsi"
   4 #include <dt-bindings/rkfb/rk_fb.h>
   5 #include "rk3188_io_vol_domain.dtsi"
   6
   7 #include <dt-bindings/sensor-dev.h>
   8
   9 / {
  10         compatible = "rockchip,rk3188";
  11         interrupt-parent = <&gic>;
  12         rockchip,sram = <&sram>;
  13
  14         aliases {
  15                 serial0 = &uart0;
  16                 serial1 = &uart1;
  17                 serial2 = &uart2;
  18                 serial3 = &uart3;
  19                 i2c0 = &i2c0;
  20                 i2c1 = &i2c1;
  21                 i2c2 = &i2c2;
  22                 i2c3 = &i2c3;
  23                 i2c4 = &i2c4;
  24                 lcdc0 = &lcdc0;
  25                 lcdc1 = &lcdc1;
  26                 spi0 = &spi0;
  27                 spi1 = &spi1;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a9";
  37                         reg = <0>;
  38                 };
  39                 cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a9";
  42                         reg = <1>;
  43                 };
  44                 cpu@2 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a9";
  47                         reg = <2>;
  48                 };
  49                 cpu@3 {
  50                         device_type = "cpu";
  51                         compatible = "arm,cortex-a9";
  52                         reg = <3>;
  53                 };
  54         };
  55
  56         twd-wdt@1013c620 {
  57                 compatible = "arm,cortex-a9-twd-wdt";
  58                 reg = <0x1013c620 0x20>;
  59                 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  60         };
  61
  62         gic: interrupt-controller@1013d000 {
  63                 compatible = "arm,cortex-a9-gic";
  64                 interrupt-controller;
  65                 #interrupt-cells = <3>;
  66                 reg = <0x1013d000 0x1000>,
  67                       <0x1013c100 0x0100>;
  68         };
  69
  70         L2: cache-controller@10138000 {
  71                 compatible = "rockchip,pl310-cache", "arm,pl310-cache";
  72                 reg = <0x10138000 0x1000>;
  73                 cache-unified;
  74                 cache-level = <2>;
  75                 arm,tag-latency = <1 1 1>;
  76                 arm,data-latency = <3 1 2>;
  77                 rockchip,prefetch-ctrl = <0x70000003>;
  78                 /* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
  79                 rockchip,power-ctrl = <0x3>;
  80 /*
  81                 (0x1 << 0) |    // Full line of write zero behavior Enabled
  82                 (0x1 << 25) |   // Round-robin replacement
  83                 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
  84                 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
  85                 (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
  86 */
  87                 rockchip,aux-ctrl = <0x72000001 (~0x72000001)>;
  88         };
  89
  90         cpu_axi_bus: cpu_axi_bus@10128000 {
  91                 compatible = "rockchip,cpu_axi_bus";
  92                 reg = <0x10128000 0x8000>;
  93                 qos {
  94                         dmac {
  95                                 rockchip,offset = <0x1000>;
  96                                 rockchip,priority = <0 0>;
  97                         };
  98                         cpu0 {
  99                                 rockchip,offset = <0x2000>;
 100                                 rockchip,priority = <0 0>;
 101                         };
 102                         cpu1r {
 103                                 rockchip,offset = <0x2080>;
 104                                 rockchip,priority = <0 0>;
 105                         };
 106                         cpu1w {
 107                                 rockchip,offset = <0x2100>;
 108                                 rockchip,priority = <0 0>;
 109                         };
 110                         peri {
 111                                 rockchip,offset = <0x4000>;
 112                                 rockchip,priority = <2 2>;
 113                         };
 114                         gpu {
 115                                 rockchip,offset = <0x5000>;
 116                                 rockchip,priority = <2 1>;
 117                         };
 118                         vpu {
 119                                 rockchip,offset = <0x6000>;
 120                         };
 121                         vop0 {
 122                                 rockchip,offset = <0x7000>;
 123                                 rockchip,priority = <3 3>;
 124                         };
 125                         cif0 {
 126                                 rockchip,offset = <0x7080>;
 127                         };
 128                         ipp {
 129                                 rockchip,offset = <0x7100>;
 130                         };
 131                         vop1 {
 132                                 rockchip,offset = <0x7180>;
 133                                 rockchip,priority = <3 3>;
 134                         };
 135                         cif1 {
 136                                 rockchip,offset = <0x7200>;
 137                         };
 138                         rga {
 139                                 rockchip,offset = <0x7280>;
 140                         };
 141                 };
 142         };
 143
 144         bootrom@10120000 {
 145                 compatible = "rockchip,bootrom";
 146                 reg = <0x10120000 0x4000>;
 147         };
 148
 149         bootram@10080000 {
 150                 compatible = "rockchip,bootram";
 151                 reg = <0x10080000 0x20>; /* 32 bytes */
 152         };
 153
 154         sram: sram@10080020 {
 155                 compatible = "mmio-sram";
 156                 reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
 157                 map-exec;
 158         };
 159
 160         pmu@20004000 {
 161                 compatible = "rockchip,pmu";
 162                 reg = <0x20004000 0x4000>;
 163         };
 164
 165         timer@20038000 {
 166                 compatible = "rockchip,timer";
 167                 reg = <0x20038000 0x20>;
 168                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 169                 rockchip,percpu = <0>;
 170         };
 171
 172         timer@20038020 {
 173                 compatible = "rockchip,timer";
 174                 reg = <0x20038020 0x20>;
 175                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 176                 rockchip,percpu = <1>;
 177         };
 178
 179         timer@20038040 {
 180                 compatible = "rockchip,timer";
 181                 reg = <0x20038040 0x20>;
 182                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 183                 rockchip,percpu = <2>;
 184         };
 185
 186         timer@20038060 {
 187                 compatible = "rockchip,timer";
 188                 reg = <0x20038060 0x20>;
 189                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 190                 rockchip,percpu = <3>;
 191         };
 192
 193         timer@20038080 {
 194                 compatible = "rockchip,timer";
 195                 reg = <0x20038080 0x20>;
 196                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 197                 rockchip,broadcast = <1>;
 198         };
 199
 200         timer@200380a0 {
 201                 compatible = "rockchip,timer";
 202                 reg = <0x200380a0 0x20>;
 203                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 204                 rockchip,clocksource = <1>;
 205         };
 206
 207         watchdog:wdt@2004c000 {
 208                 compatible = "rockchip,watch dog";
 209                 reg = <0x2004c000 0x100>;
 210                 clocks = <&clk_gates7 15>;
 211                 clock-names = "pclk_wdt";
 212                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 213                 rockchip,irq = <1>;
 214                 rockchip,timeout = <5>;
 215                 rockchip,atboot = <1>;
 216                 rockchip,debug = <0>;
 217                 status = "disabled";
 218         };
 219
 220         amba {
 221                 #address-cells = <1>;
 222                 #size-cells = <1>;
 223                 compatible = "arm,amba-bus";
 224                 interrupt-parent = <&gic>;
 225                 ranges;
 226
 227                 pdma0: pdma@20018000 {
 228                         compatible = "arm,pl330", "arm,primecell";
 229                         reg = <0x20018000 0x4000>;
 230                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 231                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 232                         #dma-cells = <1>;
 233
 234                 };
 235
 236                 pdma1: pdma@20078000 {
 237                         compatible = "arm,pl330", "arm,primecell";
 238                         reg = <0x20078000 0x4000>;
 239                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 240                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 241                         #dma-cells = <1>;
 242
 243                 };
 244         };
 245
 246
 247         uart0: serial@10124000 {
 248                 compatible = "rockchip,serial";
 249                 reg = <0x10124000 0x100>;
 250                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 251                 clock-frequency = <24000000>;
 252                 clocks = <&clk_uart0>, <&clk_gates8 0>;
 253                 clock-names = "sclk_uart", "pclk_uart";
 254                 reg-shift = <2>;
 255                 reg-io-width = <4>;
 256                 dmas = <&pdma0 0>, <&pdma0 1>;
 257                 #dma-cells = <2>;
 258                 pinctrl-names = "default";
 259                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 260                 status = "disabled";
 261         };
 262
 263         uart1: serial@10126000 {
 264                 compatible = "rockchip,serial";
 265                 reg = <0x10126000 0x100>;
 266                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 267                 clock-frequency = <24000000>;
 268                 clocks = <&clk_uart1>, <&clk_gates8 1>;
 269                 clock-names = "sclk_uart", "pclk_uart";
 270                 reg-shift = <2>;
 271                 reg-io-width = <4>;
 272                 dmas = <&pdma0 2>, <&pdma0 3>;
 273                 #dma-cells = <2>;
 274                 pinctrl-names = "default";
 275                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 276                 status = "disabled";
 277         };
 278
 279         uart2: serial@20064000 {
 280                 compatible = "rockchip,serial";
 281                 reg = <0x20064000 0x100>;
 282                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 283                 clock-frequency = <24000000>;
 284                 clocks = <&clk_uart2>, <&clk_gates8 2>;
 285                 clock-names = "sclk_uart", "pclk_uart";
 286                 current-speed = <115200>;
 287                 reg-shift = <2>;
 288                 reg-io-width = <4>;
 289                 pinctrl-names = "default";
 290                 pinctrl-0 = <&uart2_xfer>;
 291                 status = "disabled";
 292         };
 293
 294         uart3: serial@20068000 {
 295                 compatible = "rockchip,serial";
 296                 reg = <0x20068000 0x100>;
 297                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 298                 clock-frequency = <24000000>;
 299                 clocks = <&clk_uart3>, <&clk_gates8 3>;
 300                 clock-names = "sclk_uart", "pclk_uart";
 301                 reg-shift = <2>;
 302                 reg-io-width = <4>;
 303                 dmas = <&pdma1 8>, <&pdma1 9>;
 304                 #dma-cells = <2>;
 305                 pinctrl-names = "default";
 306                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 307                 status = "disabled";
 308         };
 309
 310         fiq-debugger {
 311                 compatible = "rockchip,fiq-debugger";
 312                 rockchip,serial-id = <2>;
 313                 rockchip,signal-irq = <112>;
 314                 rockchip,wake-irq = <0>;
 315                 status = "disabled";
 316         };
 317
 318         spi0: spi@20070000 {
 319                 compatible = "rockchip,rockchip-spi";
 320                 reg = <0x20070000 0x1000>;
 321                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 322                 #address-cells = <1>;
 323                 #size-cells = <0>;
 324                 pinctrl-names = "default";
 325                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 326                 rockchip,spi-src-clk = <0>;
 327                 num-cs = <2>;
 328                 clocks =<&clk_spi0>, <&clk_gates7 12>;
 329                 clock-names = "spi","pclk_spi0";
 330                 dmas = <&pdma1 10>, <&pdma1 11>;
 331                 #dma-cells = <2>;
 332                 dma-names = "tx", "rx";
 333                 status = "disabled";
 334         };
 335
 336         spi1: spi@20074000 {
 337                 compatible = "rockchip,rockchip-spi";
 338                 reg = <0x20074000 0x1000>;
 339                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 340                 #address-cells = <1>;
 341                 #size-cells = <0>;
 342                 pinctrl-names = "default";
 343                 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0 &spi1_cs1>;
 344                 rockchip,spi-src-clk = <1>;
 345                 num-cs = <2>;
 346                 clocks = <&clk_spi1>, <&clk_gates7 13>;
 347                 clock-names = "spi","pclk_spi1";
 348                 dmas = <&pdma1 12>, <&pdma1 13>;
 349                 #dma-cells = <2>;
 350                 dma-names = "tx", "rx";
 351                 status = "disabled";
 352         };
 353
 354         i2c0: i2c@2002d000 {
 355                 compatible = "rockchip,rk30-i2c";
 356                 reg = <0x2002d000 0x1000>;
 357                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 358                 #address-cells = <1>;
 359                 #size-cells = <0>;
 360                 pinctrl-names = "default", "gpio";
 361                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 362                 pinctrl-1 = <&i2c0_gpio>;
 363                 gpios = <&gpio1 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D1 GPIO_ACTIVE_LOW>;
 364                 clocks = <&clk_gates8 4>;
 365                 rockchip,check-idle = <1>;
 366                 status = "disabled";
 367         };
 368
 369         i2c1: i2c@2002f000 {
 370                 compatible = "rockchip,rk30-i2c";
 371                 reg = <0x2002f000 0x1000>;
 372                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 373                 #address-cells = <1>;
 374                 #size-cells = <0>;
 375                 pinctrl-names = "default", "gpio";
 376                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 377                 pinctrl-1 = <&i2c1_gpio>;
 378                 gpios = <&gpio1 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D3 GPIO_ACTIVE_LOW>;
 379                 clocks = <&clk_gates8 5>;
 380                 rockchip,check-idle = <1>;
 381                 status = "disabled";
 382         };
 383
 384         i2c2: i2c@20056000 {
 385                 compatible = "rockchip,rk30-i2c";
 386                 reg = <0x20056000 0x1000>;
 387                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 388                 #address-cells = <1>;
 389                 #size-cells = <0>;
 390                 pinctrl-names = "default", "gpio";
 391                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 392                 pinctrl-1 = <&i2c2_gpio>;
 393                 gpios = <&gpio1 GPIO_D4 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D5 GPIO_ACTIVE_LOW>;
 394                 clocks = <&clk_gates8 6>;
 395                 rockchip,check-idle = <1>;
 396                 status = "disabled";
 397         };
 398
 399         i2c3: i2c@2005a000 {
 400                 compatible = "rockchip,rk30-i2c";
 401                 reg = <0x2005a000 0x1000>;
 402                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 403                 #address-cells = <1>;
 404                 #size-cells = <0>;
 405                 pinctrl-names = "default", "gpio";
 406                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 407                 pinctrl-1 = <&i2c3_gpio>;
 408                 gpios = <&gpio3 GPIO_B6 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_B7 GPIO_ACTIVE_LOW>;
 409                 clocks = <&clk_gates8 7>;
 410                 rockchip,check-idle = <1>;
 411                 status = "disabled";
 412         };
 413
 414         i2c4: i2c@2005e000 {
 415                 compatible = "rockchip,rk30-i2c";
 416                 reg = <0x2005e000 0x1000>;
 417                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 418                 #address-cells = <1>;
 419                 #size-cells = <0>;
 420                 pinctrl-names = "default", "gpio";
 421                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 422                 pinctrl-1 = <&i2c4_gpio>;
 423                 gpios = <&gpio1 GPIO_D6 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D7 GPIO_ACTIVE_LOW>;
 424                 clocks = <&clk_gates8 8>;
 425                 rockchip,check-idle = <1>;
 426                 status = "disabled";
 427         };
 428
 429         clocks-init{
 430                 compatible = "rockchip,clocks-init";
 431                 rockchip,clocks-init-parent =
 432                         <&clk_core &clk_apll>,  <&aclk_cpu_mux &clk_gpll>,/*FIXME*/
 433                         <&aclk_peri_mux &clk_gpll>,     <&clk_i2s_pll_mux &clk_cpll>,
 434                         <&clk_uart_pll_mux &clk_gpll>;
 435                 rockchip,clocks-init-rate =
 436                         <&clk_core 792000000>,  <&clk_gpll 768000000>,
 437                         <&clk_cpll 594000000>,  <&aclk_cpu 192000000>,
 438                         <&hclk_cpu 96000000>,   <&pclk_cpu 48000000>,
 439                         <&pclk_ahb2apb 48000000>,       <&aclk_peri 192000000>,
 440                         <&hclk_peri 96000000>,  <&pclk_peri 48000000>,
 441                         <&clk_gpu 200000000>, <&aclk_lcdc0 300000000>,
 442                         <&aclk_lcdc1 300000000>;
 443         };
 444
 445         fb: fb{
 446                 compatible = "rockchip,rk-fb";
 447                 rockchip,disp-mode = <DUAL>;
 448         };
 449
 450         nandc: nandc {
 451                 compatible = "rockchip,rk-nandc";
 452                 reg = <0x10050000 0x4000>;
 453                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 454         };
 455
 456         lcdc0:lcdc@1010c000 {
 457                 compatible = "rockchip,rk3188-lcdc";
 458                 rockchip,prop = <PRMRY>;
 459                 rochchip,pwr18 = <0>;
 460                 reg = <0x1010c000 0x1000>;
 461                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 462                 status = "disabled";
 463         };
 464
 465         lcdc1:lcdc@1010e000 {
 466                 compatible = "rockchip,rk3188-lcdc";
 467                 rockchip,prop = <EXTEND>;
 468                 rockchip,pwr18 = <0>;
 469                 reg = <0x1010e000 0x1000>;
 470                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 471                 pinctrl-names = "default", "gpio";
 472                 pinctrl-0 = <&lcdc1_lcdc>;
 473                 pinctrl-1 = <&lcdc1_gpio>;
 474                 status = "disabled";
 475   };
 476   rga@10114000 {
 477                 compatible = "rockchip,rga";
 478                 reg = <0x10114000 0x1000>;
 479                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 480                 clocks = <&clk_gates6 10>, <&clk_gates6 11>;
 481     clock-names = "hclk_rga", "aclk_rga";
 482   };
 483
 484     adc: adc@2006c000 {
 485            compatible = "rockchip,saradc";
 486            reg = <0x2006c000 0x100>;
 487            interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 488            #io-channel-cells = <1>;
 489            io-channel-ranges;
 490            rockchip,adc-vref = <1800>;
 491            clock-frequency = <1000000>;
 492            clocks = <&clk_saradc>, <&clk_gates7 14>;
 493            clock-names = "saradc", "pclk_saradc";
 494            status = "disabled";
 495     };
 496
 497         spdif: rockchip-spdif@0x1011e000 {
 498                 compatible = "rockchip-spdif";
 499                 reg = <0x1011e000 0x2000>;
 500                 clocks = <&clk_spdif>;
 501                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 502                 dmas = <&pdma0 8>;
 503                 dma-names = "tx";
 504                 pinctrl-names = "default";
 505                 pinctrl-0 = <&spdif_tx>;
 506         };
 507
 508         i2s0: rockchip-i2s@0x1011a000 {
 509                 compatible = "rockchip-i2s";
 510                 reg = <0x1011a000 0x2000>;
 511                 i2s-id = <0>;
 512                 clocks = <&clk_i2s>;
 513                 clock-names = "i2s_clk";
 514                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 515                 dmas = <&pdma0 6>,
 516                         <&pdma0 7>;
 517                 dma-names = "tx", "rx";
 518                 pinctrl-names = "default", "sleep";
 519                 pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo>;
 520                 pinctrl-1 = <&i2s0_gpio>;
 521         };
 522
 523         pwm0: pwm@20030000{
 524                 compatible = "rockchip,pwm";
 525                 reg = <0x20030000 0x10>;
 526                 #pwm-cells = <2>;
 527                 pinctrl-names = "default";
 528                 pinctrl-0 = <&pwm0_pin>;
 529                 status = "disabled";
 530
 531         };
 532
 533         pwm1: pwm@20030010{
 534                 compatible = "rockchip,pwm";
 535                 reg = <0x20030010 0x10>; /*0x20030000*/
 536                 #pwm-cells = <2>;
 537                 pinctrl-names = "default";
 538                 pinctrl-0 = <&pwm1_pin>;
 539                 status = "disabled";
 540
 541         };
 542         pwm2: pwm@20050020{
 543                 compatible = "rockchip,pwm";
 544                 reg = <0x20050020 0x10>; /*0x20030000*/
 545                 #pwm-cells = <2>;
 546                 pinctrl-names = "default";
 547                 pinctrl-0 = <&pwm2_pin>;
 548                 status = "disabled";
 549
 550         };
 551
 552         pwm3: pwm@20050030{
 553                 compatible = "rockchip,pwm";
 554                 reg = <0x20050030 0x10>; /*0x20030000*/
 555                 #pwm-cells = <2>;
 556                 pinctrl-names = "default";
 557                 pinctrl-0 = <&pwm3_pin>;
 558                 status = "disabled";
 559
 560         };
 561         dvfs {
 562                 vd_cpu:
 563                 vd_cpu {
 564                         regulator_name="vdd_arm";
 565                         suspend_volt=<1000>; //mV
 566                         pd_a9 {
 567                                 clk_core_dvfs_table:
 568                                 clk_core {
 569                                         operating-points = <
 570                                                 /* KHz    uV */
 571                                                 312000 900000
 572                                                 504000 950000
 573                                                 816000 1000000
 574                                                 1008000 1100000
 575                                                 1200000 1200000
 576                                                 1416000 1300000
 577                                                 1608000 1350000
 578                                                 >;
 579                                 };
 580                         };
 581                 };
 582
 583                 vd_core:
 584                 vd_core {
 585                         regulator_name="vdd_logic";
 586                         suspend_volt=<1000>; //mV
 587
 588                         pd_gpu {
 589                                 clk_gpu_dvfs_table:
 590                                 clk_gpu {
 591                                         operating-points = <
 592                                                 /* KHz    uV */
 593                                                 200000 1200000
 594                                                 300000 1200000
 595                                                 400000 1200000
 596                                                 >;
 597                                 };
 598                         };
 599
 600                         pd_ddr {
 601                                 clk_ddr_dvfs_table:
 602                                 clk_ddr {
 603                                         operating-points = <
 604                                                 /* KHz    uV */
 605                                                 200000 1200000
 606                                                 300000 1200000
 607                                                 400000 1200000
 608                                                 >;
 609                                 };
 610                         };
 611                 };
 612         };
 613         ion: ion{
 614                 compatible = "rockchip,ion";
 615                 #address-cells = <1>;
 616                 #size-cells = <0>;
 617                 rockchip,ion-heap@1 { /* CMA HEAP */
 618                         compatible = "rockchip,ion-reserve";
 619                         reg = <1>;
 620                         memory-reservation = <0x00000000 0x10000000>; /* 256MB */
 621                 };
 622                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 623                         reg = <3>;
 624                 };
 625         };
 626
 627         dwc_control_usb: dwc-control-usb@200080ac {
 628                 compatible = "rockchip,rk3188-dwc-control-usb";
 629                 reg = <0x200080ac 0x4>,
 630                       <0x2000810c 0x10>,
 631                       <0x2000811c 0x10>,
 632                       <0x2000812c 0x8>,
 633                       <0x20008138 0x8>;
 634                 reg-names = "GRF_SOC_STATUS0",
 635                             "GRF_UOC0_BASE",
 636                             "GRF_UOC1_BASE",
 637                             "GRF_UOC2_BASE",
 638                             "GRF_UOC3_BASE";
 639                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 640                 interrupt-names = "bvalid";
 641                 gpios = <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D5 GPIO_ACTIVE_LOW>;
 642                 clocks = <&clk_gates4 5>;
 643                 clock-names = "hclk_usb_peri";
 644         };
 645
 646         usb@10180000 {
 647                 compatible = "rockchip,rk3188_usb20_otg";
 648                 reg = <0x10180000 0x40000>;
 649                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 650                 clocks = <&clk_otgphy0_480m>, <&clk_gates5 13>;
 651                 clock-names = "otgphy0", "hclk_otg0";
 652         };
 653
 654         usb@101c0000 {
 655                 compatible = "rockchip,rk3188_usb20_host";
 656                 reg = <0x101c0000 0x40000>;
 657                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 658                 clocks = <&clk_otgphy1_480m>, <&clk_gates7 3>;
 659                 clock-names = "otgphy1", "hclk_otg1";
 660         };
 661
 662         hsic@10240000 {
 663                 compatible = "rockchip,rk3188_rk_hsic_host";
 664                 reg = <0x10240000 0x40000>;
 665                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 666                 clocks = <&clk_hsicphy480m>, <&clk_gates7 4>,
 667                          <&clk_hsicphy12m>, <&clk_otgphy1_480m>;
 668                 clock-names = "hsicphy480m", "hclk_hsic",
 669                               "hsicphy12m", "hsic_otgphy1";
 670         };
 671
 672         vmac@10204000 {
 673                 compatible = "rockchip,vmac";
 674                 reg = <0x10204000 0x4000>;
 675                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 676                 pinctrl-names = "default", "gpio";
 677                 pinctrl-0 = <&rmii_clkoutpin &rmii_txpins &rmii_rxpins &rmii_mdpins>;
 678                 pinctrl-1 = <&rmii_clkinpin &rmii_txpins &rmii_rxpins &rmii_mdpins>;
 679         };
 680 };