arch/arm/boot/dts/rk3188.dtsi

   1
   2 #include "skeleton.dtsi"
   3 #include "rk3188-pinctrl.dtsi"
   4 #include <dt-bindings/rkfb/rk_fb.h>
   5 #include "rk3188_io_vol_domain.dtsi"
   6
   7 #include <dt-bindings/sensor-dev.h>
   8
   9 / {
  10         compatible = "rockchip,rk3188";
  11         interrupt-parent = <&gic>;
  12         rockchip,sram = <&sram>;
  13
  14         aliases {
  15                 serial0 = &uart0;
  16                 serial1 = &uart1;
  17                 serial2 = &uart2;
  18                 serial3 = &uart3;
  19                 i2c0 = &i2c0;
  20                 i2c1 = &i2c1;
  21                 i2c2 = &i2c2;
  22                 i2c3 = &i2c3;
  23                 i2c4 = &i2c4;
  24                 lcdc0 = &lcdc0;
  25                 lcdc1 = &lcdc1;
  26                 spi0 = &spi0;
  27                 spi1 = &spi1;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a9";
  37                         reg = <0>;
  38                 };
  39                 cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a9";
  42                         reg = <1>;
  43                 };
  44                 cpu@2 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a9";
  47                         reg = <2>;
  48                 };
  49                 cpu@3 {
  50                         device_type = "cpu";
  51                         compatible = "arm,cortex-a9";
  52                         reg = <3>;
  53                 };
  54         };
  55
  56         twd-wdt@1013c620 {
  57                 compatible = "arm,cortex-a9-twd-wdt";
  58                 reg = <0x1013c620 0x20>;
  59                 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  60         };
  61
  62         gic: interrupt-controller@1013d000 {
  63                 compatible = "arm,cortex-a9-gic";
  64                 interrupt-controller;
  65                 #interrupt-cells = <3>;
  66                 reg = <0x1013d000 0x1000>,
  67                       <0x1013c100 0x0100>;
  68         };
  69
  70         L2: cache-controller@10138000 {
  71                 compatible = "rockchip,pl310-cache", "arm,pl310-cache";
  72                 reg = <0x10138000 0x1000>;
  73                 cache-unified;
  74                 cache-level = <2>;
  75                 arm,tag-latency = <1 1 1>;
  76                 arm,data-latency = <3 1 2>;
  77                 rockchip,prefetch-ctrl = <0x70000003>;
  78                 /* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
  79                 rockchip,power-ctrl = <0x3>;
  80 /*
  81                 (0x1 << 0) |    // Full line of write zero behavior Enabled
  82                 (0x1 << 25) |   // Round-robin replacement
  83                 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
  84                 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
  85                 (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
  86 */
  87                 rockchip,aux-ctrl = <0x72000001 (~0x72000001)>;
  88         };
  89
  90         cpu_axi_bus: cpu_axi_bus@10128000 {
  91                 compatible = "rockchip,cpu_axi_bus";
  92                 reg = <0x10128000 0x8000>;
  93                 qos {
  94                         dmac {
  95                                 rockchip,offset = <0x1000>;
  96                                 rockchip,priority = <0 0>;
  97                         };
  98                         cpu0 {
  99                                 rockchip,offset = <0x2000>;
 100                                 rockchip,priority = <0 0>;
 101                         };
 102                         cpu1r {
 103                                 rockchip,offset = <0x2080>;
 104                                 rockchip,priority = <0 0>;
 105                         };
 106                         cpu1w {
 107                                 rockchip,offset = <0x2100>;
 108                                 rockchip,priority = <0 0>;
 109                         };
 110                         peri {
 111                                 rockchip,offset = <0x4000>;
 112                                 rockchip,priority = <2 2>;
 113                         };
 114                         gpu {
 115                                 rockchip,offset = <0x5000>;
 116                                 rockchip,priority = <2 1>;
 117                         };
 118                         vpu {
 119                                 rockchip,offset = <0x6000>;
 120                         };
 121                         vop0 {
 122                                 rockchip,offset = <0x7000>;
 123                                 rockchip,priority = <3 3>;
 124                         };
 125                         cif0 {
 126                                 rockchip,offset = <0x7080>;
 127                         };
 128                         ipp {
 129                                 rockchip,offset = <0x7100>;
 130                         };
 131                         vop1 {
 132                                 rockchip,offset = <0x7180>;
 133                                 rockchip,priority = <3 3>;
 134                         };
 135                         cif1 {
 136                                 rockchip,offset = <0x7200>;
 137                         };
 138                         rga {
 139                                 rockchip,offset = <0x7280>;
 140                         };
 141                 };
 142         };
 143
 144         bootrom@10120000 {
 145                 compatible = "rockchip,bootrom";
 146                 reg = <0x10120000 0x4000>;
 147         };
 148
 149         bootram@10080000 {
 150                 compatible = "rockchip,bootram";
 151                 reg = <0x10080000 0x20>; /* 32 bytes */
 152         };
 153
 154         sram: sram@10080020 {
 155                 compatible = "mmio-sram";
 156                 reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
 157                 map-exec;
 158         };
 159
 160         pmu@20004000 {
 161                 compatible = "rockchip,pmu";
 162                 reg = <0x20004000 0x4000>;
 163         };
 164
 165         timer@20038000 {
 166                 compatible = "rockchip,timer";
 167                 reg = <0x20038000 0x20>;
 168                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 169                 rockchip,percpu = <0>;
 170         };
 171
 172         timer@20038020 {
 173                 compatible = "rockchip,timer";
 174                 reg = <0x20038020 0x20>;
 175                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 176                 rockchip,percpu = <1>;
 177         };
 178
 179         timer@20038040 {
 180                 compatible = "rockchip,timer";
 181                 reg = <0x20038040 0x20>;
 182                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 183                 rockchip,percpu = <2>;
 184         };
 185
 186         timer@20038060 {
 187                 compatible = "rockchip,timer";
 188                 reg = <0x20038060 0x20>;
 189                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 190                 rockchip,percpu = <3>;
 191         };
 192
 193         timer@20038080 {
 194                 compatible = "rockchip,timer";
 195                 reg = <0x20038080 0x20>;
 196                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 197                 rockchip,broadcast = <1>;
 198         };
 199
 200         timer@200380a0 {
 201                 compatible = "rockchip,timer";
 202                 reg = <0x200380a0 0x20>;
 203                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 204                 rockchip,clocksource = <1>;
 205         };
 206
 207         watchdog:wdt@2004c000 {
 208                 compatible = "rockchip,watch dog";
 209                 reg = <0x2004c000 0x100>;
 210                 clocks = <&clk_gates7 15>;
 211                 clock-names = "pclk_wdt";
 212                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 213                 rockchip,irq = <1>;
 214                 rockchip,timeout = <5>;
 215                 rockchip,atboot = <1>;
 216                 rockchip,debug = <0>;
 217                 status = "disabled";
 218         };
 219
 220         amba {
 221                 #address-cells = <1>;
 222                 #size-cells = <1>;
 223                 compatible = "arm,amba-bus";
 224                 interrupt-parent = <&gic>;
 225                 ranges;
 226
 227                 pdma0: pdma@20018000 {
 228                         compatible = "arm,pl330", "arm,primecell";
 229                         reg = <0x20018000 0x4000>;
 230                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 231                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 232                         #dma-cells = <1>;
 233                 };
 234
 235                 pdma1: pdma@20078000 {
 236                         compatible = "arm,pl330", "arm,primecell";
 237                         reg = <0x20078000 0x4000>;
 238                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 239                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 240                         #dma-cells = <1>;
 241                 };
 242         };
 243
 244         uart0: serial@10124000 {
 245                 compatible = "rockchip,serial";
 246                 reg = <0x10124000 0x100>;
 247                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 248                 clock-frequency = <24000000>;
 249                 clocks = <&clk_uart0>, <&clk_gates8 0>;
 250                 clock-names = "sclk_uart", "pclk_uart";
 251                 reg-shift = <2>;
 252                 reg-io-width = <4>;
 253                 dmas = <&pdma0 0>, <&pdma0 1>;
 254                 #dma-cells = <2>;
 255                 pinctrl-names = "default";
 256                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 257                 status = "disabled";
 258         };
 259
 260         uart1: serial@10126000 {
 261                 compatible = "rockchip,serial";
 262                 reg = <0x10126000 0x100>;
 263                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 264                 clock-frequency = <24000000>;
 265                 clocks = <&clk_uart1>, <&clk_gates8 1>;
 266                 clock-names = "sclk_uart", "pclk_uart";
 267                 reg-shift = <2>;
 268                 reg-io-width = <4>;
 269                 dmas = <&pdma0 2>, <&pdma0 3>;
 270                 #dma-cells = <2>;
 271                 pinctrl-names = "default";
 272                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 273                 status = "disabled";
 274         };
 275
 276         uart2: serial@20064000 {
 277                 compatible = "rockchip,serial";
 278                 reg = <0x20064000 0x100>;
 279                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 280                 clock-frequency = <24000000>;
 281                 clocks = <&clk_uart2>, <&clk_gates8 2>;
 282                 clock-names = "sclk_uart", "pclk_uart";
 283                 current-speed = <115200>;
 284                 reg-shift = <2>;
 285                 reg-io-width = <4>;
 286                 pinctrl-names = "default";
 287                 pinctrl-0 = <&uart2_xfer>;
 288                 status = "disabled";
 289         };
 290
 291         uart3: serial@20068000 {
 292                 compatible = "rockchip,serial";
 293                 reg = <0x20068000 0x100>;
 294                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 295                 clock-frequency = <24000000>;
 296                 clocks = <&clk_uart3>, <&clk_gates8 3>;
 297                 clock-names = "sclk_uart", "pclk_uart";
 298                 reg-shift = <2>;
 299                 reg-io-width = <4>;
 300                 dmas = <&pdma1 8>, <&pdma1 9>;
 301                 #dma-cells = <2>;
 302                 pinctrl-names = "default";
 303                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 304                 status = "disabled";
 305         };
 306
 307         fiq-debugger {
 308                 compatible = "rockchip,fiq-debugger";
 309                 rockchip,serial-id = <2>;
 310                 rockchip,signal-irq = <112>;
 311                 rockchip,wake-irq = <0>;
 312                 status = "disabled";
 313         };
 314
 315         spi0: spi@20070000 {
 316                 compatible = "rockchip,rockchip-spi";
 317                 reg = <0x20070000 0x500>;
 318                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 319                 #address-cells = <1>;
 320                 #size-cells = <0>;
 321                 pinctrl-names = "default";
 322                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 323                 rockchip,spi-src-clk = <0>;
 324                 num-cs = <2>;
 325                 clocks =<&clk_spi0>, <&clk_gates7 12>;
 326                 clock-names = "spi","pclk_spi0";
 327                 dmas = <&pdma0 16>, <&pdma0 17>;
 328                 #dma-cells = <2>;
 329                 dma-names = "tx", "rx";
 330                 status = "disabled";
 331         };
 332
 333         spi1: spi@20074000 {
 334                 compatible = "rockchip,rockchip-spi";
 335                 reg = <0x20074000 0x500>;
 336                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 337                 #address-cells = <1>;
 338                 #size-cells = <0>;
 339                 pinctrl-names = "default";
 340                 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0 &spi1_cs1>;
 341                 rockchip,spi-src-clk = <1>;
 342                 num-cs = <2>;
 343                 clocks = <&clk_spi1>, <&clk_gates7 13>;
 344                 clock-names = "spi","pclk_spi1";
 345                 dmas = <&pdma0 16>, <&pdma0 17>;
 346                 #dma-cells = <2>;
 347                 dma-names = "tx", "rx";
 348                 status = "disabled";
 349         };
 350
 351         i2c0: i2c@2002d000 {
 352                 compatible = "rockchip,rk30-i2c";
 353                 reg = <0x2002d000 0x1000>;
 354                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 355                 #address-cells = <1>;
 356                 #size-cells = <0>;
 357                 pinctrl-names = "default", "gpio";
 358                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 359                 pinctrl-1 = <&i2c0_gpio>;
 360                 gpios = <&gpio1 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D1 GPIO_ACTIVE_LOW>;
 361                 clocks = <&clk_gates8 4>;
 362                 rockchip,check-idle = <1>;
 363                 status = "disabled";
 364         };
 365
 366         i2c1: i2c@2002f000 {
 367                 compatible = "rockchip,rk30-i2c";
 368                 reg = <0x2002f000 0x1000>;
 369                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 370                 #address-cells = <1>;
 371                 #size-cells = <0>;
 372                 pinctrl-names = "default", "gpio";
 373                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 374                 pinctrl-1 = <&i2c1_gpio>;
 375                 gpios = <&gpio1 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D3 GPIO_ACTIVE_LOW>;
 376                 clocks = <&clk_gates8 5>;
 377                 rockchip,check-idle = <1>;
 378                 status = "disabled";
 379         };
 380
 381         i2c2: i2c@20056000 {
 382                 compatible = "rockchip,rk30-i2c";
 383                 reg = <0x20056000 0x1000>;
 384                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 385                 #address-cells = <1>;
 386                 #size-cells = <0>;
 387                 pinctrl-names = "default", "gpio";
 388                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 389                 pinctrl-1 = <&i2c2_gpio>;
 390                 gpios = <&gpio1 GPIO_D4 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D5 GPIO_ACTIVE_LOW>;
 391                 clocks = <&clk_gates8 6>;
 392                 rockchip,check-idle = <1>;
 393                 status = "disabled";
 394         };
 395
 396         i2c3: i2c@2005a000 {
 397                 compatible = "rockchip,rk30-i2c";
 398                 reg = <0x2005a000 0x1000>;
 399                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 400                 #address-cells = <1>;
 401                 #size-cells = <0>;
 402                 pinctrl-names = "default", "gpio";
 403                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 404                 pinctrl-1 = <&i2c3_gpio>;
 405                 gpios = <&gpio3 GPIO_B6 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_B7 GPIO_ACTIVE_LOW>;
 406                 clocks = <&clk_gates8 7>;
 407                 rockchip,check-idle = <1>;
 408                 status = "disabled";
 409         };
 410
 411         i2c4: i2c@2005e000 {
 412                 compatible = "rockchip,rk30-i2c";
 413                 reg = <0x2005e000 0x1000>;
 414                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 415                 #address-cells = <1>;
 416                 #size-cells = <0>;
 417                 pinctrl-names = "default", "gpio";
 418                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 419                 pinctrl-1 = <&i2c4_gpio>;
 420                 gpios = <&gpio1 GPIO_D6 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D7 GPIO_ACTIVE_LOW>;
 421                 clocks = <&clk_gates8 8>;
 422                 rockchip,check-idle = <1>;
 423                 status = "disabled";
 424         };
 425
 426         clocks-init{
 427                 compatible = "rockchip,clocks-init";
 428                 rockchip,clocks-init-parent =
 429                         <&clk_core &clk_apll>,  <&aclk_cpu_mux &clk_gpll>,/*FIXME*/
 430                         <&aclk_peri_mux &clk_gpll>,     <&clk_i2s_pll_mux &clk_cpll>,
 431                         <&clk_uart_pll_mux &clk_gpll>;
 432                 rockchip,clocks-init-rate =
 433                         <&clk_core 792000000>,  <&clk_gpll 768000000>,
 434                         <&clk_cpll 594000000>,  <&aclk_cpu 192000000>,
 435                         <&hclk_cpu 96000000>,   <&pclk_cpu 48000000>,
 436                         <&pclk_ahb2apb 48000000>,       <&aclk_peri 192000000>,
 437                         <&hclk_peri 96000000>,  <&pclk_peri 48000000>,
 438                         <&clk_gpu 200000000>, <&aclk_lcdc0 300000000>,
 439                         <&aclk_lcdc1 300000000>;
 440         };
 441
 442         fb: fb{
 443                 compatible = "rockchip,rk-fb";
 444                 rockchip,disp-mode = <DUAL>;
 445         };
 446
 447         nandc: nandc {
 448                 compatible = "rockchip,rk-nandc";
 449                 reg = <0x10050000 0x4000>;
 450                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 451         };
 452
 453         lcdc0:lcdc@1010c000 {
 454                 compatible = "rockchip,rk3188-lcdc";
 455                 rockchip,prop = <PRMRY>;
 456                 rochchip,pwr18 = <0>;
 457                 reg = <0x1010c000 0x1000>;
 458                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 459                 status = "disabled";
 460         };
 461
 462         lcdc1:lcdc@1010e000 {
 463                 compatible = "rockchip,rk3188-lcdc";
 464                 rockchip,prop = <EXTEND>;
 465                 rockchip,pwr18 = <0>;
 466                 reg = <0x1010e000 0x1000>;
 467                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 468                 pinctrl-names = "default", "gpio";
 469                 pinctrl-0 = <&lcdc1_lcdc>;
 470                 pinctrl-1 = <&lcdc1_gpio>;
 471                 status = "disabled";
 472   };
 473   rga@10114000 {
 474                 compatible = "rockchip,rga";
 475                 reg = <0x10114000 0x1000>;
 476                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 477                 clocks = <&clk_gates6 10>, <&clk_gates6 11>;
 478     clock-names = "hclk_rga", "aclk_rga";
 479   };
 480
 481     adc: adc@2006c000 {
 482            compatible = "rockchip,saradc";
 483            reg = <0x2006c000 0x100>;
 484            interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 485            #io-channel-cells = <1>;
 486            io-channel-ranges;
 487            rockchip,adc-vref = <1800>;
 488            clock-frequency = <1000000>;
 489            clocks = <&clk_saradc>, <&clk_gates7 14>;
 490            clock-names = "saradc", "pclk_saradc";
 491            status = "disabled";
 492     };
 493
 494         spdif: rockchip-spdif@0x1011e000 {
 495                 compatible = "rockchip-spdif";
 496                 reg = <0x1011e000 0x2000>;
 497                 clocks = <&clk_spdif>;
 498                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 499                 dmas = <&pdma0 8>;
 500                 dma-names = "tx";
 501                 pinctrl-names = "default";
 502                 pinctrl-0 = <&spdif_tx>;
 503         };
 504
 505         i2s0: rockchip-i2s@0x1011a000 {
 506                 compatible = "rockchip-i2s";
 507                 reg = <0x1011a000 0x2000>;
 508                 i2s-id = <0>;
 509                 clocks = <&clk_i2s>;
 510                 clock-names = "i2s_clk";
 511                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 512                 dmas = <&pdma0 6>,
 513                         <&pdma0 7>;
 514                 dma-names = "tx", "rx";
 515                 pinctrl-names = "default", "sleep";
 516                 pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo>;
 517                 pinctrl-1 = <&i2s0_gpio>;
 518         };
 519
 520         pwm0: pwm@20030000{
 521                 compatible = "rockchip,pwm";
 522                 reg = <0x20030000 0x10>;
 523                 #pwm-cells = <2>;
 524                 pinctrl-names = "default";
 525                 pinctrl-0 = <&pwm0_pin>;
 526                 status = "disabled";
 527
 528         };
 529
 530         pwm1: pwm@20030010{
 531                 compatible = "rockchip,pwm";
 532                 reg = <0x20030010 0x10>; /*0x20030000*/
 533                 #pwm-cells = <2>;
 534                 pinctrl-names = "default";
 535                 pinctrl-0 = <&pwm1_pin>;
 536                 status = "disabled";
 537
 538         };
 539         pwm2: pwm@20050020{
 540                 compatible = "rockchip,pwm";
 541                 reg = <0x20050020 0x10>; /*0x20030000*/
 542                 #pwm-cells = <2>;
 543                 pinctrl-names = "default";
 544                 pinctrl-0 = <&pwm2_pin>;
 545                 status = "disabled";
 546
 547         };
 548
 549         pwm3: pwm@20050030{
 550                 compatible = "rockchip,pwm";
 551                 reg = <0x20050030 0x10>; /*0x20030000*/
 552                 #pwm-cells = <2>;
 553                 pinctrl-names = "default";
 554                 pinctrl-0 = <&pwm3_pin>;
 555                 status = "disabled";
 556
 557         };
 558         dvfs {
 559                 vd_cpu:
 560                 vd_cpu {
 561                         regulator_name="vdd_arm";
 562                         suspend_volt=<1000>; //mV
 563                         pd_a9 {
 564                                 clk_core_dvfs_table:
 565                                 clk_core {
 566                                         operating-points = <
 567                                                 /* KHz    uV */
 568                                                 312000 900000
 569                                                 504000 950000
 570                                                 816000 1000000
 571                                                 1008000 1100000
 572                                                 1200000 1200000
 573                                                 1416000 1300000
 574                                                 1608000 1350000
 575                                                 >;
 576                                 };
 577                         };
 578                 };
 579
 580                 vd_core:
 581                 vd_core {
 582                         regulator_name="vdd_logic";
 583                         suspend_volt=<1000>; //mV
 584
 585                         pd_gpu {
 586                                 clk_gpu_dvfs_table:
 587                                 clk_gpu {
 588                                         operating-points = <
 589                                                 /* KHz    uV */
 590                                                 200000 1200000
 591                                                 300000 1200000
 592                                                 400000 1200000
 593                                                 >;
 594                                 };
 595                         };
 596
 597                         pd_ddr {
 598                                 clk_ddr_dvfs_table:
 599                                 clk_ddr {
 600                                         operating-points = <
 601                                                 /* KHz    uV */
 602                                                 200000 1200000
 603                                                 300000 1200000
 604                                                 400000 1200000
 605                                                 >;
 606                                 };
 607                         };
 608                 };
 609         };
 610         ion: ion{
 611                 compatible = "rockchip,ion";
 612                 #address-cells = <1>;
 613                 #size-cells = <0>;
 614                 rockchip,ion-heap@1 { /* CMA HEAP */
 615                         reg = <1>;
 616                 };
 617                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 618                         reg = <3>;
 619                 };
 620         };
 621
 622         dwc_control_usb: dwc-control-usb@200080ac {
 623                 compatible = "rockchip,rk3188-dwc-control-usb";
 624                 reg = <0x200080ac 0x4>,
 625                       <0x2000810c 0x10>,
 626                       <0x2000811c 0x10>,
 627                       <0x2000812c 0x8>,
 628                       <0x20008138 0x8>;
 629                 reg-names = "GRF_SOC_STATUS0",
 630                             "GRF_UOC0_BASE",
 631                             "GRF_UOC1_BASE",
 632                             "GRF_UOC2_BASE",
 633                             "GRF_UOC3_BASE";
 634                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 635                 interrupt-names = "bvalid";
 636                 gpios = <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D5 GPIO_ACTIVE_LOW>;
 637                 clocks = <&clk_gates4 5>;
 638                 clock-names = "hclk_usb_peri";
 639         };
 640
 641         usb@10180000 {
 642                 compatible = "rockchip,rk3188_usb20_otg";
 643                 reg = <0x10180000 0x40000>;
 644                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 645                 clocks = <&clk_otgphy0_480m>, <&clk_gates5 13>;
 646                 clock-names = "otgphy0", "hclk_otg0";
 647         };
 648
 649         usb@101c0000 {
 650                 compatible = "rockchip,rk3188_usb20_host";
 651                 reg = <0x101c0000 0x40000>;
 652                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 653                 clocks = <&clk_otgphy1_480m>, <&clk_gates7 3>;
 654                 clock-names = "otgphy1", "hclk_otg1";
 655         };
 656
 657         hsic@10240000 {
 658                 compatible = "rockchip,rk3188_rk_hsic_host";
 659                 reg = <0x10240000 0x40000>;
 660                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 661                 clocks = <&clk_hsicphy480m>, <&clk_gates7 4>,
 662                          <&clk_hsicphy12m>, <&clk_otgphy1_480m>;
 663                 clock-names = "hsicphy480m", "hclk_hsic",
 664                               "hsicphy12m", "hsic_otgphy1";
 665         };
 666
 667         vmac@0x10204000 {
 668                 compatible = "rockchip,vmac";
 669                 reg = <0x10204000 0x4000>;
 670                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 671                 pinctrl-names = "default", "gpio";
 672                 pinctrl-0 = <&rmii_clkoutpin &rmii_txpins &rmii_rxpins &rmii_mdpins>;
 673                 pinctrl-1 = <&rmii_clkinpin &rmii_txpins &rmii_rxpins &rmii_mdpins>;
 674         };
 675 };