arch/arm/boot/dts/rk312x.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/soc/rockchip,boot-mode.h>
  46 #include <dt-bindings/clock/rk3128-cru.h>
  47
  48 / {
  49         interrupt-parent = <&gic>;
  50         #address-cells = <1>;
  51         #size-cells = <1>;
  52
  53         aliases {
  54                 serial0 = &uart0;
  55                 serial1 = &uart1;
  56                 serial2 = &uart2;
  57                 i2c0 = &i2c0;
  58                 i2c1 = &i2c1;
  59                 i2c2 = &i2c2;
  60                 i2c3 = &i2c3;
  61         };
  62
  63         cpus {
  64                 #address-cells = <1>;
  65                 #size-cells = <0>;
  66
  67                 cpu0: cpu@f00 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a7";
  70                         reg = <0xf00>;
  71                 };
  72                 cpu1: cpu@f01 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a7";
  75                         reg = <0xf01>;
  76                 };
  77                 cpu2: cpu@f02 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a7";
  80                         reg = <0xf02>;
  81                 };
  82                 cpu3: cpu@f03 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a7";
  85                         reg = <0xf03>;
  86                 };
  87         };
  88
  89         amba {
  90                 compatible = "simple-bus";
  91                 #address-cells = <1>;
  92                 #size-cells = <1>;
  93                 ranges;
  94
  95                 pdma: pdma@20078000 {
  96                         compatible = "arm,pl330", "arm,primecell";
  97                         reg = <0x20078000 0x4000>;
  98                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  99                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 100                         #dma-cells = <1>;
 101                         arm,pl330-broken-no-flushp;
 102                         peripherals-req-type-burst;
 103                         clocks = <&cru ACLK_DMAC>;
 104                         clock-names = "apb_pclk";
 105                 };
 106         };
 107
 108         arm-pmu {
 109                 compatible = "arm,cortex-a7-pmu";
 110                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 111                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 112                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 113                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 114                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 115         };
 116
 117         timer {
 118                 compatible = "arm,armv7-timer";
 119                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 120                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 121                 clock-frequency = <24000000>;
 122         };
 123
 124         xin24m: oscillator {
 125                 compatible = "fixed-clock";
 126                 clock-frequency = <24000000>;
 127                 clock-output-names = "xin24m";
 128                 #clock-cells = <0>;
 129         };
 130
 131         gic: interrupt-controller@10139000 {
 132                 compatible = "arm,cortex-a7-gic";
 133                 interrupt-controller;
 134                 #interrupt-cells = <3>;
 135                 #address-cells = <0>;
 136
 137                 reg = <0x10139000 0x1000>,
 138                       <0x1013a000 0x1000>,
 139                       <0x1013c000 0x2000>,
 140                       <0x1013e000 0x2000>;
 141                 interrupts = <GIC_PPI 9 0xf04>;
 142         };
 143
 144
 145         grf: syscon@20008000 {
 146                 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd";
 147                 reg = <0x20008000 0x1000>;
 148         };
 149
 150         timer@20044000 {
 151                 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
 152                 reg = <0x20044000 0x20>;
 153                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 154                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 155                 clock-names = "timer", "pclk";
 156         };
 157
 158         pwm0: pwm@20050000 {
 159                 compatible = "rockchip,rk3288-pwm";
 160                 reg = <0x20050000 0x10>;
 161                 #pwm-cells = <3>;
 162                 pinctrl-names = "default";
 163                 pinctrl-0 = <&pwm0_pin>;
 164                 clocks = <&cru PCLK_PWM>;
 165                 clock-names = "pwm";
 166                 status = "disabled";
 167         };
 168
 169         pwm1: pwm@20050010 {
 170                 compatible = "rockchip,rk3288-pwm";
 171                 reg = <0x20050010 0x10>;
 172                 #pwm-cells = <3>;
 173                 pinctrl-names = "default";
 174                 pinctrl-0 = <&pwm1_pin>;
 175                 clocks = <&cru PCLK_PWM>;
 176                 clock-names = "pwm";
 177                 status = "disabled";
 178         };
 179
 180         pwm2: pwm@20050020 {
 181                 compatible = "rockchip,rk3288-pwm";
 182                 reg = <0x20050020 0x10>;
 183                 #pwm-cells = <3>;
 184                 pinctrl-names = "default";
 185                 pinctrl-0 = <&pwm2_pin>;
 186                 clocks = <&cru PCLK_PWM>;
 187                 clock-names = "pwm";
 188                 status = "disabled";
 189         };
 190
 191         pwm3: pwm@20050030 {
 192                 compatible = "rockchip,rk3288-pwm";
 193                 reg = <0x20050030 0x10>;
 194                 #pwm-cells = <3>;
 195                 pinctrl-names = "default";
 196                 pinctrl-0 = <&pwm3_pin>;
 197                 clocks = <&cru PCLK_PWM>;
 198                 clock-names = "pwm";
 199                 status = "disabled";
 200         };
 201
 202         i2c1: i2c@20054000 {
 203                 compatible = "rockchip,rk3288-i2c";
 204                 reg = <0x20054000 0x1000>;
 205                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 206                 #address-cells = <1>;
 207                 #size-cells = <0>;
 208                 clock-names = "i2c";
 209                 clocks = <&cru PCLK_I2C1>;
 210                 pinctrl-names = "default";
 211                 pinctrl-0 = <&i2c1_xfer>;
 212                 status = "disabled";
 213         };
 214
 215         i2c2: i2c@20058000 {
 216                 compatible = "rockchip,rk3288-i2c";
 217                 reg = <0x20058000 0x1000>;
 218                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 219                 #address-cells = <1>;
 220                 #size-cells = <0>;
 221                 clock-names = "i2c";
 222                 clocks = <&cru PCLK_I2C2>;
 223                 pinctrl-names = "default";
 224                 pinctrl-0 = <&i2c2_xfer>;
 225                 status = "disabled";
 226         };
 227
 228         i2c3: i2c@2005c000 {
 229                 compatible = "rockchip,rk3288-i2c";
 230                 reg = <0x2005c000 0x1000>;
 231                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 232                 #address-cells = <1>;
 233                 #size-cells = <0>;
 234                 clock-names = "i2c";
 235                 clocks = <&cru PCLK_I2C3>;
 236                 pinctrl-names = "default";
 237                 pinctrl-0 = <&i2c3_xfer>;
 238                 status = "disabled";
 239         };
 240
 241         uart0: serial@20060000 {
 242                 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
 243                 reg = <0x20060000 0x100>;
 244                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 245                 clock-frequency = <24000000>;
 246                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 247                 clock-names = "baudclk", "apb_pclk";
 248                 reg-shift = <2>;
 249                 reg-io-width = <4>;
 250                 pinctrl-names = "default";
 251                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 252                 status = "disabled";
 253         };
 254
 255         uart1: serial@20064000 {
 256                 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
 257                 reg = <0x20064000 0x100>;
 258                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 259                 clock-frequency = <24000000>;
 260                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 261                 clock-names = "baudclk", "apb_pclk";
 262                 reg-shift = <2>;
 263                 reg-io-width = <4>;
 264                 pinctrl-names = "default";
 265                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 266                 status = "disabled";
 267         };
 268
 269         uart2: serial@20068000 {
 270                 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
 271                 reg = <0x20068000 0x100>;
 272                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 273                 clock-frequency = <24000000>;
 274                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 275                 clock-names = "baudclk", "apb_pclk";
 276                 reg-shift = <2>;
 277                 reg-io-width = <4>;
 278                 pinctrl-names = "default";
 279                 pinctrl-0 = <&uart2_xfer>;
 280                 status = "disabled";
 281         };
 282
 283         saradc: saradc@2006c000 {
 284                 compatible = "rockchip,saradc";
 285                 reg = <0x2006c000 0x100>;
 286                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 287                 #io-channel-cells = <1>;
 288                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 289                 clock-names = "saradc", "apb_pclk";
 290                 resets = <&cru SRST_SARADC>;
 291                 reset-names = "saradc-apb";
 292                 status = "disabled";
 293         };
 294
 295         i2c0: i2c@20070000 {
 296                 compatible = "rockchip,rk3288-i2c";
 297                 reg = <0x20070000 0x1000>;
 298                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 299                 #address-cells = <1>;
 300                 #size-cells = <0>;
 301                 clock-names = "i2c";
 302                 clocks = <&cru PCLK_I2C0>;
 303                 pinctrl-names = "default";
 304                 pinctrl-0 = <&i2c0_xfer>;
 305                 status = "disabled";
 306         };
 307
 308         spi0: spi@20074000 {
 309                 compatible = "rockchip,rk3288-spi";
 310                 reg = <0x20074000 0x1000>;
 311                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 312                 pinctrl-names = "default";
 313                 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
 314                 clock-names = "spiclk", "apb_pclk";
 315                 dmas = <&pdma 8>, <&pdma 9>;
 316                 dma-names = "tx", "rx";
 317                 #address-cells = <1>;
 318                 #size-cells = <0>;
 319                 status = "disabled";
 320         };
 321
 322         pinctrl: pinctrl {
 323                 compatible = "rockchip,rk3128-pinctrl";
 324                 rockchip,grf = <&grf>;
 325                 #address-cells = <1>;
 326                 #size-cells = <1>;
 327                 ranges;
 328
 329                 gpio0: gpio0@2007c000 {
 330                         compatible = "rockchip,gpio-bank";
 331                         reg = <0x2007c000 0x100>;
 332                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 333                         clocks = <&cru PCLK_GPIO0>;
 334
 335                         gpio-controller;
 336                         #gpio-cells = <2>;
 337
 338                         interrupt-controller;
 339                         #interrupt-cells = <2>;
 340                 };
 341
 342                 gpio1: gpio1@20080000 {
 343                         compatible = "rockchip,gpio-bank";
 344                         reg = <0x20080000 0x100>;
 345                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 346                         clocks = <&cru PCLK_GPIO1>;
 347
 348                         gpio-controller;
 349                         #gpio-cells = <2>;
 350
 351                         interrupt-controller;
 352                         #interrupt-cells = <2>;
 353                 };
 354
 355                 gpio2: gpio2@20084000 {
 356                         compatible = "rockchip,gpio-bank";
 357                         reg = <0x20084000 0x100>;
 358                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 359                         clocks = <&cru PCLK_GPIO2>;
 360
 361                         gpio-controller;
 362                         #gpio-cells = <2>;
 363
 364                         interrupt-controller;
 365                         #interrupt-cells = <2>;
 366                 };
 367
 368                 gpio3: gpio3@20088000 {
 369                         compatible = "rockchip,gpio-bank";
 370                         reg = <0x20088000 0x100>;
 371                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 372                         clocks = <&cru PCLK_GPIO3>;
 373
 374                         gpio-controller;
 375                         #gpio-cells = <2>;
 376
 377                         interrupt-controller;
 378                         #interrupt-cells = <2>;
 379                 };
 380
 381                 pcfg_pull_up: pcfg-pull-up {
 382                         bias-pull-up;
 383                 };
 384
 385                 pcfg_pull_down: pcfg-pull-down {
 386                         bias-pull-down;
 387                 };
 388
 389                 pcfg_pull_none: pcfg-pull-none {
 390                         bias-disable;
 391                 };
 392
 393                 emmc {
 394                         emmc_clk: emmc-clk {
 395                                 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
 396                         };
 397
 398                         emmc_cmd: emmc-cmd {
 399                                 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_up>;
 400                         };
 401
 402                         emmc_cmd1: emmc-cmd1 {
 403                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_up>;
 404                         };
 405
 406                         emmc_pwr: emmc-pwr {
 407                                 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_up>;
 408                         };
 409
 410                         emmc_bus1: emmc-bus1 {
 411                                 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>;
 412                         };
 413
 414                         emmc_bus4: emmc-bus4 {
 415                                 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>,
 416                                                 <1 RK_PD1 2 &pcfg_pull_up>,
 417                                                 <1 RK_PD2 2 &pcfg_pull_up>,
 418                                                 <1 RK_PD3 2 &pcfg_pull_up>;
 419                         };
 420
 421                         emmc_bus8: emmc-bus8 {
 422                                 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>,
 423                                                 <1 RK_PD1 2 &pcfg_pull_up>,
 424                                                 <1 RK_PD2 2 &pcfg_pull_up>,
 425                                                 <1 RK_PD3 2 &pcfg_pull_up>,
 426                                                 <1 RK_PD4 2 &pcfg_pull_up>,
 427                                                 <1 RK_PD5 2 &pcfg_pull_up>,
 428                                                 <1 RK_PD6 2 &pcfg_pull_up>,
 429                                                 <1 RK_PD7 2 &pcfg_pull_up>;
 430                         };
 431                 };
 432
 433                 i2c0 {
 434                         i2c0_xfer: i2c0-xfer {
 435                                 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
 436                                                 <0 RK_PA1 1 &pcfg_pull_none>;
 437                         };
 438                 };
 439
 440                 i2c1 {
 441                         i2c1_xfer: i2c1-xfer {
 442                                 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
 443                                                 <0 RK_PA3 1 &pcfg_pull_none>;
 444                         };
 445                 };
 446
 447                 i2c2 {
 448                         i2c2_xfer: i2c2-xfer {
 449                                 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
 450                                                 <2 RK_PC5 3 &pcfg_pull_none>;
 451                         };
 452                 };
 453
 454                 i2c3 {
 455                         i2c3_xfer: i2c3-xfer {
 456                                 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
 457                                                 <0 RK_PA7 1 &pcfg_pull_none>;
 458                         };
 459                 };
 460
 461                 uart0 {
 462                         uart0_xfer: uart0-xfer {
 463                                 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_up>,
 464                                                 <2 RK_PD3 2 &pcfg_pull_none>;
 465                         };
 466
 467                         uart0_cts: uart0-cts {
 468                                 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>;
 469                         };
 470
 471                         uart0_rts: uart0-rts {
 472                                 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>;
 473                         };
 474                 };
 475
 476                 uart1 {
 477                         uart1_xfer: uart1-xfer {
 478                                 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_up>,
 479                                                 <1 RK_PB2 2 &pcfg_pull_none>;
 480                         };
 481
 482                         uart1_cts: uart1-cts {
 483                                 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
 484                         };
 485
 486                         uart1_rts: uart1-rts {
 487                                 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
 488                         };
 489                 };
 490
 491                 uart2 {
 492                         uart2_xfer: uart2-xfer {
 493                                 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
 494                                                 <1 RK_PC3 2 &pcfg_pull_none>;
 495                         };
 496
 497                         uart2_cts: uart2-cts {
 498                                 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
 499                         };
 500
 501                         uart2_rts: uart2-rts {
 502                                 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
 503                         };
 504                 };
 505
 506                 sdmmc {
 507                         sdmmc_clk: sdmmc-clk {
 508                                 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
 509                         };
 510
 511                         sdmmc_cmd: sdmmc-cmd {
 512                                 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_up>;
 513                         };
 514
 515                         sdmmc_wp: sdmmc-wp {
 516                                 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up>;
 517                         };
 518
 519                         sdmmc_pwren: sdmmc-pwren {
 520                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up>;
 521                         };
 522
 523                         sdmmc_bus4: sdmmc-bus4 {
 524                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up>,
 525                                                 <1 RK_PC3 1 &pcfg_pull_up>,
 526                                                 <1 RK_PC4 1 &pcfg_pull_up>,
 527                                                 <1 RK_PC5 1 &pcfg_pull_up>;
 528                         };
 529                 };
 530
 531                 sdio {
 532                         sdio_clk: sdio-clk {
 533                                 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>;
 534                         };
 535
 536                         sdio_cmd: sdio-cmd {
 537                                 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_up>;
 538                         };
 539
 540                         sdio_pwren: sdio-pwren {
 541                                 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>;
 542                         };
 543
 544                         sdio_bus4: sdio-bus4 {
 545                                 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_up>,
 546                                                 <1 RK_PA2 2 &pcfg_pull_up>,
 547                                                 <1 RK_PA4 2 &pcfg_pull_up>,
 548                                                 <1 RK_PA5 2 &pcfg_pull_up>;
 549                         };
 550                 };
 551
 552                 hdmi {
 553                         hdmii2c_xfer: hdmii2c-xfer {
 554                                 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
 555                                                 <0 RK_PA7 2 &pcfg_pull_none>;
 556                         };
 557                 };
 558
 559                 i2s {
 560                         i2s_bus: i2s-bus {
 561                                 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
 562                                                 <0 RK_PB1 1 &pcfg_pull_none>,
 563                                                 <0 RK_PB3 1 &pcfg_pull_none>,
 564                                                 <0 RK_PB4 1 &pcfg_pull_none>,
 565                                                 <0 RK_PB5 1 &pcfg_pull_none>,
 566                                                 <0 RK_PB6 1 &pcfg_pull_none>;
 567                         };
 568
 569                         i2s1_bus: i2s1-bus {
 570                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>,
 571                                                 <1 RK_PA1 1 &pcfg_pull_none>,
 572                                                 <1 RK_PA2 1 &pcfg_pull_none>,
 573                                                 <1 RK_PA3 1 &pcfg_pull_none>,
 574                                                 <1 RK_PA4 1 &pcfg_pull_none>,
 575                                                 <1 RK_PA5 1 &pcfg_pull_none>;
 576                         };
 577                 };
 578
 579                 pwm0 {
 580                         pwm0_pin: pwm0-pin {
 581                                 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>;
 582                         };
 583                 };
 584
 585                 pwm1 {
 586                         pwm1_pin: pwm1-pin {
 587                                 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
 588                         };
 589                 };
 590
 591                 pwm2 {
 592                         pwm2_pin: pwm2-pin {
 593                                 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
 594                         };
 595                 };
 596
 597                 pwm3 {
 598                         pwm3_pin: pwm3-pin {
 599                                 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>;
 600                         };
 601                 };
 602
 603                 spi {
 604                         spi0_clk: spi0-clk {
 605                                 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>;
 606                         };
 607
 608                         spi0_cs0: spi0-cs0 {
 609                                 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_up>;
 610                         };
 611
 612                         spi0_tx: spi0-tx {
 613                                 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>;
 614                         };
 615
 616                         spi0_rx: spi0-rx {
 617                                 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>;
 618                         };
 619
 620                         spi0_cs1: spi0-cs1 {
 621                                 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>;
 622                         };
 623
 624                         spi1_clk: spi1-clk {
 625                                 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>;
 626                         };
 627
 628                         spi1_cs0: spi1-cs0 {
 629                                 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_up>;
 630                         };
 631
 632                         spi1_tx: spi1-tx {
 633                                 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_up>;
 634                         };
 635
 636                         spi1_rx: spi1-rx {
 637                                 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_up>;
 638                         };
 639
 640                         spi1_cs1: spi1-cs1 {
 641                                 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_up>;
 642                         };
 643
 644                         spi2_clk: spi2-clk {
 645                                 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
 646                         };
 647
 648                         spi2_cs0: spi2-cs0 {
 649                                 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
 650                         };
 651
 652                         spi2_tx: spi2-tx {
 653                                 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
 654                         };
 655
 656                         spi2_rx: spi2-rx {
 657                                 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
 658                         };
 659                 };
 660         };
 661 };