arch/arm/boot/dts/rk312x-clocks.dtsi

   1 /*
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <dt-bindings/clock/rockchip,rk312x.h>
  15
  16 /{
  17
  18         clocks {
  19                 compatible = "rockchip,rk-clocks";
  20                 #address-cells = <1>;
  21                 #size-cells = <1>;
  22                 ranges = <0x0  0x20000000  0x1f0>;
  23
  24                 fixed_rate_cons {
  25                         compatible = "rockchip,rk-fixed-rate-cons";
  26
  27                         xin24m: xin24m {
  28                                 compatible = "rockchip,rk-fixed-clock";
  29                                 clock-output-names = "xin24m";
  30                                 clock-frequency = <24000000>;
  31                                 #clock-cells = <0>;
  32                         };
  33
  34                         xin12m: xin12m {
  35                                 compatible = "rockchip,rk-fixed-clock";
  36                                 clocks = <&xin24m>;
  37                                 clock-output-names = "xin12m";
  38                                 clock-frequency = <12000000>;
  39                                 #clock-cells = <0>;
  40                         };
  41
  42                         gmac_clkin: rmii_clkin {
  43                                 compatible = "rockchip,rk-fixed-clock";
  44                                 clock-output-names = "gmac_clkin";
  45                                 clock-frequency = <0>;
  46                                 #clock-cells = <0>;
  47                         };
  48
  49                         usb480m: usb480m {
  50                                 compatible = "rockchip,rk-fixed-clock";
  51                                 clock-output-names = "usb480m";
  52                                 clock-frequency = <480000000>;
  53                                 #clock-cells = <0>;
  54                         };
  55
  56                         i2s_clkin: i2s_clkin {
  57                                 compatible = "rockchip,rk-fixed-clock";
  58                                 clock-output-names = "i2s_clkin";
  59                                 clock-frequency = <0>;
  60                                 #clock-cells = <0>;
  61                         };
  62
  63                         jtag_tck: jtag_tck {
  64                                 compatible = "rockchip,rk-fixed-clock";
  65                                 clock-output-names = "jtag_tck";
  66                                 clock-frequency = <0>;
  67                                 #clock-cells = <0>;
  68                         };
  69
  70                         pclkin_cif: pclkin_cif {
  71                                 compatible = "rockchip,rk-fixed-clock";
  72                                 clock-output-names = "pclkin_cif";
  73                                 clock-frequency = <0>;
  74                                 #clock-cells = <0>;
  75                         };
  76
  77                         clk_tsp_in: clk_tsp_in {
  78                                 compatible = "rockchip,rk-fixed-clock";
  79                                 clock-output-names = "clk_tsp_in";
  80                                 clock-frequency = <0>;
  81                                 #clock-cells = <0>;
  82                         };
  83
  84
  85                         dummy: dummy {
  86                                 compatible = "rockchip,rk-fixed-clock";
  87                                 clock-output-names = "dummy";
  88                                 clock-frequency = <0>;
  89                                 #clock-cells = <0>;
  90                         };
  91
  92                         dummy_cpll: dummy_cpll {
  93                                 compatible = "rockchip,rk-fixed-clock";
  94                                 clock-output-names = "dummy_cpll";
  95                                 clock-frequency = <0>;
  96                                 #clock-cells = <0>;
  97                         };
  98
  99                 };
 100
 101                 fixed_factor_cons {
 102                         compatible = "rockchip,rk-fixed-factor-cons";
 103
 104                         clk_gpll_div2: clk_gpll_div2 {
 105                                 compatible = "rockchip,rk-fixed-factor-clock";
 106                                 clocks = <&clk_gpll>;
 107                                 clock-output-names = "clk_gpll_div2";
 108                                 clock-div = <2>;
 109                                 clock-mult = <1>;
 110                                 #clock-cells = <0>;
 111                         };
 112
 113                         clk_gpll_div3: clk_gpll_div3 {
 114                                 compatible = "rockchip,rk-fixed-factor-clock";
 115                                 clocks = <&clk_gpll>;
 116                                 clock-output-names = "clk_gpll_div3";
 117                                 clock-div = <3>;
 118                                 clock-mult = <1>;
 119                                 #clock-cells = <0>;
 120                         };
 121
 122                         clk_pvtm_func: clk_pvtm_func {
 123                                 compatible = "rockchip,rk-fixed-factor-clock";
 124                                 clocks = <&xin24m>;
 125                                 clock-output-names = "clk_pvtm_func";
 126                                 clock-div = <1>;
 127                                 clock-mult = <1>;
 128                                 #clock-cells = <0>;
 129                         };
 130
 131                         hclk_vepu: hclk_vepu {
 132                                 compatible = "rockchip,rk-fixed-factor-clock";
 133                                 clocks = <&clk_vepu>;
 134                                 clock-output-names = "hclk_vepu";
 135                                 clock-div = <4>;
 136                                 clock-mult = <1>;
 137                                 #clock-cells = <0>;
 138                         };
 139
 140                         hclk_vdpu: hclk_vdpu {
 141                                 compatible = "rockchip,rk-fixed-factor-clock";
 142                                 clocks = <&clk_vdpu>;
 143                                 clock-output-names = "hclk_vdpu";
 144                                 clock-div = <4>;
 145                                 clock-mult = <1>;
 146                                 #clock-cells = <0>;
 147                         };
 148
 149                         pclkin_cif_inv: pclkin_cif_inv {
 150                                 compatible = "rockchip,rk-fixed-factor-clock";
 151                                 clocks = <&clk_gates3 3>;
 152                                 clock-output-names = "pclkin_cif_inv";
 153                                 clock-div = <1>;
 154                                 clock-mult = <1>;
 155                                 #clock-cells = <0>;
 156                         };
 157
 158                 };
 159
 160                 pd_cons {
 161                         compatible = "rockchip,rk-pd-cons";
 162
 163                         pd_gpu: pd_gpu {
 164                                 compatible = "rockchip,rk-pd-clock";
 165                                 clock-output-names = "pd_gpu";
 166                                 rockchip,pd-id = <CLK_PD_GPU>;
 167                                 #clock-cells = <0>;
 168                         };
 169
 170                         pd_video: pd_video {
 171                                 compatible = "rockchip,rk-pd-clock";
 172                                 clock-output-names = "pd_video";
 173                                 rockchip,pd-id = <CLK_PD_VIDEO>;
 174                                 #clock-cells = <0>;
 175                         };
 176
 177                         pd_vio: pd_vio {
 178                                 compatible = "rockchip,rk-pd-clock";
 179                                 clock-output-names = "pd_vio";
 180                                 rockchip,pd-id = <CLK_PD_VIO>;
 181                                 #clock-cells = <0>;
 182                         };
 183
 184                         pd_vop0: pd_vop0 {
 185                                 compatible = "rockchip,rk-pd-clock";
 186                                 clocks = <&pd_vio>;
 187                                 clock-output-names = "pd_vop0";
 188                                 rockchip,pd-id = <CLK_PD_VIRT>;
 189                                 #clock-cells = <0>;
 190                         };
 191
 192                         pd_vop1: pd_vop1 {
 193                                 compatible = "rockchip,rk-pd-clock";
 194                                 clocks = <&pd_vio>;
 195                                 clock-output-names = "pd_vop1";
 196                                 rockchip,pd-id = <CLK_PD_VIRT>;
 197                                 #clock-cells = <0>;
 198                         };
 199
 200                         pd_vip: pd_vip {
 201                                 compatible = "rockchip,rk-pd-clock";
 202                                 clocks = <&pd_vio>;
 203                                 clock-output-names = "pd_vip";
 204                                 rockchip,pd-id = <CLK_PD_VIRT>;
 205                                 #clock-cells = <0>;
 206                         };
 207
 208                         pd_iep: pd_iep {
 209                                 compatible = "rockchip,rk-pd-clock";
 210                                 clocks = <&pd_vio>;
 211                                 clock-output-names = "pd_iep";
 212                                 rockchip,pd-id = <CLK_PD_VIRT>;
 213                                 #clock-cells = <0>;
 214                         };
 215
 216                         pd_rga: pd_rga {
 217                                 compatible = "rockchip,rk-pd-clock";
 218                                 clocks = <&pd_vio>;
 219                                 clock-output-names = "pd_rga";
 220                                 rockchip,pd-id = <CLK_PD_VIRT>;
 221                                 #clock-cells = <0>;
 222                         };
 223
 224                         pd_ebc: pd_ebc {
 225                                 compatible = "rockchip,rk-pd-clock";
 226                                 clocks = <&pd_vio>;
 227                                 clock-output-names = "pd_ebc";
 228                                 rockchip,pd-id = <CLK_PD_VIRT>;
 229                                 #clock-cells = <0>;
 230                         };
 231
 232                         pd_mipidsi: pd_mipidsi {
 233                                 compatible = "rockchip,rk-pd-clock";
 234                                 clocks = <&pd_vio>;
 235                                 clock-output-names = "pd_mipidsi";
 236                                 rockchip,pd-id = <CLK_PD_VIRT>;
 237                                 #clock-cells = <0>;
 238                         };
 239
 240                         pd_hdmi: pd_hdmi {
 241                                 compatible = "rockchip,rk-pd-clock";
 242                                 clocks = <&pd_vio>;
 243                                 clock-output-names = "pd_hdmi";
 244                                 rockchip,pd-id = <CLK_PD_VIRT>;
 245                                 #clock-cells = <0>;
 246                         };
 247
 248                 };
 249
 250
 251                 clock_regs {
 252                         compatible = "rockchip,rk-clock-regs";
 253                         #address-cells = <1>;
 254                         #size-cells = <1>;
 255                         reg = <0x0000 0x01f0>;
 256                         ranges;
 257
 258                         /* PLL control regs */
 259                         pll_cons {
 260                                 compatible = "rockchip,rk-pll-cons";
 261                                 #address-cells = <1>;
 262                                 #size-cells = <1>;
 263                                 ranges ;
 264
 265                                 clk_apll: pll-clk@0000 {
 266                                         compatible = "rockchip,rk3188-pll-clk";
 267                                         reg = <0x0000 0x10>;
 268                                         mode-reg = <0x0040 0>;
 269                                         status-reg = <0x0004 10>;
 270                                         clocks = <&xin24m>;
 271                                         clock-output-names = "clk_apll";
 272                                         rockchip,pll-type = <CLK_PLL_3036_APLL>;
 273                                         #clock-cells = <0>;
 274                                 };
 275
 276                                 clk_dpll: pll-clk@0010 {
 277                                         compatible = "rockchip,rk3188-pll-clk";
 278                                         reg = <0x0010 0x10>;
 279                                         mode-reg = <0x0040 4>;
 280                                         status-reg = <0x0014 10>;
 281                                         clocks = <&xin24m>;
 282                                         clock-output-names = "clk_dpll";
 283                                         rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
 284                                         #clock-cells = <0>;
 285                                 };
 286
 287                                 clk_cpll: pll-clk@0020 {
 288                                         compatible = "rockchip,rk3188-pll-clk";
 289                                         reg = <0x0020 0x10>;
 290                                         mode-reg = <0x0040 8>;
 291                                         status-reg = <0x0024 10>;
 292                                         clocks = <&xin24m>;
 293                                         clock-output-names = "clk_cpll";
 294                                         rockchip,pll-type = <CLK_PLL_312XPLUS>;
 295                                         #clock-cells = <0>;
 296                                         #clock-init-cells = <1>;
 297                                 };
 298
 299                                 clk_gpll: pll-clk@0030 {
 300                                         compatible = "rockchip,rk3188-pll-clk";
 301                                         reg = <0x0030 0x10>;
 302                                         mode-reg = <0x0040 12>;
 303                                         status-reg = <0x0034 10>;
 304                                         clocks = <&xin24m>;
 305                                         clock-output-names = "clk_gpll";
 306                                         rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
 307                                         #clock-cells = <0>;
 308                                         #clock-init-cells = <1>;
 309                                 };
 310
 311                         };
 312
 313                         /* Select control regs */
 314                         clk_sel_cons {
 315                                 compatible = "rockchip,rk-sel-cons";
 316                                 #address-cells = <1>;
 317                                 #size-cells = <1>;
 318                                 ranges;
 319
 320                                 clk_sel_con0: sel-con@0044 {
 321                                         compatible = "rockchip,rk3188-selcon";
 322                                         reg = <0x0044 0x4>;
 323                                         #address-cells = <1>;
 324                                         #size-cells = <1>;
 325
 326                                         clk_core_div: clk_core_div {
 327                                                 compatible = "rockchip,rk3188-div-con";
 328                                                 rockchip,bits = <0 5>;
 329                                                 clocks = <&clk_core>;
 330                                                 clock-output-names = "clk_core";
 331                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 332                                                 #clock-cells = <0>;
 333                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 334                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 335                                                                         CLK_SET_RATE_NO_REPARENT)>;
 336                                         };
 337
 338                                         /* reg[6:5]: reserved */
 339
 340                                         clk_core: clk_core_mux {
 341                                                 compatible = "rockchip,rk3188-mux-con";
 342                                                 rockchip,bits = <7 1>;
 343                                                 clocks = <&clk_apll>, <&clk_gpll_div2>;
 344                                                 clock-output-names = "clk_core";
 345                                                 #clock-cells = <0>;
 346                                                 #clock-init-cells = <1>;
 347                                         };
 348
 349                                         aclk_cpu_div: aclk_cpu_div {
 350                                                 compatible = "rockchip,rk3188-div-con";
 351                                                 rockchip,bits = <8 5>;
 352                                                 clocks = <&aclk_cpu>;
 353                                                 clock-output-names = "aclk_cpu";
 354                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 355                                                 #clock-cells = <0>;
 356                                                 rockchip,clkops-idx =
 357                                                         <CLKOPS_RATE_MUX_DIV>;
 358                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 359                                         };
 360
 361                                         aclk_cpu: aclk_cpu_mux {
 362                                                 compatible = "rockchip,rk3188-mux-con";
 363                                                 rockchip,bits = <13 2>;
 364                                                 clocks = <&clk_apll>, <&clk_gpll>,<&clk_gpll_div2>,<&clk_gpll_div3>;
 365                                                 clock-output-names = "aclk_cpu";
 366                                                 #clock-cells = <0>;
 367                                                 #clock-init-cells = <1>;
 368                                         };
 369
 370                                         /* reg[15]: reserved */
 371
 372                                 };
 373
 374                                 clk_sel_con1: sel-con@0048 {
 375                                         compatible = "rockchip,rk3188-selcon";
 376                                         reg = <0x0048 0x4>;
 377                                         #address-cells = <1>;
 378                                         #size-cells = <1>;
 379
 380                                         pclk_dbg_div:  pclk_dbg_div {
 381                                                 compatible = "rockchip,rk3188-div-con";
 382                                                 rockchip,bits = <0 4>;
 383                                                 clocks = <&clk_core>;
 384                                                 clock-output-names = "pclk_dbg";
 385                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 386                                                 #clock-cells = <0>;
 387                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 388                                         };
 389
 390                                         aclk_core_pre: aclk_core_pre_div {
 391                                                 compatible = "rockchip,rk3188-div-con";
 392                                                 rockchip,bits = <4 3>;
 393                                                 clocks = <&clk_core>;
 394                                                 clock-output-names = "aclk_core_pre";
 395                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 396                                                 #clock-cells = <0>;
 397                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 398                                         };
 399
 400                                         /* reg[7]: reserved */
 401
 402                                         hclk_cpu_pre: hclk_cpu_pre_div {
 403                                                 compatible = "rockchip,rk3188-div-con";
 404                                                 rockchip,bits = <8 2>;
 405                                                 clocks = <&aclk_cpu>;
 406                                                 clock-output-names = "hclk_cpu_pre";
 407                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 408                                                 #clock-cells = <0>;
 409                                                 #clock-init-cells = <1>;
 410                                         };
 411
 412                                         /* reg[11:10]: reserved */
 413
 414                                         pclk_cpu_pre: pclk_cpu_pre_div {
 415                                                 compatible = "rockchip,rk3188-div-con";
 416                                                 rockchip,bits = <12 3>;
 417                                                 clocks = <&aclk_cpu>;
 418                                                 clock-output-names = "pclk_cpu_pre";
 419                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 420                                                 #clock-cells = <0>;
 421                                                 #clock-init-cells = <1>;
 422                                         };
 423
 424                                         /* reg[15]: reserved */
 425                                 };
 426
 427                                 clk_sel_con2: sel-con@004c {
 428                                         compatible = "rockchip,rk3188-selcon";
 429                                         reg = <0x004c 0x4>;
 430                                         #address-cells = <1>;
 431                                         #size-cells = <1>;
 432
 433                                         clk_pvtm_div: clk_pvtm_div {
 434                                                 compatible = "rockchip,rk3188-mux-con";
 435                                                 rockchip,bits = <0 7>;
 436                                                 clocks = <&clk_pvtm_func>;
 437                                                 clock-output-names = "clk_pvtm";
 438                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 439                                                 #clock-cells = <0>;
 440                                                 #clock-init-cells = <1>;
 441                                         };
 442
 443                                         /* reg[7]: reserved */
 444
 445                                         clk_nandc_div: clk_nandc_div {
 446                                                 compatible = "rockchip,rk3188-div-con";
 447                                                 rockchip,bits = <8 5>;
 448                                                 clocks = <&clk_nandc>;
 449                                                 clock-output-names = "clk_nandc";
 450                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 451                                                 #clock-cells = <0>;
 452                                                 rockchip,clkops-idx =
 453                                                         <CLKOPS_RATE_MUX_DIV>;
 454                                         };
 455
 456                                         /* reg[13]: reserved */
 457
 458                                         clk_nandc: clk_nandc_mux {
 459                                                 compatible = "rockchip,rk3188-mux-con";
 460                                                 rockchip,bits = <14 2>;
 461                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
 462                                                 clock-output-names = "clk_nandc";
 463                                                 #clock-cells = <0>;
 464                                                 #clock-init-cells = <1>;
 465                                         };
 466
 467                                 };
 468
 469                                 clk_sel_con3: sel-con@0050 {
 470                                         compatible = "rockchip,rk3188-selcon";
 471                                         reg = <0x0050 0x4>;
 472                                         #address-cells = <1>;
 473                                         #size-cells = <1>;
 474
 475                                         clk_i2s_2ch_pll_div: clk_i2s_2ch_pll_div {
 476                                                 compatible = "rockchip,rk3188-div-con";
 477                                                 rockchip,bits = <0 7>;
 478                                                 clocks = <&clk_i2s_2ch_pll>;
 479                                                 clock-output-names = "clk_i2s_2ch_pll";
 480                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 481                                                 #clock-cells = <0>;
 482                                                 rockchip,clkops-idx =
 483                                                         <CLKOPS_RATE_MUX_DIV>;
 484                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 485                                         };
 486
 487                                         /* reg[7]: reserved */
 488
 489                                         clk_i2s_2ch: clk_i2s_2ch_mux {
 490                                                 compatible = "rockchip,rk3188-mux-con";
 491                                                 rockchip,bits = <8 2>;
 492                                                 clocks = <&clk_i2s_2ch_pll_div>, <&i2s_2ch_frac>, <&i2s_clkin>, <&xin12m>;
 493                                                 clock-output-names = "clk_i2s_2ch";
 494                                                 #clock-cells = <0>;
 495                                                 rockchip,clkops-idx =
 496                                                         <CLKOPS_RATE_RK3288_I2S>;
 497                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 498                                         };
 499
 500                                         /* reg[11:10]: reserved */
 501
 502                                         clk_i2s_2ch_out: clk_i2s_2ch_out_mux {
 503                                                 compatible = "rockchip,rk3188-mux-con";
 504                                                 rockchip,bits = <12 1>;
 505                                                 clocks = <&clk_i2s_2ch>, <&xin12m>;
 506                                                 clock-output-names = "i2s_clkout";
 507                                                 #clock-cells = <0>;
 508                                         };
 509
 510                                         /* reg[13]: reserved */
 511
 512                                         clk_i2s_2ch_pll: i2s_2ch_pll_mux {
 513                                                 compatible = "rockchip,rk3188-mux-con";
 514                                                 rockchip,bits = <14 2>;
 515                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
 516                                                 clock-output-names = "clk_i2s_2ch_pll";
 517                                                 #clock-cells = <0>;
 518                                                 #clock-init-cells = <1>;
 519                                         };
 520
 521                                 };
 522
 523                                 clk_sel_con4: sel-con@0054 {
 524                                         compatible = "rockchip,rk3188-selcon";
 525                                         reg = <0x0054 0x4>;
 526                                         #address-cells = <1>;
 527                                         #size-cells = <1>;
 528
 529                                         clk_tsp_div: clk_tsp_div {
 530                                                 compatible = "rockchip,rk3188-div-con";
 531                                                 rockchip,bits = <0 5>;
 532                                                 clocks = <&clk_tsp>;
 533                                                 clock-output-names = "clk_tsp";
 534                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 535                                                 #clock-cells = <0>;
 536                                                 rockchip,clkops-idx =
 537                                                         <CLKOPS_RATE_MUX_DIV>;
 538                                         };
 539
 540                                         /* reg[5]: reserved */
 541
 542                                         clk_tsp: clk_tsp_mux {
 543                                                 compatible = "rockchip,rk3188-mux-con";
 544                                                 rockchip,bits = <6 2>;
 545                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
 546                                                 clock-output-names = "clk_tsp";
 547                                                 #clock-cells = <0>;
 548                                                 #clock-init-cells = <1>;
 549                                         };
 550
 551                                         clk_24m_div: clk_24m_div {
 552                                                 compatible = "rockchip,rk3188-div-con";
 553                                                 rockchip,bits = <8 5>;
 554                                                 clocks = <&xin24m>;
 555                                                 clock-output-names = "clk_24m";
 556                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 557                                                 #clock-cells = <0>;
 558                                         };
 559
 560                                         /* reg[15:13]: reserved */
 561
 562                                 };
 563
 564
 565                                 clk_sel_con5: sel-con@0058 {
 566                                         compatible = "rockchip,rk3188-selcon";
 567                                         reg = <0x0058 0x4>;
 568                                         #address-cells = <1>;
 569                                         #size-cells = <1>;
 570
 571                                         clk_mac_pll_div: clk_mac_pll_div {
 572                                                 compatible = "rockchip,rk3188-div-con";
 573                                                 rockchip,bits = <0 5>;
 574                                                 clocks = <&clk_mac_pll>;
 575                                                 clock-output-names = "clk_mac_pll";
 576                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 577                                                 #clock-cells = <0>;
 578                                                 rockchip,clkops-idx =
 579                                                         <CLKOPS_RATE_MUX_DIV>;
 580                                                 #clock-init-cells = <1>;
 581                                         };
 582
 583                                         /* reg[5]: reserved */
 584
 585                                         clk_mac_pll: clk_mac_pll_mux {
 586                                                 compatible = "rockchip,rk3188-mux-con";
 587                                                 rockchip,bits = <6 2>;
 588                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
 589                                                 clock-output-names = "clk_mac_pll";
 590                                                 #clock-cells = <0>;
 591                                                 #clock-init-cells = <1>;
 592                                         };
 593
 594                                         /* reg[14:8]: reserved */
 595
 596                                         clk_mac_ref: clk_mac_ref_mux {
 597                                                 compatible = "rockchip,rk3188-mux-con";
 598                                                 rockchip,bits = <15 1>;
 599                                                 clocks = <&clk_mac_pll_div>, <&gmac_clkin>;
 600                                                 clock-output-names = "clk_mac_ref";
 601                                                 #clock-cells = <0>;
 602                                                 rockchip,clkops-idx =
 603                                                         <CLKOPS_RATE_MAC_REF>;
 604                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 605                                                 #clock-init-cells = <1>;
 606                                         };
 607
 608                                 };
 609
 610
 611                                 clk_sel_con6: sel-con@005c {
 612                                         compatible = "rockchip,rk3188-selcon";
 613                                         reg = <0x005c 0x4>;
 614                                         #address-cells = <1>;
 615                                         #size-cells = <1>;
 616
 617                                         spdif_div: spdif_div {
 618                                                 compatible = "rockchip,rk3188-div-con";
 619                                                 rockchip,bits = <0 7>;
 620                                                 clocks = <&clk_spdif_pll>;
 621                                                 clock-output-names = "clk_spdif_pll";
 622                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 623                                                 #clock-cells = <0>;
 624                                                 rockchip,clkops-idx =
 625                                                         <CLKOPS_RATE_MUX_DIV>;
 626                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 627                                         };
 628
 629                                         /* reg[7]: reserved */
 630
 631                                         clk_spdif: spdif_mux {
 632                                                 compatible = "rockchip,rk3188-mux-con";
 633                                                 rockchip,bits = <8 2>;
 634                                                 clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>;
 635                                                 clock-output-names = "clk_spdif";
 636                                                 #clock-cells = <0>;
 637                                                 rockchip,clkops-idx =
 638                                                         <CLKOPS_RATE_RK3288_I2S>;
 639                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 640                                         };
 641
 642                                         /* reg[13:10]: reserved */
 643
 644                                         clk_spdif_pll: spdif_pll_mux {
 645                                                 compatible = "rockchip,rk3188-mux-con";
 646                                                 rockchip,bits = <14 2>;
 647                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
 648                                                 clock-output-names = "clk_spdif_pll";
 649                                                 #clock-cells = <0>;
 650                                                 #clock-init-cells = <1>;
 651                                         };
 652
 653                                 };
 654
 655                                 clk_sel_con7: sel-con@0060 {
 656                                         compatible = "rockchip,rk3188-selcon";
 657                                         reg = <0x0060 0x4>;
 658                                         #address-cells = <1>;
 659                                         #size-cells = <1>;
 660
 661                                         i2s_2ch_frac: i2s_2ch_frac {
 662                                                 compatible = "rockchip,rk3188-frac-con";
 663                                                 clocks = <&clk_i2s_2ch_pll>;
 664                                                 clock-output-names = "i2s_2ch_frac";
 665                                                 /* numerator    denominator */
 666                                                 rockchip,bits = <0 32>;
 667                                                 rockchip,clkops-idx =
 668                                                         <CLKOPS_RATE_FRAC>;
 669                                                 #clock-cells = <0>;
 670                                         };
 671                                 };
 672
 673                                 clk_sel_con8: sel-con@0064 {
 674                                         compatible = "rockchip,rk3188-selcon";
 675                                         reg = <0x0064 0x4>;
 676                                         #address-cells = <1>;
 677                                         #size-cells = <1>;
 678
 679                                         i2s_8ch_frac: i2s_8ch_frac {
 680                                                 compatible = "rockchip,rk3188-frac-con";
 681                                                 clocks = <&clk_i2s_8ch_pll>;
 682                                                 clock-output-names = "i2s_8ch_frac";
 683                                                 /* numerator    denominator */
 684                                                 rockchip,bits = <0 32>;
 685                                                 rockchip,clkops-idx =
 686                                                         <CLKOPS_RATE_FRAC>;
 687                                                 #clock-cells = <0>;
 688                                         };
 689                                 };
 690
 691                                 clk_sel_con9: sel-con@0068 {
 692                                         compatible = "rockchip,rk3188-selcon";
 693                                         reg = <0x0068 0x4>;
 694                                         #address-cells = <1>;
 695                                         #size-cells = <1>;
 696
 697                                         clk_i2s_8ch_pll_div: clk_i2s_8ch_pll_div {
 698                                                 compatible = "rockchip,rk3188-div-con";
 699                                                 rockchip,bits = <0 7>;
 700                                                 clocks = <&clk_i2s_8ch_pll>;
 701                                                 clock-output-names = "clk_i2s_8ch_pll";
 702                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 703                                                 #clock-cells = <0>;
 704                                                 rockchip,clkops-idx =
 705                                                         <CLKOPS_RATE_MUX_DIV>;
 706                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 707                                         };
 708
 709                                         /* reg[7]: reserved */
 710
 711                                         clk_i2s_8ch: clk_i2s_8ch_mux {
 712                                                 compatible = "rockchip,rk3188-mux-con";
 713                                                 rockchip,bits = <8 2>;
 714                                                 clocks = <&clk_i2s_8ch_pll_div>, <&i2s_8ch_frac>, <&i2s_clkin>, <&xin12m>;
 715                                                 clock-output-names = "clk_i2s_8ch";
 716                                                 #clock-cells = <0>;
 717                                                 rockchip,clkops-idx =
 718                                                         <CLKOPS_RATE_RK3288_I2S>;
 719                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 720                                         };
 721
 722                                         /* reg[13:10]: reserved */
 723
 724                                         clk_i2s_8ch_pll: i2s_8ch_pll_mux {
 725                                                 compatible = "rockchip,rk3188-mux-con";
 726                                                 rockchip,bits = <14 2>;
 727                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
 728                                                 clock-output-names = "clk_i2s_8ch_pll";
 729                                                 #clock-cells = <0>;
 730                                                 #clock-init-cells = <1>;
 731                                         };
 732
 733                                 };
 734
 735                                 clk_sel_con10: sel-con@006c {
 736                                         compatible = "rockchip,rk3188-selcon";
 737                                         reg = <0x006c 0x4>;
 738                                         #address-cells = <1>;
 739                                         #size-cells = <1>;
 740
 741                                         aclk_peri_div: aclk_peri_div {
 742                                                 compatible = "rockchip,rk3188-div-con";
 743                                                 rockchip,bits = <0 5>;
 744                                                 clocks = <&aclk_peri>;
 745                                                 clock-output-names = "aclk_peri";
 746                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 747                                                 #clock-cells = <0>;
 748                                                 rockchip,clkops-idx =
 749                                                         <CLKOPS_RATE_MUX_DIV>;
 750                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 751                                         };
 752
 753                                         /* reg[7:5]: reserved */
 754
 755                                         hclk_peri_pre: hclk_peri_pre_div {
 756                                                 compatible = "rockchip,rk3188-div-con";
 757                                                 rockchip,bits = <8 2>;
 758                                                 clocks = <&aclk_peri>;
 759                                                 clock-output-names = "hclk_peri_pre";
 760                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 761                                                 rockchip,div-relations =
 762                                                                 <0x0 1
 763                                                                  0x1 2
 764                                                                  0x2 4>;
 765                                                 #clock-cells = <0>;
 766                                                 #clock-init-cells = <1>;
 767                                         };
 768
 769                                         /* reg[11:10]: reserved */
 770
 771                                         pclk_peri_pre: pclk_peri_div {
 772                                                 compatible = "rockchip,rk3188-div-con";
 773                                                 rockchip,bits = <12 2>;
 774                                                 clocks = <&aclk_peri>;
 775                                                 clock-output-names = "pclk_peri_pre";
 776                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 777                                                 rockchip,div-relations =
 778                                                                 <0x0 1
 779                                                                  0x1 2
 780                                                                  0x2 4
 781                                                                  0x3 8>;
 782                                                 #clock-cells = <0>;
 783                                                 #clock-init-cells = <1>;
 784                                         };
 785
 786                                         aclk_peri: aclk_peri_mux {
 787                                                 compatible = "rockchip,rk3188-mux-con";
 788                                                 rockchip,bits = <14 2>;
 789                                                 clocks = <&clk_gpll>,<&clk_cpll>,<&clk_gpll_div2>,<&clk_gpll_div3>;
 790                                                 clock-output-names = "aclk_peri";
 791                                                 #clock-cells = <0>;
 792                                                 #clock-init-cells = <1>;
 793                                         };
 794                                 };
 795
 796                                 clk_sel_con11: sel-con@0070 {
 797                                         compatible = "rockchip,rk3188-selcon";
 798                                         reg = <0x0070 0x4>;
 799                                         #address-cells = <1>;
 800                                         #size-cells = <1>;
 801
 802                                         clk_sdmmc0_div: clk_sdmmc0_div {
 803                                                 compatible = "rockchip,rk3188-div-con";
 804                                                 rockchip,bits = <0 6>;
 805                                                 clocks = <&clk_sdmmc0>;
 806                                                 clock-output-names = "clk_sdmmc0";
 807                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 808                                                 #clock-cells = <0>;
 809                                                 rockchip,clkops-idx =
 810                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 811                                         };
 812
 813                                         clk_sdmmc0: clk_sdmmc0_mux {
 814                                                 compatible = "rockchip,rk3188-mux-con";
 815                                                 rockchip,bits = <6 2>;
 816                                                 clocks = <&clk_cpll>,<&clk_gpll>,<&clk_gpll_div2>,<&xin24m>;
 817                                                 clock-output-names = "clk_sdmmc0";
 818                                                 #clock-cells = <0>;
 819                                                 #clock-init-cells = <1>;
 820                                         };
 821
 822                                         clk_sfc_div: clk_sfc_div {
 823                                                 compatible = "rockchip,rk3188-div-con";
 824                                                 rockchip,bits = <8 5>;
 825                                                 clocks = <&clk_sfc>;
 826                                                 clock-output-names = "clk_sfc";
 827                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 828                                                 #clock-cells = <0>;
 829                                                 rockchip,clkops-idx =
 830                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 831                                         };
 832
 833                                         /* reg[13]: reserved */
 834
 835                                         clk_sfc: clk_sfc_mux {
 836                                                 compatible = "rockchip,rk3188-mux-con";
 837                                                 rockchip,bits = <14 2>;
 838                                                 clocks = <&clk_cpll>,<&clk_gpll>,<&clk_gpll_div2>,<&xin24m>;
 839                                                 clock-output-names = "clk_sfc";
 840                                                 #clock-cells = <0>;
 841                                                 #clock-init-cells = <1>;
 842                                         };
 843
 844                                 };
 845
 846                                 clk_sel_con12: sel-con@0074 {
 847                                         compatible = "rockchip,rk3188-selcon";
 848                                         reg = <0x0074 0x4>;
 849                                         #address-cells = <1>;
 850                                         #size-cells = <1>;
 851
 852                                         clk_sdio_div: clk_sdio_div {
 853                                                 compatible = "rockchip,rk3188-div-con";
 854                                                 rockchip,bits = <0 6>;
 855                                                 clocks = <&clk_sdio>;
 856                                                 clock-output-names = "clk_sdio";
 857                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 858                                                 #clock-cells = <0>;
 859                                                 rockchip,clkops-idx =
 860                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 861                                         };
 862
 863                                         clk_sdio: clk_sdio_mux {
 864                                                 compatible = "rockchip,rk3188-mux-con";
 865                                                 rockchip,bits = <6 2>;
 866                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&xin24m>;
 867                                                 clock-output-names = "clk_sdio";
 868                                                 #clock-cells = <0>;
 869                                                 #clock-init-cells = <1>;
 870                                         };
 871
 872                                         clk_emmc_div: clk_emmc_div {
 873                                                 compatible = "rockchip,rk3188-div-con";
 874                                                 rockchip,bits = <8 6>;
 875                                                 clocks = <&clk_emmc>;
 876                                                 clock-output-names = "clk_emmc";
 877                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 878                                                 #clock-cells = <0>;
 879                                                 rockchip,clkops-idx =
 880                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 881                                         };
 882
 883                                         clk_emmc: clk_emmc_mux {
 884                                                 compatible = "rockchip,rk3188-mux-con";
 885                                                 rockchip,bits = <14 2>;
 886                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&xin24m>;
 887                                                 clock-output-names = "clk_emmc";
 888                                                 #clock-cells = <0>;
 889                                                 #clock-init-cells = <1>;
 890                                         };
 891
 892                                 };
 893
 894                                 clk_sel_con13: sel-con@0078 {
 895                                         compatible = "rockchip,rk3188-selcon";
 896                                         reg = <0x0078 0x4>;
 897                                         #address-cells = <1>;
 898                                         #size-cells = <1>;
 899
 900                                         clk_uart0_pll_div: clk_uart0_pll_div {
 901                                                 compatible = "rockchip,rk3188-div-con";
 902                                                 rockchip,bits = <0 7>;
 903                                                 clocks = <&clk_uart0_pll>;
 904                                                 clock-output-names = "clk_uart0_pll";
 905                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 906                                                 #clock-cells = <0>;
 907                                         };
 908
 909                                         /* reg[7]: reserved */
 910
 911                                         clk_uart0: clk_uart0_mux {
 912                                                 compatible = "rockchip,rk3188-mux-con";
 913                                                 rockchip,bits = <8 2>;
 914                                                 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>;
 915                                                 clock-output-names = "clk_uart0";
 916                                                 #clock-cells = <0>;
 917                                                 rockchip,clkops-idx =
 918                                                         <CLKOPS_RATE_RK3288_I2S>;
 919                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 920                                         };
 921
 922                                         /* reg[11:10]: reserved */
 923
 924                                         clk_uart0_pll: clk_uart0_pll_mux {
 925                                                 compatible = "rockchip,rk3188-mux-con";
 926                                                 rockchip,bits = <12 2>;
 927                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
 928                                                 clock-output-names = "clk_uart0_pll";
 929                                                 #clock-cells = <0>;
 930                                                 #clock-init-cells = <1>;
 931                                         };
 932
 933                                         clk_uart2_pll: clk_uart2_pll_mux {
 934                                                 compatible = "rockchip,rk3188-mux-con";
 935                                                 rockchip,bits = <14 2>;
 936                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
 937                                                 clock-output-names = "clk_uart2_pll";
 938                                                 #clock-cells = <0>;
 939                                                 #clock-init-cells = <1>;
 940                                         };
 941
 942                                 };
 943
 944                                 clk_sel_con14: sel-con@007c {
 945                                         compatible = "rockchip,rk3188-selcon";
 946                                         reg = <0x007c 0x4>;
 947                                         #address-cells = <1>;
 948                                         #size-cells = <1>;
 949
 950                                         clk_uart1_div: clk_uart1_div {
 951                                                 compatible = "rockchip,rk3188-div-con";
 952                                                 rockchip,bits = <0 7>;
 953                                                 clocks = <&clk_uart2_pll>;
 954                                                 clock-output-names = "clk_uart1_div";
 955                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 956                                                 #clock-cells = <0>;
 957                                         };
 958
 959                                         /* reg[7]: reserved */
 960
 961                                         clk_uart1: clk_uart1_mux {
 962                                                 compatible = "rockchip,rk3188-mux-con";
 963                                                 rockchip,bits = <8 2>;
 964                                                 clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>;
 965                                                 clock-output-names = "clk_uart1";
 966                                                 #clock-cells = <0>;
 967                                                 rockchip,clkops-idx =
 968                                                         <CLKOPS_RATE_RK3288_I2S>;
 969                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 970                                         };
 971
 972                                         /* reg[15:10]: reserved */
 973                                 };
 974
 975                                 clk_sel_con15: sel-con@0080 {
 976                                         compatible = "rockchip,rk3188-selcon";
 977                                         reg = <0x0080 0x4>;
 978                                         #address-cells = <1>;
 979                                         #size-cells = <1>;
 980
 981                                         clk_uart2_div: clk_uart2_div {
 982                                                 compatible = "rockchip,rk3188-div-con";
 983                                                 rockchip,bits = <0 7>;
 984                                                 clocks = <&clk_uart2_pll>;
 985                                                 clock-output-names = "clk_uart2_div";
 986                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 987                                                 #clock-cells = <0>;
 988                                         };
 989
 990                                         /* reg[7]: reserved */
 991
 992                                         clk_uart2: clk_uart2_mux {
 993                                                 compatible = "rockchip,rk3188-mux-con";
 994                                                 rockchip,bits = <8 2>;
 995                                                 clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>;
 996                                                 clock-output-names = "clk_uart2";
 997                                                 #clock-cells = <0>;
 998                                                 rockchip,clkops-idx =
 999                                                         <CLKOPS_RATE_RK3288_I2S>;
1000                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1001                                         };
1002
1003                                         /* reg[15:10]: reserved */
1004                                 };
1005
1006                                 clk_sel_con17: sel-con@0088 {
1007                                         compatible = "rockchip,rk3188-selcon";
1008                                         reg = <0x0088 0x4>;
1009                                         #address-cells = <1>;
1010                                         #size-cells = <1>;
1011
1012                                         uart0_frac: uart0_frac {
1013                                                 compatible = "rockchip,rk3188-frac-con";
1014                                                 clocks = <&clk_uart0_pll>;
1015                                                 clock-output-names = "uart0_frac";
1016                                                 /* numerator    denominator */
1017                                                 rockchip,bits = <0 32>;
1018                                                 rockchip,clkops-idx =
1019                                                         <CLKOPS_RATE_FRAC>;
1020                                                 #clock-cells = <0>;
1021                                         };
1022                                 };
1023
1024                                 clk_sel_con18: sel-con@008c {
1025                                         compatible = "rockchip,rk3188-selcon";
1026                                         reg = <0x008c 0x4>;
1027                                         #address-cells = <1>;
1028                                         #size-cells = <1>;
1029
1030                                         uart1_frac: uart1_frac {
1031                                                 compatible = "rockchip,rk3188-frac-con";
1032                                                 clocks = <&clk_uart1_div>;
1033                                                 clock-output-names = "uart1_frac";
1034                                                 /* numerator    denominator */
1035                                                 rockchip,bits = <0 32>;
1036                                                 rockchip,clkops-idx =
1037                                                         <CLKOPS_RATE_FRAC>;
1038                                                 #clock-cells = <0>;
1039                                         };
1040                                 };
1041
1042                                 clk_sel_con19: sel-con@0090 {
1043                                         compatible = "rockchip,rk3188-selcon";
1044                                         reg = <0x0090 0x4>;
1045                                         #address-cells = <1>;
1046                                         #size-cells = <1>;
1047
1048                                         uart2_frac: uart2_frac {
1049                                                 compatible = "rockchip,rk3188-frac-con";
1050                                                 clocks = <&clk_uart2_div>;
1051                                                 clock-output-names = "uart2_frac";
1052                                                 /* numerator    denominator */
1053                                                 rockchip,bits = <0 32>;
1054                                                 rockchip,clkops-idx =
1055                                                         <CLKOPS_RATE_FRAC>;
1056                                                 #clock-cells = <0>;
1057                                         };
1058
1059                                 };
1060
1061                                 clk_sel_con20: sel-con@0094 {
1062                                         compatible = "rockchip,rk3188-selcon";
1063                                         reg = <0x0094 0x4>;
1064                                         #address-cells = <1>;
1065                                         #size-cells = <1>;
1066
1067                                         spdif_frac: spdif_frac {
1068                                                 compatible = "rockchip,rk3188-frac-con";
1069                                                 clocks = <&spdif_div>;
1070                                                 clock-output-names = "spdif_frac";
1071                                                 /* numerator    denominator */
1072                                                 rockchip,bits = <0 32>;
1073                                                 rockchip,clkops-idx =
1074                                                         <CLKOPS_RATE_FRAC>;
1075                                                 #clock-cells = <0>;
1076                                         };
1077
1078                                 };
1079
1080                                 clk_sel_con23: sel-con@00a0 {
1081                                         compatible = "rockchip,rk3188-selcon";
1082                                         reg = <0x00a0 0x4>;
1083                                         #address-cells = <1>;
1084                                         #size-cells = <1>;
1085
1086                                         dclk_ebc: dclk_ebc_mux {
1087                                                 compatible = "rockchip,rk3188-mux-con";
1088                                                 rockchip,bits = <0 2>;
1089                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
1090                                                 clock-output-names = "dclk_ebc";
1091                                                 #clock-cells = <0>;
1092                                                 #clock-init-cells = <1>;
1093                                         };
1094
1095                                         /* reg[7:2]: reserved */
1096
1097                                         dclk_ebc_div: dclk_ebc_div {
1098                                                 compatible = "rockchip,rk3188-div-con";
1099                                                 rockchip,bits = <8 8>;
1100                                                 clocks = <&dclk_ebc>;
1101                                                 clock-output-names = "dclk_ebc";
1102                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1103                                                 #clock-cells = <0>;
1104                                                 rockchip,clkops-idx =
1105                                                         <CLKOPS_RATE_MUX_DIV>;
1106                                         };
1107
1108                                 };
1109
1110                                 clk_sel_con24: sel-con@00a4 {
1111                                         compatible = "rockchip,rk3188-selcon";
1112                                         reg = <0x00a4 0x4>;
1113                                         #address-cells = <1>;
1114                                         #size-cells = <1>;
1115
1116                                         clk_crypto_div: clk_crypto_div {
1117                                                 compatible = "rockchip,rk3188-div-con";
1118                                                 rockchip,bits = <0 2>;
1119                                                 clocks = <&aclk_cpu>;
1120                                                 clock-output-names = "clk_crypto";
1121                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1122                                                 #clock-cells = <0>;
1123                                                 #clock-init-cells = <1>;
1124                                         };
1125
1126                                         /* reg[7:2]: reserved */
1127
1128                                         clk_saradc: clk_saradc_div {
1129                                                 compatible = "rockchip,rk3188-div-con";
1130                                                 rockchip,bits = <8 8>;
1131                                                 clocks = <&xin24m>;
1132                                                 clock-output-names = "clk_saradc";
1133                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1134                                                 #clock-cells = <0>;
1135                                                 #clock-init-cells = <1>;
1136                                         };
1137
1138                                 };
1139
1140                                 clk_sel_con25: sel-con@00a8 {
1141                                         compatible = "rockchip,rk3188-selcon";
1142                                         reg = <0x00a8 0x4>;
1143                                         #address-cells = <1>;
1144                                         #size-cells = <1>;
1145
1146                                         clk_spi0_div: clk_spi0_div {
1147                                                 compatible = "rockchip,rk3188-div-con";
1148                                                 rockchip,bits = <0 7>;
1149                                                 clocks = <&clk_spi0>;
1150                                                 clock-output-names = "clk_spi0";
1151                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1152                                                 #clock-cells = <0>;
1153                                                 rockchip,clkops-idx =
1154                                                         <CLKOPS_RATE_MUX_DIV>;
1155                                         };
1156
1157                                         /* reg[7]: reserved */
1158
1159                                         clk_spi0: clk_spi0_mux {
1160                                                 compatible = "rockchip,rk3188-mux-con";
1161                                                 rockchip,bits = <8 2>;
1162                                                 clocks = <&clk_cpll>, <&clk_gpll>,<&clk_gpll_div2>;
1163                                                 clock-output-names = "clk_spi0";
1164                                                 #clock-cells = <0>;
1165                                         };
1166
1167                                         /* reg[15:10]: reserved */
1168
1169                                 };
1170
1171                                 clk_sel_con26: sel-con@00ac {
1172                                         compatible = "rockchip,rk3188-selcon";
1173                                         reg = <0x00ac 0x4>;
1174                                         #address-cells = <1>;
1175                                         #size-cells = <1>;
1176
1177                                         ddr_div: ddr_div {
1178                                                 compatible = "rockchip,rk3188-div-con";
1179                                                 rockchip,bits = <0 2>;
1180                                                 clocks = <&clk_ddr>;
1181                                                 clock-output-names = "clk_ddr";
1182                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
1183                                                 rockchip,div-relations =
1184                                                                 <0x0 1
1185                                                                  0x1 2
1186                                                                  0x3 4>;
1187                                                 #clock-cells = <0>;
1188                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
1189                                                                         CLK_SET_RATE_NO_REPARENT)>;
1190                                                 rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
1191                                         };
1192
1193                                         /* reg[7:2]: reserved */
1194
1195                                         clk_ddr: ddr_clk_pll_mux {
1196                                                 compatible = "rockchip,rk3188-mux-con";
1197                                                 rockchip,bits = <8 1>;
1198                                                 clocks = <&clk_dpll>, <&dummy>;
1199                                                 clock-output-names = "clk_ddr";
1200                                                 #clock-cells = <0>;
1201                                         };
1202
1203                                         /* reg[15:9]: reserved */
1204                                 };
1205
1206                                 clk_sel_con27: sel-con@00b0 {
1207                                         compatible = "rockchip,rk3188-selcon";
1208                                         reg = <0x00b0 0x4>;
1209                                         #address-cells = <1>;
1210                                         #size-cells = <1>;
1211
1212                                         dclk_lcdc0: dclk_lcdc0_mux {
1213                                                 compatible = "rockchip,rk3188-mux-con";
1214                                                 rockchip,bits = <0 2>;
1215                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>;
1216                                                 clock-output-names = "dclk_lcdc0";
1217                                                 #clock-cells = <0>;
1218                                                 #clock-init-cells = <1>;
1219                                         };
1220
1221                                         /* reg[7:2]: reserved */
1222
1223                                         dclk_lcdc0_div: dclk_lcdc0_div {
1224                                                 compatible = "rockchip,rk3188-div-con";
1225                                                 rockchip,bits = <8 8>;
1226                                                 clocks = <&dclk_lcdc0>;
1227                                                 clock-output-names = "dclk_lcdc0";
1228                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1229                                                 #clock-cells = <0>;
1230                                                 rockchip,clkops-idx =
1231                                                         <CLKOPS_RATE_MUX_DIV>;
1232                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1233                                         };
1234                                 };
1235
1236                                 clk_sel_con28: sel-con@00b4 {
1237                                         compatible = "rockchip,rk3188-selcon";
1238                                         reg = <0x00b4 0x4>;
1239                                         #address-cells = <1>;
1240                                         #size-cells = <1>;
1241
1242                                         sclk_lcdc0: sclk_lcdc0_mux {
1243                                                 compatible = "rockchip,rk3188-mux-con";
1244                                                 rockchip,bits = <0 2>;
1245                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>;
1246                                                 clock-output-names = "sclk_lcdc0";
1247                                                 #clock-cells = <0>;
1248                                                 #clock-init-cells = <1>;
1249                                         };
1250
1251                                         /* reg[7:2]: reserved */
1252
1253                                         sclk_lcdc0_div: sclk_lcdc0_div {
1254                                                 compatible = "rockchip,rk3188-div-con";
1255                                                 rockchip,bits = <8 8>;
1256                                                 clocks = <&sclk_lcdc0>;
1257                                                 clock-output-names = "sclk_lcdc0";
1258                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1259                                                 #clock-cells = <0>;
1260                                                 rockchip,clkops-idx =
1261                                                         <CLKOPS_RATE_MUX_DIV>;
1262                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1263                                         };
1264                                 };
1265
1266                                 clk_sel_con29: sel-con@00b8 {
1267                                         compatible = "rockchip,rk3188-selcon";
1268                                         reg = <0x00b8 0x4>;
1269                                         #address-cells = <1>;
1270                                         #size-cells = <1>;
1271
1272                                         clk_cif_pll: clk_cif_pll_mux {
1273                                                 compatible = "rockchip,rk3188-mux-con";
1274                                                 rockchip,bits = <0 2>;
1275                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
1276                                                 clock-output-names = "clk_cif_pll";
1277                                                 #clock-cells = <0>;
1278                                                 #clock-init-cells = <1>;
1279                                         };
1280
1281                                         clk_cif_out_div: clk_cif_out_div {
1282                                                 compatible = "rockchip,rk3188-div-con";
1283                                                 rockchip,bits = <2 5>;
1284                                                 clocks = <&clk_cif_out>;
1285                                                 clock-output-names = "clk_cif_out";
1286                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1287                                                 #clock-cells = <0>;
1288                                                 rockchip,clkops-idx =
1289                                                         <CLKOPS_RATE_MUX_DIV>;
1290                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1291                                         };
1292
1293                                         clk_cif_out: clk_cif_out_mux {
1294                                                 compatible = "rockchip,rk3188-mux-con";
1295                                                 rockchip,bits = <7 1>;
1296                                                 clocks = <&clk_cif_pll>, <&xin24m>;
1297                                                 clock-output-names = "clk_cif_out";
1298                                                 #clock-cells = <0>;
1299                                                 #clock-init-cells = <1>;
1300                                         };
1301
1302                                         pclk_pmu_pre: pclk_pmu_pre_div {
1303                                                 compatible = "rockchip,rk3188-div-con";
1304                                                 rockchip,bits = <8 6>;
1305                                                 clocks = <&clk_cpll>;
1306                                                 clock-output-names = "pclk_pmu_pre";
1307                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1308                                                 #clock-cells = <0>;
1309                                                 #clock-init-cells = <1>;
1310                                         };
1311
1312                                         /* reg[15:14]: reserved */
1313                                 };
1314
1315                                 clk_sel_con30: sel-con@00bc {
1316                                         compatible = "rockchip,rk3188-selcon";
1317                                         reg = <0x00bc 0x4>;
1318                                         #address-cells = <1>;
1319                                         #size-cells = <1>;
1320
1321                                         clk_testout_div: clk_testout_div {
1322                                                 compatible = "rockchip,rk3188-div-con";
1323                                                 rockchip,bits = <0 5>;
1324                                                 clocks = <&dummy>;
1325                                                 clock-output-names = "clk_testout";
1326                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1327                                                 #clock-cells = <0>;
1328                                                 #clock-init-cells = <1>;
1329                                         };
1330
1331                                         /* reg[6:5]: reserved */
1332
1333                                         clk_cif0_in: clk_cif0_in_mux {
1334                                                 compatible = "rockchip,rk3188-mux-con";
1335                                                 rockchip,bits = <7 1>;
1336                                                 clocks = <&pclkin_cif>, <&pclkin_cif_inv>;
1337                                                 clock-output-names = "clk_cif0_in";
1338                                                 #clock-cells = <0>;
1339                                                 #clock-init-cells = <1>;
1340                                         };
1341
1342                                         hclk_vio_pre_div: hclk_vio_pre_div {
1343                                                 compatible = "rockchip,rk3188-div-con";
1344                                                 rockchip,bits = <8 5>;
1345                                                 clocks = <&hclk_vio_pre>;
1346                                                 clock-output-names = "hclk_vio_pre";
1347                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1348                                                 #clock-cells = <0>;
1349                                                 rockchip,clkops-idx =
1350                                                         <CLKOPS_RATE_MUX_DIV>;
1351                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1352                                         };
1353
1354                                         /* reg[13]: reserved */
1355
1356                                         hclk_vio_pre: hclk_vio_pre_mux {
1357                                                 compatible = "rockchip,rk3188-mux-con";
1358                                                 rockchip,bits = <14 2>;
1359                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
1360                                                 clock-output-names = "hclk_vio_pre";
1361                                                 #clock-cells = <0>;
1362                                                 #clock-init-cells = <1>;
1363                                         };
1364
1365                                 };
1366
1367                                 clk_sel_con31: sel-con@00c0 {
1368                                         compatible = "rockchip,rk3188-selcon";
1369                                         reg = <0x00c0 0x4>;
1370                                         #address-cells = <1>;
1371                                         #size-cells = <1>;
1372
1373                                         aclk_vio0_pre_div: aclk_vio0_pre_div {
1374                                                 compatible = "rockchip,rk3188-div-con";
1375                                                 rockchip,bits = <0 5>;
1376                                                 clocks = <&aclk_vio0_pre>;
1377                                                 clock-output-names = "aclk_vio0_pre";
1378                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1379                                                 #clock-cells = <0>;
1380                                                 rockchip,clkops-idx =
1381                                                         <CLKOPS_RATE_MUX_DIV>;
1382                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1383                                         };
1384
1385                                         aclk_vio0_pre: aclk_vio0_pre_mux {
1386                                                 compatible = "rockchip,rk3188-mux-con";
1387                                                 rockchip,bits = <5 3>;
1388                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1389                                                 clock-output-names = "aclk_vio0_pre";
1390                                                 #clock-cells = <0>;
1391                                                 #clock-init-cells = <1>;
1392                                         };
1393
1394                                         aclk_vio1_pre_div: aclk_vio1_pre_div {
1395                                                 compatible = "rockchip,rk3188-div-con";
1396                                                 rockchip,bits = <8 5>;
1397                                                 clocks = <&aclk_vio1_pre>;
1398                                                 clock-output-names = "aclk_vio1_pre";
1399                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1400                                                 #clock-cells = <0>;
1401                                                 rockchip,clkops-idx =
1402                                                         <CLKOPS_RATE_MUX_DIV>;
1403                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1404                                         };
1405
1406                                         aclk_vio1_pre: aclk_vio1_pre_mux {
1407                                                 compatible = "rockchip,rk3188-mux-con";
1408                                                 rockchip,bits = <13 3>;
1409                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1410                                                 clock-output-names = "aclk_vio1_pre";
1411                                                 #clock-cells = <0>;
1412                                                 #clock-init-cells = <1>;
1413                                         };
1414
1415                                 };
1416
1417                                 clk_sel_con32: sel-con@00c4 {
1418                                         compatible = "rockchip,rk3188-selcon";
1419                                         reg = <0x00c4 0x4>;
1420                                         #address-cells = <1>;
1421                                         #size-cells = <1>;
1422
1423                                         clk_vepu_div: clk_vepu_div {
1424                                                 compatible = "rockchip,rk3188-div-con";
1425                                                 rockchip,bits = <0 5>;
1426                                                 clocks = <&clk_vepu>;
1427                                                 clock-output-names = "clk_vepu";
1428                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1429                                                 #clock-cells = <0>;
1430                                                 rockchip,clkops-idx =
1431                                                         <CLKOPS_RATE_MUX_DIV>;
1432                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1433                                         };
1434
1435                                         clk_vepu: clk_vepu_mux {
1436                                                 compatible = "rockchip,rk3188-mux-con";
1437                                                 rockchip,bits = <5 3>;
1438                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1439                                                 clock-output-names = "clk_vepu";
1440                                                 #clock-cells = <0>;
1441                                                 #clock-init-cells = <1>;
1442                                         };
1443
1444                                         clk_vdpu_div: clk_vdpu_div {
1445                                                 compatible = "rockchip,rk3188-div-con";
1446                                                 rockchip,bits = <8 5>;
1447                                                 clocks = <&clk_vdpu>;
1448                                                 clock-output-names = "clk_vdpu";
1449                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1450                                                 #clock-cells = <0>;
1451                                                 rockchip,clkops-idx =
1452                                                         <CLKOPS_RATE_MUX_DIV>;
1453                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1454                                         };
1455
1456                                         clk_vdpu: clk_vdpu_mux {
1457                                                 compatible = "rockchip,rk3188-mux-con";
1458                                                 rockchip,bits = <13 3>;
1459                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1460                                                 clock-output-names = "clk_vdpu";
1461                                                 #clock-cells = <0>;
1462                                                 #clock-init-cells = <1>;
1463                                         };
1464
1465                                 };
1466
1467                                 clk_sel_con34: sel-con@00cc {
1468                                         compatible = "rockchip,rk3188-selcon";
1469                                         reg = <0x00cc 0x4>;
1470                                         #address-cells = <1>;
1471                                         #size-cells = <1>;
1472
1473                                         clk_gpu_div: clk_gpu_div {
1474                                                 compatible = "rockchip,rk3188-div-con";
1475                                                 rockchip,bits = <0 5>;
1476                                                 clocks = <&clk_gpu>;
1477                                                 clock-output-names = "clk_gpu";
1478                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1479                                                 #clock-cells = <0>;
1480                                                 rockchip,clkops-idx =
1481                                                         <CLKOPS_RATE_MUX_DIV>;
1482                                                 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
1483                                         };
1484
1485                                         clk_gpu: clk_gpu_mux {
1486                                                 compatible = "rockchip,rk3188-mux-con";
1487                                                 rockchip,bits = <5 3>;
1488                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1489                                                 clock-output-names = "clk_gpu";
1490                                                 #clock-cells = <0>;
1491                                                 #clock-init-cells = <1>;
1492                                         };
1493
1494                                         clk_hevc_core_div: clk_hevc_core_div {
1495                                                 compatible = "rockchip,rk3188-div-con";
1496                                                 rockchip,bits = <8 5>;
1497                                                 clocks = <&clk_hevc_core>;
1498                                                 clock-output-names = "clk_hevc_core";
1499                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1500                                                 #clock-cells = <0>;
1501                                                 rockchip,clkops-idx =
1502                                                         <CLKOPS_RATE_MUX_DIV>;
1503                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1504                                         };
1505
1506                                         clk_hevc_core: clk_hevc_core_mux {
1507                                                 compatible = "rockchip,rk3188-mux-con";
1508                                                 rockchip,bits = <13 3>;
1509                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1510                                                 clock-output-names = "clk_hevc_core";
1511                                                 #clock-cells = <0>;
1512                                                 #clock-init-cells = <1>;
1513                                         };
1514
1515                                 };
1516
1517                         };
1518
1519
1520                         /* Gate control regs */
1521                         clk_gate_cons {
1522                                 compatible = "rockchip,rk-gate-cons";
1523                                 #address-cells = <1>;
1524                                 #size-cells = <1>;
1525                                 ranges ;
1526
1527                                 clk_gates0: gate-clk@00d0{
1528                                         compatible = "rockchip,rk3188-gate-clk";
1529                                         reg = <0x00d0 0x4>;
1530                                         clocks =
1531                                                 <&clk_core>,            <&dummy>,
1532                                                 <&dummy>,       <&aclk_cpu>,
1533
1534                                                 <&aclk_cpu>,    <&aclk_cpu>,
1535                                                 <&dummy>,               <&clk_core>,
1536
1537                                                 <&dummy>,       <&clk_i2s_2ch_pll>,
1538                                                 <&i2s_2ch_frac>,        <&hclk_vio_pre>,
1539
1540                                                 <&aclk_cpu>,            <&clk_i2s_2ch_out>,
1541                                                 <&clk_i2s_2ch>,         <&dummy>;
1542
1543                                         clock-output-names =
1544                                                 "pclk_dbg",                     "aclk_cpu",      /*clk_cpu_cpll*/
1545                                                 "clk_ddr",              "aclk_cpu_pre",
1546
1547                                                 "hclk_cpu_pre",         "pclk_cpu_pre",
1548                                                 "clk_core",             "aclk_core_pre",
1549
1550                                                 "reserved",             "clk_i2s_2ch_pll",
1551                                                 "i2s_2ch_frac",         "hclk_vio_pre",
1552
1553                                                 "clk_crypto",           "clk_i2s_2ch_out",
1554                                                 "clk_i2s_2ch",          "clk_testout";
1555                                         rockchip,suspend-clkgating-setting=<0x0 0x0>;
1556
1557                                         #clock-cells = <1>;
1558                                 };
1559
1560                                 clk_gates1: gate-clk@00d4{
1561                                         compatible = "rockchip,rk3188-gate-clk";
1562                                         reg = <0x00d4 0x4>;
1563                                         clocks =
1564                                                 <&clk_cpll>,            <&dummy>,
1565                                                 <&dummy>,               <&jtag_tck>,
1566
1567                                                 <&aclk_vio1_pre>,               <&xin12m>,
1568                                                 <&xin12m>,              <&clk_mac_pll>,
1569
1570                                                 <&clk_uart0_pll>,               <&uart0_frac>,
1571                                                 <&clk_uart1_div>,               <&uart1_frac>,
1572
1573                                                 <&clk_uart2_div>,               <&uart2_frac>,
1574                                                 <&clk_tsp>,             <&dummy>;
1575
1576                                         clock-output-names =
1577                                                 "pclk_pmu_pre",         "reserved",
1578                                                 "reserved",             "clk_jtag",
1579
1580                                                 "aclk_vio1_pre",                "clk_otgphy0",
1581                                                 "clk_otgphy1",                  "clk_mac_pll",
1582
1583                                                 "clk_uart0_pll",        "uart0_frac",
1584                                                 "clk_uart1_div",        "uart1_frac",
1585
1586                                                 "clk_uart2_div",        "uart2_frac",
1587                                                 "clk_tsp",      "reserved";
1588
1589                                          rockchip,suspend-clkgating-setting=<0x0 0x0>;
1590                                         #clock-cells = <1>;
1591                                 };
1592
1593                                 clk_gates2: gate-clk@00d8 {
1594                                         compatible = "rockchip,rk3188-gate-clk";
1595                                         reg = <0x00d8 0x4>;
1596                                         clocks =
1597                                                 <&aclk_peri>,           <&aclk_peri>,
1598                                                 <&aclk_peri>,           <&aclk_peri>,
1599
1600                                                 <&clk_mac_ref>,         <&clk_mac_ref>,
1601                                                 <&clk_mac_ref>,         <&clk_mac_ref>,
1602
1603                                                 <&clk_saradc>,          <&clk_spi0>,
1604                                                 <&clk_spdif_pll>,               <&clk_sdmmc0>,
1605
1606                                                 <&spdif_frac>,          <&clk_sdio>,
1607                                                 <&clk_emmc>,            <&xin24m>;
1608                                         clock-output-names =
1609                                                 "aclk_peri",            "aclk_peri_pre",
1610                                                 "hclk_peri_pre",                "pclk_peri_pre",
1611
1612                                                 "clk_mac_ref",          "clk_mac_refout",
1613                                                 "clk_mac_rx",           "clk_mac_tx",
1614
1615                                                 "clk_saradc",           "clk_spi0",
1616                                                 "clk_spdif_pll",                "clk_sdmmc0",
1617
1618                                                 "spdif_frac",           "clk_sdio",
1619                                                 "clk_emmc",             "clk_mipi_24m";
1620                                             rockchip,suspend-clkgating-setting=<0x0 0x0>;
1621
1622                                         #clock-cells = <1>;
1623                                 };
1624
1625                                 clk_gates3: gate-clk@00dc {
1626                                         compatible = "rockchip,rk3188-gate-clk";
1627                                         reg = <0x00dc 0x4>;
1628                                         clocks =
1629                                                 <&aclk_vio0_pre>,               <&dclk_lcdc0>,
1630                                                 <&sclk_lcdc0>,          <&pclkin_cif>,
1631
1632                                                 <&dclk_ebc>,                    <&hclk_cpu_pre>,
1633                                                 <&hclk_peri_pre>,               <&clk_cif_pll>,
1634
1635                                                 <&pclk_cpu_pre>,                <&clk_vepu>,
1636                                                 <&clk_hevc_core>,               <&clk_vdpu>,
1637
1638                                                 <&hclk_vdpu>,           <&clk_gpu>,
1639                                                 <&aclk_peri>,           <&clk_sfc>;
1640
1641                                         clock-output-names =
1642                                                 "aclk_vio0_pre",                "dclk_lcdc0",
1643                                                 "sclk_lcdc0",           "pclkin_cif",
1644
1645                                                 "dclk_ebc",             "g_hclk_crypto",
1646                                                 "g_hclk_em_peri",               "clk_cif_pll",
1647
1648                                                 "g_pclk_hdmi",          "clk_vepu",
1649                                                 "clk_hevc_core",                "clk_vdpu",
1650
1651                                                 "hclk_vdpu",            "clk_gpu",
1652                                                 "g_hclk_gps",           "clk_sfc";
1653                                        rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
1654
1655                                         #clock-cells = <1>;
1656                                 };
1657
1658                                 clk_gates4: gate-clk@00e0{
1659                                         compatible = "rockchip,rk3188-gate-clk";
1660                                         reg = <0x00e0 0x4>;
1661                                         clocks =
1662                                                 <&hclk_peri_pre>,               <&pclk_peri_pre>,
1663                                                 <&aclk_peri>,           <&aclk_peri>,
1664
1665                                                 <&clk_i2s_8ch_pll>,             <&i2s_8ch_frac>,
1666                                                 <&clk_i2s_8ch>,         <&dummy>,
1667
1668                                                 <&dummy>,               <&dummy>,
1669                                                 <&aclk_cpu>,            <&dummy>,
1670
1671                                                 <&aclk_cpu>,            <&dummy>,
1672                                                 <&dummy>,               <&dummy>;
1673
1674                                         clock-output-names =
1675                                                 "g_hp_axi_matrix",              "g_pp_axi_matrix",
1676                                                 "g_aclk_cpu_peri",              "g_ap_axi_matrix",
1677
1678                                                 "clk_i2s_8ch_pll",              "i2s_8ch_frac",
1679                                                 "clk_i2s_8ch",          "reserved",
1680
1681                                                 "reserved",             "reserved",
1682                                                 "g_aclk_strc_sys",              "reserved",
1683
1684                                                 /* Not use these ddr gates */
1685                                                 "g_aclk_intmem",                "reserved",
1686                                                 "reserved",             "reserved";
1687
1688                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1689                                         #clock-cells = <1>;
1690                                 };
1691
1692                                 clk_gates5: gate-clk@00e4 {
1693                                         compatible = "rockchip,rk3188-gate-clk";
1694                                         reg = <0x00e4 0x4>;
1695                                         clocks =
1696                                                 <&pclk_cpu_pre>,                <&aclk_peri>,
1697                                                 <&pclk_peri_pre>,               <&dummy>,
1698
1699                                                 <&pclk_cpu_pre>,                <&dummy>,
1700                                                 <&hclk_cpu_pre>,                <&pclk_cpu_pre>,
1701
1702                                                 <&dummy>,               <&hclk_peri_pre>,
1703                                                 <&hclk_peri_pre>,               <&hclk_peri_pre>,
1704
1705                                                 <&dummy>,               <&hclk_peri_pre>,
1706                                                 <&pclk_cpu_pre>,                <&dummy>;
1707
1708                                         clock-output-names =
1709                                                 "g_pclk_mipiphy",               "g_aclk_dmac",
1710                                                 "g_pclk_efuse", "reserved",
1711
1712                                                 "g_pclk_grf",           "reserved",
1713                                                 "g_hclk_rom",           "g_pclk_ddrupctl",
1714
1715                                                 "reserved",             "g_hclk_nandc",
1716                                                 "g_hclk_sdmmc0",                "g_hclk_sdio",
1717
1718                                                 "reserved",             "g_hclk_otg0",
1719                                                 "g_pclk_acodec",                "reserved";
1720
1721                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1722
1723                                         #clock-cells = <1>;
1724                                 };
1725
1726                                 clk_gates6: gate-clk@00e8 {
1727                                         compatible = "rockchip,rk3188-gate-clk";
1728                                         reg = <0x00e8 0x4>;
1729                                         clocks =
1730                                                 <&aclk_vio0_pre>,               <&hclk_vio_pre>,
1731                                                 <&dummy>,               <&dummy>,
1732
1733                                                 <&hclk_vio_pre>,                <&aclk_vio0_pre>,
1734                                                 <&dummy>,               <&dummy>,
1735
1736                                                 <&dummy>,               <&dummy>,
1737                                                 <&hclk_vio_pre>,                        <&aclk_vio0_pre>,
1738
1739                                                 <&hclk_vio_pre>,                <&aclk_vio0_pre>,
1740                                                 <&dummy>,               <&dummy>;
1741
1742                                         clock-output-names =
1743                                                 "g_aclk_lcdc0",         "g_hclk_lcdc0",
1744                                                 "reserved",             "reserved",
1745
1746                                                 "g_hclk_cif",           "g_aclk_cif",
1747                                                 "reserved",             "reserved",
1748
1749                                                 "reserved",             "reserved",
1750                                                 "g_hclk_rga",           "g_aclk_rga",
1751
1752                                                 "g_hclk_vio_bus",               "g_aclk_vio",
1753                                                 "reserved",             "reserved";
1754
1755                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1756
1757                                         #clock-cells = <1>;
1758                                 };
1759
1760                                 clk_gates7: gate-clk@00ec {
1761                                         compatible = "rockchip,rk3188-gate-clk";
1762                                         reg = <0x00ec 0x4>;
1763                                         clocks =
1764                                                 <&hclk_peri_pre>,               <&hclk_peri_pre>,
1765                                                 <&hclk_peri_pre>,               <&hclk_peri_pre>,
1766
1767                                                 <&hclk_peri_pre>,               <&dummy>,
1768                                                 <&dummy>,               <&pclk_peri_pre>,
1769
1770                                                 <&dummy>,               <&dummy>,
1771                                                 <&pclk_peri_pre>,               <&dummy>,
1772
1773                                                 <&pclk_peri_pre>,               <&dummy>,
1774                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>;
1775
1776                                         clock-output-names =
1777                                                 "g_hclk_emmc",          "g_hclk_sfc",
1778                                                 "g_hclk_i2s_2ch",               "g_hclk_host",
1779
1780                                                 "g_hclk_i2s_8ch",               "reserved",
1781                                                 "reserved",             "g_pclk_timer",
1782
1783                                                 "reserved",             "reserved",
1784                                                 "g_pclk_pwm",           "reserved",
1785
1786                                                 "g_pclk_spi0",          "reserved",
1787                                                 "g_pclk_saradc",                "g_pclk_wdt";
1788
1789                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1790
1791                                         #clock-cells = <1>;
1792                                 };
1793
1794                                 clk_gates8: gate-clk@00f0 {
1795                                         compatible = "rockchip,rk3188-gate-clk";
1796                                         reg = <0x00f0 0x4>;
1797                                         clocks =
1798                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1799                                                 <&pclk_peri_pre>,               <&dummy>,
1800
1801                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1802                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1803
1804                                                 <&dummy>,               <&pclk_peri_pre>,
1805                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1806
1807                                                 <&pclk_peri_pre>,               <&dummy>,
1808                                                 <&dummy>,               <&dummy>;
1809
1810                                         clock-output-names =
1811                                                 "g_pclk_uart0",         "g_pclk_uart1",
1812                                                 "g_pclk_uart2",         "reserved",
1813
1814                                                 "g_pclk_i2c0",          "g_pclk_i2c1",
1815                                                 "g_pclk_i2c2",          "g_pclk_i2c3",
1816
1817                                                 "reserved",             "g_pclk_gpio0",
1818                                                 "g_pclk_gpio1",         "g_pclk_gpio2",
1819
1820                                                 "g_pclk_gpio3",         "reserved",
1821                                                 "reserved",             "reserved";
1822
1823                                         rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
1824                                         #clock-cells = <1>;
1825                                 };
1826
1827                                 clk_gates9: gate-clk@00f4 {
1828                                         compatible = "rockchip,rk3188-gate-clk";
1829                                         reg = <0x00f4 0x4>;
1830                                         clocks =
1831                                                 <&dummy>,               <&dummy>,
1832                                                 <&pclk_pmu_pre>,                <&pclk_pmu_pre>,
1833
1834                                                 <&dummy>,               <&hclk_vio_pre>,
1835                                                 <&hclk_vio_pre>,                <&hclk_vio_pre>,
1836
1837                                                 <&aclk_vio1_pre>,               <&hclk_vio_pre>,
1838                                                 <&aclk_vio1_pre>,               <&dummy>,
1839
1840                                                 <&pclk_peri_pre>,               <&hclk_peri_pre>,
1841                                                 <&hclk_peri_pre>,               <&aclk_peri>;
1842
1843                                         clock-output-names =
1844                                                 "reserved",             "reserved",
1845                                                 "g_pclk_pmu",           "g_pclk_pmu_noc",
1846
1847                                                 "reserved",             "g_hclk_vio_h2p",
1848                                                 "g_pclk_mipi",          "g_hclk_iep",
1849
1850                                                 "g_aclk_iep",           "g_hclk_ebc",
1851                                                 "g_aclk_vio1_niu",              "reserved",
1852
1853                                                 "g_pclk_sim_card",              "g_hclk_usb_peri",
1854                                                 "g_hclk_pe_arbi",               "g_aclk_peri_niu";
1855
1856                                         rockchip,suspend-clkgating-setting=<0x0 0x0>;
1857
1858                                         #clock-cells = <1>;
1859                                 };
1860
1861                                 clk_gates10: gate-clk@00f8 {
1862                                         compatible = "rockchip,rk3188-gate-clk";
1863                                         reg = <0x00f8 0x4>;
1864                                         clocks =
1865                                                 <&xin24m>,              <&xin24m>,
1866                                                 <&xin24m>,              <&xin24m>,
1867
1868                                                 <&xin24m>,              <&xin24m>,
1869                                                 <&xin24m>,              <&xin24m>,
1870
1871                                                 <&xin24m>,              <&hclk_peri_pre>,
1872                                                 <&aclk_peri>,           <&pclk_peri_pre>,
1873
1874                                                 <&hclk_peri_pre>,               <&clk_tsp_in>,
1875                                                 <&hclk_peri_pre>,               <&clk_nandc>;
1876
1877                                         clock-output-names =
1878                                                 "clk_pvtm_core",                "clk_pvtm_gpu",
1879                                                 "clk_pvtm_func",                "clk_timer0",
1880
1881                                                 "clk_timer1",           "clk_timer2",
1882                                                 "clk_timer3",           "clk_timer4",
1883
1884                                                 "clk_timer5",           "g_hclk_spdif",
1885                                                 "g_aclk_gmac",          "g_pclk_gmac",
1886
1887                                                 "g_hclk_tsp",           "g_clkin0_tsp",
1888                                                 "g_hclk_usbhost",               "clk_nandc";
1889
1890                                         rockchip,suspend-clkgating-setting = <0x0 0x0>; /* pwm logic vol */
1891
1892                                         #clock-cells = <1>;
1893                                 };
1894
1895                         };
1896                 };
1897         };
1898 };