arch/arm/boot/dts/rk312x-clocks.dtsi

   1 /*
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <dt-bindings/clock/rockchip,rk312x.h>
  15
  16 /{
  17
  18         clocks {
  19                 compatible = "rockchip,rk-clocks";
  20                 #address-cells = <1>;
  21                 #size-cells = <1>;
  22                 ranges = <0x0  0x20000000  0x1f0>;
  23
  24                 fixed_rate_cons {
  25                         compatible = "rockchip,rk-fixed-rate-cons";
  26
  27                         xin24m: xin24m {
  28                                 compatible = "rockchip,rk-fixed-clock";
  29                                 clock-output-names = "xin24m";
  30                                 clock-frequency = <24000000>;
  31                                 #clock-cells = <0>;
  32                         };
  33
  34                         xin12m: xin12m {
  35                                 compatible = "rockchip,rk-fixed-clock";
  36                                 clocks = <&xin24m>;
  37                                 clock-output-names = "xin12m";
  38                                 clock-frequency = <12000000>;
  39                                 #clock-cells = <0>;
  40                         };
  41
  42                         gmac_clkin: rmii_clkin {
  43                                 compatible = "rockchip,rk-fixed-clock";
  44                                 clock-output-names = "gmac_clkin";
  45                                 clock-frequency = <0>;
  46                                 #clock-cells = <0>;
  47                         };
  48
  49                         usb480m: usb480m {
  50                                 compatible = "rockchip,rk-fixed-clock";
  51                                 clock-output-names = "usb480m";
  52                                 clock-frequency = <480000000>;
  53                                 #clock-cells = <0>;
  54                         };
  55
  56                         i2s_clkin: i2s_clkin {
  57                                 compatible = "rockchip,rk-fixed-clock";
  58                                 clock-output-names = "i2s_clkin";
  59                                 clock-frequency = <0>;
  60                                 #clock-cells = <0>;
  61                         };
  62
  63                         jtag_tck: jtag_tck {
  64                                 compatible = "rockchip,rk-fixed-clock";
  65                                 clock-output-names = "jtag_tck";
  66                                 clock-frequency = <0>;
  67                                 #clock-cells = <0>;
  68                         };
  69
  70                         pclkin_cif: pclkin_cif {
  71                                 compatible = "rockchip,rk-fixed-clock";
  72                                 clock-output-names = "pclkin_cif";
  73                                 clock-frequency = <0>;
  74                                 #clock-cells = <0>;
  75                         };
  76
  77                         clk_tsp_in: clk_tsp_in {
  78                                 compatible = "rockchip,rk-fixed-clock";
  79                                 clock-output-names = "clk_tsp_in";
  80                                 clock-frequency = <0>;
  81                                 #clock-cells = <0>;
  82                         };
  83
  84
  85                         dummy: dummy {
  86                                 compatible = "rockchip,rk-fixed-clock";
  87                                 clock-output-names = "dummy";
  88                                 clock-frequency = <0>;
  89                                 #clock-cells = <0>;
  90                         };
  91
  92                         dummy_cpll: dummy_cpll {
  93                                 compatible = "rockchip,rk-fixed-clock";
  94                                 clock-output-names = "dummy_cpll";
  95                                 clock-frequency = <0>;
  96                                 #clock-cells = <0>;
  97                         };
  98
  99                 };
 100
 101                 fixed_factor_cons {
 102                         compatible = "rockchip,rk-fixed-factor-cons";
 103
 104                         clk_gpll_div2: clk_gpll_div2 {
 105                                 compatible = "rockchip,rk-fixed-factor-clock";
 106                                 clocks = <&clk_gpll>;
 107                                 clock-output-names = "clk_gpll_div2";
 108                                 clock-div = <2>;
 109                                 clock-mult = <1>;
 110                                 #clock-cells = <0>;
 111                         };
 112
 113                         clk_gpll_div3: clk_gpll_div3 {
 114                                 compatible = "rockchip,rk-fixed-factor-clock";
 115                                 clocks = <&clk_gpll>;
 116                                 clock-output-names = "clk_gpll_div3";
 117                                 clock-div = <3>;
 118                                 clock-mult = <1>;
 119                                 #clock-cells = <0>;
 120                         };
 121
 122                         clk_pvtm_func: clk_pvtm_func {
 123                                 compatible = "rockchip,rk-fixed-factor-clock";
 124                                 clocks = <&xin24m>;
 125                                 clock-output-names = "clk_pvtm_func";
 126                                 clock-div = <1>;
 127                                 clock-mult = <1>;
 128                                 #clock-cells = <0>;
 129                         };
 130
 131                         hclk_vepu: hclk_vepu {
 132                                 compatible = "rockchip,rk-fixed-factor-clock";
 133                                 clocks = <&clk_vepu>;
 134                                 clock-output-names = "hclk_vepu";
 135                                 clock-div = <4>;
 136                                 clock-mult = <1>;
 137                                 #clock-cells = <0>;
 138                         };
 139
 140                         hclk_vdpu: hclk_vdpu {
 141                                 compatible = "rockchip,rk-fixed-factor-clock";
 142                                 clocks = <&clk_vdpu>;
 143                                 clock-output-names = "hclk_vdpu";
 144                                 clock-div = <4>;
 145                                 clock-mult = <1>;
 146                                 #clock-cells = <0>;
 147                         };
 148
 149                         pclkin_cif_inv: pclkin_cif_inv {
 150                                 compatible = "rockchip,rk-fixed-factor-clock";
 151                                 clocks = <&clk_gates3 3>;
 152                                 clock-output-names = "pclkin_cif_inv";
 153                                 clock-div = <1>;
 154                                 clock-mult = <1>;
 155                                 #clock-cells = <0>;
 156                         };
 157
 158                 };
 159
 160                 clock_regs {
 161                         compatible = "rockchip,rk-clock-regs";
 162                         #address-cells = <1>;
 163                         #size-cells = <1>;
 164                         reg = <0x0000 0x01f0>;
 165                         ranges;
 166
 167                         /* PLL control regs */
 168                         pll_cons {
 169                                 compatible = "rockchip,rk-pll-cons";
 170                                 #address-cells = <1>;
 171                                 #size-cells = <1>;
 172                                 ranges ;
 173
 174                                 clk_apll: pll-clk@0000 {
 175                                         compatible = "rockchip,rk3188-pll-clk";
 176                                         reg = <0x0000 0x10>;
 177                                         mode-reg = <0x0040 0>;
 178                                         status-reg = <0x0004 10>;
 179                                         clocks = <&xin24m>;
 180                                         clock-output-names = "clk_apll";
 181                                         rockchip,pll-type = <CLK_PLL_3036_APLL>;
 182                                         #clock-cells = <0>;
 183                                 };
 184
 185                                 clk_dpll: pll-clk@0010 {
 186                                         compatible = "rockchip,rk3188-pll-clk";
 187                                         reg = <0x0010 0x10>;
 188                                         mode-reg = <0x0040 4>;
 189                                         status-reg = <0x0014 10>;
 190                                         clocks = <&xin24m>;
 191                                         clock-output-names = "clk_dpll";
 192                                         rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
 193                                         #clock-cells = <0>;
 194                                 };
 195
 196                                 clk_cpll: pll-clk@0020 {
 197                                         compatible = "rockchip,rk3188-pll-clk";
 198                                         reg = <0x0020 0x10>;
 199                                         mode-reg = <0x0040 8>;
 200                                         status-reg = <0x0024 10>;
 201                                         clocks = <&xin24m>;
 202                                         clock-output-names = "clk_cpll";
 203                                         rockchip,pll-type = <CLK_PLL_312XPLUS>;
 204                                         #clock-cells = <0>;
 205                                         #clock-init-cells = <1>;
 206                                 };
 207
 208                                 clk_gpll: pll-clk@0030 {
 209                                         compatible = "rockchip,rk3188-pll-clk";
 210                                         reg = <0x0030 0x10>;
 211                                         mode-reg = <0x0040 12>;
 212                                         status-reg = <0x0034 10>;
 213                                         clocks = <&xin24m>;
 214                                         clock-output-names = "clk_gpll";
 215                                         rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
 216                                         #clock-cells = <0>;
 217                                         #clock-init-cells = <1>;
 218                                 };
 219
 220                         };
 221
 222                         /* Select control regs */
 223                         clk_sel_cons {
 224                                 compatible = "rockchip,rk-sel-cons";
 225                                 #address-cells = <1>;
 226                                 #size-cells = <1>;
 227                                 ranges;
 228
 229                                 clk_sel_con0: sel-con@0044 {
 230                                         compatible = "rockchip,rk3188-selcon";
 231                                         reg = <0x0044 0x4>;
 232                                         #address-cells = <1>;
 233                                         #size-cells = <1>;
 234
 235                                         clk_core_div: clk_core_div {
 236                                                 compatible = "rockchip,rk3188-div-con";
 237                                                 rockchip,bits = <0 5>;
 238                                                 clocks = <&clk_core>;
 239                                                 clock-output-names = "clk_core";
 240                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 241                                                 #clock-cells = <0>;
 242                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 243                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 244                                                                         CLK_SET_RATE_NO_REPARENT)>;
 245                                         };
 246
 247                                         /* reg[6:5]: reserved */
 248
 249                                         clk_core: clk_core_mux {
 250                                                 compatible = "rockchip,rk3188-mux-con";
 251                                                 rockchip,bits = <7 1>;
 252                                                 clocks = <&clk_apll>, <&clk_gpll_div2>;
 253                                                 clock-output-names = "clk_core";
 254                                                 #clock-cells = <0>;
 255                                                 #clock-init-cells = <1>;
 256                                         };
 257
 258                                         aclk_cpu_div: aclk_cpu_div {
 259                                                 compatible = "rockchip,rk3188-div-con";
 260                                                 rockchip,bits = <8 5>;
 261                                                 clocks = <&aclk_cpu>;
 262                                                 clock-output-names = "aclk_cpu";
 263                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 264                                                 #clock-cells = <0>;
 265                                                 rockchip,clkops-idx =
 266                                                         <CLKOPS_RATE_MUX_DIV>;
 267                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 268                                         };
 269
 270                                         aclk_cpu: aclk_cpu_mux {
 271                                                 compatible = "rockchip,rk3188-mux-con";
 272                                                 rockchip,bits = <13 2>;
 273                                                 clocks = <&clk_apll>, <&clk_gpll>,<&clk_gpll_div2>,<&clk_gpll_div3>;
 274                                                 clock-output-names = "aclk_cpu";
 275                                                 #clock-cells = <0>;
 276                                                 #clock-init-cells = <1>;
 277                                         };
 278
 279                                         /* reg[15]: reserved */
 280
 281                                 };
 282
 283                                 clk_sel_con1: sel-con@0048 {
 284                                         compatible = "rockchip,rk3188-selcon";
 285                                         reg = <0x0048 0x4>;
 286                                         #address-cells = <1>;
 287                                         #size-cells = <1>;
 288
 289                                         pclk_dbg_div:  pclk_dbg_div {
 290                                                 compatible = "rockchip,rk3188-div-con";
 291                                                 rockchip,bits = <0 4>;
 292                                                 clocks = <&clk_core>;
 293                                                 clock-output-names = "pclk_dbg";
 294                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 295                                                 #clock-cells = <0>;
 296                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 297                                         };
 298
 299                                         aclk_core_pre: aclk_core_pre_div {
 300                                                 compatible = "rockchip,rk3188-div-con";
 301                                                 rockchip,bits = <4 3>;
 302                                                 clocks = <&clk_core>;
 303                                                 clock-output-names = "aclk_core_pre";
 304                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 305                                                 #clock-cells = <0>;
 306                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 307                                         };
 308
 309                                         /* reg[7]: reserved */
 310
 311                                         hclk_cpu_pre: hclk_cpu_pre_div {
 312                                                 compatible = "rockchip,rk3188-div-con";
 313                                                 rockchip,bits = <8 2>;
 314                                                 clocks = <&aclk_cpu>;
 315                                                 clock-output-names = "hclk_cpu_pre";
 316                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 317                                                 #clock-cells = <0>;
 318                                                 #clock-init-cells = <1>;
 319                                         };
 320
 321                                         /* reg[11:10]: reserved */
 322
 323                                         pclk_cpu_pre: pclk_cpu_pre_div {
 324                                                 compatible = "rockchip,rk3188-div-con";
 325                                                 rockchip,bits = <12 3>;
 326                                                 clocks = <&aclk_cpu>;
 327                                                 clock-output-names = "pclk_cpu_pre";
 328                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 329                                                 #clock-cells = <0>;
 330                                                 #clock-init-cells = <1>;
 331                                         };
 332
 333                                         /* reg[15]: reserved */
 334                                 };
 335
 336                                 clk_sel_con2: sel-con@004c {
 337                                         compatible = "rockchip,rk3188-selcon";
 338                                         reg = <0x004c 0x4>;
 339                                         #address-cells = <1>;
 340                                         #size-cells = <1>;
 341
 342                                         clk_pvtm_div: clk_pvtm_div {
 343                                                 compatible = "rockchip,rk3188-mux-con";
 344                                                 rockchip,bits = <0 7>;
 345                                                 clocks = <&clk_pvtm_func>;
 346                                                 clock-output-names = "clk_pvtm";
 347                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 348                                                 #clock-cells = <0>;
 349                                                 #clock-init-cells = <1>;
 350                                         };
 351
 352                                         /* reg[7]: reserved */
 353
 354                                         clk_nandc_div: clk_nandc_div {
 355                                                 compatible = "rockchip,rk3188-div-con";
 356                                                 rockchip,bits = <8 5>;
 357                                                 clocks = <&clk_nandc>;
 358                                                 clock-output-names = "clk_nandc";
 359                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 360                                                 #clock-cells = <0>;
 361                                                 rockchip,clkops-idx =
 362                                                         <CLKOPS_RATE_MUX_DIV>;
 363                                         };
 364
 365                                         /* reg[13]: reserved */
 366
 367                                         clk_nandc: clk_nandc_mux {
 368                                                 compatible = "rockchip,rk3188-mux-con";
 369                                                 rockchip,bits = <14 2>;
 370                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
 371                                                 clock-output-names = "clk_nandc";
 372                                                 #clock-cells = <0>;
 373                                                 #clock-init-cells = <1>;
 374                                         };
 375
 376                                 };
 377
 378                                 clk_sel_con3: sel-con@0050 {
 379                                         compatible = "rockchip,rk3188-selcon";
 380                                         reg = <0x0050 0x4>;
 381                                         #address-cells = <1>;
 382                                         #size-cells = <1>;
 383
 384                                         clk_i2s_2ch_pll_div: clk_i2s_2ch_pll_div {
 385                                                 compatible = "rockchip,rk3188-div-con";
 386                                                 rockchip,bits = <0 7>;
 387                                                 clocks = <&clk_i2s_2ch_pll>;
 388                                                 clock-output-names = "clk_i2s_2ch_pll";
 389                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 390                                                 #clock-cells = <0>;
 391                                                 rockchip,clkops-idx =
 392                                                         <CLKOPS_RATE_MUX_DIV>;
 393                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 394                                         };
 395
 396                                         /* reg[7]: reserved */
 397
 398                                         clk_i2s_2ch: clk_i2s_2ch_mux {
 399                                                 compatible = "rockchip,rk3188-mux-con";
 400                                                 rockchip,bits = <8 2>;
 401                                                 clocks = <&clk_i2s_2ch_pll_div>, <&i2s_2ch_frac>, <&i2s_clkin>, <&xin12m>;
 402                                                 clock-output-names = "clk_i2s_2ch";
 403                                                 #clock-cells = <0>;
 404                                                 rockchip,clkops-idx =
 405                                                         <CLKOPS_RATE_RK3288_I2S>;
 406                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 407                                         };
 408
 409                                         /* reg[11:10]: reserved */
 410
 411                                         clk_i2s_2ch_out: clk_i2s_2ch_out_mux {
 412                                                 compatible = "rockchip,rk3188-mux-con";
 413                                                 rockchip,bits = <12 1>;
 414                                                 clocks = <&clk_i2s_2ch>, <&xin12m>;
 415                                                 clock-output-names = "i2s_clkout";
 416                                                 #clock-cells = <0>;
 417                                         };
 418
 419                                         /* reg[13]: reserved */
 420
 421                                         clk_i2s_2ch_pll: i2s_2ch_pll_mux {
 422                                                 compatible = "rockchip,rk3188-mux-con";
 423                                                 rockchip,bits = <14 2>;
 424                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
 425                                                 clock-output-names = "clk_i2s_2ch_pll";
 426                                                 #clock-cells = <0>;
 427                                                 #clock-init-cells = <1>;
 428                                         };
 429
 430                                 };
 431
 432                                 clk_sel_con4: sel-con@0054 {
 433                                         compatible = "rockchip,rk3188-selcon";
 434                                         reg = <0x0054 0x4>;
 435                                         #address-cells = <1>;
 436                                         #size-cells = <1>;
 437
 438                                         clk_tsp_div: clk_tsp_div {
 439                                                 compatible = "rockchip,rk3188-div-con";
 440                                                 rockchip,bits = <0 5>;
 441                                                 clocks = <&clk_tsp>;
 442                                                 clock-output-names = "clk_tsp";
 443                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 444                                                 #clock-cells = <0>;
 445                                                 rockchip,clkops-idx =
 446                                                         <CLKOPS_RATE_MUX_DIV>;
 447                                         };
 448
 449                                         /* reg[5]: reserved */
 450
 451                                         clk_tsp: clk_tsp_mux {
 452                                                 compatible = "rockchip,rk3188-mux-con";
 453                                                 rockchip,bits = <6 2>;
 454                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
 455                                                 clock-output-names = "clk_tsp";
 456                                                 #clock-cells = <0>;
 457                                                 #clock-init-cells = <1>;
 458                                         };
 459
 460                                         clk_24m_div: clk_24m_div {
 461                                                 compatible = "rockchip,rk3188-div-con";
 462                                                 rockchip,bits = <8 5>;
 463                                                 clocks = <&xin24m>;
 464                                                 clock-output-names = "clk_24m";
 465                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 466                                                 #clock-cells = <0>;
 467                                         };
 468
 469                                         /* reg[15:13]: reserved */
 470
 471                                 };
 472
 473
 474                                 clk_sel_con5: sel-con@0058 {
 475                                         compatible = "rockchip,rk3188-selcon";
 476                                         reg = <0x0058 0x4>;
 477                                         #address-cells = <1>;
 478                                         #size-cells = <1>;
 479
 480                                         clk_mac_pll_div: clk_mac_pll_div {
 481                                                 compatible = "rockchip,rk3188-div-con";
 482                                                 rockchip,bits = <0 5>;
 483                                                 clocks = <&clk_mac_pll>;
 484                                                 clock-output-names = "clk_mac_pll";
 485                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 486                                                 #clock-cells = <0>;
 487                                                 rockchip,clkops-idx =
 488                                                         <CLKOPS_RATE_MUX_DIV>;
 489                                                 #clock-init-cells = <1>;
 490                                         };
 491
 492                                         /* reg[5]: reserved */
 493
 494                                         clk_mac_pll: clk_mac_pll_mux {
 495                                                 compatible = "rockchip,rk3188-mux-con";
 496                                                 rockchip,bits = <6 2>;
 497                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
 498                                                 clock-output-names = "clk_mac_pll";
 499                                                 #clock-cells = <0>;
 500                                                 #clock-init-cells = <1>;
 501                                         };
 502
 503                                         /* reg[14:8]: reserved */
 504
 505                                         clk_mac_ref: clk_mac_ref_mux {
 506                                                 compatible = "rockchip,rk3188-mux-con";
 507                                                 rockchip,bits = <15 1>;
 508                                                 clocks = <&clk_mac_pll_div>, <&gmac_clkin>;
 509                                                 clock-output-names = "clk_mac_ref";
 510                                                 #clock-cells = <0>;
 511                                                 rockchip,clkops-idx =
 512                                                         <CLKOPS_RATE_MAC_REF>;
 513                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 514                                                 #clock-init-cells = <1>;
 515                                         };
 516
 517                                 };
 518
 519
 520                                 clk_sel_con6: sel-con@005c {
 521                                         compatible = "rockchip,rk3188-selcon";
 522                                         reg = <0x005c 0x4>;
 523                                         #address-cells = <1>;
 524                                         #size-cells = <1>;
 525
 526                                         spdif_div: spdif_div {
 527                                                 compatible = "rockchip,rk3188-div-con";
 528                                                 rockchip,bits = <0 7>;
 529                                                 clocks = <&clk_spdif_pll>;
 530                                                 clock-output-names = "clk_spdif_pll";
 531                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 532                                                 #clock-cells = <0>;
 533                                                 rockchip,clkops-idx =
 534                                                         <CLKOPS_RATE_MUX_DIV>;
 535                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 536                                         };
 537
 538                                         /* reg[7]: reserved */
 539
 540                                         clk_spdif: spdif_mux {
 541                                                 compatible = "rockchip,rk3188-mux-con";
 542                                                 rockchip,bits = <8 2>;
 543                                                 clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>;
 544                                                 clock-output-names = "clk_spdif";
 545                                                 #clock-cells = <0>;
 546                                                 rockchip,clkops-idx =
 547                                                         <CLKOPS_RATE_RK3288_I2S>;
 548                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 549                                         };
 550
 551                                         /* reg[13:10]: reserved */
 552
 553                                         clk_spdif_pll: spdif_pll_mux {
 554                                                 compatible = "rockchip,rk3188-mux-con";
 555                                                 rockchip,bits = <14 2>;
 556                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
 557                                                 clock-output-names = "clk_spdif_pll";
 558                                                 #clock-cells = <0>;
 559                                                 #clock-init-cells = <1>;
 560                                         };
 561
 562                                 };
 563
 564                                 clk_sel_con7: sel-con@0060 {
 565                                         compatible = "rockchip,rk3188-selcon";
 566                                         reg = <0x0060 0x4>;
 567                                         #address-cells = <1>;
 568                                         #size-cells = <1>;
 569
 570                                         i2s_2ch_frac: i2s_2ch_frac {
 571                                                 compatible = "rockchip,rk3188-frac-con";
 572                                                 clocks = <&clk_i2s_2ch_pll>;
 573                                                 clock-output-names = "i2s_2ch_frac";
 574                                                 /* numerator    denominator */
 575                                                 rockchip,bits = <0 32>;
 576                                                 rockchip,clkops-idx =
 577                                                         <CLKOPS_RATE_FRAC>;
 578                                                 #clock-cells = <0>;
 579                                         };
 580                                 };
 581
 582                                 clk_sel_con8: sel-con@0064 {
 583                                         compatible = "rockchip,rk3188-selcon";
 584                                         reg = <0x0064 0x4>;
 585                                         #address-cells = <1>;
 586                                         #size-cells = <1>;
 587
 588                                         i2s_8ch_frac: i2s_8ch_frac {
 589                                                 compatible = "rockchip,rk3188-frac-con";
 590                                                 clocks = <&clk_i2s_8ch_pll>;
 591                                                 clock-output-names = "i2s_8ch_frac";
 592                                                 /* numerator    denominator */
 593                                                 rockchip,bits = <0 32>;
 594                                                 rockchip,clkops-idx =
 595                                                         <CLKOPS_RATE_FRAC>;
 596                                                 #clock-cells = <0>;
 597                                         };
 598                                 };
 599
 600                                 clk_sel_con9: sel-con@0068 {
 601                                         compatible = "rockchip,rk3188-selcon";
 602                                         reg = <0x0068 0x4>;
 603                                         #address-cells = <1>;
 604                                         #size-cells = <1>;
 605
 606                                         clk_i2s_8ch_pll_div: clk_i2s_8ch_pll_div {
 607                                                 compatible = "rockchip,rk3188-div-con";
 608                                                 rockchip,bits = <0 7>;
 609                                                 clocks = <&clk_i2s_8ch_pll>;
 610                                                 clock-output-names = "clk_i2s_8ch_pll";
 611                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 612                                                 #clock-cells = <0>;
 613                                                 rockchip,clkops-idx =
 614                                                         <CLKOPS_RATE_MUX_DIV>;
 615                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 616                                         };
 617
 618                                         /* reg[7]: reserved */
 619
 620                                         clk_i2s_8ch: clk_i2s_8ch_mux {
 621                                                 compatible = "rockchip,rk3188-mux-con";
 622                                                 rockchip,bits = <8 2>;
 623                                                 clocks = <&clk_i2s_8ch_pll_div>, <&i2s_8ch_frac>, <&i2s_clkin>, <&xin12m>;
 624                                                 clock-output-names = "clk_i2s_8ch";
 625                                                 #clock-cells = <0>;
 626                                                 rockchip,clkops-idx =
 627                                                         <CLKOPS_RATE_RK3288_I2S>;
 628                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 629                                         };
 630
 631                                         /* reg[13:10]: reserved */
 632
 633                                         clk_i2s_8ch_pll: i2s_8ch_pll_mux {
 634                                                 compatible = "rockchip,rk3188-mux-con";
 635                                                 rockchip,bits = <14 2>;
 636                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
 637                                                 clock-output-names = "clk_i2s_8ch_pll";
 638                                                 #clock-cells = <0>;
 639                                                 #clock-init-cells = <1>;
 640                                         };
 641
 642                                 };
 643
 644                                 clk_sel_con10: sel-con@006c {
 645                                         compatible = "rockchip,rk3188-selcon";
 646                                         reg = <0x006c 0x4>;
 647                                         #address-cells = <1>;
 648                                         #size-cells = <1>;
 649
 650                                         aclk_peri_div: aclk_peri_div {
 651                                                 compatible = "rockchip,rk3188-div-con";
 652                                                 rockchip,bits = <0 5>;
 653                                                 clocks = <&aclk_peri>;
 654                                                 clock-output-names = "aclk_peri";
 655                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 656                                                 #clock-cells = <0>;
 657                                                 rockchip,clkops-idx =
 658                                                         <CLKOPS_RATE_MUX_DIV>;
 659                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 660                                         };
 661
 662                                         /* reg[7:5]: reserved */
 663
 664                                         hclk_peri_pre: hclk_peri_pre_div {
 665                                                 compatible = "rockchip,rk3188-div-con";
 666                                                 rockchip,bits = <8 2>;
 667                                                 clocks = <&aclk_peri>;
 668                                                 clock-output-names = "hclk_peri_pre";
 669                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 670                                                 rockchip,div-relations =
 671                                                                 <0x0 1
 672                                                                  0x1 2
 673                                                                  0x2 4>;
 674                                                 #clock-cells = <0>;
 675                                                 #clock-init-cells = <1>;
 676                                         };
 677
 678                                         /* reg[11:10]: reserved */
 679
 680                                         pclk_peri_pre: pclk_peri_div {
 681                                                 compatible = "rockchip,rk3188-div-con";
 682                                                 rockchip,bits = <12 2>;
 683                                                 clocks = <&aclk_peri>;
 684                                                 clock-output-names = "pclk_peri_pre";
 685                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 686                                                 rockchip,div-relations =
 687                                                                 <0x0 1
 688                                                                  0x1 2
 689                                                                  0x2 4
 690                                                                  0x3 8>;
 691                                                 #clock-cells = <0>;
 692                                                 #clock-init-cells = <1>;
 693                                         };
 694
 695                                         aclk_peri: aclk_peri_mux {
 696                                                 compatible = "rockchip,rk3188-mux-con";
 697                                                 rockchip,bits = <14 2>;
 698                                                 clocks = <&clk_gpll>,<&clk_cpll>,<&clk_gpll_div2>,<&clk_gpll_div3>;
 699                                                 clock-output-names = "aclk_peri";
 700                                                 #clock-cells = <0>;
 701                                                 #clock-init-cells = <1>;
 702                                         };
 703                                 };
 704
 705                                 clk_sel_con11: sel-con@0070 {
 706                                         compatible = "rockchip,rk3188-selcon";
 707                                         reg = <0x0070 0x4>;
 708                                         #address-cells = <1>;
 709                                         #size-cells = <1>;
 710
 711                                         clk_sdmmc0_div: clk_sdmmc0_div {
 712                                                 compatible = "rockchip,rk3188-div-con";
 713                                                 rockchip,bits = <0 6>;
 714                                                 clocks = <&clk_sdmmc0>;
 715                                                 clock-output-names = "clk_sdmmc0";
 716                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 717                                                 #clock-cells = <0>;
 718                                                 rockchip,clkops-idx =
 719                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 720                                         };
 721
 722                                         clk_sdmmc0: clk_sdmmc0_mux {
 723                                                 compatible = "rockchip,rk3188-mux-con";
 724                                                 rockchip,bits = <6 2>;
 725                                                 clocks = <&clk_cpll>,<&clk_gpll>,<&clk_gpll_div2>,<&xin24m>;
 726                                                 clock-output-names = "clk_sdmmc0";
 727                                                 #clock-cells = <0>;
 728                                                 #clock-init-cells = <1>;
 729                                         };
 730
 731                                         clk_sfc_div: clk_sfc_div {
 732                                                 compatible = "rockchip,rk3188-div-con";
 733                                                 rockchip,bits = <8 5>;
 734                                                 clocks = <&clk_sfc>;
 735                                                 clock-output-names = "clk_sfc";
 736                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 737                                                 #clock-cells = <0>;
 738                                                 rockchip,clkops-idx =
 739                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 740                                         };
 741
 742                                         /* reg[13]: reserved */
 743
 744                                         clk_sfc: clk_sfc_mux {
 745                                                 compatible = "rockchip,rk3188-mux-con";
 746                                                 rockchip,bits = <14 2>;
 747                                                 clocks = <&clk_cpll>,<&clk_gpll>,<&clk_gpll_div2>,<&xin24m>;
 748                                                 clock-output-names = "clk_sfc";
 749                                                 #clock-cells = <0>;
 750                                                 #clock-init-cells = <1>;
 751                                         };
 752
 753                                 };
 754
 755                                 clk_sel_con12: sel-con@0074 {
 756                                         compatible = "rockchip,rk3188-selcon";
 757                                         reg = <0x0074 0x4>;
 758                                         #address-cells = <1>;
 759                                         #size-cells = <1>;
 760
 761                                         clk_sdio_div: clk_sdio_div {
 762                                                 compatible = "rockchip,rk3188-div-con";
 763                                                 rockchip,bits = <0 6>;
 764                                                 clocks = <&clk_sdio>;
 765                                                 clock-output-names = "clk_sdio";
 766                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 767                                                 #clock-cells = <0>;
 768                                                 rockchip,clkops-idx =
 769                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 770                                         };
 771
 772                                         clk_sdio: clk_sdio_mux {
 773                                                 compatible = "rockchip,rk3188-mux-con";
 774                                                 rockchip,bits = <6 2>;
 775                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&xin24m>;
 776                                                 clock-output-names = "clk_sdio";
 777                                                 #clock-cells = <0>;
 778                                                 #clock-init-cells = <1>;
 779                                         };
 780
 781                                         clk_emmc_div: clk_emmc_div {
 782                                                 compatible = "rockchip,rk3188-div-con";
 783                                                 rockchip,bits = <8 6>;
 784                                                 clocks = <&clk_emmc>;
 785                                                 clock-output-names = "clk_emmc";
 786                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 787                                                 #clock-cells = <0>;
 788                                                 rockchip,clkops-idx =
 789                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 790                                         };
 791
 792                                         clk_emmc: clk_emmc_mux {
 793                                                 compatible = "rockchip,rk3188-mux-con";
 794                                                 rockchip,bits = <14 2>;
 795                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&xin24m>;
 796                                                 clock-output-names = "clk_emmc";
 797                                                 #clock-cells = <0>;
 798                                                 #clock-init-cells = <1>;
 799                                         };
 800
 801                                 };
 802
 803                                 clk_sel_con13: sel-con@0078 {
 804                                         compatible = "rockchip,rk3188-selcon";
 805                                         reg = <0x0078 0x4>;
 806                                         #address-cells = <1>;
 807                                         #size-cells = <1>;
 808
 809                                         clk_uart0_pll_div: clk_uart0_pll_div {
 810                                                 compatible = "rockchip,rk3188-div-con";
 811                                                 rockchip,bits = <0 7>;
 812                                                 clocks = <&clk_uart0_pll>;
 813                                                 clock-output-names = "clk_uart0_pll";
 814                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 815                                                 #clock-cells = <0>;
 816                                         };
 817
 818                                         /* reg[7]: reserved */
 819
 820                                         clk_uart0: clk_uart0_mux {
 821                                                 compatible = "rockchip,rk3188-mux-con";
 822                                                 rockchip,bits = <8 2>;
 823                                                 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>;
 824                                                 clock-output-names = "clk_uart0";
 825                                                 #clock-cells = <0>;
 826                                                 rockchip,clkops-idx =
 827                                                         <CLKOPS_RATE_RK3288_I2S>;
 828                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 829                                         };
 830
 831                                         /* reg[11:10]: reserved */
 832
 833                                         clk_uart0_pll: clk_uart0_pll_mux {
 834                                                 compatible = "rockchip,rk3188-mux-con";
 835                                                 rockchip,bits = <12 2>;
 836                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
 837                                                 clock-output-names = "clk_uart0_pll";
 838                                                 #clock-cells = <0>;
 839                                                 #clock-init-cells = <1>;
 840                                         };
 841
 842                                         clk_uart2_pll: clk_uart2_pll_mux {
 843                                                 compatible = "rockchip,rk3188-mux-con";
 844                                                 rockchip,bits = <14 2>;
 845                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
 846                                                 clock-output-names = "clk_uart2_pll";
 847                                                 #clock-cells = <0>;
 848                                                 #clock-init-cells = <1>;
 849                                         };
 850
 851                                 };
 852
 853                                 clk_sel_con14: sel-con@007c {
 854                                         compatible = "rockchip,rk3188-selcon";
 855                                         reg = <0x007c 0x4>;
 856                                         #address-cells = <1>;
 857                                         #size-cells = <1>;
 858
 859                                         clk_uart1_div: clk_uart1_div {
 860                                                 compatible = "rockchip,rk3188-div-con";
 861                                                 rockchip,bits = <0 7>;
 862                                                 clocks = <&clk_uart2_pll>;
 863                                                 clock-output-names = "clk_uart1_div";
 864                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 865                                                 #clock-cells = <0>;
 866                                         };
 867
 868                                         /* reg[7]: reserved */
 869
 870                                         clk_uart1: clk_uart1_mux {
 871                                                 compatible = "rockchip,rk3188-mux-con";
 872                                                 rockchip,bits = <8 2>;
 873                                                 clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>;
 874                                                 clock-output-names = "clk_uart1";
 875                                                 #clock-cells = <0>;
 876                                                 rockchip,clkops-idx =
 877                                                         <CLKOPS_RATE_RK3288_I2S>;
 878                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 879                                         };
 880
 881                                         /* reg[15:10]: reserved */
 882                                 };
 883
 884                                 clk_sel_con15: sel-con@0080 {
 885                                         compatible = "rockchip,rk3188-selcon";
 886                                         reg = <0x0080 0x4>;
 887                                         #address-cells = <1>;
 888                                         #size-cells = <1>;
 889
 890                                         clk_uart2_div: clk_uart2_div {
 891                                                 compatible = "rockchip,rk3188-div-con";
 892                                                 rockchip,bits = <0 7>;
 893                                                 clocks = <&clk_uart2_pll>;
 894                                                 clock-output-names = "clk_uart2_div";
 895                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 896                                                 #clock-cells = <0>;
 897                                         };
 898
 899                                         /* reg[7]: reserved */
 900
 901                                         clk_uart2: clk_uart2_mux {
 902                                                 compatible = "rockchip,rk3188-mux-con";
 903                                                 rockchip,bits = <8 2>;
 904                                                 clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>;
 905                                                 clock-output-names = "clk_uart2";
 906                                                 #clock-cells = <0>;
 907                                                 rockchip,clkops-idx =
 908                                                         <CLKOPS_RATE_RK3288_I2S>;
 909                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 910                                         };
 911
 912                                         /* reg[15:10]: reserved */
 913                                 };
 914
 915                                 clk_sel_con17: sel-con@0088 {
 916                                         compatible = "rockchip,rk3188-selcon";
 917                                         reg = <0x0088 0x4>;
 918                                         #address-cells = <1>;
 919                                         #size-cells = <1>;
 920
 921                                         uart0_frac: uart0_frac {
 922                                                 compatible = "rockchip,rk3188-frac-con";
 923                                                 clocks = <&clk_uart0_pll>;
 924                                                 clock-output-names = "uart0_frac";
 925                                                 /* numerator    denominator */
 926                                                 rockchip,bits = <0 32>;
 927                                                 rockchip,clkops-idx =
 928                                                         <CLKOPS_RATE_FRAC>;
 929                                                 #clock-cells = <0>;
 930                                         };
 931                                 };
 932
 933                                 clk_sel_con18: sel-con@008c {
 934                                         compatible = "rockchip,rk3188-selcon";
 935                                         reg = <0x008c 0x4>;
 936                                         #address-cells = <1>;
 937                                         #size-cells = <1>;
 938
 939                                         uart1_frac: uart1_frac {
 940                                                 compatible = "rockchip,rk3188-frac-con";
 941                                                 clocks = <&clk_uart1_div>;
 942                                                 clock-output-names = "uart1_frac";
 943                                                 /* numerator    denominator */
 944                                                 rockchip,bits = <0 32>;
 945                                                 rockchip,clkops-idx =
 946                                                         <CLKOPS_RATE_FRAC>;
 947                                                 #clock-cells = <0>;
 948                                         };
 949                                 };
 950
 951                                 clk_sel_con19: sel-con@0090 {
 952                                         compatible = "rockchip,rk3188-selcon";
 953                                         reg = <0x0090 0x4>;
 954                                         #address-cells = <1>;
 955                                         #size-cells = <1>;
 956
 957                                         uart2_frac: uart2_frac {
 958                                                 compatible = "rockchip,rk3188-frac-con";
 959                                                 clocks = <&clk_uart2_div>;
 960                                                 clock-output-names = "uart2_frac";
 961                                                 /* numerator    denominator */
 962                                                 rockchip,bits = <0 32>;
 963                                                 rockchip,clkops-idx =
 964                                                         <CLKOPS_RATE_FRAC>;
 965                                                 #clock-cells = <0>;
 966                                         };
 967
 968                                 };
 969
 970                                 clk_sel_con20: sel-con@0094 {
 971                                         compatible = "rockchip,rk3188-selcon";
 972                                         reg = <0x0094 0x4>;
 973                                         #address-cells = <1>;
 974                                         #size-cells = <1>;
 975
 976                                         spdif_frac: spdif_frac {
 977                                                 compatible = "rockchip,rk3188-frac-con";
 978                                                 clocks = <&spdif_div>;
 979                                                 clock-output-names = "spdif_frac";
 980                                                 /* numerator    denominator */
 981                                                 rockchip,bits = <0 32>;
 982                                                 rockchip,clkops-idx =
 983                                                         <CLKOPS_RATE_FRAC>;
 984                                                 #clock-cells = <0>;
 985                                         };
 986
 987                                 };
 988
 989                                 clk_sel_con23: sel-con@00a0 {
 990                                         compatible = "rockchip,rk3188-selcon";
 991                                         reg = <0x00a0 0x4>;
 992                                         #address-cells = <1>;
 993                                         #size-cells = <1>;
 994
 995                                         dclk_ebc: dclk_ebc_mux {
 996                                                 compatible = "rockchip,rk3188-mux-con";
 997                                                 rockchip,bits = <0 2>;
 998                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
 999                                                 clock-output-names = "dclk_ebc";
1000                                                 #clock-cells = <0>;
1001                                                 #clock-init-cells = <1>;
1002                                         };
1003
1004                                         /* reg[7:2]: reserved */
1005
1006                                         dclk_ebc_div: dclk_ebc_div {
1007                                                 compatible = "rockchip,rk3188-div-con";
1008                                                 rockchip,bits = <8 8>;
1009                                                 clocks = <&dclk_ebc>;
1010                                                 clock-output-names = "dclk_ebc";
1011                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1012                                                 #clock-cells = <0>;
1013                                                 rockchip,clkops-idx =
1014                                                         <CLKOPS_RATE_MUX_DIV>;
1015                                         };
1016
1017                                 };
1018
1019                                 clk_sel_con24: sel-con@00a4 {
1020                                         compatible = "rockchip,rk3188-selcon";
1021                                         reg = <0x00a4 0x4>;
1022                                         #address-cells = <1>;
1023                                         #size-cells = <1>;
1024
1025                                         clk_crypto_div: clk_crypto_div {
1026                                                 compatible = "rockchip,rk3188-div-con";
1027                                                 rockchip,bits = <0 2>;
1028                                                 clocks = <&aclk_cpu>;
1029                                                 clock-output-names = "clk_crypto";
1030                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1031                                                 #clock-cells = <0>;
1032                                                 #clock-init-cells = <1>;
1033                                         };
1034
1035                                         /* reg[7:2]: reserved */
1036
1037                                         clk_saradc: clk_saradc_div {
1038                                                 compatible = "rockchip,rk3188-div-con";
1039                                                 rockchip,bits = <8 8>;
1040                                                 clocks = <&xin24m>;
1041                                                 clock-output-names = "clk_saradc";
1042                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1043                                                 #clock-cells = <0>;
1044                                                 #clock-init-cells = <1>;
1045                                         };
1046
1047                                 };
1048
1049                                 clk_sel_con25: sel-con@00a8 {
1050                                         compatible = "rockchip,rk3188-selcon";
1051                                         reg = <0x00a8 0x4>;
1052                                         #address-cells = <1>;
1053                                         #size-cells = <1>;
1054
1055                                         clk_spi0_div: clk_spi0_div {
1056                                                 compatible = "rockchip,rk3188-div-con";
1057                                                 rockchip,bits = <0 7>;
1058                                                 clocks = <&clk_spi0>;
1059                                                 clock-output-names = "clk_spi0";
1060                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1061                                                 #clock-cells = <0>;
1062                                                 rockchip,clkops-idx =
1063                                                         <CLKOPS_RATE_MUX_DIV>;
1064                                         };
1065
1066                                         /* reg[7]: reserved */
1067
1068                                         clk_spi0: clk_spi0_mux {
1069                                                 compatible = "rockchip,rk3188-mux-con";
1070                                                 rockchip,bits = <8 2>;
1071                                                 clocks = <&clk_cpll>, <&clk_gpll>,<&clk_gpll_div2>;
1072                                                 clock-output-names = "clk_spi0";
1073                                                 #clock-cells = <0>;
1074                                         };
1075
1076                                         /* reg[15:10]: reserved */
1077
1078                                 };
1079
1080                                 clk_sel_con26: sel-con@00ac {
1081                                         compatible = "rockchip,rk3188-selcon";
1082                                         reg = <0x00ac 0x4>;
1083                                         #address-cells = <1>;
1084                                         #size-cells = <1>;
1085
1086                                         ddr_div: ddr_div {
1087                                                 compatible = "rockchip,rk3188-div-con";
1088                                                 rockchip,bits = <0 2>;
1089                                                 clocks = <&clk_ddr>;
1090                                                 clock-output-names = "clk_ddr";
1091                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
1092                                                 rockchip,div-relations =
1093                                                                 <0x0 1
1094                                                                  0x1 2
1095                                                                  0x3 4>;
1096                                                 #clock-cells = <0>;
1097                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
1098                                                                         CLK_SET_RATE_NO_REPARENT)>;
1099                                                 rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
1100                                         };
1101
1102                                         /* reg[7:2]: reserved */
1103
1104                                         clk_ddr: ddr_clk_pll_mux {
1105                                                 compatible = "rockchip,rk3188-mux-con";
1106                                                 rockchip,bits = <8 1>;
1107                                                 clocks = <&clk_dpll>, <&dummy>;
1108                                                 clock-output-names = "clk_ddr";
1109                                                 #clock-cells = <0>;
1110                                         };
1111
1112                                         /* reg[15:9]: reserved */
1113                                 };
1114
1115                                 clk_sel_con27: sel-con@00b0 {
1116                                         compatible = "rockchip,rk3188-selcon";
1117                                         reg = <0x00b0 0x4>;
1118                                         #address-cells = <1>;
1119                                         #size-cells = <1>;
1120
1121                                         dclk_lcdc0: dclk_lcdc0_mux {
1122                                                 compatible = "rockchip,rk3188-mux-con";
1123                                                 rockchip,bits = <0 2>;
1124                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>;
1125                                                 clock-output-names = "dclk_lcdc0";
1126                                                 #clock-cells = <0>;
1127                                                 #clock-init-cells = <1>;
1128                                         };
1129
1130                                         /* reg[7:2]: reserved */
1131
1132                                         dclk_lcdc0_div: dclk_lcdc0_div {
1133                                                 compatible = "rockchip,rk3188-div-con";
1134                                                 rockchip,bits = <8 8>;
1135                                                 clocks = <&dclk_lcdc0>;
1136                                                 clock-output-names = "dclk_lcdc0";
1137                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1138                                                 #clock-cells = <0>;
1139                                                 rockchip,clkops-idx =
1140                                                         <CLKOPS_RATE_MUX_DIV>;
1141                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1142                                         };
1143                                 };
1144
1145                                 clk_sel_con28: sel-con@00b4 {
1146                                         compatible = "rockchip,rk3188-selcon";
1147                                         reg = <0x00b4 0x4>;
1148                                         #address-cells = <1>;
1149                                         #size-cells = <1>;
1150
1151                                         sclk_lcdc0: sclk_lcdc0_mux {
1152                                                 compatible = "rockchip,rk3188-mux-con";
1153                                                 rockchip,bits = <0 2>;
1154                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>;
1155                                                 clock-output-names = "sclk_lcdc0";
1156                                                 #clock-cells = <0>;
1157                                                 #clock-init-cells = <1>;
1158                                         };
1159
1160                                         /* reg[7:2]: reserved */
1161
1162                                         sclk_lcdc0_div: sclk_lcdc0_div {
1163                                                 compatible = "rockchip,rk3188-div-con";
1164                                                 rockchip,bits = <8 8>;
1165                                                 clocks = <&sclk_lcdc0>;
1166                                                 clock-output-names = "sclk_lcdc0";
1167                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1168                                                 #clock-cells = <0>;
1169                                                 rockchip,clkops-idx =
1170                                                         <CLKOPS_RATE_MUX_DIV>;
1171                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1172                                         };
1173                                 };
1174
1175                                 clk_sel_con29: sel-con@00b8 {
1176                                         compatible = "rockchip,rk3188-selcon";
1177                                         reg = <0x00b8 0x4>;
1178                                         #address-cells = <1>;
1179                                         #size-cells = <1>;
1180
1181                                         clk_cif_pll: clk_cif_pll_mux {
1182                                                 compatible = "rockchip,rk3188-mux-con";
1183                                                 rockchip,bits = <0 2>;
1184                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
1185                                                 clock-output-names = "clk_cif_pll";
1186                                                 #clock-cells = <0>;
1187                                                 #clock-init-cells = <1>;
1188                                         };
1189
1190                                         clk_cif_out_div: clk_cif_out_div {
1191                                                 compatible = "rockchip,rk3188-div-con";
1192                                                 rockchip,bits = <2 5>;
1193                                                 clocks = <&clk_cif_out>;
1194                                                 clock-output-names = "clk_cif_out";
1195                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1196                                                 #clock-cells = <0>;
1197                                                 rockchip,clkops-idx =
1198                                                         <CLKOPS_RATE_MUX_DIV>;
1199                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1200                                         };
1201
1202                                         clk_cif_out: clk_cif_out_mux {
1203                                                 compatible = "rockchip,rk3188-mux-con";
1204                                                 rockchip,bits = <7 1>;
1205                                                 clocks = <&clk_cif_pll>, <&xin24m>;
1206                                                 clock-output-names = "clk_cif_out";
1207                                                 #clock-cells = <0>;
1208                                                 #clock-init-cells = <1>;
1209                                         };
1210
1211                                         pclk_pmu_pre: pclk_pmu_pre_div {
1212                                                 compatible = "rockchip,rk3188-div-con";
1213                                                 rockchip,bits = <8 6>;
1214                                                 clocks = <&clk_cpll>;
1215                                                 clock-output-names = "pclk_pmu_pre";
1216                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1217                                                 #clock-cells = <0>;
1218                                                 #clock-init-cells = <1>;
1219                                         };
1220
1221                                         /* reg[15:14]: reserved */
1222                                 };
1223
1224                                 clk_sel_con30: sel-con@00bc {
1225                                         compatible = "rockchip,rk3188-selcon";
1226                                         reg = <0x00bc 0x4>;
1227                                         #address-cells = <1>;
1228                                         #size-cells = <1>;
1229
1230                                         clk_testout_div: clk_testout_div {
1231                                                 compatible = "rockchip,rk3188-div-con";
1232                                                 rockchip,bits = <0 5>;
1233                                                 clocks = <&dummy>;
1234                                                 clock-output-names = "clk_testout";
1235                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1236                                                 #clock-cells = <0>;
1237                                                 #clock-init-cells = <1>;
1238                                         };
1239
1240                                         /* reg[6:5]: reserved */
1241
1242                                         clk_cif0_in: clk_cif0_in_mux {
1243                                                 compatible = "rockchip,rk3188-mux-con";
1244                                                 rockchip,bits = <7 1>;
1245                                                 clocks = <&pclkin_cif>, <&pclkin_cif_inv>;
1246                                                 clock-output-names = "clk_cif0_in";
1247                                                 #clock-cells = <0>;
1248                                                 #clock-init-cells = <1>;
1249                                         };
1250
1251                                         hclk_vio_pre_div: hclk_vio_pre_div {
1252                                                 compatible = "rockchip,rk3188-div-con";
1253                                                 rockchip,bits = <8 5>;
1254                                                 clocks = <&hclk_vio_pre>;
1255                                                 clock-output-names = "hclk_vio_pre";
1256                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1257                                                 #clock-cells = <0>;
1258                                                 rockchip,clkops-idx =
1259                                                         <CLKOPS_RATE_MUX_DIV>;
1260                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1261                                         };
1262
1263                                         /* reg[13]: reserved */
1264
1265                                         hclk_vio_pre: hclk_vio_pre_mux {
1266                                                 compatible = "rockchip,rk3188-mux-con";
1267                                                 rockchip,bits = <14 2>;
1268                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
1269                                                 clock-output-names = "hclk_vio_pre";
1270                                                 #clock-cells = <0>;
1271                                                 #clock-init-cells = <1>;
1272                                         };
1273
1274                                 };
1275
1276                                 clk_sel_con31: sel-con@00c0 {
1277                                         compatible = "rockchip,rk3188-selcon";
1278                                         reg = <0x00c0 0x4>;
1279                                         #address-cells = <1>;
1280                                         #size-cells = <1>;
1281
1282                                         aclk_vio0_pre_div: aclk_vio0_pre_div {
1283                                                 compatible = "rockchip,rk3188-div-con";
1284                                                 rockchip,bits = <0 5>;
1285                                                 clocks = <&aclk_vio0_pre>;
1286                                                 clock-output-names = "aclk_vio0_pre";
1287                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1288                                                 #clock-cells = <0>;
1289                                                 rockchip,clkops-idx =
1290                                                         <CLKOPS_RATE_MUX_DIV>;
1291                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1292                                         };
1293
1294                                         aclk_vio0_pre: aclk_vio0_pre_mux {
1295                                                 compatible = "rockchip,rk3188-mux-con";
1296                                                 rockchip,bits = <5 3>;
1297                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1298                                                 clock-output-names = "aclk_vio0_pre";
1299                                                 #clock-cells = <0>;
1300                                                 #clock-init-cells = <1>;
1301                                         };
1302
1303                                         aclk_vio1_pre_div: aclk_vio1_pre_div {
1304                                                 compatible = "rockchip,rk3188-div-con";
1305                                                 rockchip,bits = <8 5>;
1306                                                 clocks = <&aclk_vio1_pre>;
1307                                                 clock-output-names = "aclk_vio1_pre";
1308                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1309                                                 #clock-cells = <0>;
1310                                                 rockchip,clkops-idx =
1311                                                         <CLKOPS_RATE_MUX_DIV>;
1312                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1313                                         };
1314
1315                                         aclk_vio1_pre: aclk_vio1_pre_mux {
1316                                                 compatible = "rockchip,rk3188-mux-con";
1317                                                 rockchip,bits = <13 3>;
1318                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1319                                                 clock-output-names = "aclk_vio1_pre";
1320                                                 #clock-cells = <0>;
1321                                                 #clock-init-cells = <1>;
1322                                         };
1323
1324                                 };
1325
1326                                 clk_sel_con32: sel-con@00c4 {
1327                                         compatible = "rockchip,rk3188-selcon";
1328                                         reg = <0x00c4 0x4>;
1329                                         #address-cells = <1>;
1330                                         #size-cells = <1>;
1331
1332                                         clk_vepu_div: clk_vepu_div {
1333                                                 compatible = "rockchip,rk3188-div-con";
1334                                                 rockchip,bits = <0 5>;
1335                                                 clocks = <&clk_vepu>;
1336                                                 clock-output-names = "clk_vepu";
1337                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1338                                                 #clock-cells = <0>;
1339                                                 rockchip,clkops-idx =
1340                                                         <CLKOPS_RATE_MUX_DIV>;
1341                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1342                                         };
1343
1344                                         clk_vepu: clk_vepu_mux {
1345                                                 compatible = "rockchip,rk3188-mux-con";
1346                                                 rockchip,bits = <5 3>;
1347                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1348                                                 clock-output-names = "clk_vepu";
1349                                                 #clock-cells = <0>;
1350                                                 #clock-init-cells = <1>;
1351                                         };
1352
1353                                         clk_vdpu_div: clk_vdpu_div {
1354                                                 compatible = "rockchip,rk3188-div-con";
1355                                                 rockchip,bits = <8 5>;
1356                                                 clocks = <&clk_vdpu>;
1357                                                 clock-output-names = "clk_vdpu";
1358                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1359                                                 #clock-cells = <0>;
1360                                                 rockchip,clkops-idx =
1361                                                         <CLKOPS_RATE_MUX_DIV>;
1362                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1363                                         };
1364
1365                                         clk_vdpu: clk_vdpu_mux {
1366                                                 compatible = "rockchip,rk3188-mux-con";
1367                                                 rockchip,bits = <13 3>;
1368                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1369                                                 clock-output-names = "clk_vdpu";
1370                                                 #clock-cells = <0>;
1371                                                 #clock-init-cells = <1>;
1372                                         };
1373
1374                                 };
1375
1376                                 clk_sel_con34: sel-con@00cc {
1377                                         compatible = "rockchip,rk3188-selcon";
1378                                         reg = <0x00cc 0x4>;
1379                                         #address-cells = <1>;
1380                                         #size-cells = <1>;
1381
1382                                         clk_gpu_pre_div: clk_gpu_pre_div {
1383                                                 compatible = "rockchip,rk3188-div-con";
1384                                                 rockchip,bits = <0 5>;
1385                                                 clocks = <&clk_gpu_pre>;
1386                                                 clock-output-names = "clk_gpu_pre";
1387                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1388                                                 #clock-cells = <0>;
1389                                                 rockchip,clkops-idx =
1390                                                         <CLKOPS_RATE_MUX_DIV>;
1391                                                 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
1392                                         };
1393
1394                                         clk_gpu_pre: clk_gpu_pre_mux {
1395                                                 compatible = "rockchip,rk3188-mux-con";
1396                                                 rockchip,bits = <5 3>;
1397                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1398                                                 clock-output-names = "clk_gpu_pre";
1399                                                 #clock-cells = <0>;
1400                                                 #clock-init-cells = <1>;
1401                                         };
1402
1403                                         clk_hevc_core_div: clk_hevc_core_div {
1404                                                 compatible = "rockchip,rk3188-div-con";
1405                                                 rockchip,bits = <8 5>;
1406                                                 clocks = <&clk_hevc_core>;
1407                                                 clock-output-names = "clk_hevc_core";
1408                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1409                                                 #clock-cells = <0>;
1410                                                 rockchip,clkops-idx =
1411                                                         <CLKOPS_RATE_MUX_DIV>;
1412                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1413                                         };
1414
1415                                         clk_hevc_core: clk_hevc_core_mux {
1416                                                 compatible = "rockchip,rk3188-mux-con";
1417                                                 rockchip,bits = <13 3>;
1418                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1419                                                 clock-output-names = "clk_hevc_core";
1420                                                 #clock-cells = <0>;
1421                                                 #clock-init-cells = <1>;
1422                                         };
1423
1424                                 };
1425
1426                         };
1427
1428
1429                         /* Gate control regs */
1430                         clk_gate_cons {
1431                                 compatible = "rockchip,rk-gate-cons";
1432                                 #address-cells = <1>;
1433                                 #size-cells = <1>;
1434                                 ranges ;
1435
1436                                 clk_gates0: gate-clk@00d0{
1437                                         compatible = "rockchip,rk3188-gate-clk";
1438                                         reg = <0x00d0 0x4>;
1439                                         clocks =
1440                                                 <&clk_core>,            <&dummy>,
1441                                                 <&dummy>,       <&aclk_cpu>,
1442
1443                                                 <&aclk_cpu>,    <&aclk_cpu>,
1444                                                 <&dummy>,               <&clk_core>,
1445
1446                                                 <&dummy>,       <&clk_i2s_2ch_pll>,
1447                                                 <&i2s_2ch_frac>,        <&hclk_vio_pre>,
1448
1449                                                 <&aclk_cpu>,            <&clk_i2s_2ch_out>,
1450                                                 <&clk_i2s_2ch>,         <&dummy>;
1451
1452                                         clock-output-names =
1453                                                 "pclk_dbg",                     "aclk_cpu",      /*clk_cpu_cpll*/
1454                                                 "clk_ddr",              "aclk_cpu_pre",
1455
1456                                                 "hclk_cpu_pre",         "pclk_cpu_pre",
1457                                                 "clk_core",             "aclk_core_pre",
1458
1459                                                 "reserved",             "clk_i2s_2ch_pll",
1460                                                 "i2s_2ch_frac",         "hclk_vio_pre",
1461
1462                                                 "clk_crypto",           "clk_i2s_2ch_out",
1463                                                 "clk_i2s_2ch",          "clk_testout";
1464                                         rockchip,suspend-clkgating-setting=<0x0 0x0>;
1465
1466                                         #clock-cells = <1>;
1467                                 };
1468
1469                                 clk_gates1: gate-clk@00d4{
1470                                         compatible = "rockchip,rk3188-gate-clk";
1471                                         reg = <0x00d4 0x4>;
1472                                         clocks =
1473                                                 <&clk_cpll>,            <&dummy>,
1474                                                 <&dummy>,               <&jtag_tck>,
1475
1476                                                 <&aclk_vio1_pre>,               <&xin12m>,
1477                                                 <&xin12m>,              <&clk_mac_pll>,
1478
1479                                                 <&clk_uart0_pll>,               <&uart0_frac>,
1480                                                 <&clk_uart1_div>,               <&uart1_frac>,
1481
1482                                                 <&clk_uart2_div>,               <&uart2_frac>,
1483                                                 <&clk_tsp>,             <&dummy>;
1484
1485                                         clock-output-names =
1486                                                 "pclk_pmu_pre",         "reserved",
1487                                                 "reserved",             "clk_jtag",
1488
1489                                                 "aclk_vio1_pre",                "clk_otgphy0",
1490                                                 "clk_otgphy1",                  "clk_mac_pll",
1491
1492                                                 "clk_uart0_pll",        "uart0_frac",
1493                                                 "clk_uart1_div",        "uart1_frac",
1494
1495                                                 "clk_uart2_div",        "uart2_frac",
1496                                                 "clk_tsp",      "reserved";
1497
1498                                          rockchip,suspend-clkgating-setting=<0x0 0x0>;
1499                                         #clock-cells = <1>;
1500                                 };
1501
1502                                 clk_gates2: gate-clk@00d8 {
1503                                         compatible = "rockchip,rk3188-gate-clk";
1504                                         reg = <0x00d8 0x4>;
1505                                         clocks =
1506                                                 <&aclk_peri>,           <&aclk_peri>,
1507                                                 <&aclk_peri>,           <&aclk_peri>,
1508
1509                                                 <&clk_mac_ref>,         <&clk_mac_ref>,
1510                                                 <&clk_mac_ref>,         <&clk_mac_ref>,
1511
1512                                                 <&clk_saradc>,          <&clk_spi0>,
1513                                                 <&clk_spdif_pll>,               <&clk_sdmmc0>,
1514
1515                                                 <&spdif_frac>,          <&clk_sdio>,
1516                                                 <&clk_emmc>,            <&xin24m>;
1517                                         clock-output-names =
1518                                                 "aclk_peri",            "aclk_peri_pre",
1519                                                 "hclk_peri_pre",                "pclk_peri_pre",
1520
1521                                                 "clk_mac_ref",          "clk_mac_refout",
1522                                                 "clk_mac_rx",           "clk_mac_tx",
1523
1524                                                 "clk_saradc",           "clk_spi0",
1525                                                 "clk_spdif_pll",                "clk_sdmmc0",
1526
1527                                                 "spdif_frac",           "clk_sdio",
1528                                                 "clk_emmc",             "clk_mipi_24m";
1529                                             rockchip,suspend-clkgating-setting=<0x0 0x0>;
1530
1531                                         #clock-cells = <1>;
1532                                 };
1533
1534                                 clk_gates3: gate-clk@00dc {
1535                                         compatible = "rockchip,rk3188-gate-clk";
1536                                         reg = <0x00dc 0x4>;
1537                                         clocks =
1538                                                 <&aclk_vio0_pre>,               <&dclk_lcdc0>,
1539                                                 <&sclk_lcdc0>,          <&pclkin_cif>,
1540
1541                                                 <&dclk_ebc>,                    <&hclk_cpu_pre>,
1542                                                 <&hclk_peri_pre>,               <&clk_cif_pll>,
1543
1544                                                 <&pclk_cpu_pre>,                <&clk_vepu>,
1545                                                 <&clk_hevc_core>,               <&clk_vdpu>,
1546
1547                                                 <&hclk_vdpu>,           <&clk_gpu_pre>,
1548                                                 <&aclk_peri>,           <&clk_sfc>;
1549
1550                                         clock-output-names =
1551                                                 "aclk_vio0_pre",                "dclk_lcdc0",
1552                                                 "sclk_lcdc0",           "pclkin_cif",
1553
1554                                                 "dclk_ebc",             "g_hclk_crypto",
1555                                                 "g_hclk_em_peri",               "clk_cif_pll",
1556
1557                                                 "g_pclk_hdmi",          "clk_vepu",
1558                                                 "clk_hevc_core",                "clk_vdpu",
1559
1560                                                 "hclk_vdpu",            "clk_gpu_pre",
1561                                                 "g_hclk_gps",           "clk_sfc";
1562                                        rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
1563
1564                                         #clock-cells = <1>;
1565                                 };
1566
1567                                 clk_gates4: gate-clk@00e0{
1568                                         compatible = "rockchip,rk3188-gate-clk";
1569                                         reg = <0x00e0 0x4>;
1570                                         clocks =
1571                                                 <&hclk_peri_pre>,               <&pclk_peri_pre>,
1572                                                 <&aclk_peri>,           <&aclk_peri>,
1573
1574                                                 <&clk_i2s_8ch_pll>,             <&i2s_8ch_frac>,
1575                                                 <&clk_i2s_8ch>,         <&dummy>,
1576
1577                                                 <&dummy>,               <&dummy>,
1578                                                 <&aclk_cpu>,            <&dummy>,
1579
1580                                                 <&aclk_cpu>,            <&dummy>,
1581                                                 <&dummy>,               <&dummy>;
1582
1583                                         clock-output-names =
1584                                                 "g_hp_axi_matrix",              "g_pp_axi_matrix",
1585                                                 "g_aclk_cpu_peri",              "g_ap_axi_matrix",
1586
1587                                                 "clk_i2s_8ch_pll",              "i2s_8ch_frac",
1588                                                 "clk_i2s_8ch",          "reserved",
1589
1590                                                 "reserved",             "reserved",
1591                                                 "g_aclk_strc_sys",              "reserved",
1592
1593                                                 /* Not use these ddr gates */
1594                                                 "g_aclk_intmem",                "reserved",
1595                                                 "reserved",             "reserved";
1596
1597                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1598                                         #clock-cells = <1>;
1599                                 };
1600
1601                                 clk_gates5: gate-clk@00e4 {
1602                                         compatible = "rockchip,rk3188-gate-clk";
1603                                         reg = <0x00e4 0x4>;
1604                                         clocks =
1605                                                 <&pclk_cpu_pre>,                <&aclk_peri>,
1606                                                 <&pclk_peri_pre>,               <&dummy>,
1607
1608                                                 <&pclk_cpu_pre>,                <&dummy>,
1609                                                 <&hclk_cpu_pre>,                <&pclk_cpu_pre>,
1610
1611                                                 <&dummy>,               <&hclk_peri_pre>,
1612                                                 <&hclk_peri_pre>,               <&hclk_peri_pre>,
1613
1614                                                 <&dummy>,               <&hclk_peri_pre>,
1615                                                 <&pclk_cpu_pre>,                <&dummy>;
1616
1617                                         clock-output-names =
1618                                                 "g_pclk_mipiphy",               "g_aclk_dmac",
1619                                                 "g_pclk_efuse", "reserved",
1620
1621                                                 "g_pclk_grf",           "reserved",
1622                                                 "g_hclk_rom",           "g_pclk_ddrupctl",
1623
1624                                                 "reserved",             "g_hclk_nandc",
1625                                                 "g_hclk_sdmmc0",                "g_hclk_sdio",
1626
1627                                                 "reserved",             "g_hclk_otg0",
1628                                                 "g_pclk_acodec",                "reserved";
1629
1630                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1631
1632                                         #clock-cells = <1>;
1633                                 };
1634
1635                                 clk_gates6: gate-clk@00e8 {
1636                                         compatible = "rockchip,rk3188-gate-clk";
1637                                         reg = <0x00e8 0x4>;
1638                                         clocks =
1639                                                 <&aclk_vio0_pre>,               <&hclk_vio_pre>,
1640                                                 <&dummy>,               <&dummy>,
1641
1642                                                 <&hclk_vio_pre>,                <&aclk_vio0_pre>,
1643                                                 <&dummy>,               <&dummy>,
1644
1645                                                 <&dummy>,               <&dummy>,
1646                                                 <&hclk_vio_pre>,                        <&aclk_vio0_pre>,
1647
1648                                                 <&hclk_vio_pre>,                <&aclk_vio0_pre>,
1649                                                 <&dummy>,               <&dummy>;
1650
1651                                         clock-output-names =
1652                                                 "g_aclk_lcdc0",         "g_hclk_lcdc0",
1653                                                 "reserved",             "reserved",
1654
1655                                                 "g_hclk_cif",           "g_aclk_cif",
1656                                                 "reserved",             "reserved",
1657
1658                                                 "reserved",             "reserved",
1659                                                 "g_hclk_rga",           "g_aclk_rga",
1660
1661                                                 "g_hclk_vio_bus",               "g_aclk_vio",
1662                                                 "reserved",             "reserved";
1663
1664                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1665
1666                                         #clock-cells = <1>;
1667                                 };
1668
1669                                 clk_gates7: gate-clk@00ec {
1670                                         compatible = "rockchip,rk3188-gate-clk";
1671                                         reg = <0x00ec 0x4>;
1672                                         clocks =
1673                                                 <&hclk_peri_pre>,               <&hclk_peri_pre>,
1674                                                 <&hclk_peri_pre>,               <&hclk_peri_pre>,
1675
1676                                                 <&hclk_peri_pre>,               <&dummy>,
1677                                                 <&dummy>,               <&pclk_peri_pre>,
1678
1679                                                 <&dummy>,               <&dummy>,
1680                                                 <&pclk_peri_pre>,               <&dummy>,
1681
1682                                                 <&pclk_peri_pre>,               <&dummy>,
1683                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>;
1684
1685                                         clock-output-names =
1686                                                 "g_hclk_emmc",          "g_hclk_sfc",
1687                                                 "g_hclk_i2s_2ch",               "g_hclk_host",
1688
1689                                                 "g_hclk_i2s_8ch",               "reserved",
1690                                                 "reserved",             "g_pclk_timer",
1691
1692                                                 "reserved",             "reserved",
1693                                                 "g_pclk_pwm",           "reserved",
1694
1695                                                 "g_pclk_spi0",          "reserved",
1696                                                 "g_pclk_saradc",                "g_pclk_wdt";
1697
1698                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1699
1700                                         #clock-cells = <1>;
1701                                 };
1702
1703                                 clk_gates8: gate-clk@00f0 {
1704                                         compatible = "rockchip,rk3188-gate-clk";
1705                                         reg = <0x00f0 0x4>;
1706                                         clocks =
1707                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1708                                                 <&pclk_peri_pre>,               <&dummy>,
1709
1710                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1711                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1712
1713                                                 <&dummy>,               <&pclk_peri_pre>,
1714                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1715
1716                                                 <&pclk_peri_pre>,               <&dummy>,
1717                                                 <&dummy>,               <&dummy>;
1718
1719                                         clock-output-names =
1720                                                 "g_pclk_uart0",         "g_pclk_uart1",
1721                                                 "g_pclk_uart2",         "reserved",
1722
1723                                                 "g_pclk_i2c0",          "g_pclk_i2c1",
1724                                                 "g_pclk_i2c2",          "g_pclk_i2c3",
1725
1726                                                 "reserved",             "g_pclk_gpio0",
1727                                                 "g_pclk_gpio1",         "g_pclk_gpio2",
1728
1729                                                 "g_pclk_gpio3",         "reserved",
1730                                                 "reserved",             "reserved";
1731
1732                                         rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
1733                                         #clock-cells = <1>;
1734                                 };
1735
1736                                 clk_gates9: gate-clk@00f4 {
1737                                         compatible = "rockchip,rk3188-gate-clk";
1738                                         reg = <0x00f4 0x4>;
1739                                         clocks =
1740                                                 <&dummy>,               <&dummy>,
1741                                                 <&pclk_pmu_pre>,                <&pclk_pmu_pre>,
1742
1743                                                 <&dummy>,               <&hclk_vio_pre>,
1744                                                 <&hclk_vio_pre>,                <&hclk_vio_pre>,
1745
1746                                                 <&aclk_vio1_pre>,               <&hclk_vio_pre>,
1747                                                 <&aclk_vio1_pre>,               <&dummy>,
1748
1749                                                 <&pclk_peri_pre>,               <&hclk_peri_pre>,
1750                                                 <&hclk_peri_pre>,               <&aclk_peri>;
1751
1752                                         clock-output-names =
1753                                                 "reserved",             "reserved",
1754                                                 "g_pclk_pmu",           "g_pclk_pmu_noc",
1755
1756                                                 "reserved",             "g_hclk_vio_h2p",
1757                                                 "g_pclk_mipi",          "g_hclk_iep",
1758
1759                                                 "g_aclk_iep",           "g_hclk_ebc",
1760                                                 "g_aclk_vio1_niu",              "reserved",
1761
1762                                                 "g_pclk_sim_card",              "g_hclk_usb_peri",
1763                                                 "g_hclk_pe_arbi",               "g_aclk_peri_niu";
1764
1765                                         rockchip,suspend-clkgating-setting=<0x0 0x0>;
1766
1767                                         #clock-cells = <1>;
1768                                 };
1769
1770                                 clk_gates10: gate-clk@00f8 {
1771                                         compatible = "rockchip,rk3188-gate-clk";
1772                                         reg = <0x00f8 0x4>;
1773                                         clocks =
1774                                                 <&xin24m>,              <&xin24m>,
1775                                                 <&xin24m>,              <&xin24m>,
1776
1777                                                 <&xin24m>,              <&xin24m>,
1778                                                 <&xin24m>,              <&xin24m>,
1779
1780                                                 <&xin24m>,              <&hclk_peri_pre>,
1781                                                 <&aclk_peri>,           <&pclk_peri_pre>,
1782
1783                                                 <&hclk_peri_pre>,               <&clk_tsp_in>,
1784                                                 <&hclk_peri_pre>,               <&clk_nandc>;
1785
1786                                         clock-output-names =
1787                                                 "clk_pvtm_core",                "clk_pvtm_gpu",
1788                                                 "clk_pvtm_func",                "clk_timer0",
1789
1790                                                 "clk_timer1",           "clk_timer2",
1791                                                 "clk_timer3",           "clk_timer4",
1792
1793                                                 "clk_timer5",           "g_hclk_spdif",
1794                                                 "g_aclk_gmac",          "g_pclk_gmac",
1795
1796                                                 "g_hclk_tsp",           "g_clkin0_tsp",
1797                                                 "g_hclk_usbhost",               "clk_nandc";
1798
1799                                         rockchip,suspend-clkgating-setting = <0x0 0x0>; /* pwm logic vol */
1800
1801                                         #clock-cells = <1>;
1802                                 };
1803
1804                         };
1805                 };
1806         };
1807 };