arch/arm/boot/dts/rk312x-clocks.dtsi

   1 /*
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <dt-bindings/clock/rockchip,rk312x.h>
  15
  16 /{
  17
  18         clocks {
  19                 compatible = "rockchip,rk-clocks";
  20                 #address-cells = <1>;
  21                 #size-cells = <1>;
  22                 ranges = <0x0  0x20000000  0x1f0>;
  23
  24                 fixed_rate_cons {
  25                         compatible = "rockchip,rk-fixed-rate-cons";
  26
  27                         xin24m: xin24m {
  28                                 compatible = "rockchip,rk-fixed-clock";
  29                                 clock-output-names = "xin24m";
  30                                 clock-frequency = <24000000>;
  31                                 #clock-cells = <0>;
  32                         };
  33
  34                         xin12m: xin12m {
  35                                 compatible = "rockchip,rk-fixed-clock";
  36                                 clocks = <&xin24m>;
  37                                 clock-output-names = "xin12m";
  38                                 clock-frequency = <12000000>;
  39                                 #clock-cells = <0>;
  40                         };
  41
  42                         gmac_clkin: rmii_clkin {
  43                                 compatible = "rockchip,rk-fixed-clock";
  44                                 clock-output-names = "gmac_clkin";
  45                                 clock-frequency = <0>;
  46                                 #clock-cells = <0>;
  47                         };
  48
  49                         usb480m: usb480m {
  50                                 compatible = "rockchip,rk-fixed-clock";
  51                                 clock-output-names = "usb480m";
  52                                 clock-frequency = <480000000>;
  53                                 #clock-cells = <0>;
  54                         };
  55
  56                         i2s_clkin: i2s_clkin {
  57                                 compatible = "rockchip,rk-fixed-clock";
  58                                 clock-output-names = "i2s_clkin";
  59                                 clock-frequency = <0>;
  60                                 #clock-cells = <0>;
  61                         };
  62
  63                         jtag_tck: jtag_tck {
  64                                 compatible = "rockchip,rk-fixed-clock";
  65                                 clock-output-names = "jtag_tck";
  66                                 clock-frequency = <0>;
  67                                 #clock-cells = <0>;
  68                         };
  69
  70                         pclkin_cif: pclkin_cif {
  71                                 compatible = "rockchip,rk-fixed-clock";
  72                                 clock-output-names = "pclkin_cif";
  73                                 clock-frequency = <0>;
  74                                 #clock-cells = <0>;
  75                         };
  76
  77                         clk_tsp_in: clk_tsp_in {
  78                                 compatible = "rockchip,rk-fixed-clock";
  79                                 clock-output-names = "clk_tsp_in";
  80                                 clock-frequency = <0>;
  81                                 #clock-cells = <0>;
  82                         };
  83
  84
  85                         dummy: dummy {
  86                                 compatible = "rockchip,rk-fixed-clock";
  87                                 clock-output-names = "dummy";
  88                                 clock-frequency = <0>;
  89                                 #clock-cells = <0>;
  90                         };
  91
  92                         dummy_cpll: dummy_cpll {
  93                                 compatible = "rockchip,rk-fixed-clock";
  94                                 clock-output-names = "dummy_cpll";
  95                                 clock-frequency = <0>;
  96                                 #clock-cells = <0>;
  97                         };
  98
  99                 };
 100
 101                 fixed_factor_cons {
 102                         compatible = "rockchip,rk-fixed-factor-cons";
 103
 104                         clk_gpll_div2: clk_gpll_div2 {
 105                                 compatible = "rockchip,rk-fixed-factor-clock";
 106                                 clocks = <&clk_gpll>;
 107                                 clock-output-names = "clk_gpll_div2";
 108                                 clock-div = <2>;
 109                                 clock-mult = <20>;
 110                                 #clock-cells = <0>;
 111                         };
 112
 113                         clk_gpll_div3: clk_gpll_div3 {
 114                                 compatible = "rockchip,rk-fixed-factor-clock";
 115                                 clocks = <&clk_gpll>;
 116                                 clock-output-names = "clk_gpll_div3";
 117                                 clock-div = <3>;
 118                                 clock-mult = <20>;
 119                                 #clock-cells = <0>;
 120                         };
 121
 122                         clk_pvtm_func: clk_pvtm_func {
 123                                 compatible = "rockchip,rk-fixed-factor-clock";
 124                                 clocks = <&xin24m>;
 125                                 clock-output-names = "clk_pvtm_func";
 126                                 clock-div = <1>;
 127                                 clock-mult = <20>;
 128                                 #clock-cells = <0>;
 129                         };
 130
 131                         hclk_vepu: hclk_vepu {
 132                                 compatible = "rockchip,rk-fixed-factor-clock";
 133                                 clocks = <&clk_vepu>;
 134                                 clock-output-names = "hclk_vepu";
 135                                 clock-div = <4>;
 136                                 clock-mult = <1>;
 137                                 #clock-cells = <0>;
 138                         };
 139
 140                         hclk_vdpu: hclk_vdpu {
 141                                 compatible = "rockchip,rk-fixed-factor-clock";
 142                                 clocks = <&clk_vdpu>;
 143                                 clock-output-names = "hclk_vdpu";
 144                                 clock-div = <4>;
 145                                 clock-mult = <1>;
 146                                 #clock-cells = <0>;
 147                         };
 148
 149                 };
 150
 151                 clock_regs {
 152                         compatible = "rockchip,rk-clock-regs";
 153                         #address-cells = <1>;
 154                         #size-cells = <1>;
 155                         reg = <0x0000 0x01f0>;
 156                         ranges;
 157
 158                         /* PLL control regs */
 159                         pll_cons {
 160                                 compatible = "rockchip,rk-pll-cons";
 161                                 #address-cells = <1>;
 162                                 #size-cells = <1>;
 163                                 ranges ;
 164
 165                                 clk_apll: pll-clk@0000 {
 166                                         compatible = "rockchip,rk3188-pll-clk";
 167                                         reg = <0x0000 0x10>;
 168                                         mode-reg = <0x0040 0>;
 169                                         status-reg = <0x0004 10>;
 170                                         clocks = <&xin24m>;
 171                                         clock-output-names = "clk_apll";
 172                                         rockchip,pll-type = <CLK_PLL_3036_APLL>;
 173                                         #clock-cells = <0>;
 174                                 };
 175
 176                                 clk_dpll: pll-clk@0010 {
 177                                         compatible = "rockchip,rk3188-pll-clk";
 178                                         reg = <0x0010 0x10>;
 179                                         mode-reg = <0x0040 4>;
 180                                         status-reg = <0x0014 10>;
 181                                         clocks = <&xin24m>;
 182                                         clock-output-names = "clk_dpll";
 183                                         rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
 184                                         #clock-cells = <0>;
 185                                 };
 186
 187                                 clk_cpll: pll-clk@0020 {
 188                                         compatible = "rockchip,rk3188-pll-clk";
 189                                         reg = <0x0020 0x10>;
 190                                         mode-reg = <0x0040 8>;
 191                                         status-reg = <0x0024 10>;
 192                                         clocks = <&xin24m>;
 193                                         clock-output-names = "clk_cpll";
 194                                         rockchip,pll-type = <CLK_PLL_312XPLUS>;
 195                                         #clock-cells = <0>;
 196                                 };
 197
 198                                 clk_gpll: pll-clk@0030 {
 199                                         compatible = "rockchip,rk3188-pll-clk";
 200                                         reg = <0x0030 0x10>;
 201                                         mode-reg = <0x0040 12>;
 202                                         status-reg = <0x0034 10>;
 203                                         clocks = <&xin24m>;
 204                                         clock-output-names = "clk_gpll";
 205                                         rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
 206                                         #clock-cells = <0>;
 207                                         #clock-init-cells = <1>;
 208                                 };
 209
 210                         };
 211
 212                         /* Select control regs */
 213                         clk_sel_cons {
 214                                 compatible = "rockchip,rk-sel-cons";
 215                                 #address-cells = <1>;
 216                                 #size-cells = <1>;
 217                                 ranges;
 218
 219                                 clk_sel_con0: sel-con@0044 {
 220                                         compatible = "rockchip,rk3188-selcon";
 221                                         reg = <0x0044 0x4>;
 222                                         #address-cells = <1>;
 223                                         #size-cells = <1>;
 224
 225                                         clk_core_div: clk_core_div {
 226                                                 compatible = "rockchip,rk3188-div-con";
 227                                                 rockchip,bits = <0 5>;
 228                                                 clocks = <&clk_core>;
 229                                                 clock-output-names = "clk_core";
 230                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 231                                                 #clock-cells = <0>;
 232                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 233                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 234                                                                         CLK_SET_RATE_NO_REPARENT)>;
 235                                         };
 236
 237                                         /* reg[6:5]: reserved */
 238
 239                                         clk_core: clk_core_mux {
 240                                                 compatible = "rockchip,rk3188-mux-con";
 241                                                 rockchip,bits = <7 1>;
 242                                                 clocks = <&clk_apll>, <&clk_gpll_div2>;
 243                                                 clock-output-names = "clk_core";
 244                                                 #clock-cells = <0>;
 245                                                 #clock-init-cells = <1>;
 246                                         };
 247
 248                                         aclk_cpu_pre_div: aclk_cpu_pre_div {
 249                                                 compatible = "rockchip,rk3188-div-con";
 250                                                 rockchip,bits = <8 5>;
 251                                                 clocks = <&aclk_cpu_pre>;
 252                                                 clock-output-names = "aclk_cpu_pre";
 253                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 254                                                 #clock-cells = <0>;
 255                                                 rockchip,clkops-idx =
 256                                                         <CLKOPS_RATE_MUX_DIV>;
 257                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 258                                         };
 259
 260                                         aclk_cpu_pre: aclk_cpu_pre_mux {
 261                                                 compatible = "rockchip,rk3188-mux-con";
 262                                                 rockchip,bits = <13 2>;
 263                                                 clocks = <&clk_apll>, <&clk_gpll>,<&clk_gpll_div2>,<&clk_gpll_div3>;
 264                                                 clock-output-names = "aclk_cpu_pre";
 265                                                 #clock-cells = <0>;
 266                                                 #clock-init-cells = <1>;
 267                                         };
 268
 269                                         /* reg[15]: reserved */
 270
 271                                 };
 272
 273                                 clk_sel_con1: sel-con@0048 {
 274                                         compatible = "rockchip,rk3188-selcon";
 275                                         reg = <0x0048 0x4>;
 276                                         #address-cells = <1>;
 277                                         #size-cells = <1>;
 278
 279                                         pclk_dbg_div:  pclk_dbg_div {
 280                                                 compatible = "rockchip,rk3188-div-con";
 281                                                 rockchip,bits = <0 4>;
 282                                                 clocks = <&clk_core>;
 283                                                 clock-output-names = "pclk_dbg";
 284                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 285                                                 #clock-cells = <0>;
 286                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 287                                         };
 288
 289                                         aclk_core_pre: aclk_core_pre_div {
 290                                                 compatible = "rockchip,rk3188-div-con";
 291                                                 rockchip,bits = <4 3>;
 292                                                 clocks = <&clk_core>;
 293                                                 clock-output-names = "aclk_core_pre";
 294                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 295                                                 #clock-cells = <0>;
 296                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 297                                         };
 298
 299                                         /* reg[7]: reserved */
 300
 301                                         hclk_cpu_pre: hclk_cpu_pre_div {
 302                                                 compatible = "rockchip,rk3188-div-con";
 303                                                 rockchip,bits = <8 2>;
 304                                                 clocks = <&aclk_cpu_pre>;
 305                                                 clock-output-names = "hclk_cpu_pre";
 306                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 307                                                 #clock-cells = <0>;
 308                                                 #clock-init-cells = <1>;
 309                                         };
 310
 311                                         /* reg[11:10]: reserved */
 312
 313                                         pclk_cpu_pre: pclk_cpu_pre_div {
 314                                                 compatible = "rockchip,rk3188-div-con";
 315                                                 rockchip,bits = <12 3>;
 316                                                 clocks = <&aclk_cpu_pre>;
 317                                                 clock-output-names = "pclk_cpu_pre";
 318                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 319                                                 #clock-cells = <0>;
 320                                                 #clock-init-cells = <1>;
 321                                         };
 322
 323                                         /* reg[15]: reserved */
 324                                 };
 325
 326                                 clk_sel_con2: sel-con@004c {
 327                                         compatible = "rockchip,rk3188-selcon";
 328                                         reg = <0x004c 0x4>;
 329                                         #address-cells = <1>;
 330                                         #size-cells = <1>;
 331
 332                                         clk_pvtm_div: clk_pvtm_div {
 333                                                 compatible = "rockchip,rk3188-mux-con";
 334                                                 rockchip,bits = <0 7>;
 335                                                 clocks = <&clk_pvtm_func>;
 336                                                 clock-output-names = "clk_pvtm";
 337                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 338                                                 #clock-cells = <0>;
 339                                                 #clock-init-cells = <1>;
 340                                         };
 341
 342                                         /* reg[7]: reserved */
 343
 344                                         clk_nandc_div: clk_nandc_div {
 345                                                 compatible = "rockchip,rk3188-div-con";
 346                                                 rockchip,bits = <8 5>;
 347                                                 clocks = <&clk_nandc>;
 348                                                 clock-output-names = "clk_nandc";
 349                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 350                                                 #clock-cells = <0>;
 351                                                 rockchip,clkops-idx =
 352                                                         <CLKOPS_RATE_MUX_DIV>;
 353                                         };
 354
 355                                         /* reg[13]: reserved */
 356
 357                                         clk_nandc: clk_nandc_mux {
 358                                                 compatible = "rockchip,rk3188-mux-con";
 359                                                 rockchip,bits = <14 2>;
 360                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
 361                                                 clock-output-names = "clk_nandc";
 362                                                 #clock-cells = <0>;
 363                                         };
 364
 365                                 };
 366
 367                                 clk_sel_con3: sel-con@0050 {
 368                                         compatible = "rockchip,rk3188-selcon";
 369                                         reg = <0x0050 0x4>;
 370                                         #address-cells = <1>;
 371                                         #size-cells = <1>;
 372
 373                                         clk_i2s_2ch_pll_div: clk_i2s_2ch_pll_div {
 374                                                 compatible = "rockchip,rk3188-div-con";
 375                                                 rockchip,bits = <0 7>;
 376                                                 clocks = <&clk_i2s_2ch_pll>;
 377                                                 clock-output-names = "clk_i2s_2ch_pll";
 378                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 379                                                 #clock-cells = <0>;
 380                                                 rockchip,clkops-idx =
 381                                                         <CLKOPS_RATE_MUX_DIV>;
 382                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 383                                         };
 384
 385                                         /* reg[7]: reserved */
 386
 387                                         clk_i2s_2ch: clk_i2s_2ch_mux {
 388                                                 compatible = "rockchip,rk3188-mux-con";
 389                                                 rockchip,bits = <8 2>;
 390                                                 clocks = <&clk_i2s_2ch_pll_div>, <&i2s_2ch_frac>, <&i2s_clkin>, <&xin12m>;
 391                                                 clock-output-names = "clk_i2s_2ch";
 392                                                 #clock-cells = <0>;
 393                                                 rockchip,clkops-idx =
 394                                                         <CLKOPS_RATE_RK3288_I2S>;
 395                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 396                                         };
 397
 398                                         /* reg[11:10]: reserved */
 399
 400                                         clk_i2s_2ch_out: clk_i2s_2ch_out_mux {
 401                                                 compatible = "rockchip,rk3188-mux-con";
 402                                                 rockchip,bits = <12 1>;
 403                                                 clocks = <&clk_i2s_2ch>, <&xin12m>;
 404                                                 clock-output-names = "i2s_clkout";
 405                                                 #clock-cells = <0>;
 406                                         };
 407
 408                                         /* reg[13]: reserved */
 409
 410                                         clk_i2s_2ch_pll: i2s_2ch_pll_mux {
 411                                                 compatible = "rockchip,rk3188-mux-con";
 412                                                 rockchip,bits = <14 2>;
 413                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
 414                                                 clock-output-names = "clk_i2s_2ch_pll";
 415                                                 #clock-cells = <0>;
 416                                                 #clock-init-cells = <1>;
 417                                         };
 418
 419                                 };
 420
 421                                 clk_sel_con4: sel-con@0054 {
 422                                         compatible = "rockchip,rk3188-selcon";
 423                                         reg = <0x0054 0x4>;
 424                                         #address-cells = <1>;
 425                                         #size-cells = <1>;
 426
 427                                         clk_tsp_div: clk_tsp_div {
 428                                                 compatible = "rockchip,rk3188-div-con";
 429                                                 rockchip,bits = <0 5>;
 430                                                 clocks = <&clk_tsp>;
 431                                                 clock-output-names = "clk_tsp";
 432                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 433                                                 #clock-cells = <0>;
 434                                                 rockchip,clkops-idx =
 435                                                         <CLKOPS_RATE_MUX_DIV>;
 436                                         };
 437
 438                                         /* reg[5]: reserved */
 439
 440                                         clk_tsp: clk_tsp_mux {
 441                                                 compatible = "rockchip,rk3188-mux-con";
 442                                                 rockchip,bits = <6 2>;
 443                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
 444                                                 clock-output-names = "clk_tsp";
 445                                                 #clock-cells = <0>;
 446                                                 #clock-init-cells = <1>;
 447                                         };
 448
 449                                         clk_24m_div: clk_24m_div {
 450                                                 compatible = "rockchip,rk3188-div-con";
 451                                                 rockchip,bits = <8 5>;
 452                                                 clocks = <&xin24m>;
 453                                                 clock-output-names = "clk_24m";
 454                                                 #clock-cells = <0>;
 455                                         };
 456
 457                                         /* reg[15:13]: reserved */
 458
 459                                 };
 460
 461
 462                                 clk_sel_con5: sel-con@0058 {
 463                                         compatible = "rockchip,rk3188-selcon";
 464                                         reg = <0x0058 0x4>;
 465                                         #address-cells = <1>;
 466                                         #size-cells = <1>;
 467
 468                                         clk_mac_pll_div: clk_mac_pll_div {
 469                                                 compatible = "rockchip,rk3188-div-con";
 470                                                 rockchip,bits = <0 5>;
 471                                                 clocks = <&clk_mac_pll>;
 472                                                 clock-output-names = "clk_mac_pll";
 473                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 474                                                 #clock-cells = <0>;
 475                                                 rockchip,clkops-idx =
 476                                                         <CLKOPS_RATE_MUX_DIV>;
 477                                         };
 478
 479                                         /* reg[5]: reserved */
 480
 481                                         clk_mac_pll: clk_mac_pll_mux {
 482                                                 compatible = "rockchip,rk3188-mux-con";
 483                                                 rockchip,bits = <6 2>;
 484                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
 485                                                 clock-output-names = "clk_mac_pll";
 486                                                 #clock-cells = <0>;
 487                                                 #clock-init-cells = <1>;
 488                                         };
 489
 490                                         /* reg[14:8]: reserved */
 491
 492                                         clk_mac_ref: clk_mac_ref_mux {
 493                                                 compatible = "rockchip,rk3188-mux-con";
 494                                                 rockchip,bits = <15 1>;
 495                                                 clocks = <&clk_mac_pll_div>, <&gmac_clkin>;
 496                                                 clock-output-names = "clk_mac_ref";
 497                                                 #clock-cells = <0>;
 498                                                 rockchip,clkops-idx =
 499                                                         <CLKOPS_RATE_MAC_REF>;
 500                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 501                                                 #clock-init-cells = <1>;
 502                                         };
 503
 504                                 };
 505
 506
 507                                 clk_sel_con6: sel-con@005c {
 508                                         compatible = "rockchip,rk3188-selcon";
 509                                         reg = <0x005c 0x4>;
 510                                         #address-cells = <1>;
 511                                         #size-cells = <1>;
 512
 513                                         spdif_div: spdif_div {
 514                                                 compatible = "rockchip,rk3188-div-con";
 515                                                 rockchip,bits = <0 7>;
 516                                                 clocks = <&clk_spdif_pll>;
 517                                                 clock-output-names = "clk_spdif_pll";
 518                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 519                                                 #clock-cells = <0>;
 520                                                 rockchip,clkops-idx =
 521                                                         <CLKOPS_RATE_MUX_DIV>;
 522                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 523                                         };
 524
 525                                         /* reg[7]: reserved */
 526
 527                                         clk_spdif: spdif_mux {
 528                                                 compatible = "rockchip,rk3188-mux-con";
 529                                                 rockchip,bits = <8 2>;
 530                                                 clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>;
 531                                                 clock-output-names = "clk_spdif";
 532                                                 #clock-cells = <0>;
 533                                                 rockchip,clkops-idx =
 534                                                         <CLKOPS_RATE_RK3288_I2S>;
 535                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 536                                         };
 537
 538                                         /* reg[13:10]: reserved */
 539
 540                                         clk_spdif_pll: spdif_pll_mux {
 541                                                 compatible = "rockchip,rk3188-mux-con";
 542                                                 rockchip,bits = <14 2>;
 543                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
 544                                                 clock-output-names = "clk_spdif_pll";
 545                                                 #clock-cells = <0>;
 546                                                 #clock-init-cells = <1>;
 547                                         };
 548
 549                                 };
 550
 551                                 clk_sel_con7: sel-con@0060 {
 552                                         compatible = "rockchip,rk3188-selcon";
 553                                         reg = <0x0060 0x4>;
 554                                         #address-cells = <1>;
 555                                         #size-cells = <1>;
 556
 557                                         i2s_2ch_frac: i2s_2ch_frac {
 558                                                 compatible = "rockchip,rk3188-frac-con";
 559                                                 clocks = <&clk_i2s_2ch_pll>;
 560                                                 clock-output-names = "i2s_2ch_frac";
 561                                                 /* numerator    denominator */
 562                                                 rockchip,bits = <0 32>;
 563                                                 rockchip,clkops-idx =
 564                                                         <CLKOPS_RATE_FRAC>;
 565                                                 #clock-cells = <0>;
 566                                         };
 567                                 };
 568
 569                                 clk_sel_con8: sel-con@0064 {
 570                                         compatible = "rockchip,rk3188-selcon";
 571                                         reg = <0x0064 0x4>;
 572                                         #address-cells = <1>;
 573                                         #size-cells = <1>;
 574
 575                                         i2s_8ch_frac: i2s_8ch_frac {
 576                                                 compatible = "rockchip,rk3188-frac-con";
 577                                                 clocks = <&clk_i2s_8ch_pll>;
 578                                                 clock-output-names = "i2s_8ch_frac";
 579                                                 /* numerator    denominator */
 580                                                 rockchip,bits = <0 32>;
 581                                                 rockchip,clkops-idx =
 582                                                         <CLKOPS_RATE_FRAC>;
 583                                                 #clock-cells = <0>;
 584                                         };
 585                                 };
 586
 587                                 clk_sel_con9: sel-con@0068 {
 588                                         compatible = "rockchip,rk3188-selcon";
 589                                         reg = <0x0068 0x4>;
 590                                         #address-cells = <1>;
 591                                         #size-cells = <1>;
 592
 593                                         clk_i2s_8ch_pll_div: clk_i2s_8ch_pll_div {
 594                                                 compatible = "rockchip,rk3188-div-con";
 595                                                 rockchip,bits = <0 7>;
 596                                                 clocks = <&clk_i2s_8ch_pll>;
 597                                                 clock-output-names = "clk_i2s_8ch_pll";
 598                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 599                                                 #clock-cells = <0>;
 600                                                 rockchip,clkops-idx =
 601                                                         <CLKOPS_RATE_MUX_DIV>;
 602                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 603                                         };
 604
 605                                         /* reg[7]: reserved */
 606
 607                                         clk_i2s_8ch: clk_i2s_8ch_mux {
 608                                                 compatible = "rockchip,rk3188-mux-con";
 609                                                 rockchip,bits = <8 2>;
 610                                                 clocks = <&clk_i2s_8ch_pll_div>, <&i2s_8ch_frac>, <&i2s_clkin>, <&xin12m>;
 611                                                 clock-output-names = "clk_i2s_8ch";
 612                                                 #clock-cells = <0>;
 613                                                 rockchip,clkops-idx =
 614                                                         <CLKOPS_RATE_RK3288_I2S>;
 615                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 616                                         };
 617
 618                                         /* reg[13:10]: reserved */
 619
 620                                         clk_i2s_8ch_pll: i2s_8ch_pll_mux {
 621                                                 compatible = "rockchip,rk3188-mux-con";
 622                                                 rockchip,bits = <14 2>;
 623                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
 624                                                 clock-output-names = "clk_i2s_8ch_pll";
 625                                                 #clock-cells = <0>;
 626                                                 #clock-init-cells = <1>;
 627                                         };
 628
 629                                 };
 630
 631                                 clk_sel_con10: sel-con@006c {
 632                                         compatible = "rockchip,rk3188-selcon";
 633                                         reg = <0x006c 0x4>;
 634                                         #address-cells = <1>;
 635                                         #size-cells = <1>;
 636
 637                                         aclk_peri_pre_div: aclk_peri_pre_div {
 638                                                 compatible = "rockchip,rk3188-div-con";
 639                                                 rockchip,bits = <0 5>;
 640                                                 clocks = <&aclk_peri_pre>;
 641                                                 clock-output-names = "aclk_peri_pre";
 642                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 643                                                 #clock-cells = <0>;
 644                                                 rockchip,clkops-idx =
 645                                                         <CLKOPS_RATE_MUX_DIV>;
 646                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 647                                         };
 648
 649                                         /* reg[7:5]: reserved */
 650
 651                                         hclk_peri_pre: hclk_peri_pre_div {
 652                                                 compatible = "rockchip,rk3188-div-con";
 653                                                 rockchip,bits = <8 2>;
 654                                                 clocks = <&aclk_peri_pre>;
 655                                                 clock-output-names = "hclk_peri_pre";
 656                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 657                                                 rockchip,div-relations =
 658                                                                 <0x0 1
 659                                                                  0x1 2
 660                                                                  0x2 4>;
 661                                                 #clock-cells = <0>;
 662                                                 #clock-init-cells = <1>;
 663                                         };
 664
 665                                         /* reg[11:10]: reserved */
 666
 667                                         pclk_peri_pre: pclk_peri_div {
 668                                                 compatible = "rockchip,rk3188-div-con";
 669                                                 rockchip,bits = <12 2>;
 670                                                 clocks = <&aclk_peri_pre>;
 671                                                 clock-output-names = "pclk_peri_pre";
 672                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 673                                                 rockchip,div-relations =
 674                                                                 <0x0 1
 675                                                                  0x1 2
 676                                                                  0x2 4
 677                                                                  0x3 8>;
 678                                                 #clock-cells = <0>;
 679                                                 #clock-init-cells = <1>;
 680                                         };
 681
 682                                         aclk_peri_pre: aclk_peri_pre_mux {
 683                                                 compatible = "rockchip,rk3188-mux-con";
 684                                                 rockchip,bits = <14 2>;
 685                                                 clocks = <&clk_gpll>,<&clk_cpll>,<&clk_gpll_div2>,<&clk_gpll_div3>;
 686                                                 clock-output-names = "aclk_peri_pre";
 687                                                 #clock-cells = <0>;
 688                                                 #clock-init-cells = <1>;
 689                                         };
 690                                 };
 691
 692                                 clk_sel_con11: sel-con@0070 {
 693                                         compatible = "rockchip,rk3188-selcon";
 694                                         reg = <0x0070 0x4>;
 695                                         #address-cells = <1>;
 696                                         #size-cells = <1>;
 697
 698                                         clk_sdmmc0_div: clk_sdmmc0_div {
 699                                                 compatible = "rockchip,rk3188-div-con";
 700                                                 rockchip,bits = <0 6>;
 701                                                 clocks = <&clk_sdmmc0>;
 702                                                 clock-output-names = "clk_sdmmc0";
 703                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 704                                                 #clock-cells = <0>;
 705                                                 rockchip,clkops-idx =
 706                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 707                                         };
 708
 709                                         clk_sdmmc0: clk_sdmmc0_mux {
 710                                                 compatible = "rockchip,rk3188-mux-con";
 711                                                 rockchip,bits = <6 2>;
 712                                                 clocks = <&clk_cpll>,<&clk_gpll>,<&clk_gpll_div2>,<&xin24m>;
 713                                                 clock-output-names = "clk_sdmmc0";
 714                                                 #clock-cells = <0>;
 715                                                 #clock-init-cells = <1>;
 716                                         };
 717
 718                                         clk_sfc_div: clk_sfc_div {
 719                                                 compatible = "rockchip,rk3188-div-con";
 720                                                 rockchip,bits = <8 5>;
 721                                                 clocks = <&clk_sfc>;
 722                                                 clock-output-names = "clk_sfc";
 723                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 724                                                 #clock-cells = <0>;
 725                                                 rockchip,clkops-idx =
 726                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 727                                         };
 728
 729                                         /* reg[13]: reserved */
 730
 731                                         clk_sfc: clk_sfc_mux {
 732                                                 compatible = "rockchip,rk3188-mux-con";
 733                                                 rockchip,bits = <14 2>;
 734                                                 clocks = <&clk_cpll>,<&clk_gpll>,<&clk_gpll_div2>,<&xin24m>;
 735                                                 clock-output-names = "clk_sfc";
 736                                                 #clock-cells = <0>;
 737                                                 #clock-init-cells = <1>;
 738                                         };
 739
 740                                 };
 741
 742                                 clk_sel_con12: sel-con@0074 {
 743                                         compatible = "rockchip,rk3188-selcon";
 744                                         reg = <0x0074 0x4>;
 745                                         #address-cells = <1>;
 746                                         #size-cells = <1>;
 747
 748                                         clk_sdio_div: clk_sdio_div {
 749                                                 compatible = "rockchip,rk3188-div-con";
 750                                                 rockchip,bits = <0 6>;
 751                                                 clocks = <&clk_sdio>;
 752                                                 clock-output-names = "clk_sdio";
 753                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 754                                                 #clock-cells = <0>;
 755                                                 rockchip,clkops-idx =
 756                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 757                                         };
 758
 759                                         clk_sdio: clk_sdio_mux {
 760                                                 compatible = "rockchip,rk3188-mux-con";
 761                                                 rockchip,bits = <6 2>;
 762                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&xin24m>;
 763                                                 clock-output-names = "clk_sdio";
 764                                                 #clock-cells = <0>;
 765                                         };
 766
 767                                         clk_emmc_div: clk_emmc_div {
 768                                                 compatible = "rockchip,rk3188-div-con";
 769                                                 rockchip,bits = <8 6>;
 770                                                 clocks = <&clk_emmc>;
 771                                                 clock-output-names = "clk_emmc";
 772                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 773                                                 #clock-cells = <0>;
 774                                                 rockchip,clkops-idx =
 775                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 776                                         };
 777
 778                                         clk_emmc: clk_emmc_mux {
 779                                                 compatible = "rockchip,rk3188-mux-con";
 780                                                 rockchip,bits = <14 2>;
 781                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&xin24m>;
 782                                                 clock-output-names = "clk_emmc";
 783                                                 #clock-cells = <0>;
 784                                         };
 785
 786                                 };
 787
 788                                 clk_sel_con13: sel-con@0078 {
 789                                         compatible = "rockchip,rk3188-selcon";
 790                                         reg = <0x0078 0x4>;
 791                                         #address-cells = <1>;
 792                                         #size-cells = <1>;
 793
 794                                         clk_uart0_pll_div: clk_uart0_pll_div {
 795                                                 compatible = "rockchip,rk3188-div-con";
 796                                                 rockchip,bits = <0 7>;
 797                                                 clocks = <&clk_uart0_pll>;
 798                                                 clock-output-names = "clk_uart0_pll";
 799                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 800                                                 #clock-cells = <0>;
 801                                         };
 802
 803                                         /* reg[7]: reserved */
 804
 805                                         clk_uart0: clk_uart0_mux {
 806                                                 compatible = "rockchip,rk3188-mux-con";
 807                                                 rockchip,bits = <8 2>;
 808                                                 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>;
 809                                                 clock-output-names = "clk_uart0";
 810                                                 #clock-cells = <0>;
 811                                                 rockchip,clkops-idx =
 812                                                         <CLKOPS_RATE_RK3288_I2S>;
 813                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 814                                         };
 815
 816                                         /* reg[11:10]: reserved */
 817
 818                                         clk_uart0_pll: clk_uart0_pll_mux {
 819                                                 compatible = "rockchip,rk3188-mux-con";
 820                                                 rockchip,bits = <12 2>;
 821                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
 822                                                 clock-output-names = "clk_uart0_pll";
 823                                                 #clock-cells = <0>;
 824                                                 #clock-init-cells = <1>;
 825                                         };
 826
 827                                         clk_uart2_pll: clk_uart2_pll_mux {
 828                                                 compatible = "rockchip,rk3188-mux-con";
 829                                                 rockchip,bits = <14 2>;
 830                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
 831                                                 clock-output-names = "clk_uart2_pll";
 832                                                 #clock-cells = <0>;
 833                                                 #clock-init-cells = <1>;
 834                                         };
 835
 836                                 };
 837
 838                                 clk_sel_con14: sel-con@007c {
 839                                         compatible = "rockchip,rk3188-selcon";
 840                                         reg = <0x007c 0x4>;
 841                                         #address-cells = <1>;
 842                                         #size-cells = <1>;
 843
 844                                         clk_uart1_div: clk_uart1_div {
 845                                                 compatible = "rockchip,rk3188-div-con";
 846                                                 rockchip,bits = <0 7>;
 847                                                 clocks = <&clk_uart2_pll>;
 848                                                 clock-output-names = "clk_uart1_div";
 849                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 850                                                 #clock-cells = <0>;
 851                                         };
 852
 853                                         /* reg[7]: reserved */
 854
 855                                         clk_uart1: clk_uart1_mux {
 856                                                 compatible = "rockchip,rk3188-mux-con";
 857                                                 rockchip,bits = <8 2>;
 858                                                 clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>;
 859                                                 clock-output-names = "clk_uart1";
 860                                                 #clock-cells = <0>;
 861                                                 rockchip,clkops-idx =
 862                                                         <CLKOPS_RATE_RK3288_I2S>;
 863                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 864                                         };
 865
 866                                         /* reg[15:10]: reserved */
 867                                 };
 868
 869                                 clk_sel_con15: sel-con@0080 {
 870                                         compatible = "rockchip,rk3188-selcon";
 871                                         reg = <0x0080 0x4>;
 872                                         #address-cells = <1>;
 873                                         #size-cells = <1>;
 874
 875                                         clk_uart2_div: clk_uart2_div {
 876                                                 compatible = "rockchip,rk3188-div-con";
 877                                                 rockchip,bits = <0 7>;
 878                                                 clocks = <&clk_uart2_pll>;
 879                                                 clock-output-names = "clk_uart2_div";
 880                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 881                                                 #clock-cells = <0>;
 882                                         };
 883
 884                                         /* reg[7]: reserved */
 885
 886                                         clk_uart2: clk_uart2_mux {
 887                                                 compatible = "rockchip,rk3188-mux-con";
 888                                                 rockchip,bits = <8 2>;
 889                                                 clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>;
 890                                                 clock-output-names = "clk_uart2";
 891                                                 #clock-cells = <0>;
 892                                                 rockchip,clkops-idx =
 893                                                         <CLKOPS_RATE_RK3288_I2S>;
 894                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 895                                         };
 896
 897                                         /* reg[15:10]: reserved */
 898                                 };
 899
 900                                 clk_sel_con17: sel-con@0088 {
 901                                         compatible = "rockchip,rk3188-selcon";
 902                                         reg = <0x0088 0x4>;
 903                                         #address-cells = <1>;
 904                                         #size-cells = <1>;
 905
 906                                         uart0_frac: uart0_frac {
 907                                                 compatible = "rockchip,rk3188-frac-con";
 908                                                 clocks = <&clk_uart0_pll>;
 909                                                 clock-output-names = "uart0_frac";
 910                                                 /* numerator    denominator */
 911                                                 rockchip,bits = <0 32>;
 912                                                 rockchip,clkops-idx =
 913                                                         <CLKOPS_RATE_FRAC>;
 914                                                 #clock-cells = <0>;
 915                                         };
 916                                 };
 917
 918                                 clk_sel_con18: sel-con@008c {
 919                                         compatible = "rockchip,rk3188-selcon";
 920                                         reg = <0x008c 0x4>;
 921                                         #address-cells = <1>;
 922                                         #size-cells = <1>;
 923
 924                                         uart1_frac: uart1_frac {
 925                                                 compatible = "rockchip,rk3188-frac-con";
 926                                                 clocks = <&clk_uart1_div>;
 927                                                 clock-output-names = "uart1_frac";
 928                                                 /* numerator    denominator */
 929                                                 rockchip,bits = <0 32>;
 930                                                 rockchip,clkops-idx =
 931                                                         <CLKOPS_RATE_FRAC>;
 932                                                 #clock-cells = <0>;
 933                                         };
 934                                 };
 935
 936                                 clk_sel_con19: sel-con@0090 {
 937                                         compatible = "rockchip,rk3188-selcon";
 938                                         reg = <0x0090 0x4>;
 939                                         #address-cells = <1>;
 940                                         #size-cells = <1>;
 941
 942                                         uart2_frac: uart2_frac {
 943                                                 compatible = "rockchip,rk3188-frac-con";
 944                                                 clocks = <&clk_uart2_div>;
 945                                                 clock-output-names = "uart2_frac";
 946                                                 /* numerator    denominator */
 947                                                 rockchip,bits = <0 32>;
 948                                                 rockchip,clkops-idx =
 949                                                         <CLKOPS_RATE_FRAC>;
 950                                                 #clock-cells = <0>;
 951                                         };
 952
 953                                 };
 954
 955                                 clk_sel_con20: sel-con@0094 {
 956                                         compatible = "rockchip,rk3188-selcon";
 957                                         reg = <0x0094 0x4>;
 958                                         #address-cells = <1>;
 959                                         #size-cells = <1>;
 960
 961                                         spdif_frac: spdif_frac {
 962                                                 compatible = "rockchip,rk3188-frac-con";
 963                                                 clocks = <&spdif_div>;
 964                                                 clock-output-names = "spdif_frac";
 965                                                 /* numerator    denominator */
 966                                                 rockchip,bits = <0 32>;
 967                                                 rockchip,clkops-idx =
 968                                                         <CLKOPS_RATE_FRAC>;
 969                                                 #clock-cells = <0>;
 970                                         };
 971
 972                                 };
 973
 974                                 clk_sel_con23: sel-con@00a0 {
 975                                         compatible = "rockchip,rk3188-selcon";
 976                                         reg = <0x00a0 0x4>;
 977                                         #address-cells = <1>;
 978                                         #size-cells = <1>;
 979
 980                                         dclk_ebc: dclk_ebc_mux {
 981                                                 compatible = "rockchip,rk3188-mux-con";
 982                                                 rockchip,bits = <0 2>;
 983                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
 984                                                 clock-output-names = "dclk_ebc";
 985                                                 #clock-cells = <0>;
 986                                         };
 987
 988                                         /* reg[7:2]: reserved */
 989
 990                                         dclk_ebc_div: dclk_ebc_div {
 991                                                 compatible = "rockchip,rk3188-div-con";
 992                                                 rockchip,bits = <8 8>;
 993                                                 clocks = <&dclk_ebc>;
 994                                                 clock-output-names = "dclk_ebc";
 995                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 996                                                 #clock-cells = <0>;
 997                                                 rockchip,clkops-idx =
 998                                                         <CLKOPS_RATE_MUX_DIV>;
 999                                         };
1000
1001                                 };
1002
1003                                 clk_sel_con24: sel-con@00a4 {
1004                                         compatible = "rockchip,rk3188-selcon";
1005                                         reg = <0x00a4 0x4>;
1006                                         #address-cells = <1>;
1007                                         #size-cells = <1>;
1008
1009                                         clk_crypto_div: clk_crypto_div {
1010                                                 compatible = "rockchip,rk3188-div-con";
1011                                                 rockchip,bits = <0 2>;
1012                                                 clocks = <&aclk_cpu_pre>;
1013                                                 clock-output-names = "clk_crypto";
1014                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1015                                                 #clock-cells = <0>;
1016                                                 #clock-init-cells = <1>;
1017                                         };
1018
1019                                         /* reg[7:2]: reserved */
1020
1021                                         clk_saradc: clk_saradc_div {
1022                                                 compatible = "rockchip,rk3188-div-con";
1023                                                 rockchip,bits = <8 8>;
1024                                                 clocks = <&xin24m>;
1025                                                 clock-output-names = "clk_saradc";
1026                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1027                                                 #clock-cells = <0>;
1028                                                 #clock-init-cells = <1>;
1029                                         };
1030
1031                                 };
1032
1033                                 clk_sel_con25: sel-con@00a8 {
1034                                         compatible = "rockchip,rk3188-selcon";
1035                                         reg = <0x00a8 0x4>;
1036                                         #address-cells = <1>;
1037                                         #size-cells = <1>;
1038
1039                                         clk_spi0_div: clk_spi0_div {
1040                                                 compatible = "rockchip,rk3188-div-con";
1041                                                 rockchip,bits = <0 7>;
1042                                                 clocks = <&clk_spi0>;
1043                                                 clock-output-names = "clk_spi0";
1044                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1045                                                 #clock-cells = <0>;
1046                                                 rockchip,clkops-idx =
1047                                                         <CLKOPS_RATE_MUX_DIV>;
1048                                         };
1049
1050                                         /* reg[7]: reserved */
1051
1052                                         clk_spi0: clk_spi0_mux {
1053                                                 compatible = "rockchip,rk3188-mux-con";
1054                                                 rockchip,bits = <8 2>;
1055                                                 clocks = <&clk_cpll>, <&clk_gpll>,<&clk_gpll_div2>;
1056                                                 clock-output-names = "clk_spi0";
1057                                                 #clock-cells = <0>;
1058                                         };
1059
1060                                         /* reg[15:10]: reserved */
1061
1062                                 };
1063
1064                                 clk_sel_con26: sel-con@00ac {
1065                                         compatible = "rockchip,rk3188-selcon";
1066                                         reg = <0x00ac 0x4>;
1067                                         #address-cells = <1>;
1068                                         #size-cells = <1>;
1069
1070                                         ddr_div: ddr_div {
1071                                                 compatible = "rockchip,rk3188-div-con";
1072                                                 rockchip,bits = <0 2>;
1073                                                 clocks = <&clk_ddr>;
1074                                                 clock-output-names = "clk_ddr";
1075                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
1076                                                 rockchip,div-relations =
1077                                                                 <0x0 1
1078                                                                  0x1 2
1079                                                                  0x3 4>;
1080                                                 #clock-cells = <0>;
1081                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
1082                                                                         CLK_SET_RATE_NO_REPARENT)>;
1083                                                 rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
1084                                         };
1085
1086                                         /* reg[7:2]: reserved */
1087
1088                                         clk_ddr: ddr_clk_pll_mux {
1089                                                 compatible = "rockchip,rk3188-mux-con";
1090                                                 rockchip,bits = <8 1>;
1091                                                 clocks = <&clk_dpll>, <&clk_gpll_div2>;
1092                                                 clock-output-names = "clk_ddr";
1093                                                 #clock-cells = <0>;
1094                                         };
1095
1096                                         /* reg[15:9]: reserved */
1097                                 };
1098
1099                                 clk_sel_con27: sel-con@00b0 {
1100                                         compatible = "rockchip,rk3188-selcon";
1101                                         reg = <0x00b0 0x4>;
1102                                         #address-cells = <1>;
1103                                         #size-cells = <1>;
1104
1105                                         dclk_lcdc0: dclk_lcdc0_mux {
1106                                                 compatible = "rockchip,rk3188-mux-con";
1107                                                 rockchip,bits = <0 2>;
1108                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>;
1109                                                 clock-output-names = "dclk_lcdc0";
1110                                                 #clock-cells = <0>;
1111                                                 #clock-init-cells = <1>;
1112                                         };
1113
1114                                         /* reg[7:2]: reserved */
1115
1116                                         dclk_lcdc0_div: dclk_lcdc0_div {
1117                                                 compatible = "rockchip,rk3188-div-con";
1118                                                 rockchip,bits = <8 8>;
1119                                                 clocks = <&dclk_lcdc0>;
1120                                                 clock-output-names = "dclk_lcdc0";
1121                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1122                                                 #clock-cells = <0>;
1123                                                 rockchip,clkops-idx =
1124                                                         <CLKOPS_RATE_MUX_DIV>;
1125                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1126                                         };
1127                                 };
1128
1129                                 clk_sel_con28: sel-con@00b4 {
1130                                         compatible = "rockchip,rk3188-selcon";
1131                                         reg = <0x00b4 0x4>;
1132                                         #address-cells = <1>;
1133                                         #size-cells = <1>;
1134
1135                                         sclk_lcdc0: sclk_lcdc0_mux {
1136                                                 compatible = "rockchip,rk3188-mux-con";
1137                                                 rockchip,bits = <0 2>;
1138                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>;
1139                                                 clock-output-names = "sclk_lcdc0";
1140                                                 #clock-cells = <0>;
1141                                                 #clock-init-cells = <1>;
1142                                         };
1143
1144                                         /* reg[7:2]: reserved */
1145
1146                                         sclk_lcdc0_div: sclk_lcdc0_div {
1147                                                 compatible = "rockchip,rk3188-div-con";
1148                                                 rockchip,bits = <8 8>;
1149                                                 clocks = <&sclk_lcdc0>;
1150                                                 clock-output-names = "sclk_lcdc0";
1151                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1152                                                 #clock-cells = <0>;
1153                                                 rockchip,clkops-idx =
1154                                                         <CLKOPS_RATE_MUX_DIV>;
1155                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1156                                         };
1157                                 };
1158
1159                                 clk_sel_con29: sel-con@00b8 {
1160                                         compatible = "rockchip,rk3188-selcon";
1161                                         reg = <0x00b8 0x4>;
1162                                         #address-cells = <1>;
1163                                         #size-cells = <1>;
1164
1165                                         clk_cif_pll: clk_cif_pll_mux {
1166                                                 compatible = "rockchip,rk3188-mux-con";
1167                                                 rockchip,bits = <0 2>;
1168                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
1169                                                 clock-output-names = "clk_cif_pll";
1170                                                 #clock-cells = <0>;
1171                                                 #clock-init-cells = <1>;
1172                                         };
1173
1174                                         clk_cif_out_div: clk_cif_out_div {
1175                                                 compatible = "rockchip,rk3188-div-con";
1176                                                 rockchip,bits = <2 5>;
1177                                                 clocks = <&clk_cif_out>;
1178                                                 clock-output-names = "clk_cif_out";
1179                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1180                                                 #clock-cells = <0>;
1181                                                 rockchip,clkops-idx =
1182                                                         <CLKOPS_RATE_MUX_DIV>;
1183                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1184                                         };
1185
1186                                         clk_cif_out: clk_cif_out_mux {
1187                                                 compatible = "rockchip,rk3188-mux-con";
1188                                                 rockchip,bits = <7 1>;
1189                                                 clocks = <&clk_cif_pll>, <&xin24m>;
1190                                                 clock-output-names = "clk_cif_out";
1191                                                 #clock-cells = <0>;
1192                                                 #clock-init-cells = <1>;
1193                                         };
1194
1195                                         pclk_pmu_pre: pclk_pmu_pre_div {
1196                                                 compatible = "rockchip,rk3188-div-con";
1197                                                 rockchip,bits = <8 6>;
1198                                                 clocks = <&clk_cpll>;
1199                                                 clock-output-names = "pclk_pmu_pre";
1200                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1201                                                 #clock-cells = <0>;
1202                                                 #clock-init-cells = <1>;
1203                                         };
1204
1205                                         /* reg[15:14]: reserved */
1206                                 };
1207
1208                                 clk_sel_con30: sel-con@00bc {
1209                                         compatible = "rockchip,rk3188-selcon";
1210                                         reg = <0x00bc 0x4>;
1211                                         #address-cells = <1>;
1212                                         #size-cells = <1>;
1213
1214                                         clk_testout_div: clk_testout_div {
1215                                                 compatible = "rockchip,rk3188-div-con";
1216                                                 rockchip,bits = <0 5>;
1217                                                 clocks = <&dummy>;
1218                                                 clock-output-names = "clk_testout";
1219                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1220                                                 #clock-cells = <0>;
1221                                                 #clock-init-cells = <1>;
1222                                         };
1223
1224                                         /* reg[6:5]: reserved */
1225
1226                                         clk_cif0_in: clk_cif0_in_mux {
1227                                                 compatible = "rockchip,rk3188-mux-con";
1228                                                 rockchip,bits = <7 1>;
1229                                                 clocks = <&pclkin_cif>, <&dummy>;
1230                                                 clock-output-names = "clk_cif0_in";
1231                                                 #clock-cells = <0>;
1232                                                 #clock-init-cells = <1>;
1233                                         };
1234
1235                                         hclk_vio_pre_div: hclk_vio_pre_div {
1236                                                 compatible = "rockchip,rk3188-div-con";
1237                                                 rockchip,bits = <8 5>;
1238                                                 clocks = <&hclk_vio_pre>;
1239                                                 clock-output-names = "hclk_vio_pre";
1240                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1241                                                 #clock-cells = <0>;
1242                                                 rockchip,clkops-idx =
1243                                                         <CLKOPS_RATE_MUX_DIV>;
1244                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1245                                         };
1246
1247                                         /* reg[13]: reserved */
1248
1249                                         hclk_vio_pre: hclk_vio_pre_mux {
1250                                                 compatible = "rockchip,rk3188-mux-con";
1251                                                 rockchip,bits = <14 2>;
1252                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
1253                                                 clock-output-names = "hclk_vio_pre";
1254                                                 #clock-cells = <0>;
1255                                                 #clock-init-cells = <1>;
1256                                         };
1257
1258                                 };
1259
1260                                 clk_sel_con31: sel-con@00c0 {
1261                                         compatible = "rockchip,rk3188-selcon";
1262                                         reg = <0x00c0 0x4>;
1263                                         #address-cells = <1>;
1264                                         #size-cells = <1>;
1265
1266                                         aclk_vio0_pre_div: aclk_vio0_pre_div {
1267                                                 compatible = "rockchip,rk3188-div-con";
1268                                                 rockchip,bits = <0 5>;
1269                                                 clocks = <&aclk_vio0_pre>;
1270                                                 clock-output-names = "aclk_vio0_pre";
1271                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1272                                                 #clock-cells = <0>;
1273                                                 rockchip,clkops-idx =
1274                                                         <CLKOPS_RATE_MUX_DIV>;
1275                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1276                                         };
1277
1278                                         aclk_vio0_pre: aclk_vio0_pre_mux {
1279                                                 compatible = "rockchip,rk3188-mux-con";
1280                                                 rockchip,bits = <5 3>;
1281                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1282                                                 clock-output-names = "aclk_vio0_pre";
1283                                                 #clock-cells = <0>;
1284                                                 #clock-init-cells = <1>;
1285                                         };
1286
1287                                         aclk_vio1_pre_div: aclk_vio1_pre_div {
1288                                                 compatible = "rockchip,rk3188-div-con";
1289                                                 rockchip,bits = <8 5>;
1290                                                 clocks = <&aclk_vio1_pre>;
1291                                                 clock-output-names = "aclk_vio1_pre";
1292                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1293                                                 #clock-cells = <0>;
1294                                                 rockchip,clkops-idx =
1295                                                         <CLKOPS_RATE_MUX_DIV>;
1296                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1297                                         };
1298
1299                                         aclk_vio1_pre: aclk_vio1_pre_mux {
1300                                                 compatible = "rockchip,rk3188-mux-con";
1301                                                 rockchip,bits = <13 3>;
1302                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1303                                                 clock-output-names = "aclk_vio1_pre";
1304                                                 #clock-cells = <0>;
1305                                                 #clock-init-cells = <1>;
1306                                         };
1307
1308                                 };
1309
1310                                 clk_sel_con32: sel-con@00c4 {
1311                                         compatible = "rockchip,rk3188-selcon";
1312                                         reg = <0x00c4 0x4>;
1313                                         #address-cells = <1>;
1314                                         #size-cells = <1>;
1315
1316                                         clk_vepu_div: clk_vepu_div {
1317                                                 compatible = "rockchip,rk3188-div-con";
1318                                                 rockchip,bits = <0 5>;
1319                                                 clocks = <&clk_vepu>;
1320                                                 clock-output-names = "clk_vepu";
1321                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1322                                                 #clock-cells = <0>;
1323                                                 rockchip,clkops-idx =
1324                                                         <CLKOPS_RATE_MUX_DIV>;
1325                                         };
1326
1327                                         clk_vepu: clk_vepu_mux {
1328                                                 compatible = "rockchip,rk3188-mux-con";
1329                                                 rockchip,bits = <5 3>;
1330                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1331                                                 clock-output-names = "clk_vepu";
1332                                                 #clock-cells = <0>;
1333                                                 #clock-init-cells = <1>;
1334                                         };
1335
1336                                         clk_vdpu_div: clk_vdpu_div {
1337                                                 compatible = "rockchip,rk3188-div-con";
1338                                                 rockchip,bits = <8 5>;
1339                                                 clocks = <&clk_vdpu>;
1340                                                 clock-output-names = "clk_vdpu";
1341                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1342                                                 #clock-cells = <0>;
1343                                                 rockchip,clkops-idx =
1344                                                         <CLKOPS_RATE_MUX_DIV>;
1345                                         };
1346
1347                                         clk_vdpu: clk_vdpu_mux {
1348                                                 compatible = "rockchip,rk3188-mux-con";
1349                                                 rockchip,bits = <13 3>;
1350                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1351                                                 clock-output-names = "clk_vdpu";
1352                                                 #clock-cells = <0>;
1353                                                 #clock-init-cells = <1>;
1354                                         };
1355
1356                                 };
1357
1358                                 clk_sel_con34: sel-con@00cc {
1359                                         compatible = "rockchip,rk3188-selcon";
1360                                         reg = <0x00cc 0x4>;
1361                                         #address-cells = <1>;
1362                                         #size-cells = <1>;
1363
1364                                         clk_gpu_pre_div: clk_gpu_pre_div {
1365                                                 compatible = "rockchip,rk3188-div-con";
1366                                                 rockchip,bits = <0 5>;
1367                                                 clocks = <&clk_gpu_pre>;
1368                                                 clock-output-names = "clk_gpu_pre";
1369                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1370                                                 #clock-cells = <0>;
1371                                                 rockchip,clkops-idx =
1372                                                         <CLKOPS_RATE_MUX_DIV>;
1373                                                 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
1374                                         };
1375
1376                                         clk_gpu_pre: clk_gpu_pre_mux {
1377                                                 compatible = "rockchip,rk3188-mux-con";
1378                                                 rockchip,bits = <5 3>;
1379                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1380                                                 clock-output-names = "clk_gpu_pre";
1381                                                 #clock-cells = <0>;
1382                                                 #clock-init-cells = <1>;
1383                                         };
1384
1385                                         clk_hevc_core_div: clk_hevc_core_div {
1386                                                 compatible = "rockchip,rk3188-div-con";
1387                                                 rockchip,bits = <8 5>;
1388                                                 clocks = <&clk_hevc_core>;
1389                                                 clock-output-names = "clk_hevc_core";
1390                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1391                                                 #clock-cells = <0>;
1392                                                 rockchip,clkops-idx =
1393                                                         <CLKOPS_RATE_MUX_DIV>;
1394                                         };
1395
1396                                         clk_hevc_core: clk_hevc_core_mux {
1397                                                 compatible = "rockchip,rk3188-mux-con";
1398                                                 rockchip,bits = <13 3>;
1399                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1400                                                 clock-output-names = "clk_hevc_core";
1401                                                 #clock-cells = <0>;
1402                                                 #clock-init-cells = <1>;
1403                                         };
1404
1405                                 };
1406
1407                         };
1408
1409
1410                         /* Gate control regs */
1411                         clk_gate_cons {
1412                                 compatible = "rockchip,rk-gate-cons";
1413                                 #address-cells = <1>;
1414                                 #size-cells = <1>;
1415                                 ranges ;
1416
1417                                 clk_gates0: gate-clk@00d0{
1418                                         compatible = "rockchip,rk3188-gate-clk";
1419                                         reg = <0x00d0 0x4>;
1420                                         clocks =
1421                                                 <&clk_core>,            <&dummy>,
1422                                                 <&dummy>,       <&aclk_cpu_pre>,
1423
1424                                                 <&aclk_cpu_pre>,        <&aclk_cpu_pre>,
1425                                                 <&dummy>,               <&clk_core>,
1426
1427                                                 <&dummy>,       <&clk_i2s_2ch_pll>,
1428                                                 <&i2s_2ch_frac>,        <&hclk_vio_pre>,
1429
1430                                                 <&aclk_cpu_pre>,                <&clk_i2s_2ch_out>,
1431                                                 <&clk_i2s_2ch>,         <&dummy>;
1432
1433                                         clock-output-names =
1434                                                 "pclk_dbg",                     "aclk_cpu_pre",  /*clk_cpu_cpll*/
1435                                                 "clk_ddr",              "aclk_cpu_pre",
1436
1437                                                 "hclk_cpu_pre",         "pclk_cpu_pre",
1438                                                 "clk_core",             "aclk_core_pre",
1439
1440                                                 "reserved",             "clk_i2s_2ch_pll",
1441                                                 "i2s_2ch_frac",         "hclk_vio_pre",
1442
1443                                                 "clk_crypto",           "clk_i2s_2ch_out",
1444                                                 "clk_i2s_2ch",          "clk_testout";
1445                                         rockchip,suspend-clkgating-setting=<0x0 0x0>;
1446
1447                                         #clock-cells = <1>;
1448                                 };
1449
1450                                 clk_gates1: gate-clk@00d4{
1451                                         compatible = "rockchip,rk3188-gate-clk";
1452                                         reg = <0x00d4 0x4>;
1453                                         clocks =
1454                                                 <&clk_cpll>,            <&dummy>,
1455                                                 <&dummy>,               <&jtag_tck>,
1456
1457                                                 <&aclk_vio1_pre>,               <&xin12m>,
1458                                                 <&xin12m>,              <&clk_mac_pll>,
1459
1460                                                 <&clk_uart0_pll>,               <&uart0_frac>,
1461                                                 <&clk_uart1_div>,               <&uart1_frac>,
1462
1463                                                 <&clk_uart2_div>,               <&uart2_frac>,
1464                                                 <&clk_tsp>,             <&dummy>;
1465
1466                                         clock-output-names =
1467                                                 "pclk_pmu_pre",         "reserved",
1468                                                 "reserved",             "clk_jtag",
1469
1470                                                 "aclk_vio1_pre",                "clk_otgphy0",
1471                                                 "clk_otgphy1",                  "clk_mac_pll",
1472
1473                                                 "clk_uart0_pll",        "uart0_frac",
1474                                                 "clk_uart1_div",        "uart1_frac",
1475
1476                                                 "clk_uart2_div",        "uart2_frac",
1477                                                 "clk_tsp",      "reserved";
1478
1479                                          rockchip,suspend-clkgating-setting=<0x0 0x0>;
1480                                         #clock-cells = <1>;
1481                                 };
1482
1483                                 clk_gates2: gate-clk@00d8 {
1484                                         compatible = "rockchip,rk3188-gate-clk";
1485                                         reg = <0x00d8 0x4>;
1486                                         clocks =
1487                                                 <&dummy>,               <&aclk_peri_pre>,
1488                                                 <&aclk_peri_pre>,               <&aclk_peri_pre>,
1489
1490                                                 <&clk_mac_ref>,         <&clk_mac_ref>,
1491                                                 <&clk_mac_ref>,         <&clk_mac_ref>,
1492
1493                                                 <&clk_saradc>,          <&clk_spi0>,
1494                                                 <&clk_spdif_pll>,               <&clk_sdmmc0>,
1495
1496                                                 <&spdif_frac>,          <&clk_sdio>,
1497                                                 <&clk_emmc>,            <&xin24m>;
1498                                         clock-output-names =
1499                                                 "aclk_peri_pre",                "aclk_peri_pre",
1500                                                 "hclk_peri_pre",                "pclk_peri_pre",
1501
1502                                                 "clk_mac_ref",          "clk_mac_refout",
1503                                                 "clk_mac_rx",           "clk_mac_tx",
1504
1505                                                 "clk_saradc",           "clk_spi0",
1506                                                 "clk_spdif_pll",                "clk_sdmmc0",
1507
1508                                                 "spdif_frac",           "clk_sdio",
1509                                                 "clk_emmc",             "clk_mipi_24m";
1510                                             rockchip,suspend-clkgating-setting=<0x0 0x0>;
1511
1512                                         #clock-cells = <1>;
1513                                 };
1514
1515                                 clk_gates3: gate-clk@00dc {
1516                                         compatible = "rockchip,rk3188-gate-clk";
1517                                         reg = <0x00dc 0x4>;
1518                                         clocks =
1519                                                 <&aclk_vio0_pre>,               <&dclk_lcdc0>,
1520                                                 <&sclk_lcdc0>,          <&pclkin_cif>,
1521
1522                                                 <&dclk_ebc>,                    <&hclk_cpu_pre>,
1523                                                 <&hclk_peri_pre>,               <&clk_cif_pll>,
1524
1525                                                 <&pclk_cpu_pre>,                <&clk_vepu>,
1526                                                 <&clk_hevc_core>,               <&clk_vdpu>,
1527
1528                                                 <&hclk_vdpu>,           <&clk_gpu_pre>,
1529                                                 <&aclk_peri_pre>,               <&clk_sfc>;
1530
1531                                         clock-output-names =
1532                                                 "aclk_vio0_pre",                "dclk_lcdc0",
1533                                                 "sclk_lcdc0",           "pclkin_cif",
1534
1535                                                 "dclk_ebc",             "g_hclk_crypto",
1536                                                 "g_hclk_em_peri",               "clk_cif_pll",
1537
1538                                                 "g_pclk_hdmi",          "clk_vepu",
1539                                                 "clk_hevc_core",                "clk_vdpu",
1540
1541                                                 "hclk_vdpu",            "clk_gpu_pre",
1542                                                 "g_hclk_gps",           "clk_sfc";
1543                                        rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
1544
1545                                         #clock-cells = <1>;
1546                                 };
1547
1548                                 clk_gates4: gate-clk@00e0{
1549                                         compatible = "rockchip,rk3188-gate-clk";
1550                                         reg = <0x00e0 0x4>;
1551                                         clocks =
1552                                                 <&hclk_peri_pre>,               <&pclk_peri_pre>,
1553                                                 <&aclk_peri_pre>,               <&aclk_peri_pre>,
1554
1555                                                 <&clk_i2s_8ch_pll>,             <&i2s_8ch_frac>,
1556                                                 <&clk_i2s_8ch>,         <&dummy>,
1557
1558                                                 <&dummy>,               <&dummy>,
1559                                                 <&aclk_cpu_pre>,                <&dummy>,
1560
1561                                                 <&aclk_cpu_pre>,                <&dummy>,
1562                                                 <&dummy>,               <&dummy>;
1563
1564                                         clock-output-names =
1565                                                 "g_hp_axi_matrix",              "g_pp_axi_matrix",
1566                                                 "g_aclk_cpu_peri",              "g_ap_axi_matrix",
1567
1568                                                 "clk_i2s_8ch_pll",              "i2s_8ch_frac",
1569                                                 "clk_i2s_8ch",          "reserved",
1570
1571                                                 "reserved",             "reserved",
1572                                                 "g_aclk_strc_sys",              "reserved",
1573
1574                                                 /* Not use these ddr gates */
1575                                                 "g_aclk_intmem",                "reserved",
1576                                                 "reserved",             "reserved";
1577
1578                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1579                                         #clock-cells = <1>;
1580                                 };
1581
1582                                 clk_gates5: gate-clk@00e4 {
1583                                         compatible = "rockchip,rk3188-gate-clk";
1584                                         reg = <0x00e4 0x4>;
1585                                         clocks =
1586                                                 <&pclk_cpu_pre>,                <&aclk_peri_pre>,
1587                                                 <&pclk_peri_pre>,               <&dummy>,
1588
1589                                                 <&pclk_cpu_pre>,                <&dummy>,
1590                                                 <&hclk_cpu_pre>,                <&pclk_cpu_pre>,
1591
1592                                                 <&dummy>,               <&hclk_peri_pre>,
1593                                                 <&hclk_peri_pre>,               <&hclk_peri_pre>,
1594
1595                                                 <&dummy>,               <&hclk_peri_pre>,
1596                                                 <&pclk_cpu_pre>,                <&dummy>;
1597
1598                                         clock-output-names =
1599                                                 "g_pclk_mipiphy",               "g_aclk_dmac",
1600                                                 "g_pclk_efuse", "reserved",
1601
1602                                                 "g_pclk_grf",           "reserved",
1603                                                 "g_hclk_rom",           "g_pclk_ddrupctl",
1604
1605                                                 "reserved",             "g_hclk_nandc",
1606                                                 "g_hclk_sdmmc0",                "g_hclk_sdio",
1607
1608                                                 "reserved",             "g_hclk_otg0",
1609                                                 "g_pclk_acodec",                "reserved";
1610
1611                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1612
1613                                         #clock-cells = <1>;
1614                                 };
1615
1616                                 clk_gates6: gate-clk@00e8 {
1617                                         compatible = "rockchip,rk3188-gate-clk";
1618                                         reg = <0x00e8 0x4>;
1619                                         clocks =
1620                                                 <&aclk_vio0_pre>,               <&hclk_vio_pre>,
1621                                                 <&dummy>,               <&dummy>,
1622
1623                                                 <&hclk_vio_pre>,                <&aclk_vio0_pre>,
1624                                                 <&dummy>,               <&dummy>,
1625
1626                                                 <&dummy>,               <&dummy>,
1627                                                 <&hclk_vio_pre>,                        <&aclk_vio0_pre>,
1628
1629                                                 <&hclk_vio_pre>,                <&aclk_vio0_pre>,
1630                                                 <&dummy>,               <&dummy>;
1631
1632                                         clock-output-names =
1633                                                 "g_aclk_lcdc0",         "g_hclk_lcdc0",
1634                                                 "reserved",             "reserved",
1635
1636                                                 "g_hclk_cif",           "g_aclk_cif",
1637                                                 "reserved",             "reserved",
1638
1639                                                 "reserved",             "reserved",
1640                                                 "g_hclk_rga",           "g_aclk_rga",
1641
1642                                                 "g_hclk_vio_bus",               "g_aclk_vio",
1643                                                 "reserved",             "reserved";
1644
1645                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1646
1647                                         #clock-cells = <1>;
1648                                 };
1649
1650                                 clk_gates7: gate-clk@00ec {
1651                                         compatible = "rockchip,rk3188-gate-clk";
1652                                         reg = <0x00ec 0x4>;
1653                                         clocks =
1654                                                 <&hclk_peri_pre>,               <&hclk_peri_pre>,
1655                                                 <&hclk_peri_pre>,               <&hclk_peri_pre>,
1656
1657                                                 <&hclk_peri_pre>,               <&dummy>,
1658                                                 <&dummy>,               <&pclk_peri_pre>,
1659
1660                                                 <&dummy>,               <&dummy>,
1661                                                 <&pclk_peri_pre>,               <&dummy>,
1662
1663                                                 <&pclk_peri_pre>,               <&dummy>,
1664                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>;
1665
1666                                         clock-output-names =
1667                                                 "g_hclk_emmc",          "g_hclk_sfc",
1668                                                 "g_hclk_i2s_2ch",               "g_hclk_host",
1669
1670                                                 "g_hclk_i2s_8ch",               "reserved",
1671                                                 "reserved",             "g_pclk_timer",
1672
1673                                                 "reserved",             "reserved",
1674                                                 "g_pclk_pwm",           "reserved",
1675
1676                                                 "g_pclk_spi0",          "reserved",
1677                                                 "g_pclk_saradc",                "g_pclk_wdt";
1678
1679                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1680
1681                                         #clock-cells = <1>;
1682                                 };
1683
1684                                 clk_gates8: gate-clk@00f0 {
1685                                         compatible = "rockchip,rk3188-gate-clk";
1686                                         reg = <0x00f0 0x4>;
1687                                         clocks =
1688                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1689                                                 <&pclk_peri_pre>,               <&dummy>,
1690
1691                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1692                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1693
1694                                                 <&dummy>,               <&pclk_peri_pre>,
1695                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1696
1697                                                 <&pclk_peri_pre>,               <&dummy>,
1698                                                 <&dummy>,               <&dummy>;
1699
1700                                         clock-output-names =
1701                                                 "g_pclk_uart0",         "g_pclk_uart1",
1702                                                 "g_pclk_uart2",         "reserved",
1703
1704                                                 "g_pclk_i2c0",          "g_pclk_i2c1",
1705                                                 "g_pclk_i2c2",          "g_pclk_i2c3",
1706
1707                                                 "reserved",             "g_pclk_gpio0",
1708                                                 "g_pclk_gpio1",         "g_pclk_gpio2",
1709
1710                                                 "g_pclk_gpio3",         "reserved",
1711                                                 "reserved",             "reserved";
1712
1713                                         rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
1714                                         #clock-cells = <1>;
1715                                 };
1716
1717                                 clk_gates9: gate-clk@00f4 {
1718                                         compatible = "rockchip,rk3188-gate-clk";
1719                                         reg = <0x00f4 0x4>;
1720                                         clocks =
1721                                                 <&dummy>,               <&dummy>,
1722                                                 <&pclk_pmu_pre>,                <&pclk_pmu_pre>,
1723
1724                                                 <&dummy>,               <&hclk_vio_pre>,
1725                                                 <&hclk_vio_pre>,                <&hclk_vio_pre>,
1726
1727                                                 <&aclk_vio1_pre>,               <&hclk_vio_pre>,
1728                                                 <&aclk_vio1_pre>,               <&dummy>,
1729
1730                                                 <&pclk_peri_pre>,               <&hclk_peri_pre>,
1731                                                 <&hclk_peri_pre>,               <&aclk_peri_pre>;
1732
1733                                         clock-output-names =
1734                                                 "reserved",             "reserved",
1735                                                 "g_pclk_pmu",           "g_pclk_pmu_noc",
1736
1737                                                 "reserved",             "g_hclk_vio_h2p",
1738                                                 "g_pclk_mipi",          "g_hclk_iep",
1739
1740                                                 "g_aclk_iep",           "g_hclk_ebc",
1741                                                 "g_aclk_vio1_niu",              "reserved",
1742
1743                                                 "g_pclk_sim_card",              "g_hclk_usb_peri",
1744                                                 "g_hclk_pe_arbi",               "g_aclk_peri_niu";
1745
1746                                         rockchip,suspend-clkgating-setting=<0x0 0x0>;
1747
1748                                         #clock-cells = <1>;
1749                                 };
1750
1751                                 clk_gates10: gate-clk@00f8 {
1752                                         compatible = "rockchip,rk3188-gate-clk";
1753                                         reg = <0x00f8 0x4>;
1754                                         clocks =
1755                                                 <&xin24m>,              <&xin24m>,
1756                                                 <&xin24m>,              <&xin24m>,
1757
1758                                                 <&xin24m>,              <&xin24m>,
1759                                                 <&xin24m>,              <&xin24m>,
1760
1761                                                 <&xin24m>,              <&hclk_peri_pre>,
1762                                                 <&aclk_peri_pre>,               <&pclk_peri_pre>,
1763
1764                                                 <&hclk_peri_pre>,               <&clk_tsp_in>,
1765                                                 <&hclk_peri_pre>,               <&clk_nandc>;
1766
1767                                         clock-output-names =
1768                                                 "clk_pvtm_core",                "clk_pvtm_gpu",
1769                                                 "clk_pvtm_func",                "clk_timer0",
1770
1771                                                 "clk_timer1",           "clk_timer2",
1772                                                 "clk_timer3",           "clk_timer4",
1773
1774                                                 "clk_timer5",           "g_hclk_spdif",
1775                                                 "g_aclk_gmac",          "g_pclk_gmac",
1776
1777                                                 "g_hclk_tsp",           "g_clkin0_tsp",
1778                                                 "g_hclk_usbhost",               "clk_nandc";
1779
1780                                         rockchip,suspend-clkgating-setting = <0x0 0x0>; /* pwm logic vol */
1781
1782                                         #clock-cells = <1>;
1783                                 };
1784
1785                         };
1786                 };
1787         };
1788 };