arch/arm/boot/dts/rk312x-clocks.dtsi

   1 /*
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <dt-bindings/clock/rockchip,rk312x.h>
  15
  16 /{
  17
  18         clocks {
  19                 compatible = "rockchip,rk-clocks";
  20                 #address-cells = <1>;
  21                 #size-cells = <1>;
  22                 ranges = <0x0  0x20000000  0x1f0>;
  23
  24                 fixed_rate_cons {
  25                         compatible = "rockchip,rk-fixed-rate-cons";
  26
  27                         xin24m: xin24m {
  28                                 compatible = "rockchip,rk-fixed-clock";
  29                                 clock-output-names = "xin24m";
  30                                 clock-frequency = <24000000>;
  31                                 #clock-cells = <0>;
  32                         };
  33
  34                         xin12m: xin12m {
  35                                 compatible = "rockchip,rk-fixed-clock";
  36                                 clocks = <&xin24m>;
  37                                 clock-output-names = "xin12m";
  38                                 clock-frequency = <12000000>;
  39                                 #clock-cells = <0>;
  40                         };
  41
  42                         gmac_clkin: gmac_clkin {
  43                                 compatible = "rockchip,rk-fixed-clock";
  44                                 clock-output-names = "gmac_clkin";
  45                                 clock-frequency = <125000000>;
  46                                 #clock-cells = <0>;
  47                         };
  48
  49                         usb480m: usb480m {
  50                                 compatible = "rockchip,rk-fixed-clock";
  51                                 clock-output-names = "usb480m";
  52                                 clock-frequency = <480000000>;
  53                                 #clock-cells = <0>;
  54                         };
  55
  56                         i2s_clkin: i2s_clkin {
  57                                 compatible = "rockchip,rk-fixed-clock";
  58                                 clock-output-names = "i2s_clkin";
  59                                 clock-frequency = <0>;
  60                                 #clock-cells = <0>;
  61                         };
  62
  63                         jtag_tck: jtag_tck {
  64                                 compatible = "rockchip,rk-fixed-clock";
  65                                 clock-output-names = "jtag_tck";
  66                                 clock-frequency = <0>;
  67                                 #clock-cells = <0>;
  68                         };
  69
  70                         pclkin_cif: pclkin_cif {
  71                                 compatible = "rockchip,rk-fixed-clock";
  72                                 clock-output-names = "pclkin_cif";
  73                                 clock-frequency = <0>;
  74                                 #clock-cells = <0>;
  75                         };
  76
  77                         clk_tsp_in: clk_tsp_in {
  78                                 compatible = "rockchip,rk-fixed-clock";
  79                                 clock-output-names = "clk_tsp_in";
  80                                 clock-frequency = <0>;
  81                                 #clock-cells = <0>;
  82                         };
  83
  84
  85                         dummy: dummy {
  86                                 compatible = "rockchip,rk-fixed-clock";
  87                                 clock-output-names = "dummy";
  88                                 clock-frequency = <0>;
  89                                 #clock-cells = <0>;
  90                         };
  91
  92                         dummy_cpll: dummy_cpll {
  93                                 compatible = "rockchip,rk-fixed-clock";
  94                                 clock-output-names = "dummy_cpll";
  95                                 clock-frequency = <0>;
  96                                 #clock-cells = <0>;
  97                         };
  98
  99                 };
 100
 101                 fixed_factor_cons {
 102                         compatible = "rockchip,rk-fixed-factor-cons";
 103
 104                         clk_gpll_div2: clk_gpll_div2 {
 105                                 compatible = "rockchip,rk-fixed-factor-clock";
 106                                 clocks = <&clk_gpll>;
 107                                 clock-output-names = "clk_gpll_div2";
 108                                 clock-div = <2>;
 109                                 clock-mult = <1>;
 110                                 #clock-cells = <0>;
 111                         };
 112
 113                         clk_gpll_div3: clk_gpll_div3 {
 114                                 compatible = "rockchip,rk-fixed-factor-clock";
 115                                 clocks = <&clk_gpll>;
 116                                 clock-output-names = "clk_gpll_div3";
 117                                 clock-div = <3>;
 118                                 clock-mult = <1>;
 119                                 #clock-cells = <0>;
 120                         };
 121
 122                         g_clk_pvtm_func: g_clk_pvtm_func {
 123                                 compatible = "rockchip,rk-fixed-factor-clock";
 124                                 clocks = <&xin24m>;
 125                                 clock-output-names = "g_clk_pvtm_func";
 126                                 clock-div = <1>;
 127                                 clock-mult = <1>;
 128                                 #clock-cells = <0>;
 129                         };
 130
 131                         hclk_vepu: hclk_vepu {
 132                                 compatible = "rockchip,rk-fixed-factor-clock";
 133                                 clocks = <&clk_vepu>;
 134                                 clock-output-names = "hclk_vepu";
 135                                 clock-div = <4>;
 136                                 clock-mult = <1>;
 137                                 #clock-cells = <0>;
 138                         };
 139
 140                         hclk_vdpu: hclk_vdpu {
 141                                 compatible = "rockchip,rk-fixed-factor-clock";
 142                                 clocks = <&clk_vdpu>;
 143                                 clock-output-names = "hclk_vdpu";
 144                                 clock-div = <4>;
 145                                 clock-mult = <1>;
 146                                 #clock-cells = <0>;
 147                         };
 148
 149                         pclkin_cif_inv: pclkin_cif_inv {
 150                                 compatible = "rockchip,rk-fixed-factor-clock";
 151                                 clocks = <&clk_gates3 3>;
 152                                 clock-output-names = "pclkin_cif_inv";
 153                                 clock-div = <1>;
 154                                 clock-mult = <1>;
 155                                 #clock-cells = <0>;
 156                         };
 157
 158                 };
 159
 160                 pd_cons {
 161                         compatible = "rockchip,rk-pd-cons";
 162
 163                         pd_gpu: pd_gpu {
 164                                 compatible = "rockchip,rk-pd-clock";
 165                                 clock-output-names = "pd_gpu";
 166                                 rockchip,pd-id = <CLK_PD_GPU>;
 167                                 #clock-cells = <0>;
 168                         };
 169
 170                         pd_video: pd_video {
 171                                 compatible = "rockchip,rk-pd-clock";
 172                                 clock-output-names = "pd_video";
 173                                 rockchip,pd-id = <CLK_PD_VIDEO>;
 174                                 #clock-cells = <0>;
 175                         };
 176
 177                         pd_vio: pd_vio {
 178                                 compatible = "rockchip,rk-pd-clock";
 179                                 clock-output-names = "pd_vio";
 180                                 rockchip,pd-id = <CLK_PD_VIO>;
 181                                 #clock-cells = <0>;
 182                         };
 183
 184                         pd_vop: pd_vop {
 185                                 compatible = "rockchip,rk-pd-clock";
 186                                 clocks = <&pd_vio>;
 187                                 clock-output-names = "pd_vop";
 188                                 rockchip,pd-id = <CLK_PD_VIRT>;
 189                                 #clock-cells = <0>;
 190                         };
 191
 192                         pd_vip: pd_vip {
 193                                 compatible = "rockchip,rk-pd-clock";
 194                                 clocks = <&pd_vio>;
 195                                 clock-output-names = "pd_vip";
 196                                 rockchip,pd-id = <CLK_PD_VIRT>;
 197                                 #clock-cells = <0>;
 198                         };
 199
 200                         pd_iep: pd_iep {
 201                                 compatible = "rockchip,rk-pd-clock";
 202                                 clocks = <&pd_vio>;
 203                                 clock-output-names = "pd_iep";
 204                                 rockchip,pd-id = <CLK_PD_VIRT>;
 205                                 #clock-cells = <0>;
 206                         };
 207
 208                         pd_rga: pd_rga {
 209                                 compatible = "rockchip,rk-pd-clock";
 210                                 clocks = <&pd_vio>;
 211                                 clock-output-names = "pd_rga";
 212                                 rockchip,pd-id = <CLK_PD_VIRT>;
 213                                 #clock-cells = <0>;
 214                         };
 215
 216                         pd_ebc: pd_ebc {
 217                                 compatible = "rockchip,rk-pd-clock";
 218                                 clocks = <&pd_vio>;
 219                                 clock-output-names = "pd_ebc";
 220                                 rockchip,pd-id = <CLK_PD_VIRT>;
 221                                 #clock-cells = <0>;
 222                         };
 223
 224                         pd_mipidsi: pd_mipidsi {
 225                                 compatible = "rockchip,rk-pd-clock";
 226                                 clocks = <&pd_vio>;
 227                                 clock-output-names = "pd_mipidsi";
 228                                 rockchip,pd-id = <CLK_PD_VIRT>;
 229                                 #clock-cells = <0>;
 230                         };
 231
 232                         pd_hdmi: pd_hdmi {
 233                                 compatible = "rockchip,rk-pd-clock";
 234                                 clocks = <&pd_vio>;
 235                                 clock-output-names = "pd_hdmi";
 236                                 rockchip,pd-id = <CLK_PD_VIRT>;
 237                                 #clock-cells = <0>;
 238                         };
 239
 240                 };
 241
 242
 243                 clock_regs {
 244                         compatible = "rockchip,rk-clock-regs";
 245                         #address-cells = <1>;
 246                         #size-cells = <1>;
 247                         reg = <0x0000 0x01f0>;
 248                         ranges;
 249
 250                         /* PLL control regs */
 251                         pll_cons {
 252                                 compatible = "rockchip,rk-pll-cons";
 253                                 #address-cells = <1>;
 254                                 #size-cells = <1>;
 255                                 ranges ;
 256
 257                                 clk_apll: pll-clk@0000 {
 258                                         compatible = "rockchip,rk3188-pll-clk";
 259                                         reg = <0x0000 0x10>;
 260                                         mode-reg = <0x0040 0>;
 261                                         status-reg = <0x0004 10>;
 262                                         clocks = <&xin24m>;
 263                                         clock-output-names = "clk_apll";
 264                                         rockchip,pll-type = <CLK_PLL_3036_APLL>;
 265                                         #clock-cells = <0>;
 266                                 };
 267
 268                                 clk_dpll: pll-clk@0010 {
 269                                         compatible = "rockchip,rk3188-pll-clk";
 270                                         reg = <0x0010 0x10>;
 271                                         mode-reg = <0x0040 4>;
 272                                         status-reg = <0x0014 10>;
 273                                         clocks = <&xin24m>;
 274                                         clock-output-names = "clk_dpll";
 275                                         rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
 276                                         #clock-cells = <0>;
 277                                 };
 278
 279                                 clk_cpll: pll-clk@0020 {
 280                                         compatible = "rockchip,rk3188-pll-clk";
 281                                         reg = <0x0020 0x10>;
 282                                         mode-reg = <0x0040 8>;
 283                                         status-reg = <0x0024 10>;
 284                                         clocks = <&xin24m>;
 285                                         clock-output-names = "clk_cpll";
 286                                         rockchip,pll-type = <CLK_PLL_312XPLUS>;
 287                                         #clock-cells = <0>;
 288                                         #clock-init-cells = <1>;
 289                                 };
 290
 291                                 clk_gpll: pll-clk@0030 {
 292                                         compatible = "rockchip,rk3188-pll-clk";
 293                                         reg = <0x0030 0x10>;
 294                                         mode-reg = <0x0040 12>;
 295                                         status-reg = <0x0034 10>;
 296                                         clocks = <&xin24m>;
 297                                         clock-output-names = "clk_gpll";
 298                                         rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
 299                                         #clock-cells = <0>;
 300                                         #clock-init-cells = <1>;
 301                                 };
 302
 303                         };
 304
 305                         /* Select control regs */
 306                         clk_sel_cons {
 307                                 compatible = "rockchip,rk-sel-cons";
 308                                 #address-cells = <1>;
 309                                 #size-cells = <1>;
 310                                 ranges;
 311
 312                                 clk_sel_con0: sel-con@0044 {
 313                                         compatible = "rockchip,rk3188-selcon";
 314                                         reg = <0x0044 0x4>;
 315                                         #address-cells = <1>;
 316                                         #size-cells = <1>;
 317
 318                                         clk_core_div: clk_core_div {
 319                                                 compatible = "rockchip,rk3188-div-con";
 320                                                 rockchip,bits = <0 5>;
 321                                                 clocks = <&clk_core>;
 322                                                 clock-output-names = "clk_core";
 323                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 324                                                 #clock-cells = <0>;
 325                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 326                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 327                                                                         CLK_SET_RATE_NO_REPARENT)>;
 328                                         };
 329
 330                                         /* reg[6:5]: reserved */
 331
 332                                         clk_core: clk_core_mux {
 333                                                 compatible = "rockchip,rk3188-mux-con";
 334                                                 rockchip,bits = <7 1>;
 335                                                 clocks = <&clk_apll>, <&clk_gpll_div2>;
 336                                                 clock-output-names = "clk_core";
 337                                                 #clock-cells = <0>;
 338                                                 #clock-init-cells = <1>;
 339                                         };
 340
 341                                         aclk_cpu_div: aclk_cpu_div {
 342                                                 compatible = "rockchip,rk3188-div-con";
 343                                                 rockchip,bits = <8 5>;
 344                                                 clocks = <&aclk_cpu>;
 345                                                 clock-output-names = "aclk_cpu";
 346                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 347                                                 #clock-cells = <0>;
 348                                                 rockchip,clkops-idx =
 349                                                         <CLKOPS_RATE_MUX_DIV>;
 350                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 351                                         };
 352
 353                                         aclk_cpu: aclk_cpu_mux {
 354                                                 compatible = "rockchip,rk3188-mux-con";
 355                                                 rockchip,bits = <13 2>;
 356                                                 clocks = <&clk_apll>, <&clk_gpll>,<&clk_gpll_div2>,<&clk_gpll_div3>;
 357                                                 clock-output-names = "aclk_cpu";
 358                                                 #clock-cells = <0>;
 359                                                 #clock-init-cells = <1>;
 360                                         };
 361
 362                                         /* reg[15]: reserved */
 363
 364                                 };
 365
 366                                 clk_sel_con1: sel-con@0048 {
 367                                         compatible = "rockchip,rk3188-selcon";
 368                                         reg = <0x0048 0x4>;
 369                                         #address-cells = <1>;
 370                                         #size-cells = <1>;
 371
 372                                         pclk_dbg_div:  pclk_dbg_div {
 373                                                 compatible = "rockchip,rk3188-div-con";
 374                                                 rockchip,bits = <0 4>;
 375                                                 clocks = <&clk_core>;
 376                                                 clock-output-names = "pclk_dbg";
 377                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 378                                                 #clock-cells = <0>;
 379                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 380                                         };
 381
 382                                         aclk_core_pre: aclk_core_pre_div {
 383                                                 compatible = "rockchip,rk3188-div-con";
 384                                                 rockchip,bits = <4 3>;
 385                                                 clocks = <&clk_core>;
 386                                                 clock-output-names = "aclk_core_pre";
 387                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 388                                                 #clock-cells = <0>;
 389                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 390                                         };
 391
 392                                         /* reg[7]: reserved */
 393
 394                                         hclk_cpu_pre: hclk_cpu_pre_div {
 395                                                 compatible = "rockchip,rk3188-div-con";
 396                                                 rockchip,bits = <8 2>;
 397                                                 clocks = <&aclk_cpu>;
 398                                                 clock-output-names = "hclk_cpu_pre";
 399                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 400                                                 #clock-cells = <0>;
 401                                                 #clock-init-cells = <1>;
 402                                         };
 403
 404                                         /* reg[11:10]: reserved */
 405
 406                                         pclk_cpu_pre: pclk_cpu_pre_div {
 407                                                 compatible = "rockchip,rk3188-div-con";
 408                                                 rockchip,bits = <12 3>;
 409                                                 clocks = <&aclk_cpu>;
 410                                                 clock-output-names = "pclk_cpu_pre";
 411                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 412                                                 #clock-cells = <0>;
 413                                                 #clock-init-cells = <1>;
 414                                         };
 415
 416                                         /* reg[15]: reserved */
 417                                 };
 418
 419                                 clk_sel_con2: sel-con@004c {
 420                                         compatible = "rockchip,rk3188-selcon";
 421                                         reg = <0x004c 0x4>;
 422                                         #address-cells = <1>;
 423                                         #size-cells = <1>;
 424
 425                                         clk_pvtm_div: clk_pvtm_div {
 426                                                 compatible = "rockchip,rk3188-mux-con";
 427                                                 rockchip,bits = <0 7>;
 428                                                 clocks = <&g_clk_pvtm_func>;
 429                                                 clock-output-names = "clk_pvtm";
 430                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 431                                                 #clock-cells = <0>;
 432                                                 #clock-init-cells = <1>;
 433                                         };
 434
 435                                         /* reg[7]: reserved */
 436
 437                                         clk_nandc_div: clk_nandc_div {
 438                                                 compatible = "rockchip,rk3188-div-con";
 439                                                 rockchip,bits = <8 5>;
 440                                                 clocks = <&clk_nandc>;
 441                                                 clock-output-names = "clk_nandc";
 442                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 443                                                 #clock-cells = <0>;
 444                                                 rockchip,clkops-idx =
 445                                                         <CLKOPS_RATE_MUX_DIV>;
 446                                         };
 447
 448                                         /* reg[13]: reserved */
 449
 450                                         clk_nandc: clk_nandc_mux {
 451                                                 compatible = "rockchip,rk3188-mux-con";
 452                                                 rockchip,bits = <14 2>;
 453                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
 454                                                 clock-output-names = "clk_nandc";
 455                                                 #clock-cells = <0>;
 456                                                 #clock-init-cells = <1>;
 457                                         };
 458
 459                                 };
 460
 461                                 clk_sel_con3: sel-con@0050 {
 462                                         compatible = "rockchip,rk3188-selcon";
 463                                         reg = <0x0050 0x4>;
 464                                         #address-cells = <1>;
 465                                         #size-cells = <1>;
 466
 467                                         clk_i2s_2ch_pll_div: clk_i2s_2ch_pll_div {
 468                                                 compatible = "rockchip,rk3188-div-con";
 469                                                 rockchip,bits = <0 7>;
 470                                                 clocks = <&clk_i2s_2ch_pll>;
 471                                                 clock-output-names = "clk_i2s_2ch_pll";
 472                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 473                                                 #clock-cells = <0>;
 474                                                 rockchip,clkops-idx =
 475                                                         <CLKOPS_RATE_MUX_DIV>;
 476                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 477                                         };
 478
 479                                         /* reg[7]: reserved */
 480
 481                                         clk_i2s_2ch: clk_i2s_2ch_mux {
 482                                                 compatible = "rockchip,rk3188-mux-con";
 483                                                 rockchip,bits = <8 2>;
 484                                                 clocks = <&clk_i2s_2ch_pll_div>, <&i2s_2ch_frac>, <&i2s_clkin>, <&xin12m>;
 485                                                 clock-output-names = "clk_i2s_2ch";
 486                                                 #clock-cells = <0>;
 487                                                 rockchip,clkops-idx =
 488                                                         <CLKOPS_RATE_RK3288_I2S>;
 489                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 490                                         };
 491
 492                                         /* reg[11:10]: reserved */
 493
 494                                         clk_i2s_2ch_out: clk_i2s_2ch_out_mux {
 495                                                 compatible = "rockchip,rk3188-mux-con";
 496                                                 rockchip,bits = <12 1>;
 497                                                 clocks = <&clk_i2s_2ch>, <&xin12m>;
 498                                                 clock-output-names = "i2s_clkout";
 499                                                 #clock-cells = <0>;
 500                                         };
 501
 502                                         /* reg[13]: reserved */
 503
 504                                         clk_i2s_2ch_pll: i2s_2ch_pll_mux {
 505                                                 compatible = "rockchip,rk3188-mux-con";
 506                                                 rockchip,bits = <14 2>;
 507                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
 508                                                 clock-output-names = "clk_i2s_2ch_pll";
 509                                                 #clock-cells = <0>;
 510                                                 #clock-init-cells = <1>;
 511                                         };
 512
 513                                 };
 514
 515                                 clk_sel_con4: sel-con@0054 {
 516                                         compatible = "rockchip,rk3188-selcon";
 517                                         reg = <0x0054 0x4>;
 518                                         #address-cells = <1>;
 519                                         #size-cells = <1>;
 520
 521                                         clk_tsp_div: clk_tsp_div {
 522                                                 compatible = "rockchip,rk3188-div-con";
 523                                                 rockchip,bits = <0 5>;
 524                                                 clocks = <&clk_tsp>;
 525                                                 clock-output-names = "clk_tsp";
 526                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 527                                                 #clock-cells = <0>;
 528                                                 rockchip,clkops-idx =
 529                                                         <CLKOPS_RATE_MUX_DIV>;
 530                                         };
 531
 532                                         /* reg[5]: reserved */
 533
 534                                         clk_tsp: clk_tsp_mux {
 535                                                 compatible = "rockchip,rk3188-mux-con";
 536                                                 rockchip,bits = <6 2>;
 537                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
 538                                                 clock-output-names = "clk_tsp";
 539                                                 #clock-cells = <0>;
 540                                                 #clock-init-cells = <1>;
 541                                         };
 542
 543                                         clk_24m_div: clk_24m_div {
 544                                                 compatible = "rockchip,rk3188-div-con";
 545                                                 rockchip,bits = <8 5>;
 546                                                 clocks = <&xin24m>;
 547                                                 clock-output-names = "clk_24m";
 548                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 549                                                 #clock-cells = <0>;
 550                                         };
 551
 552                                         /* reg[15:13]: reserved */
 553
 554                                 };
 555
 556
 557                                 clk_sel_con5: sel-con@0058 {
 558                                         compatible = "rockchip,rk3188-selcon";
 559                                         reg = <0x0058 0x4>;
 560                                         #address-cells = <1>;
 561                                         #size-cells = <1>;
 562
 563                                         clk_mac_pll_div: clk_mac_pll_div {
 564                                                 compatible = "rockchip,rk3188-div-con";
 565                                                 rockchip,bits = <0 5>;
 566                                                 clocks = <&clk_mac_pll>;
 567                                                 clock-output-names = "clk_mac_pll";
 568                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 569                                                 #clock-cells = <0>;
 570                                                 rockchip,clkops-idx =
 571                                                         <CLKOPS_RATE_MUX_DIV>;
 572                                                 #clock-init-cells = <1>;
 573                                         };
 574
 575                                         /* reg[5]: reserved */
 576
 577                                         clk_mac_pll: clk_mac_pll_mux {
 578                                                 compatible = "rockchip,rk3188-mux-con";
 579                                                 rockchip,bits = <6 2>;
 580                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
 581                                                 clock-output-names = "clk_mac_pll";
 582                                                 #clock-cells = <0>;
 583                                                 #clock-init-cells = <1>;
 584                                         };
 585
 586                                         /* reg[14:8]: reserved */
 587
 588                                         clk_mac_ref: clk_mac_ref_mux {
 589                                                 compatible = "rockchip,rk3188-mux-con";
 590                                                 rockchip,bits = <15 1>;
 591                                                 clocks = <&clk_mac_pll_div>, <&gmac_clkin>;
 592                                                 clock-output-names = "clk_mac_ref";
 593                                                 #clock-cells = <0>;
 594                                                 rockchip,clkops-idx =
 595                                                         <CLKOPS_RATE_MAC_REF>;
 596                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 597                                                 #clock-init-cells = <1>;
 598                                         };
 599
 600                                 };
 601
 602
 603                                 clk_sel_con6: sel-con@005c {
 604                                         compatible = "rockchip,rk3188-selcon";
 605                                         reg = <0x005c 0x4>;
 606                                         #address-cells = <1>;
 607                                         #size-cells = <1>;
 608
 609                                         spdif_div: spdif_div {
 610                                                 compatible = "rockchip,rk3188-div-con";
 611                                                 rockchip,bits = <0 7>;
 612                                                 clocks = <&clk_spdif_pll>;
 613                                                 clock-output-names = "clk_spdif_pll";
 614                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 615                                                 #clock-cells = <0>;
 616                                                 rockchip,clkops-idx =
 617                                                         <CLKOPS_RATE_MUX_DIV>;
 618                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 619                                         };
 620
 621                                         /* reg[7]: reserved */
 622
 623                                         clk_spdif: spdif_mux {
 624                                                 compatible = "rockchip,rk3188-mux-con";
 625                                                 rockchip,bits = <8 2>;
 626                                                 clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>;
 627                                                 clock-output-names = "clk_spdif";
 628                                                 #clock-cells = <0>;
 629                                                 rockchip,clkops-idx =
 630                                                         <CLKOPS_RATE_RK3288_I2S>;
 631                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 632                                         };
 633
 634                                         /* reg[13:10]: reserved */
 635
 636                                         clk_spdif_pll: spdif_pll_mux {
 637                                                 compatible = "rockchip,rk3188-mux-con";
 638                                                 rockchip,bits = <14 2>;
 639                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
 640                                                 clock-output-names = "clk_spdif_pll";
 641                                                 #clock-cells = <0>;
 642                                                 #clock-init-cells = <1>;
 643                                         };
 644
 645                                 };
 646
 647                                 clk_sel_con7: sel-con@0060 {
 648                                         compatible = "rockchip,rk3188-selcon";
 649                                         reg = <0x0060 0x4>;
 650                                         #address-cells = <1>;
 651                                         #size-cells = <1>;
 652
 653                                         i2s_2ch_frac: i2s_2ch_frac {
 654                                                 compatible = "rockchip,rk3188-frac-con";
 655                                                 clocks = <&clk_i2s_2ch_pll>;
 656                                                 clock-output-names = "i2s_2ch_frac";
 657                                                 /* numerator    denominator */
 658                                                 rockchip,bits = <0 32>;
 659                                                 rockchip,clkops-idx =
 660                                                         <CLKOPS_RATE_FRAC>;
 661                                                 #clock-cells = <0>;
 662                                         };
 663                                 };
 664
 665                                 clk_sel_con8: sel-con@0064 {
 666                                         compatible = "rockchip,rk3188-selcon";
 667                                         reg = <0x0064 0x4>;
 668                                         #address-cells = <1>;
 669                                         #size-cells = <1>;
 670
 671                                         i2s_8ch_frac: i2s_8ch_frac {
 672                                                 compatible = "rockchip,rk3188-frac-con";
 673                                                 clocks = <&clk_i2s_8ch_pll>;
 674                                                 clock-output-names = "i2s_8ch_frac";
 675                                                 /* numerator    denominator */
 676                                                 rockchip,bits = <0 32>;
 677                                                 rockchip,clkops-idx =
 678                                                         <CLKOPS_RATE_FRAC>;
 679                                                 #clock-cells = <0>;
 680                                         };
 681                                 };
 682
 683                                 clk_sel_con9: sel-con@0068 {
 684                                         compatible = "rockchip,rk3188-selcon";
 685                                         reg = <0x0068 0x4>;
 686                                         #address-cells = <1>;
 687                                         #size-cells = <1>;
 688
 689                                         clk_i2s_8ch_pll_div: clk_i2s_8ch_pll_div {
 690                                                 compatible = "rockchip,rk3188-div-con";
 691                                                 rockchip,bits = <0 7>;
 692                                                 clocks = <&clk_i2s_8ch_pll>;
 693                                                 clock-output-names = "clk_i2s_8ch_pll";
 694                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 695                                                 #clock-cells = <0>;
 696                                                 rockchip,clkops-idx =
 697                                                         <CLKOPS_RATE_MUX_DIV>;
 698                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 699                                         };
 700
 701                                         /* reg[7]: reserved */
 702
 703                                         clk_i2s_8ch: clk_i2s_8ch_mux {
 704                                                 compatible = "rockchip,rk3188-mux-con";
 705                                                 rockchip,bits = <8 2>;
 706                                                 clocks = <&clk_i2s_8ch_pll_div>, <&i2s_8ch_frac>, <&i2s_clkin>, <&xin12m>;
 707                                                 clock-output-names = "clk_i2s_8ch";
 708                                                 #clock-cells = <0>;
 709                                                 rockchip,clkops-idx =
 710                                                         <CLKOPS_RATE_RK3288_I2S>;
 711                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 712                                         };
 713
 714                                         /* reg[13:10]: reserved */
 715
 716                                         clk_i2s_8ch_pll: i2s_8ch_pll_mux {
 717                                                 compatible = "rockchip,rk3188-mux-con";
 718                                                 rockchip,bits = <14 2>;
 719                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
 720                                                 clock-output-names = "clk_i2s_8ch_pll";
 721                                                 #clock-cells = <0>;
 722                                                 #clock-init-cells = <1>;
 723                                         };
 724
 725                                 };
 726
 727                                 clk_sel_con10: sel-con@006c {
 728                                         compatible = "rockchip,rk3188-selcon";
 729                                         reg = <0x006c 0x4>;
 730                                         #address-cells = <1>;
 731                                         #size-cells = <1>;
 732
 733                                         aclk_peri_div: aclk_peri_div {
 734                                                 compatible = "rockchip,rk3188-div-con";
 735                                                 rockchip,bits = <0 5>;
 736                                                 clocks = <&aclk_peri>;
 737                                                 clock-output-names = "aclk_peri";
 738                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 739                                                 #clock-cells = <0>;
 740                                                 rockchip,clkops-idx =
 741                                                         <CLKOPS_RATE_MUX_DIV>;
 742                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 743                                         };
 744
 745                                         /* reg[7:5]: reserved */
 746
 747                                         hclk_peri_pre: hclk_peri_pre_div {
 748                                                 compatible = "rockchip,rk3188-div-con";
 749                                                 rockchip,bits = <8 2>;
 750                                                 clocks = <&aclk_peri>;
 751                                                 clock-output-names = "hclk_peri_pre";
 752                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 753                                                 rockchip,div-relations =
 754                                                                 <0x0 1
 755                                                                  0x1 2
 756                                                                  0x2 4>;
 757                                                 #clock-cells = <0>;
 758                                                 #clock-init-cells = <1>;
 759                                         };
 760
 761                                         /* reg[11:10]: reserved */
 762
 763                                         pclk_peri_pre: pclk_peri_div {
 764                                                 compatible = "rockchip,rk3188-div-con";
 765                                                 rockchip,bits = <12 2>;
 766                                                 clocks = <&aclk_peri>;
 767                                                 clock-output-names = "pclk_peri_pre";
 768                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 769                                                 rockchip,div-relations =
 770                                                                 <0x0 1
 771                                                                  0x1 2
 772                                                                  0x2 4
 773                                                                  0x3 8>;
 774                                                 #clock-cells = <0>;
 775                                                 #clock-init-cells = <1>;
 776                                         };
 777
 778                                         aclk_peri: aclk_peri_mux {
 779                                                 compatible = "rockchip,rk3188-mux-con";
 780                                                 rockchip,bits = <14 2>;
 781                                                 clocks = <&clk_gpll>,<&clk_cpll>,<&clk_gpll_div2>,<&clk_gpll_div3>;
 782                                                 clock-output-names = "aclk_peri";
 783                                                 #clock-cells = <0>;
 784                                                 #clock-init-cells = <1>;
 785                                         };
 786                                 };
 787
 788                                 clk_sel_con11: sel-con@0070 {
 789                                         compatible = "rockchip,rk3188-selcon";
 790                                         reg = <0x0070 0x4>;
 791                                         #address-cells = <1>;
 792                                         #size-cells = <1>;
 793
 794                                         clk_sdmmc0_div: clk_sdmmc0_div {
 795                                                 compatible = "rockchip,rk3188-div-con";
 796                                                 rockchip,bits = <0 6>;
 797                                                 clocks = <&clk_sdmmc0>;
 798                                                 clock-output-names = "clk_sdmmc0";
 799                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 800                                                 #clock-cells = <0>;
 801                                                 rockchip,clkops-idx =
 802                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 803                                         };
 804
 805                                         clk_sdmmc0: clk_sdmmc0_mux {
 806                                                 compatible = "rockchip,rk3188-mux-con";
 807                                                 rockchip,bits = <6 2>;
 808                                                 clocks = <&clk_cpll>,<&clk_gpll>,<&clk_gpll_div2>,<&xin24m>;
 809                                                 clock-output-names = "clk_sdmmc0";
 810                                                 #clock-cells = <0>;
 811                                                 #clock-init-cells = <1>;
 812                                         };
 813
 814                                         clk_sfc_div: clk_sfc_div {
 815                                                 compatible = "rockchip,rk3188-div-con";
 816                                                 rockchip,bits = <8 5>;
 817                                                 clocks = <&clk_sfc>;
 818                                                 clock-output-names = "clk_sfc";
 819                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 820                                                 #clock-cells = <0>;
 821                                                 rockchip,clkops-idx =
 822                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 823                                         };
 824
 825                                         /* reg[13]: reserved */
 826
 827                                         clk_sfc: clk_sfc_mux {
 828                                                 compatible = "rockchip,rk3188-mux-con";
 829                                                 rockchip,bits = <14 2>;
 830                                                 clocks = <&clk_cpll>,<&clk_gpll>,<&clk_gpll_div2>,<&xin24m>;
 831                                                 clock-output-names = "clk_sfc";
 832                                                 #clock-cells = <0>;
 833                                                 #clock-init-cells = <1>;
 834                                         };
 835
 836                                 };
 837
 838                                 clk_sel_con12: sel-con@0074 {
 839                                         compatible = "rockchip,rk3188-selcon";
 840                                         reg = <0x0074 0x4>;
 841                                         #address-cells = <1>;
 842                                         #size-cells = <1>;
 843
 844                                         clk_sdio_div: clk_sdio_div {
 845                                                 compatible = "rockchip,rk3188-div-con";
 846                                                 rockchip,bits = <0 6>;
 847                                                 clocks = <&clk_sdio>;
 848                                                 clock-output-names = "clk_sdio";
 849                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 850                                                 #clock-cells = <0>;
 851                                                 rockchip,clkops-idx =
 852                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 853                                         };
 854
 855                                         clk_sdio: clk_sdio_mux {
 856                                                 compatible = "rockchip,rk3188-mux-con";
 857                                                 rockchip,bits = <6 2>;
 858                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&xin24m>;
 859                                                 clock-output-names = "clk_sdio";
 860                                                 #clock-cells = <0>;
 861                                                 #clock-init-cells = <1>;
 862                                         };
 863
 864                                         clk_emmc_div: clk_emmc_div {
 865                                                 compatible = "rockchip,rk3188-div-con";
 866                                                 rockchip,bits = <8 6>;
 867                                                 clocks = <&clk_emmc>;
 868                                                 clock-output-names = "clk_emmc";
 869                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 870                                                 #clock-cells = <0>;
 871                                                 rockchip,clkops-idx =
 872                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 873                                         };
 874
 875                                         clk_emmc: clk_emmc_mux {
 876                                                 compatible = "rockchip,rk3188-mux-con";
 877                                                 rockchip,bits = <14 2>;
 878                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&xin24m>;
 879                                                 clock-output-names = "clk_emmc";
 880                                                 #clock-cells = <0>;
 881                                                 #clock-init-cells = <1>;
 882                                         };
 883
 884                                 };
 885
 886                                 clk_sel_con13: sel-con@0078 {
 887                                         compatible = "rockchip,rk3188-selcon";
 888                                         reg = <0x0078 0x4>;
 889                                         #address-cells = <1>;
 890                                         #size-cells = <1>;
 891
 892                                         clk_uart0_pll_div: clk_uart0_pll_div {
 893                                                 compatible = "rockchip,rk3188-div-con";
 894                                                 rockchip,bits = <0 7>;
 895                                                 clocks = <&clk_uart0_pll>;
 896                                                 clock-output-names = "clk_uart0_pll";
 897                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 898                                                 #clock-cells = <0>;
 899                                         };
 900
 901                                         /* reg[7]: reserved */
 902
 903                                         clk_uart0: clk_uart0_mux {
 904                                                 compatible = "rockchip,rk3188-mux-con";
 905                                                 rockchip,bits = <8 2>;
 906                                                 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>;
 907                                                 clock-output-names = "clk_uart0";
 908                                                 #clock-cells = <0>;
 909                                                 rockchip,clkops-idx =
 910                                                         <CLKOPS_RATE_RK3288_I2S>;
 911                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 912                                         };
 913
 914                                         /* reg[11:10]: reserved */
 915
 916                                         clk_uart0_pll: clk_uart0_pll_mux {
 917                                                 compatible = "rockchip,rk3188-mux-con";
 918                                                 rockchip,bits = <12 2>;
 919                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
 920                                                 clock-output-names = "clk_uart0_pll";
 921                                                 #clock-cells = <0>;
 922                                                 #clock-init-cells = <1>;
 923                                         };
 924
 925                                         clk_uart2_pll: clk_uart2_pll_mux {
 926                                                 compatible = "rockchip,rk3188-mux-con";
 927                                                 rockchip,bits = <14 2>;
 928                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
 929                                                 clock-output-names = "clk_uart2_pll";
 930                                                 #clock-cells = <0>;
 931                                                 #clock-init-cells = <1>;
 932                                         };
 933
 934                                 };
 935
 936                                 clk_sel_con14: sel-con@007c {
 937                                         compatible = "rockchip,rk3188-selcon";
 938                                         reg = <0x007c 0x4>;
 939                                         #address-cells = <1>;
 940                                         #size-cells = <1>;
 941
 942                                         clk_uart1_div: clk_uart1_div {
 943                                                 compatible = "rockchip,rk3188-div-con";
 944                                                 rockchip,bits = <0 7>;
 945                                                 clocks = <&clk_uart2_pll>;
 946                                                 clock-output-names = "clk_uart1_div";
 947                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 948                                                 #clock-cells = <0>;
 949                                         };
 950
 951                                         /* reg[7]: reserved */
 952
 953                                         clk_uart1: clk_uart1_mux {
 954                                                 compatible = "rockchip,rk3188-mux-con";
 955                                                 rockchip,bits = <8 2>;
 956                                                 clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>;
 957                                                 clock-output-names = "clk_uart1";
 958                                                 #clock-cells = <0>;
 959                                                 rockchip,clkops-idx =
 960                                                         <CLKOPS_RATE_RK3288_I2S>;
 961                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 962                                         };
 963
 964                                         /* reg[15:10]: reserved */
 965                                 };
 966
 967                                 clk_sel_con15: sel-con@0080 {
 968                                         compatible = "rockchip,rk3188-selcon";
 969                                         reg = <0x0080 0x4>;
 970                                         #address-cells = <1>;
 971                                         #size-cells = <1>;
 972
 973                                         clk_uart2_div: clk_uart2_div {
 974                                                 compatible = "rockchip,rk3188-div-con";
 975                                                 rockchip,bits = <0 7>;
 976                                                 clocks = <&clk_uart2_pll>;
 977                                                 clock-output-names = "clk_uart2_div";
 978                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 979                                                 #clock-cells = <0>;
 980                                         };
 981
 982                                         /* reg[7]: reserved */
 983
 984                                         clk_uart2: clk_uart2_mux {
 985                                                 compatible = "rockchip,rk3188-mux-con";
 986                                                 rockchip,bits = <8 2>;
 987                                                 clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>;
 988                                                 clock-output-names = "clk_uart2";
 989                                                 #clock-cells = <0>;
 990                                                 rockchip,clkops-idx =
 991                                                         <CLKOPS_RATE_RK3288_I2S>;
 992                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 993                                         };
 994
 995                                         /* reg[15:10]: reserved */
 996                                 };
 997
 998                                 clk_sel_con17: sel-con@0088 {
 999                                         compatible = "rockchip,rk3188-selcon";
1000                                         reg = <0x0088 0x4>;
1001                                         #address-cells = <1>;
1002                                         #size-cells = <1>;
1003
1004                                         uart0_frac: uart0_frac {
1005                                                 compatible = "rockchip,rk3188-frac-con";
1006                                                 clocks = <&clk_uart0_pll>;
1007                                                 clock-output-names = "uart0_frac";
1008                                                 /* numerator    denominator */
1009                                                 rockchip,bits = <0 32>;
1010                                                 rockchip,clkops-idx =
1011                                                         <CLKOPS_RATE_FRAC>;
1012                                                 #clock-cells = <0>;
1013                                         };
1014                                 };
1015
1016                                 clk_sel_con18: sel-con@008c {
1017                                         compatible = "rockchip,rk3188-selcon";
1018                                         reg = <0x008c 0x4>;
1019                                         #address-cells = <1>;
1020                                         #size-cells = <1>;
1021
1022                                         uart1_frac: uart1_frac {
1023                                                 compatible = "rockchip,rk3188-frac-con";
1024                                                 clocks = <&clk_uart1_div>;
1025                                                 clock-output-names = "uart1_frac";
1026                                                 /* numerator    denominator */
1027                                                 rockchip,bits = <0 32>;
1028                                                 rockchip,clkops-idx =
1029                                                         <CLKOPS_RATE_FRAC>;
1030                                                 #clock-cells = <0>;
1031                                         };
1032                                 };
1033
1034                                 clk_sel_con19: sel-con@0090 {
1035                                         compatible = "rockchip,rk3188-selcon";
1036                                         reg = <0x0090 0x4>;
1037                                         #address-cells = <1>;
1038                                         #size-cells = <1>;
1039
1040                                         uart2_frac: uart2_frac {
1041                                                 compatible = "rockchip,rk3188-frac-con";
1042                                                 clocks = <&clk_uart2_div>;
1043                                                 clock-output-names = "uart2_frac";
1044                                                 /* numerator    denominator */
1045                                                 rockchip,bits = <0 32>;
1046                                                 rockchip,clkops-idx =
1047                                                         <CLKOPS_RATE_FRAC>;
1048                                                 #clock-cells = <0>;
1049                                         };
1050
1051                                 };
1052
1053                                 clk_sel_con20: sel-con@0094 {
1054                                         compatible = "rockchip,rk3188-selcon";
1055                                         reg = <0x0094 0x4>;
1056                                         #address-cells = <1>;
1057                                         #size-cells = <1>;
1058
1059                                         spdif_frac: spdif_frac {
1060                                                 compatible = "rockchip,rk3188-frac-con";
1061                                                 clocks = <&spdif_div>;
1062                                                 clock-output-names = "spdif_frac";
1063                                                 /* numerator    denominator */
1064                                                 rockchip,bits = <0 32>;
1065                                                 rockchip,clkops-idx =
1066                                                         <CLKOPS_RATE_FRAC>;
1067                                                 #clock-cells = <0>;
1068                                         };
1069
1070                                 };
1071
1072                                 clk_sel_con23: sel-con@00a0 {
1073                                         compatible = "rockchip,rk3188-selcon";
1074                                         reg = <0x00a0 0x4>;
1075                                         #address-cells = <1>;
1076                                         #size-cells = <1>;
1077
1078                                         dclk_ebc: dclk_ebc_mux {
1079                                                 compatible = "rockchip,rk3188-mux-con";
1080                                                 rockchip,bits = <0 2>;
1081                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
1082                                                 clock-output-names = "dclk_ebc";
1083                                                 #clock-cells = <0>;
1084                                                 #clock-init-cells = <1>;
1085                                         };
1086
1087                                         /* reg[7:2]: reserved */
1088
1089                                         dclk_ebc_div: dclk_ebc_div {
1090                                                 compatible = "rockchip,rk3188-div-con";
1091                                                 rockchip,bits = <8 8>;
1092                                                 clocks = <&dclk_ebc>;
1093                                                 clock-output-names = "dclk_ebc";
1094                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1095                                                 #clock-cells = <0>;
1096                                                 rockchip,clkops-idx =
1097                                                         <CLKOPS_RATE_MUX_DIV>;
1098                                         };
1099
1100                                 };
1101
1102                                 clk_sel_con24: sel-con@00a4 {
1103                                         compatible = "rockchip,rk3188-selcon";
1104                                         reg = <0x00a4 0x4>;
1105                                         #address-cells = <1>;
1106                                         #size-cells = <1>;
1107
1108                                         clk_crypto_div: clk_crypto_div {
1109                                                 compatible = "rockchip,rk3188-div-con";
1110                                                 rockchip,bits = <0 2>;
1111                                                 clocks = <&aclk_cpu>;
1112                                                 clock-output-names = "clk_crypto";
1113                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1114                                                 #clock-cells = <0>;
1115                                                 #clock-init-cells = <1>;
1116                                         };
1117
1118                                         /* reg[7:2]: reserved */
1119
1120                                         clk_saradc: clk_saradc_div {
1121                                                 compatible = "rockchip,rk3188-div-con";
1122                                                 rockchip,bits = <8 8>;
1123                                                 clocks = <&xin24m>;
1124                                                 clock-output-names = "clk_saradc";
1125                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1126                                                 #clock-cells = <0>;
1127                                                 #clock-init-cells = <1>;
1128                                         };
1129
1130                                 };
1131
1132                                 clk_sel_con25: sel-con@00a8 {
1133                                         compatible = "rockchip,rk3188-selcon";
1134                                         reg = <0x00a8 0x4>;
1135                                         #address-cells = <1>;
1136                                         #size-cells = <1>;
1137
1138                                         clk_spi0_div: clk_spi0_div {
1139                                                 compatible = "rockchip,rk3188-div-con";
1140                                                 rockchip,bits = <0 7>;
1141                                                 clocks = <&clk_spi0>;
1142                                                 clock-output-names = "clk_spi0";
1143                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1144                                                 #clock-cells = <0>;
1145                                                 rockchip,clkops-idx =
1146                                                         <CLKOPS_RATE_MUX_DIV>;
1147                                         };
1148
1149                                         /* reg[7]: reserved */
1150
1151                                         clk_spi0: clk_spi0_mux {
1152                                                 compatible = "rockchip,rk3188-mux-con";
1153                                                 rockchip,bits = <8 2>;
1154                                                 clocks = <&clk_cpll>, <&clk_gpll>,<&clk_gpll_div2>;
1155                                                 clock-output-names = "clk_spi0";
1156                                                 #clock-cells = <0>;
1157                                         };
1158
1159                                         /* reg[15:10]: reserved */
1160
1161                                 };
1162
1163                                 clk_sel_con26: sel-con@00ac {
1164                                         compatible = "rockchip,rk3188-selcon";
1165                                         reg = <0x00ac 0x4>;
1166                                         #address-cells = <1>;
1167                                         #size-cells = <1>;
1168
1169                                         ddr_div: ddr_div {
1170                                                 compatible = "rockchip,rk3188-div-con";
1171                                                 rockchip,bits = <0 2>;
1172                                                 clocks = <&clk_ddr>;
1173                                                 clock-output-names = "clk_ddr";
1174                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
1175                                                 rockchip,div-relations =
1176                                                                 <0x0 1
1177                                                                  0x1 2
1178                                                                  0x3 4>;
1179                                                 #clock-cells = <0>;
1180                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
1181                                                                         CLK_SET_RATE_NO_REPARENT)>;
1182                                                 rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
1183                                         };
1184
1185                                         /* reg[7:2]: reserved */
1186
1187                                         clk_ddr: ddr_clk_pll_mux {
1188                                                 compatible = "rockchip,rk3188-mux-con";
1189                                                 rockchip,bits = <8 1>;
1190                                                 clocks = <&clk_dpll>, <&dummy>;
1191                                                 clock-output-names = "clk_ddr";
1192                                                 #clock-cells = <0>;
1193                                         };
1194
1195                                         /* reg[15:9]: reserved */
1196                                 };
1197
1198                                 clk_sel_con27: sel-con@00b0 {
1199                                         compatible = "rockchip,rk3188-selcon";
1200                                         reg = <0x00b0 0x4>;
1201                                         #address-cells = <1>;
1202                                         #size-cells = <1>;
1203
1204                                         dclk_lcdc0: dclk_lcdc0_mux {
1205                                                 compatible = "rockchip,rk3188-mux-con";
1206                                                 rockchip,bits = <0 2>;
1207                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>;
1208                                                 clock-output-names = "dclk_lcdc0";
1209                                                 #clock-cells = <0>;
1210                                                 #clock-init-cells = <1>;
1211                                         };
1212
1213                                         /* reg[7:2]: reserved */
1214
1215                                         dclk_lcdc0_div: dclk_lcdc0_div {
1216                                                 compatible = "rockchip,rk3188-div-con";
1217                                                 rockchip,bits = <8 8>;
1218                                                 clocks = <&dclk_lcdc0>;
1219                                                 clock-output-names = "dclk_lcdc0";
1220                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1221                                                 #clock-cells = <0>;
1222                                                 rockchip,clkops-idx =
1223                                                         <CLKOPS_RATE_MUX_DIV>;
1224                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1225                                         };
1226                                 };
1227
1228                                 clk_sel_con28: sel-con@00b4 {
1229                                         compatible = "rockchip,rk3188-selcon";
1230                                         reg = <0x00b4 0x4>;
1231                                         #address-cells = <1>;
1232                                         #size-cells = <1>;
1233
1234                                         sclk_lcdc0: sclk_lcdc0_mux {
1235                                                 compatible = "rockchip,rk3188-mux-con";
1236                                                 rockchip,bits = <0 2>;
1237                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>;
1238                                                 clock-output-names = "sclk_lcdc0";
1239                                                 #clock-cells = <0>;
1240                                                 #clock-init-cells = <1>;
1241                                         };
1242
1243                                         /* reg[7:2]: reserved */
1244
1245                                         sclk_lcdc0_div: sclk_lcdc0_div {
1246                                                 compatible = "rockchip,rk3188-div-con";
1247                                                 rockchip,bits = <8 8>;
1248                                                 clocks = <&sclk_lcdc0>;
1249                                                 clock-output-names = "sclk_lcdc0";
1250                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1251                                                 #clock-cells = <0>;
1252                                                 rockchip,clkops-idx =
1253                                                         <CLKOPS_RATE_MUX_DIV>;
1254                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1255                                         };
1256                                 };
1257
1258                                 clk_sel_con29: sel-con@00b8 {
1259                                         compatible = "rockchip,rk3188-selcon";
1260                                         reg = <0x00b8 0x4>;
1261                                         #address-cells = <1>;
1262                                         #size-cells = <1>;
1263
1264                                         clk_cif_pll: clk_cif_pll_mux {
1265                                                 compatible = "rockchip,rk3188-mux-con";
1266                                                 rockchip,bits = <0 2>;
1267                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
1268                                                 clock-output-names = "clk_cif_pll";
1269                                                 #clock-cells = <0>;
1270                                                 #clock-init-cells = <1>;
1271                                         };
1272
1273                                         clk_cif_out_div: clk_cif_out_div {
1274                                                 compatible = "rockchip,rk3188-div-con";
1275                                                 rockchip,bits = <2 5>;
1276                                                 clocks = <&clk_cif_out>;
1277                                                 clock-output-names = "clk_cif_out";
1278                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1279                                                 #clock-cells = <0>;
1280                                                 rockchip,clkops-idx =
1281                                                         <CLKOPS_RATE_MUX_DIV>;
1282                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1283                                         };
1284
1285                                         clk_cif_out: clk_cif_out_mux {
1286                                                 compatible = "rockchip,rk3188-mux-con";
1287                                                 rockchip,bits = <7 1>;
1288                                                 clocks = <&clk_cif_pll>, <&xin24m>;
1289                                                 clock-output-names = "clk_cif_out";
1290                                                 #clock-cells = <0>;
1291                                                 #clock-init-cells = <1>;
1292                                         };
1293
1294                                         pclk_pmu_pre: pclk_pmu_pre_div {
1295                                                 compatible = "rockchip,rk3188-div-con";
1296                                                 rockchip,bits = <8 6>;
1297                                                 clocks = <&clk_cpll>;
1298                                                 clock-output-names = "pclk_pmu_pre";
1299                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1300                                                 #clock-cells = <0>;
1301                                                 #clock-init-cells = <1>;
1302                                         };
1303
1304                                         /* reg[15:14]: reserved */
1305                                 };
1306
1307                                 clk_sel_con30: sel-con@00bc {
1308                                         compatible = "rockchip,rk3188-selcon";
1309                                         reg = <0x00bc 0x4>;
1310                                         #address-cells = <1>;
1311                                         #size-cells = <1>;
1312
1313                                         clk_testout_div: clk_testout_div {
1314                                                 compatible = "rockchip,rk3188-div-con";
1315                                                 rockchip,bits = <0 5>;
1316                                                 clocks = <&dummy>;
1317                                                 clock-output-names = "clk_testout";
1318                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1319                                                 #clock-cells = <0>;
1320                                                 #clock-init-cells = <1>;
1321                                         };
1322
1323                                         /* reg[6:5]: reserved */
1324
1325                                         clk_cif0_in: clk_cif0_in_mux {
1326                                                 compatible = "rockchip,rk3188-mux-con";
1327                                                 rockchip,bits = <7 1>;
1328                                                 clocks = <&pclkin_cif>, <&pclkin_cif_inv>;
1329                                                 clock-output-names = "clk_cif0_in";
1330                                                 #clock-cells = <0>;
1331                                                 #clock-init-cells = <1>;
1332                                         };
1333
1334                                         hclk_vio_pre_div: hclk_vio_pre_div {
1335                                                 compatible = "rockchip,rk3188-div-con";
1336                                                 rockchip,bits = <8 5>;
1337                                                 clocks = <&hclk_vio_pre>;
1338                                                 clock-output-names = "hclk_vio_pre";
1339                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1340                                                 #clock-cells = <0>;
1341                                                 rockchip,clkops-idx =
1342                                                         <CLKOPS_RATE_MUX_DIV>;
1343                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1344                                         };
1345
1346                                         /* reg[13]: reserved */
1347
1348                                         hclk_vio_pre: hclk_vio_pre_mux {
1349                                                 compatible = "rockchip,rk3188-mux-con";
1350                                                 rockchip,bits = <14 2>;
1351                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
1352                                                 clock-output-names = "hclk_vio_pre";
1353                                                 #clock-cells = <0>;
1354                                                 #clock-init-cells = <1>;
1355                                         };
1356
1357                                 };
1358
1359                                 clk_sel_con31: sel-con@00c0 {
1360                                         compatible = "rockchip,rk3188-selcon";
1361                                         reg = <0x00c0 0x4>;
1362                                         #address-cells = <1>;
1363                                         #size-cells = <1>;
1364
1365                                         aclk_vio0_pre_div: aclk_vio0_pre_div {
1366                                                 compatible = "rockchip,rk3188-div-con";
1367                                                 rockchip,bits = <0 5>;
1368                                                 clocks = <&aclk_vio0_pre>;
1369                                                 clock-output-names = "aclk_vio0_pre";
1370                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1371                                                 #clock-cells = <0>;
1372                                                 rockchip,clkops-idx =
1373                                                         <CLKOPS_RATE_MUX_DIV>;
1374                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1375                                         };
1376
1377                                         aclk_vio0_pre: aclk_vio0_pre_mux {
1378                                                 compatible = "rockchip,rk3188-mux-con";
1379                                                 rockchip,bits = <5 3>;
1380                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1381                                                 clock-output-names = "aclk_vio0_pre";
1382                                                 #clock-cells = <0>;
1383                                                 #clock-init-cells = <1>;
1384                                         };
1385
1386                                         aclk_vio1_pre_div: aclk_vio1_pre_div {
1387                                                 compatible = "rockchip,rk3188-div-con";
1388                                                 rockchip,bits = <8 5>;
1389                                                 clocks = <&aclk_vio1_pre>;
1390                                                 clock-output-names = "aclk_vio1_pre";
1391                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1392                                                 #clock-cells = <0>;
1393                                                 rockchip,clkops-idx =
1394                                                         <CLKOPS_RATE_MUX_DIV>;
1395                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1396                                         };
1397
1398                                         aclk_vio1_pre: aclk_vio1_pre_mux {
1399                                                 compatible = "rockchip,rk3188-mux-con";
1400                                                 rockchip,bits = <13 3>;
1401                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1402                                                 clock-output-names = "aclk_vio1_pre";
1403                                                 #clock-cells = <0>;
1404                                                 #clock-init-cells = <1>;
1405                                         };
1406
1407                                 };
1408
1409                                 clk_sel_con32: sel-con@00c4 {
1410                                         compatible = "rockchip,rk3188-selcon";
1411                                         reg = <0x00c4 0x4>;
1412                                         #address-cells = <1>;
1413                                         #size-cells = <1>;
1414
1415                                         clk_vepu_div: clk_vepu_div {
1416                                                 compatible = "rockchip,rk3188-div-con";
1417                                                 rockchip,bits = <0 5>;
1418                                                 clocks = <&clk_vepu>;
1419                                                 clock-output-names = "clk_vepu";
1420                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1421                                                 #clock-cells = <0>;
1422                                                 rockchip,clkops-idx =
1423                                                         <CLKOPS_RATE_MUX_DIV>;
1424                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1425                                         };
1426
1427                                         clk_vepu: clk_vepu_mux {
1428                                                 compatible = "rockchip,rk3188-mux-con";
1429                                                 rockchip,bits = <5 3>;
1430                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1431                                                 clock-output-names = "clk_vepu";
1432                                                 #clock-cells = <0>;
1433                                                 #clock-init-cells = <1>;
1434                                         };
1435
1436                                         clk_vdpu_div: clk_vdpu_div {
1437                                                 compatible = "rockchip,rk3188-div-con";
1438                                                 rockchip,bits = <8 5>;
1439                                                 clocks = <&clk_vdpu>;
1440                                                 clock-output-names = "clk_vdpu";
1441                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1442                                                 #clock-cells = <0>;
1443                                                 rockchip,clkops-idx =
1444                                                         <CLKOPS_RATE_MUX_DIV>;
1445                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1446                                         };
1447
1448                                         clk_vdpu: clk_vdpu_mux {
1449                                                 compatible = "rockchip,rk3188-mux-con";
1450                                                 rockchip,bits = <13 3>;
1451                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1452                                                 clock-output-names = "clk_vdpu";
1453                                                 #clock-cells = <0>;
1454                                                 #clock-init-cells = <1>;
1455                                         };
1456
1457                                 };
1458
1459                                 clk_sel_con34: sel-con@00cc {
1460                                         compatible = "rockchip,rk3188-selcon";
1461                                         reg = <0x00cc 0x4>;
1462                                         #address-cells = <1>;
1463                                         #size-cells = <1>;
1464
1465                                         clk_gpu_div: clk_gpu_div {
1466                                                 compatible = "rockchip,rk3188-div-con";
1467                                                 rockchip,bits = <0 5>;
1468                                                 clocks = <&clk_gpu>;
1469                                                 clock-output-names = "clk_gpu";
1470                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1471                                                 #clock-cells = <0>;
1472                                                 rockchip,clkops-idx =
1473                                                         <CLKOPS_RATE_MUX_DIV>;
1474                                                 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
1475                                         };
1476
1477                                         clk_gpu: clk_gpu_mux {
1478                                                 compatible = "rockchip,rk3188-mux-con";
1479                                                 rockchip,bits = <5 3>;
1480                                                 clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1481                                                 clock-output-names = "clk_gpu";
1482                                                 #clock-cells = <0>;
1483                                                 #clock-init-cells = <1>;
1484                                         };
1485
1486                                         clk_hevc_core_div: clk_hevc_core_div {
1487                                                 compatible = "rockchip,rk3188-div-con";
1488                                                 rockchip,bits = <8 5>;
1489                                                 clocks = <&clk_hevc_core>;
1490                                                 clock-output-names = "clk_hevc_core";
1491                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1492                                                 #clock-cells = <0>;
1493                                                 rockchip,clkops-idx =
1494                                                         <CLKOPS_RATE_MUX_DIV>;
1495                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1496                                         };
1497
1498                                         clk_hevc_core: clk_hevc_core_mux {
1499                                                 compatible = "rockchip,rk3188-mux-con";
1500                                                 rockchip,bits = <13 3>;
1501                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1502                                                 clock-output-names = "clk_hevc_core";
1503                                                 #clock-cells = <0>;
1504                                                 #clock-init-cells = <1>;
1505                                         };
1506
1507                                 };
1508
1509                         };
1510
1511
1512                         /* Gate control regs */
1513                         clk_gate_cons {
1514                                 compatible = "rockchip,rk-gate-cons";
1515                                 #address-cells = <1>;
1516                                 #size-cells = <1>;
1517                                 ranges ;
1518
1519                                 clk_gates0: gate-clk@00d0{
1520                                         compatible = "rockchip,rk3188-gate-clk";
1521                                         reg = <0x00d0 0x4>;
1522                                         clocks =
1523                                                 <&clk_core>,            <&dummy>,
1524                                                 <&dummy>,       <&aclk_cpu>,
1525
1526                                                 <&aclk_cpu>,    <&aclk_cpu>,
1527                                                 <&dummy>,               <&clk_core>,
1528
1529                                                 <&dummy>,       <&clk_i2s_2ch_pll>,
1530                                                 <&i2s_2ch_frac>,        <&hclk_vio_pre>,
1531
1532                                                 <&aclk_cpu>,            <&clk_i2s_2ch_out>,
1533                                                 <&clk_i2s_2ch>,         <&dummy>;
1534
1535                                         clock-output-names =
1536                                                 "pclk_dbg",                     "aclk_cpu",      /*clk_cpu_cpll*/
1537                                                 "reserved",             "aclk_cpu_pre",
1538
1539                                                 "hclk_cpu_pre",         "pclk_cpu_pre",
1540                                                 "clk_core",             "aclk_core_pre",
1541
1542                                                 "reserved",             "clk_i2s_2ch_pll",
1543                                                 "i2s_2ch_frac",         "hclk_vio_pre",
1544
1545                                                 "clk_crypto",           "clk_i2s_2ch_out",
1546                                                 "clk_i2s_2ch",          "clk_testout";
1547                                         rockchip,suspend-clkgating-setting=<0x11ff 0x0>;
1548
1549                                         #clock-cells = <1>;
1550                                 };
1551
1552                                 clk_gates1: gate-clk@00d4{
1553                                         compatible = "rockchip,rk3188-gate-clk";
1554                                         reg = <0x00d4 0x4>;
1555                                         clocks =
1556                                                 <&clk_cpll>,            <&dummy>,
1557                                                 <&dummy>,               <&jtag_tck>,
1558
1559                                                 <&aclk_vio1_pre>,               <&xin12m>,
1560                                                 <&xin12m>,              <&clk_mac_pll>,
1561
1562                                                 <&clk_uart0_pll>,               <&uart0_frac>,
1563                                                 <&clk_uart1_div>,               <&uart1_frac>,
1564
1565                                                 <&clk_uart2_div>,               <&uart2_frac>,
1566                                                 <&clk_tsp>,             <&dummy>;
1567
1568                                         clock-output-names =
1569                                                 "pclk_pmu_pre",         "reserved",
1570                                                 "reserved",             "clk_jtag",
1571
1572                                                 "aclk_vio1_pre",                "clk_otgphy0",
1573                                                 "clk_otgphy1",                  "clk_mac_pll",
1574
1575                                                 "clk_uart0_pll",        "uart0_frac",
1576                                                 "clk_uart1_div",        "uart1_frac",
1577
1578                                                 "clk_uart2_div",        "uart2_frac",
1579                                                 "clk_tsp",      "reserved";
1580
1581                                          rockchip,suspend-clkgating-setting=<0x000f 0x0>;
1582                                         #clock-cells = <1>;
1583                                 };
1584
1585                                 clk_gates2: gate-clk@00d8 {
1586                                         compatible = "rockchip,rk3188-gate-clk";
1587                                         reg = <0x00d8 0x4>;
1588                                         clocks =
1589                                                 <&aclk_peri>,           <&aclk_peri>,
1590                                                 <&aclk_peri>,           <&aclk_peri>,
1591
1592                                                 <&clk_mac_ref>,         <&clk_mac_ref>,
1593                                                 <&clk_mac_ref>,         <&clk_mac_ref>,
1594
1595                                                 <&clk_saradc>,          <&clk_spi0>,
1596                                                 <&clk_spdif_pll>,               <&clk_sdmmc0>,
1597
1598                                                 <&spdif_frac>,          <&clk_sdio>,
1599                                                 <&clk_emmc>,            <&xin24m>;
1600                                         clock-output-names =
1601                                                 "aclk_peri",            "aclk_peri_pre",
1602                                                 "hclk_peri_pre",                "pclk_peri_pre",
1603
1604                                                 "clk_mac_ref",          "clk_mac_refout",
1605                                                 "clk_mac_rx",           "clk_mac_tx",
1606
1607                                                 "clk_saradc",           "clk_spi0",
1608                                                 "clk_spdif_pll",                "clk_sdmmc0",
1609
1610                                                 "spdif_frac",           "clk_sdio",
1611                                                 "clk_emmc",             "clk_mipi_24m";
1612                                             rockchip,suspend-clkgating-setting=<0x000f 0x0>;
1613
1614                                         #clock-cells = <1>;
1615                                 };
1616
1617                                 clk_gates3: gate-clk@00dc {
1618                                         compatible = "rockchip,rk3188-gate-clk";
1619                                         reg = <0x00dc 0x4>;
1620                                         clocks =
1621                                                 <&aclk_vio0_pre>,               <&dclk_lcdc0>,
1622                                                 <&sclk_lcdc0>,          <&pclkin_cif>,
1623
1624                                                 <&dclk_ebc>,                    <&hclk_cpu_pre>,
1625                                                 <&hclk_peri_pre>,               <&clk_cif_pll>,
1626
1627                                                 <&pclk_cpu_pre>,                <&clk_vepu>,
1628                                                 <&clk_hevc_core>,               <&clk_vdpu>,
1629
1630                                                 <&hclk_vdpu>,           <&clk_gpu>,
1631                                                 <&aclk_peri>,           <&clk_sfc>;
1632
1633                                         clock-output-names =
1634                                                 "aclk_vio0_pre",                "dclk_lcdc0",
1635                                                 "sclk_lcdc0",           "pclkin_cif",
1636
1637                                                 "dclk_ebc",             "g_hclk_crypto",
1638                                                 "g_hclk_em_peri",               "clk_cif_pll",
1639
1640                                                 "g_pclk_hdmi",          "clk_vepu",
1641                                                 "clk_hevc_core",                "clk_vdpu",
1642
1643                                                 "hclk_vdpu",            "clk_gpu",
1644                                                 "g_hclk_gps",           "clk_sfc";
1645                                        rockchip,suspend-clkgating-setting=<0x0060 0x0000>;
1646
1647                                         #clock-cells = <1>;
1648                                 };
1649
1650                                 clk_gates4: gate-clk@00e0{
1651                                         compatible = "rockchip,rk3188-gate-clk";
1652                                         reg = <0x00e0 0x4>;
1653                                         clocks =
1654                                                 <&hclk_peri_pre>,               <&pclk_peri_pre>,
1655                                                 <&aclk_peri>,           <&aclk_peri>,
1656
1657                                                 <&clk_i2s_8ch_pll>,             <&i2s_8ch_frac>,
1658                                                 <&clk_i2s_8ch>,         <&dummy>,
1659
1660                                                 <&dummy>,               <&dummy>,
1661                                                 <&aclk_cpu>,            <&dummy>,
1662
1663                                                 <&aclk_cpu>,            <&dummy>,
1664                                                 <&dummy>,               <&dummy>;
1665
1666                                         clock-output-names =
1667                                                 "g_hp_axi_matrix",              "g_pp_axi_matrix",
1668                                                 "g_aclk_cpu_peri",              "g_ap_axi_matrix",
1669
1670                                                 "clk_i2s_8ch_pll",              "i2s_8ch_frac",
1671                                                 "clk_i2s_8ch",          "reserved",
1672
1673                                                 "reserved",             "reserved",
1674                                                 "g_aclk_strc_sys",              "reserved",
1675
1676                                                 /* Not use these ddr gates */
1677                                                 "g_aclk_intmem",                "reserved",
1678                                                 "reserved",             "reserved";
1679
1680                                         rockchip,suspend-clkgating-setting = <0xff8f 0x0000>;
1681                                         #clock-cells = <1>;
1682                                 };
1683
1684                                 clk_gates5: gate-clk@00e4 {
1685                                         compatible = "rockchip,rk3188-gate-clk";
1686                                         reg = <0x00e4 0x4>;
1687                                         clocks =
1688                                                 <&pclk_cpu_pre>,                <&aclk_peri>,
1689                                                 <&pclk_peri_pre>,               <&dummy>,
1690
1691                                                 <&pclk_cpu_pre>,                <&dummy>,
1692                                                 <&hclk_cpu_pre>,                <&pclk_cpu_pre>,
1693
1694                                                 <&dummy>,               <&hclk_peri_pre>,
1695                                                 <&hclk_peri_pre>,               <&hclk_peri_pre>,
1696
1697                                                 <&dummy>,               <&hclk_peri_pre>,
1698                                                 <&pclk_cpu_pre>,                <&dummy>;
1699
1700                                         clock-output-names =
1701                                                 "g_pclk_mipiphy",               "g_aclk_dmac",
1702                                                 "g_pclk_efuse", "reserved",
1703
1704                                                 "g_pclk_grf",           "reserved",
1705                                                 "g_hclk_rom",           "g_pclk_ddrupctl",
1706
1707                                                 "reserved",             "g_hclk_nandc",
1708                                                 "g_hclk_sdmmc0",                "g_hclk_sdio",
1709
1710                                                 "reserved",             "g_hclk_otg0",
1711                                                 "g_pclk_acodec",                "reserved";
1712
1713                                         rockchip,suspend-clkgating-setting = <0x00f0 0x0000>;
1714
1715                                         #clock-cells = <1>;
1716                                 };
1717
1718                                 clk_gates6: gate-clk@00e8 {
1719                                         compatible = "rockchip,rk3188-gate-clk";
1720                                         reg = <0x00e8 0x4>;
1721                                         clocks =
1722                                                 <&aclk_vio0_pre>,               <&hclk_vio_pre>,
1723                                                 <&dummy>,               <&dummy>,
1724
1725                                                 <&hclk_vio_pre>,                <&aclk_vio0_pre>,
1726                                                 <&dummy>,               <&dummy>,
1727
1728                                                 <&dummy>,               <&dummy>,
1729                                                 <&hclk_vio_pre>,                        <&aclk_vio0_pre>,
1730
1731                                                 <&hclk_vio_pre>,                <&aclk_vio0_pre>,
1732                                                 <&dummy>,               <&dummy>;
1733
1734                                         clock-output-names =
1735                                                 "g_aclk_lcdc0",         "g_hclk_lcdc0",
1736                                                 "reserved",             "reserved",
1737
1738                                                 "g_hclk_cif",           "g_aclk_cif",
1739                                                 "reserved",             "reserved",
1740
1741                                                 "reserved",             "reserved",
1742                                                 "g_hclk_rga",           "g_aclk_rga",
1743
1744                                                 "g_hclk_vio_bus",               "g_aclk_vio",
1745                                                 "reserved",             "reserved";
1746
1747                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1748
1749                                         #clock-cells = <1>;
1750                                 };
1751
1752                                 clk_gates7: gate-clk@00ec {
1753                                         compatible = "rockchip,rk3188-gate-clk";
1754                                         reg = <0x00ec 0x4>;
1755                                         clocks =
1756                                                 <&hclk_peri_pre>,               <&hclk_peri_pre>,
1757                                                 <&hclk_peri_pre>,               <&hclk_peri_pre>,
1758
1759                                                 <&hclk_peri_pre>,               <&dummy>,
1760                                                 <&dummy>,               <&pclk_peri_pre>,
1761
1762                                                 <&dummy>,               <&dummy>,
1763                                                 <&pclk_peri_pre>,               <&dummy>,
1764
1765                                                 <&pclk_peri_pre>,               <&dummy>,
1766                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>;
1767
1768                                         clock-output-names =
1769                                                 "g_hclk_emmc",          "g_hclk_sfc",
1770                                                 "g_hclk_i2s_2ch",               "g_hclk_host",
1771
1772                                                 "g_hclk_i2s_8ch",               "reserved",
1773                                                 "reserved",             "g_pclk_timer",
1774
1775                                                 "reserved",             "reserved",
1776                                                 "g_pclk_pwm",           "reserved",
1777
1778                                                 "g_pclk_spi0",          "reserved",
1779                                                 "g_pclk_saradc",                "g_pclk_wdt";
1780
1781                                         rockchip,suspend-clkgating-setting = <0x8080 0x0000>;
1782
1783                                         #clock-cells = <1>;
1784                                 };
1785
1786                                 clk_gates8: gate-clk@00f0 {
1787                                         compatible = "rockchip,rk3188-gate-clk";
1788                                         reg = <0x00f0 0x4>;
1789                                         clocks =
1790                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1791                                                 <&pclk_peri_pre>,               <&dummy>,
1792
1793                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1794                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1795
1796                                                 <&dummy>,               <&pclk_peri_pre>,
1797                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1798
1799                                                 <&pclk_peri_pre>,               <&dummy>,
1800                                                 <&dummy>,               <&dummy>;
1801
1802                                         clock-output-names =
1803                                                 "g_pclk_uart0",         "g_pclk_uart1",
1804                                                 "g_pclk_uart2",         "reserved",
1805
1806                                                 "g_pclk_i2c0",          "g_pclk_i2c1",
1807                                                 "g_pclk_i2c2",          "g_pclk_i2c3",
1808
1809                                                 "reserved",             "g_pclk_gpio0",
1810                                                 "g_pclk_gpio1",         "g_pclk_gpio2",
1811
1812                                                 "g_pclk_gpio3",         "reserved",
1813                                                 "reserved",             "reserved";
1814
1815                                         rockchip,suspend-clkgating-setting=<0xff0f 0x0000>;
1816                                         #clock-cells = <1>;
1817                                 };
1818
1819                                 clk_gates9: gate-clk@00f4 {
1820                                         compatible = "rockchip,rk3188-gate-clk";
1821                                         reg = <0x00f4 0x4>;
1822                                         clocks =
1823                                                 <&dummy>,               <&dummy>,
1824                                                 <&pclk_pmu_pre>,                <&pclk_pmu_pre>,
1825
1826                                                 <&dummy>,               <&hclk_vio_pre>,
1827                                                 <&hclk_vio_pre>,                <&hclk_vio_pre>,
1828
1829                                                 <&aclk_vio1_pre>,               <&hclk_vio_pre>,
1830                                                 <&aclk_vio1_pre>,               <&dummy>,
1831
1832                                                 <&pclk_peri_pre>,               <&hclk_peri_pre>,
1833                                                 <&hclk_peri_pre>,               <&aclk_peri>;
1834
1835                                         clock-output-names =
1836                                                 "reserved",             "reserved",
1837                                                 "g_pclk_pmu",           "g_pclk_pmu_noc",
1838
1839                                                 "reserved",             "g_hclk_vio_h2p",
1840                                                 "g_pclk_mipi",          "g_hclk_iep",
1841
1842                                                 "g_aclk_iep",           "g_hclk_ebc",
1843                                                 "g_aclk_vio1_niu",              "reserved",
1844
1845                                                 "g_pclk_sim_card",              "g_hclk_usb_peri",
1846                                                 "g_hclk_pe_arbi",               "g_aclk_peri_niu";
1847
1848                                         rockchip,suspend-clkgating-setting=<0xf00f 0x0>;
1849
1850                                         #clock-cells = <1>;
1851                                 };
1852
1853                                 clk_gates10: gate-clk@00f8 {
1854                                         compatible = "rockchip,rk3188-gate-clk";
1855                                         reg = <0x00f8 0x4>;
1856                                         clocks =
1857                                                 <&xin24m>,              <&xin24m>,
1858                                                 <&xin24m>,              <&xin24m>,
1859
1860                                                 <&xin24m>,              <&xin24m>,
1861                                                 <&xin24m>,              <&xin24m>,
1862
1863                                                 <&xin24m>,              <&hclk_peri_pre>,
1864                                                 <&aclk_peri>,           <&pclk_peri_pre>,
1865
1866                                                 <&hclk_peri_pre>,               <&clk_tsp_in>,
1867                                                 <&hclk_peri_pre>,               <&clk_nandc>;
1868
1869                                         clock-output-names =
1870                                                 "g_clk_pvtm_core",              "g_clk_pvtm_gpu",
1871                                                 "g_clk_pvtm_func",              "clk_timer0",
1872
1873                                                 "clk_timer1",           "clk_timer2",
1874                                                 "clk_timer3",           "clk_timer4",
1875
1876                                                 "clk_timer5",           "g_hclk_spdif",
1877                                                 "g_aclk_gmac",          "g_pclk_gmac",
1878
1879                                                 "g_hclk_tsp",           "g_clkin0_tsp",
1880                                                 "g_hclk_usbhost",               "clk_nandc";
1881
1882                                         rockchip,suspend-clkgating-setting = <0x0000 0x0>;      /* pwm logic vol */
1883
1884                                         #clock-cells = <1>;
1885                                 };
1886
1887                         };
1888                 };
1889         };
1890 };