arch/arm/boot/dts/rk312x-clocks.dtsi

   1 /*
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <dt-bindings/clock/rockchip,rk312x.h>
  15
  16 /{
  17
  18         clocks {
  19                 compatible = "rockchip,rk-clocks";
  20                 #address-cells = <1>;
  21                 #size-cells = <1>;
  22                 ranges = <0x0  0x20000000  0x1f0>;
  23
  24                 fixed_rate_cons {
  25                         compatible = "rockchip,rk-fixed-rate-cons";
  26
  27                         xin24m: xin24m {
  28                                 compatible = "rockchip,rk-fixed-clock";
  29                                 clock-output-names = "xin24m";
  30                                 clock-frequency = <24000000>;
  31                                 #clock-cells = <0>;
  32                         };
  33
  34                         xin12m: xin12m {
  35                                 compatible = "rockchip,rk-fixed-clock";
  36                                 clocks = <&xin24m>;
  37                                 clock-output-names = "xin12m";
  38                                 clock-frequency = <12000000>;
  39                                 #clock-cells = <0>;
  40                         };
  41
  42                         gmac_clkin: gmac_clkin {
  43                                 compatible = "rockchip,rk-fixed-clock";
  44                                 clock-output-names = "gmac_clkin";
  45                                 clock-frequency = <125000000>;
  46                                 #clock-cells = <0>;
  47                         };
  48
  49                         usb480m: usb480m {
  50                                 compatible = "rockchip,rk-fixed-clock";
  51                                 clock-output-names = "usb480m";
  52                                 clock-frequency = <480000000>;
  53                                 #clock-cells = <0>;
  54                         };
  55
  56                         i2s_clkin: i2s_clkin {
  57                                 compatible = "rockchip,rk-fixed-clock";
  58                                 clock-output-names = "i2s_clkin";
  59                                 clock-frequency = <0>;
  60                                 #clock-cells = <0>;
  61                         };
  62
  63                         jtag_tck: jtag_tck {
  64                                 compatible = "rockchip,rk-fixed-clock";
  65                                 clock-output-names = "jtag_tck";
  66                                 clock-frequency = <0>;
  67                                 #clock-cells = <0>;
  68                         };
  69
  70                         pclkin_cif: pclkin_cif {
  71                                 compatible = "rockchip,rk-fixed-clock";
  72                                 clock-output-names = "pclkin_cif";
  73                                 clock-frequency = <0>;
  74                                 #clock-cells = <0>;
  75                         };
  76
  77                         clk_tsp_in: clk_tsp_in {
  78                                 compatible = "rockchip,rk-fixed-clock";
  79                                 clock-output-names = "clk_tsp_in";
  80                                 clock-frequency = <0>;
  81                                 #clock-cells = <0>;
  82                         };
  83
  84
  85                         dummy: dummy {
  86                                 compatible = "rockchip,rk-fixed-clock";
  87                                 clock-output-names = "dummy";
  88                                 clock-frequency = <0>;
  89                                 #clock-cells = <0>;
  90                         };
  91
  92                         dummy_cpll: dummy_cpll {
  93                                 compatible = "rockchip,rk-fixed-clock";
  94                                 clock-output-names = "dummy_cpll";
  95                                 clock-frequency = <0>;
  96                                 #clock-cells = <0>;
  97                         };
  98
  99                 };
 100
 101                 fixed_factor_cons {
 102                         compatible = "rockchip,rk-fixed-factor-cons";
 103
 104                         clk_gpll_div2: clk_gpll_div2 {
 105                                 compatible = "rockchip,rk-fixed-factor-clock";
 106                                 clocks = <&clk_gpll>;
 107                                 clock-output-names = "clk_gpll_div2";
 108                                 clock-div = <2>;
 109                                 clock-mult = <1>;
 110                                 #clock-cells = <0>;
 111                         };
 112
 113                         clk_gpll_div3: clk_gpll_div3 {
 114                                 compatible = "rockchip,rk-fixed-factor-clock";
 115                                 clocks = <&clk_gpll>;
 116                                 clock-output-names = "clk_gpll_div3";
 117                                 clock-div = <3>;
 118                                 clock-mult = <1>;
 119                                 #clock-cells = <0>;
 120                         };
 121
 122                         g_clk_pvtm_func: g_clk_pvtm_func {
 123                                 compatible = "rockchip,rk-fixed-factor-clock";
 124                                 clocks = <&xin24m>;
 125                                 clock-output-names = "g_clk_pvtm_func";
 126                                 clock-div = <1>;
 127                                 clock-mult = <1>;
 128                                 #clock-cells = <0>;
 129                         };
 130
 131                         hclk_vepu: hclk_vepu {
 132                                 compatible = "rockchip,rk-fixed-factor-clock";
 133                                 clocks = <&clk_vepu>;
 134                                 clock-output-names = "hclk_vepu";
 135                                 clock-div = <4>;
 136                                 clock-mult = <1>;
 137                                 #clock-cells = <0>;
 138                         };
 139
 140                         hclk_vdpu: hclk_vdpu {
 141                                 compatible = "rockchip,rk-fixed-factor-clock";
 142                                 clocks = <&clk_vdpu>;
 143                                 clock-output-names = "hclk_vdpu";
 144                                 clock-div = <4>;
 145                                 clock-mult = <1>;
 146                                 #clock-cells = <0>;
 147                         };
 148
 149                         pclkin_cif_inv: pclkin_cif_inv {
 150                                 compatible = "rockchip,rk-fixed-factor-clock";
 151                                 clocks = <&clk_gates3 3>;
 152                                 clock-output-names = "pclkin_cif_inv";
 153                                 clock-div = <1>;
 154                                 clock-mult = <1>;
 155                                 #clock-cells = <0>;
 156                         };
 157
 158                         hclk_vio_niu: hclk_vio_niu {
 159                                 compatible = "rockchip,rk-fixed-factor-clock";
 160                                 clocks = <&hclk_vio_pre>;
 161                                 clock-output-names = "hclk_vio_niu";
 162                                 clock-div = <1>;
 163                                 clock-mult = <1>;
 164                                 #clock-cells = <0>;
 165                         };
 166
 167                         aclk_vio0_niu: aclk_vio0_niu {
 168                                 compatible = "rockchip,rk-fixed-factor-clock";
 169                                 clocks = <&aclk_vio0_pre>;
 170                                 clock-output-names = "aclk_vio0_niu";
 171                                 clock-div = <1>;
 172                                 clock-mult = <1>;
 173                                 #clock-cells = <0>;
 174                         };
 175
 176                         aclk_vio1_niu: aclk_vio1_niu {
 177                                 compatible = "rockchip,rk-fixed-factor-clock";
 178                                 clocks = <&aclk_vio1_pre>;
 179                                 clock-output-names = "aclk_vio1_niu";
 180                                 clock-div = <1>;
 181                                 clock-mult = <1>;
 182                                 #clock-cells = <0>;
 183                         };
 184
 185                 };
 186
 187                 pd_cons {
 188                         compatible = "rockchip,rk-pd-cons";
 189
 190                         pd_gpu: pd_gpu {
 191                                 compatible = "rockchip,rk-pd-clock";
 192                                 clock-output-names = "pd_gpu";
 193                                 rockchip,pd-id = <CLK_PD_GPU>;
 194                                 #clock-cells = <0>;
 195                         };
 196
 197                         pd_video: pd_video {
 198                                 compatible = "rockchip,rk-pd-clock";
 199                                 clock-output-names = "pd_video";
 200                                 rockchip,pd-id = <CLK_PD_VIDEO>;
 201                                 #clock-cells = <0>;
 202                         };
 203
 204                         pd_vio: pd_vio {
 205                                 compatible = "rockchip,rk-pd-clock";
 206                                 clock-output-names = "pd_vio";
 207                                 rockchip,pd-id = <CLK_PD_VIO>;
 208                                 #clock-cells = <0>;
 209                         };
 210
 211                         pd_vop: pd_vop {
 212                                 compatible = "rockchip,rk-pd-clock";
 213                                 clocks = <&pd_vio>;
 214                                 clock-output-names = "pd_vop";
 215                                 rockchip,pd-id = <CLK_PD_VIRT>;
 216                                 #clock-cells = <0>;
 217                         };
 218
 219                         pd_vip: pd_vip {
 220                                 compatible = "rockchip,rk-pd-clock";
 221                                 clocks = <&pd_vio>;
 222                                 clock-output-names = "pd_vip";
 223                                 rockchip,pd-id = <CLK_PD_VIRT>;
 224                                 #clock-cells = <0>;
 225                         };
 226
 227                         pd_iep: pd_iep {
 228                                 compatible = "rockchip,rk-pd-clock";
 229                                 clocks = <&pd_vio>;
 230                                 clock-output-names = "pd_iep";
 231                                 rockchip,pd-id = <CLK_PD_VIRT>;
 232                                 #clock-cells = <0>;
 233                         };
 234
 235                         pd_rga: pd_rga {
 236                                 compatible = "rockchip,rk-pd-clock";
 237                                 clocks = <&pd_vio>;
 238                                 clock-output-names = "pd_rga";
 239                                 rockchip,pd-id = <CLK_PD_VIRT>;
 240                                 #clock-cells = <0>;
 241                         };
 242
 243                         pd_ebc: pd_ebc {
 244                                 compatible = "rockchip,rk-pd-clock";
 245                                 clocks = <&pd_vio>;
 246                                 clock-output-names = "pd_ebc";
 247                                 rockchip,pd-id = <CLK_PD_VIRT>;
 248                                 #clock-cells = <0>;
 249                         };
 250
 251                         pd_mipidsi: pd_mipidsi {
 252                                 compatible = "rockchip,rk-pd-clock";
 253                                 clocks = <&pd_vio>;
 254                                 clock-output-names = "pd_mipidsi";
 255                                 rockchip,pd-id = <CLK_PD_VIRT>;
 256                                 #clock-cells = <0>;
 257                         };
 258
 259                         pd_hdmi: pd_hdmi {
 260                                 compatible = "rockchip,rk-pd-clock";
 261                                 clocks = <&pd_vio>;
 262                                 clock-output-names = "pd_hdmi";
 263                                 rockchip,pd-id = <CLK_PD_VIRT>;
 264                                 #clock-cells = <0>;
 265                         };
 266
 267                 };
 268
 269
 270                 clock_regs {
 271                         compatible = "rockchip,rk-clock-regs";
 272                         #address-cells = <1>;
 273                         #size-cells = <1>;
 274                         reg = <0x0000 0x01f0>;
 275                         ranges;
 276
 277                         /* PLL control regs */
 278                         pll_cons {
 279                                 compatible = "rockchip,rk-pll-cons";
 280                                 #address-cells = <1>;
 281                                 #size-cells = <1>;
 282                                 ranges ;
 283
 284                                 clk_apll: pll-clk@0000 {
 285                                         compatible = "rockchip,rk3188-pll-clk";
 286                                         reg = <0x0000 0x10>;
 287                                         mode-reg = <0x0040 0>;
 288                                         status-reg = <0x0004 10>;
 289                                         clocks = <&xin24m>;
 290                                         clock-output-names = "clk_apll";
 291                                         rockchip,pll-type = <CLK_PLL_3036_APLL>;
 292                                         #clock-cells = <0>;
 293                                 };
 294
 295                                 clk_dpll: pll-clk@0010 {
 296                                         compatible = "rockchip,rk3188-pll-clk";
 297                                         reg = <0x0010 0x10>;
 298                                         mode-reg = <0x0040 4>;
 299                                         status-reg = <0x0014 10>;
 300                                         clocks = <&xin24m>;
 301                                         clock-output-names = "clk_dpll";
 302                                         rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
 303                                         #clock-cells = <0>;
 304                                 };
 305
 306                                 clk_cpll: pll-clk@0020 {
 307                                         compatible = "rockchip,rk3188-pll-clk";
 308                                         reg = <0x0020 0x10>;
 309                                         mode-reg = <0x0040 8>;
 310                                         status-reg = <0x0024 10>;
 311                                         clocks = <&xin24m>;
 312                                         clock-output-names = "clk_cpll";
 313                                         rockchip,pll-type = <CLK_PLL_312XPLUS>;
 314                                         #clock-cells = <0>;
 315                                         #clock-init-cells = <1>;
 316                                 };
 317
 318                                 clk_gpll: pll-clk@0030 {
 319                                         compatible = "rockchip,rk3188-pll-clk";
 320                                         reg = <0x0030 0x10>;
 321                                         mode-reg = <0x0040 12>;
 322                                         status-reg = <0x0034 10>;
 323                                         clocks = <&xin24m>;
 324                                         clock-output-names = "clk_gpll";
 325                                         rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
 326                                         #clock-cells = <0>;
 327                                         #clock-init-cells = <1>;
 328                                 };
 329
 330                         };
 331
 332                         /* Select control regs */
 333                         clk_sel_cons {
 334                                 compatible = "rockchip,rk-sel-cons";
 335                                 #address-cells = <1>;
 336                                 #size-cells = <1>;
 337                                 ranges;
 338
 339                                 clk_sel_con0: sel-con@0044 {
 340                                         compatible = "rockchip,rk3188-selcon";
 341                                         reg = <0x0044 0x4>;
 342                                         #address-cells = <1>;
 343                                         #size-cells = <1>;
 344
 345                                         clk_core_div: clk_core_div {
 346                                                 compatible = "rockchip,rk3188-div-con";
 347                                                 rockchip,bits = <0 5>;
 348                                                 clocks = <&clk_core>;
 349                                                 clock-output-names = "clk_core";
 350                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 351                                                 #clock-cells = <0>;
 352                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 353                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 354                                                                         CLK_SET_RATE_NO_REPARENT)>;
 355                                         };
 356
 357                                         /* reg[6:5]: reserved */
 358
 359                                         clk_core: clk_core_mux {
 360                                                 compatible = "rockchip,rk3188-mux-con";
 361                                                 rockchip,bits = <7 1>;
 362                                                 clocks = <&clk_apll>, <&clk_gpll_div2>;
 363                                                 clock-output-names = "clk_core";
 364                                                 #clock-cells = <0>;
 365                                                 #clock-init-cells = <1>;
 366                                         };
 367
 368                                         aclk_cpu_div: aclk_cpu_div {
 369                                                 compatible = "rockchip,rk3188-div-con";
 370                                                 rockchip,bits = <8 5>;
 371                                                 clocks = <&aclk_cpu>;
 372                                                 clock-output-names = "aclk_cpu";
 373                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 374                                                 #clock-cells = <0>;
 375                                                 rockchip,clkops-idx =
 376                                                         <CLKOPS_RATE_MUX_DIV>;
 377                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 378                                         };
 379
 380                                         aclk_cpu: aclk_cpu_mux {
 381                                                 compatible = "rockchip,rk3188-mux-con";
 382                                                 rockchip,bits = <13 2>;
 383                                                 clocks = <&clk_apll>, <&clk_gpll>,<&clk_gpll_div2>,<&clk_gpll_div3>;
 384                                                 clock-output-names = "aclk_cpu";
 385                                                 #clock-cells = <0>;
 386                                                 #clock-init-cells = <1>;
 387                                         };
 388
 389                                         /* reg[15]: reserved */
 390
 391                                 };
 392
 393                                 clk_sel_con1: sel-con@0048 {
 394                                         compatible = "rockchip,rk3188-selcon";
 395                                         reg = <0x0048 0x4>;
 396                                         #address-cells = <1>;
 397                                         #size-cells = <1>;
 398
 399                                         pclk_dbg_div:  pclk_dbg_div {
 400                                                 compatible = "rockchip,rk3188-div-con";
 401                                                 rockchip,bits = <0 4>;
 402                                                 clocks = <&clk_core>;
 403                                                 clock-output-names = "pclk_dbg";
 404                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 405                                                 #clock-cells = <0>;
 406                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 407                                         };
 408
 409                                         aclk_core_pre: aclk_core_pre_div {
 410                                                 compatible = "rockchip,rk3188-div-con";
 411                                                 rockchip,bits = <4 3>;
 412                                                 clocks = <&clk_core>;
 413                                                 clock-output-names = "aclk_core_pre";
 414                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 415                                                 #clock-cells = <0>;
 416                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 417                                         };
 418
 419                                         /* reg[7]: reserved */
 420
 421                                         hclk_cpu_pre: hclk_cpu_pre_div {
 422                                                 compatible = "rockchip,rk3188-div-con";
 423                                                 rockchip,bits = <8 2>;
 424                                                 clocks = <&aclk_cpu>;
 425                                                 clock-output-names = "hclk_cpu_pre";
 426                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 427                                                 #clock-cells = <0>;
 428                                                 #clock-init-cells = <1>;
 429                                         };
 430
 431                                         /* reg[11:10]: reserved */
 432
 433                                         pclk_cpu_pre: pclk_cpu_pre_div {
 434                                                 compatible = "rockchip,rk3188-div-con";
 435                                                 rockchip,bits = <12 3>;
 436                                                 clocks = <&aclk_cpu>;
 437                                                 clock-output-names = "pclk_cpu_pre";
 438                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 439                                                 #clock-cells = <0>;
 440                                                 #clock-init-cells = <1>;
 441                                         };
 442
 443                                         /* reg[15]: reserved */
 444                                 };
 445
 446                                 clk_sel_con2: sel-con@004c {
 447                                         compatible = "rockchip,rk3188-selcon";
 448                                         reg = <0x004c 0x4>;
 449                                         #address-cells = <1>;
 450                                         #size-cells = <1>;
 451
 452                                         clk_pvtm_div: clk_pvtm_div {
 453                                                 compatible = "rockchip,rk3188-mux-con";
 454                                                 rockchip,bits = <0 7>;
 455                                                 clocks = <&g_clk_pvtm_func>;
 456                                                 clock-output-names = "clk_pvtm";
 457                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 458                                                 #clock-cells = <0>;
 459                                                 #clock-init-cells = <1>;
 460                                         };
 461
 462                                         /* reg[7]: reserved */
 463
 464                                         clk_nandc_div: clk_nandc_div {
 465                                                 compatible = "rockchip,rk3188-div-con";
 466                                                 rockchip,bits = <8 5>;
 467                                                 clocks = <&clk_nandc>;
 468                                                 clock-output-names = "clk_nandc";
 469                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 470                                                 #clock-cells = <0>;
 471                                                 rockchip,clkops-idx =
 472                                                         <CLKOPS_RATE_MUX_DIV>;
 473                                         };
 474
 475                                         /* reg[13]: reserved */
 476
 477                                         clk_nandc: clk_nandc_mux {
 478                                                 compatible = "rockchip,rk3188-mux-con";
 479                                                 rockchip,bits = <14 2>;
 480                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
 481                                                 clock-output-names = "clk_nandc";
 482                                                 #clock-cells = <0>;
 483                                                 #clock-init-cells = <1>;
 484                                         };
 485
 486                                 };
 487
 488                                 clk_sel_con3: sel-con@0050 {
 489                                         compatible = "rockchip,rk3188-selcon";
 490                                         reg = <0x0050 0x4>;
 491                                         #address-cells = <1>;
 492                                         #size-cells = <1>;
 493
 494                                         clk_i2s_2ch_pll_div: clk_i2s_2ch_pll_div {
 495                                                 compatible = "rockchip,rk3188-div-con";
 496                                                 rockchip,bits = <0 7>;
 497                                                 clocks = <&clk_i2s_2ch_pll>;
 498                                                 clock-output-names = "clk_i2s_2ch_pll";
 499                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 500                                                 #clock-cells = <0>;
 501                                                 rockchip,clkops-idx =
 502                                                         <CLKOPS_RATE_MUX_DIV>;
 503                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 504                                         };
 505
 506                                         /* reg[7]: reserved */
 507
 508                                         clk_i2s_2ch: clk_i2s_2ch_mux {
 509                                                 compatible = "rockchip,rk3188-mux-con";
 510                                                 rockchip,bits = <8 2>;
 511                                                 clocks = <&clk_i2s_2ch_pll_div>, <&i2s_2ch_frac>, <&i2s_clkin>, <&xin12m>;
 512                                                 clock-output-names = "clk_i2s_2ch";
 513                                                 #clock-cells = <0>;
 514                                                 rockchip,clkops-idx =
 515                                                         <CLKOPS_RATE_RK3288_I2S>;
 516                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 517                                         };
 518
 519                                         /* reg[11:10]: reserved */
 520
 521                                         clk_i2s_2ch_out: clk_i2s_2ch_out_mux {
 522                                                 compatible = "rockchip,rk3188-mux-con";
 523                                                 rockchip,bits = <12 1>;
 524                                                 clocks = <&clk_i2s_2ch>, <&xin12m>;
 525                                                 clock-output-names = "i2s_clkout";
 526                                                 #clock-cells = <0>;
 527                                         };
 528
 529                                         /* reg[13]: reserved */
 530
 531                                         clk_i2s_2ch_pll: i2s_2ch_pll_mux {
 532                                                 compatible = "rockchip,rk3188-mux-con";
 533                                                 rockchip,bits = <14 2>;
 534                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
 535                                                 clock-output-names = "clk_i2s_2ch_pll";
 536                                                 #clock-cells = <0>;
 537                                                 #clock-init-cells = <1>;
 538                                         };
 539
 540                                 };
 541
 542                                 clk_sel_con4: sel-con@0054 {
 543                                         compatible = "rockchip,rk3188-selcon";
 544                                         reg = <0x0054 0x4>;
 545                                         #address-cells = <1>;
 546                                         #size-cells = <1>;
 547
 548                                         clk_tsp_div: clk_tsp_div {
 549                                                 compatible = "rockchip,rk3188-div-con";
 550                                                 rockchip,bits = <0 5>;
 551                                                 clocks = <&clk_tsp>;
 552                                                 clock-output-names = "clk_tsp";
 553                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 554                                                 #clock-cells = <0>;
 555                                                 rockchip,clkops-idx =
 556                                                         <CLKOPS_RATE_MUX_DIV>;
 557                                         };
 558
 559                                         /* reg[5]: reserved */
 560
 561                                         clk_tsp: clk_tsp_mux {
 562                                                 compatible = "rockchip,rk3188-mux-con";
 563                                                 rockchip,bits = <6 2>;
 564                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
 565                                                 clock-output-names = "clk_tsp";
 566                                                 #clock-cells = <0>;
 567                                                 #clock-init-cells = <1>;
 568                                         };
 569
 570                                         clk_24m_div: clk_24m_div {
 571                                                 compatible = "rockchip,rk3188-div-con";
 572                                                 rockchip,bits = <8 5>;
 573                                                 clocks = <&xin24m>;
 574                                                 clock-output-names = "clk_24m";
 575                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 576                                                 #clock-cells = <0>;
 577                                         };
 578
 579                                         /* reg[15:13]: reserved */
 580
 581                                 };
 582
 583
 584                                 clk_sel_con5: sel-con@0058 {
 585                                         compatible = "rockchip,rk3188-selcon";
 586                                         reg = <0x0058 0x4>;
 587                                         #address-cells = <1>;
 588                                         #size-cells = <1>;
 589
 590                                         clk_mac_pll_div: clk_mac_pll_div {
 591                                                 compatible = "rockchip,rk3188-div-con";
 592                                                 rockchip,bits = <0 5>;
 593                                                 clocks = <&clk_mac_pll>;
 594                                                 clock-output-names = "clk_mac_pll";
 595                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 596                                                 #clock-cells = <0>;
 597                                                 rockchip,clkops-idx =
 598                                                         <CLKOPS_RATE_MUX_DIV>;
 599                                                 #clock-init-cells = <1>;
 600                                         };
 601
 602                                         /* reg[5]: reserved */
 603
 604                                         clk_mac_pll: clk_mac_pll_mux {
 605                                                 compatible = "rockchip,rk3188-mux-con";
 606                                                 rockchip,bits = <6 2>;
 607                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
 608                                                 clock-output-names = "clk_mac_pll";
 609                                                 #clock-cells = <0>;
 610                                                 #clock-init-cells = <1>;
 611                                         };
 612
 613                                         /* reg[14:8]: reserved */
 614
 615                                         clk_mac_ref: clk_mac_ref_mux {
 616                                                 compatible = "rockchip,rk3188-mux-con";
 617                                                 rockchip,bits = <15 1>;
 618                                                 clocks = <&clk_mac_pll_div>, <&gmac_clkin>;
 619                                                 clock-output-names = "clk_mac_ref";
 620                                                 #clock-cells = <0>;
 621                                                 rockchip,clkops-idx =
 622                                                         <CLKOPS_RATE_MAC_REF>;
 623                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 624                                                 #clock-init-cells = <1>;
 625                                         };
 626
 627                                 };
 628
 629
 630                                 clk_sel_con6: sel-con@005c {
 631                                         compatible = "rockchip,rk3188-selcon";
 632                                         reg = <0x005c 0x4>;
 633                                         #address-cells = <1>;
 634                                         #size-cells = <1>;
 635
 636                                         spdif_div: spdif_div {
 637                                                 compatible = "rockchip,rk3188-div-con";
 638                                                 rockchip,bits = <0 7>;
 639                                                 clocks = <&clk_spdif_pll>;
 640                                                 clock-output-names = "clk_spdif_pll";
 641                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 642                                                 #clock-cells = <0>;
 643                                                 rockchip,clkops-idx =
 644                                                         <CLKOPS_RATE_MUX_DIV>;
 645                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 646                                         };
 647
 648                                         /* reg[7]: reserved */
 649
 650                                         clk_spdif: spdif_mux {
 651                                                 compatible = "rockchip,rk3188-mux-con";
 652                                                 rockchip,bits = <8 2>;
 653                                                 clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>;
 654                                                 clock-output-names = "clk_spdif";
 655                                                 #clock-cells = <0>;
 656                                                 rockchip,clkops-idx =
 657                                                         <CLKOPS_RATE_RK3288_I2S>;
 658                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 659                                         };
 660
 661                                         /* reg[13:10]: reserved */
 662
 663                                         clk_spdif_pll: spdif_pll_mux {
 664                                                 compatible = "rockchip,rk3188-mux-con";
 665                                                 rockchip,bits = <14 2>;
 666                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
 667                                                 clock-output-names = "clk_spdif_pll";
 668                                                 #clock-cells = <0>;
 669                                                 #clock-init-cells = <1>;
 670                                         };
 671
 672                                 };
 673
 674                                 clk_sel_con7: sel-con@0060 {
 675                                         compatible = "rockchip,rk3188-selcon";
 676                                         reg = <0x0060 0x4>;
 677                                         #address-cells = <1>;
 678                                         #size-cells = <1>;
 679
 680                                         i2s_2ch_frac: i2s_2ch_frac {
 681                                                 compatible = "rockchip,rk3188-frac-con";
 682                                                 clocks = <&clk_i2s_2ch_pll>;
 683                                                 clock-output-names = "i2s_2ch_frac";
 684                                                 /* numerator    denominator */
 685                                                 rockchip,bits = <0 32>;
 686                                                 rockchip,clkops-idx =
 687                                                         <CLKOPS_RATE_FRAC>;
 688                                                 #clock-cells = <0>;
 689                                         };
 690                                 };
 691
 692                                 clk_sel_con8: sel-con@0064 {
 693                                         compatible = "rockchip,rk3188-selcon";
 694                                         reg = <0x0064 0x4>;
 695                                         #address-cells = <1>;
 696                                         #size-cells = <1>;
 697
 698                                         i2s_8ch_frac: i2s_8ch_frac {
 699                                                 compatible = "rockchip,rk3188-frac-con";
 700                                                 clocks = <&clk_i2s_8ch_pll>;
 701                                                 clock-output-names = "i2s_8ch_frac";
 702                                                 /* numerator    denominator */
 703                                                 rockchip,bits = <0 32>;
 704                                                 rockchip,clkops-idx =
 705                                                         <CLKOPS_RATE_FRAC>;
 706                                                 #clock-cells = <0>;
 707                                         };
 708                                 };
 709
 710                                 clk_sel_con9: sel-con@0068 {
 711                                         compatible = "rockchip,rk3188-selcon";
 712                                         reg = <0x0068 0x4>;
 713                                         #address-cells = <1>;
 714                                         #size-cells = <1>;
 715
 716                                         clk_i2s_8ch_pll_div: clk_i2s_8ch_pll_div {
 717                                                 compatible = "rockchip,rk3188-div-con";
 718                                                 rockchip,bits = <0 7>;
 719                                                 clocks = <&clk_i2s_8ch_pll>;
 720                                                 clock-output-names = "clk_i2s_8ch_pll";
 721                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 722                                                 #clock-cells = <0>;
 723                                                 rockchip,clkops-idx =
 724                                                         <CLKOPS_RATE_MUX_DIV>;
 725                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 726                                         };
 727
 728                                         /* reg[7]: reserved */
 729
 730                                         clk_i2s_8ch: clk_i2s_8ch_mux {
 731                                                 compatible = "rockchip,rk3188-mux-con";
 732                                                 rockchip,bits = <8 2>;
 733                                                 clocks = <&clk_i2s_8ch_pll_div>, <&i2s_8ch_frac>, <&i2s_clkin>, <&xin12m>;
 734                                                 clock-output-names = "clk_i2s_8ch";
 735                                                 #clock-cells = <0>;
 736                                                 rockchip,clkops-idx =
 737                                                         <CLKOPS_RATE_RK3288_I2S>;
 738                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 739                                         };
 740
 741                                         /* reg[13:10]: reserved */
 742
 743                                         clk_i2s_8ch_pll: i2s_8ch_pll_mux {
 744                                                 compatible = "rockchip,rk3188-mux-con";
 745                                                 rockchip,bits = <14 2>;
 746                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
 747                                                 clock-output-names = "clk_i2s_8ch_pll";
 748                                                 #clock-cells = <0>;
 749                                                 #clock-init-cells = <1>;
 750                                         };
 751
 752                                 };
 753
 754                                 clk_sel_con10: sel-con@006c {
 755                                         compatible = "rockchip,rk3188-selcon";
 756                                         reg = <0x006c 0x4>;
 757                                         #address-cells = <1>;
 758                                         #size-cells = <1>;
 759
 760                                         aclk_peri_div: aclk_peri_div {
 761                                                 compatible = "rockchip,rk3188-div-con";
 762                                                 rockchip,bits = <0 5>;
 763                                                 clocks = <&aclk_peri>;
 764                                                 clock-output-names = "aclk_peri";
 765                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 766                                                 #clock-cells = <0>;
 767                                                 rockchip,clkops-idx =
 768                                                         <CLKOPS_RATE_MUX_DIV>;
 769                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 770                                         };
 771
 772                                         /* reg[7:5]: reserved */
 773
 774                                         hclk_peri_pre: hclk_peri_pre_div {
 775                                                 compatible = "rockchip,rk3188-div-con";
 776                                                 rockchip,bits = <8 2>;
 777                                                 clocks = <&aclk_peri>;
 778                                                 clock-output-names = "hclk_peri_pre";
 779                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 780                                                 rockchip,div-relations =
 781                                                                 <0x0 1
 782                                                                  0x1 2
 783                                                                  0x2 4>;
 784                                                 #clock-cells = <0>;
 785                                                 #clock-init-cells = <1>;
 786                                         };
 787
 788                                         /* reg[11:10]: reserved */
 789
 790                                         pclk_peri_pre: pclk_peri_div {
 791                                                 compatible = "rockchip,rk3188-div-con";
 792                                                 rockchip,bits = <12 2>;
 793                                                 clocks = <&aclk_peri>;
 794                                                 clock-output-names = "pclk_peri_pre";
 795                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 796                                                 rockchip,div-relations =
 797                                                                 <0x0 1
 798                                                                  0x1 2
 799                                                                  0x2 4
 800                                                                  0x3 8>;
 801                                                 #clock-cells = <0>;
 802                                                 #clock-init-cells = <1>;
 803                                         };
 804
 805                                         aclk_peri: aclk_peri_mux {
 806                                                 compatible = "rockchip,rk3188-mux-con";
 807                                                 rockchip,bits = <14 2>;
 808                                                 clocks = <&clk_gpll>,<&clk_cpll>,<&clk_gpll_div2>,<&clk_gpll_div3>;
 809                                                 clock-output-names = "aclk_peri";
 810                                                 #clock-cells = <0>;
 811                                                 #clock-init-cells = <1>;
 812                                         };
 813                                 };
 814
 815                                 clk_sel_con11: sel-con@0070 {
 816                                         compatible = "rockchip,rk3188-selcon";
 817                                         reg = <0x0070 0x4>;
 818                                         #address-cells = <1>;
 819                                         #size-cells = <1>;
 820
 821                                         clk_sdmmc0_div: clk_sdmmc0_div {
 822                                                 compatible = "rockchip,rk3188-div-con";
 823                                                 rockchip,bits = <0 6>;
 824                                                 clocks = <&clk_sdmmc0>;
 825                                                 clock-output-names = "clk_sdmmc0";
 826                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 827                                                 #clock-cells = <0>;
 828                                                 rockchip,clkops-idx =
 829                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 830                                         };
 831
 832                                         clk_sdmmc0: clk_sdmmc0_mux {
 833                                                 compatible = "rockchip,rk3188-mux-con";
 834                                                 rockchip,bits = <6 2>;
 835                                                 clocks = <&clk_cpll>,<&clk_gpll>,<&clk_gpll_div2>,<&xin24m>;
 836                                                 clock-output-names = "clk_sdmmc0";
 837                                                 #clock-cells = <0>;
 838                                                 #clock-init-cells = <1>;
 839                                         };
 840
 841                                         clk_sfc_div: clk_sfc_div {
 842                                                 compatible = "rockchip,rk3188-div-con";
 843                                                 rockchip,bits = <8 5>;
 844                                                 clocks = <&clk_sfc>;
 845                                                 clock-output-names = "clk_sfc";
 846                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 847                                                 #clock-cells = <0>;
 848                                                 rockchip,clkops-idx =
 849                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 850                                         };
 851
 852                                         /* reg[13]: reserved */
 853
 854                                         clk_sfc: clk_sfc_mux {
 855                                                 compatible = "rockchip,rk3188-mux-con";
 856                                                 rockchip,bits = <14 2>;
 857                                                 clocks = <&clk_cpll>,<&clk_gpll>,<&clk_gpll_div2>,<&xin24m>;
 858                                                 clock-output-names = "clk_sfc";
 859                                                 #clock-cells = <0>;
 860                                                 #clock-init-cells = <1>;
 861                                         };
 862
 863                                 };
 864
 865                                 clk_sel_con12: sel-con@0074 {
 866                                         compatible = "rockchip,rk3188-selcon";
 867                                         reg = <0x0074 0x4>;
 868                                         #address-cells = <1>;
 869                                         #size-cells = <1>;
 870
 871                                         clk_sdio_div: clk_sdio_div {
 872                                                 compatible = "rockchip,rk3188-div-con";
 873                                                 rockchip,bits = <0 6>;
 874                                                 clocks = <&clk_sdio>;
 875                                                 clock-output-names = "clk_sdio";
 876                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 877                                                 #clock-cells = <0>;
 878                                                 rockchip,clkops-idx =
 879                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 880                                         };
 881
 882                                         clk_sdio: clk_sdio_mux {
 883                                                 compatible = "rockchip,rk3188-mux-con";
 884                                                 rockchip,bits = <6 2>;
 885                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&xin24m>;
 886                                                 clock-output-names = "clk_sdio";
 887                                                 #clock-cells = <0>;
 888                                                 #clock-init-cells = <1>;
 889                                         };
 890
 891                                         clk_emmc_div: clk_emmc_div {
 892                                                 compatible = "rockchip,rk3188-div-con";
 893                                                 rockchip,bits = <8 6>;
 894                                                 clocks = <&clk_emmc>;
 895                                                 clock-output-names = "clk_emmc";
 896                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 897                                                 #clock-cells = <0>;
 898                                                 rockchip,clkops-idx =
 899                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 900                                         };
 901
 902                                         clk_emmc: clk_emmc_mux {
 903                                                 compatible = "rockchip,rk3188-mux-con";
 904                                                 rockchip,bits = <14 2>;
 905                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&xin24m>;
 906                                                 clock-output-names = "clk_emmc";
 907                                                 #clock-cells = <0>;
 908                                                 #clock-init-cells = <1>;
 909                                         };
 910
 911                                 };
 912
 913                                 clk_sel_con13: sel-con@0078 {
 914                                         compatible = "rockchip,rk3188-selcon";
 915                                         reg = <0x0078 0x4>;
 916                                         #address-cells = <1>;
 917                                         #size-cells = <1>;
 918
 919                                         clk_uart0_pll_div: clk_uart0_pll_div {
 920                                                 compatible = "rockchip,rk3188-div-con";
 921                                                 rockchip,bits = <0 7>;
 922                                                 clocks = <&clk_uart0_pll>;
 923                                                 clock-output-names = "clk_uart0_pll";
 924                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 925                                                 #clock-cells = <0>;
 926                                         };
 927
 928                                         /* reg[7]: reserved */
 929
 930                                         clk_uart0: clk_uart0_mux {
 931                                                 compatible = "rockchip,rk3188-mux-con";
 932                                                 rockchip,bits = <8 2>;
 933                                                 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>;
 934                                                 clock-output-names = "clk_uart0";
 935                                                 #clock-cells = <0>;
 936                                                 rockchip,clkops-idx =
 937                                                         <CLKOPS_RATE_RK3288_I2S>;
 938                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 939                                         };
 940
 941                                         /* reg[11:10]: reserved */
 942
 943                                         clk_uart0_pll: clk_uart0_pll_mux {
 944                                                 compatible = "rockchip,rk3188-mux-con";
 945                                                 rockchip,bits = <12 2>;
 946                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
 947                                                 clock-output-names = "clk_uart0_pll";
 948                                                 #clock-cells = <0>;
 949                                                 #clock-init-cells = <1>;
 950                                         };
 951
 952                                         clk_uart2_pll: clk_uart2_pll_mux {
 953                                                 compatible = "rockchip,rk3188-mux-con";
 954                                                 rockchip,bits = <14 2>;
 955                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
 956                                                 clock-output-names = "clk_uart2_pll";
 957                                                 #clock-cells = <0>;
 958                                                 #clock-init-cells = <1>;
 959                                         };
 960
 961                                 };
 962
 963                                 clk_sel_con14: sel-con@007c {
 964                                         compatible = "rockchip,rk3188-selcon";
 965                                         reg = <0x007c 0x4>;
 966                                         #address-cells = <1>;
 967                                         #size-cells = <1>;
 968
 969                                         clk_uart1_div: clk_uart1_div {
 970                                                 compatible = "rockchip,rk3188-div-con";
 971                                                 rockchip,bits = <0 7>;
 972                                                 clocks = <&clk_uart2_pll>;
 973                                                 clock-output-names = "clk_uart1_div";
 974                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 975                                                 #clock-cells = <0>;
 976                                         };
 977
 978                                         /* reg[7]: reserved */
 979
 980                                         clk_uart1: clk_uart1_mux {
 981                                                 compatible = "rockchip,rk3188-mux-con";
 982                                                 rockchip,bits = <8 2>;
 983                                                 clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>;
 984                                                 clock-output-names = "clk_uart1";
 985                                                 #clock-cells = <0>;
 986                                                 rockchip,clkops-idx =
 987                                                         <CLKOPS_RATE_RK3288_I2S>;
 988                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 989                                         };
 990
 991                                         /* reg[15:10]: reserved */
 992                                 };
 993
 994                                 clk_sel_con15: sel-con@0080 {
 995                                         compatible = "rockchip,rk3188-selcon";
 996                                         reg = <0x0080 0x4>;
 997                                         #address-cells = <1>;
 998                                         #size-cells = <1>;
 999
1000                                         clk_uart2_div: clk_uart2_div {
1001                                                 compatible = "rockchip,rk3188-div-con";
1002                                                 rockchip,bits = <0 7>;
1003                                                 clocks = <&clk_uart2_pll>;
1004                                                 clock-output-names = "clk_uart2_div";
1005                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1006                                                 #clock-cells = <0>;
1007                                         };
1008
1009                                         /* reg[7]: reserved */
1010
1011                                         clk_uart2: clk_uart2_mux {
1012                                                 compatible = "rockchip,rk3188-mux-con";
1013                                                 rockchip,bits = <8 2>;
1014                                                 clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>;
1015                                                 clock-output-names = "clk_uart2";
1016                                                 #clock-cells = <0>;
1017                                                 rockchip,clkops-idx =
1018                                                         <CLKOPS_RATE_RK3288_I2S>;
1019                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1020                                         };
1021
1022                                         /* reg[15:10]: reserved */
1023                                 };
1024
1025                                 clk_sel_con17: sel-con@0088 {
1026                                         compatible = "rockchip,rk3188-selcon";
1027                                         reg = <0x0088 0x4>;
1028                                         #address-cells = <1>;
1029                                         #size-cells = <1>;
1030
1031                                         uart0_frac: uart0_frac {
1032                                                 compatible = "rockchip,rk3188-frac-con";
1033                                                 clocks = <&clk_uart0_pll>;
1034                                                 clock-output-names = "uart0_frac";
1035                                                 /* numerator    denominator */
1036                                                 rockchip,bits = <0 32>;
1037                                                 rockchip,clkops-idx =
1038                                                         <CLKOPS_RATE_FRAC>;
1039                                                 #clock-cells = <0>;
1040                                         };
1041                                 };
1042
1043                                 clk_sel_con18: sel-con@008c {
1044                                         compatible = "rockchip,rk3188-selcon";
1045                                         reg = <0x008c 0x4>;
1046                                         #address-cells = <1>;
1047                                         #size-cells = <1>;
1048
1049                                         uart1_frac: uart1_frac {
1050                                                 compatible = "rockchip,rk3188-frac-con";
1051                                                 clocks = <&clk_uart1_div>;
1052                                                 clock-output-names = "uart1_frac";
1053                                                 /* numerator    denominator */
1054                                                 rockchip,bits = <0 32>;
1055                                                 rockchip,clkops-idx =
1056                                                         <CLKOPS_RATE_FRAC>;
1057                                                 #clock-cells = <0>;
1058                                         };
1059                                 };
1060
1061                                 clk_sel_con19: sel-con@0090 {
1062                                         compatible = "rockchip,rk3188-selcon";
1063                                         reg = <0x0090 0x4>;
1064                                         #address-cells = <1>;
1065                                         #size-cells = <1>;
1066
1067                                         uart2_frac: uart2_frac {
1068                                                 compatible = "rockchip,rk3188-frac-con";
1069                                                 clocks = <&clk_uart2_div>;
1070                                                 clock-output-names = "uart2_frac";
1071                                                 /* numerator    denominator */
1072                                                 rockchip,bits = <0 32>;
1073                                                 rockchip,clkops-idx =
1074                                                         <CLKOPS_RATE_FRAC>;
1075                                                 #clock-cells = <0>;
1076                                         };
1077
1078                                 };
1079
1080                                 clk_sel_con20: sel-con@0094 {
1081                                         compatible = "rockchip,rk3188-selcon";
1082                                         reg = <0x0094 0x4>;
1083                                         #address-cells = <1>;
1084                                         #size-cells = <1>;
1085
1086                                         spdif_frac: spdif_frac {
1087                                                 compatible = "rockchip,rk3188-frac-con";
1088                                                 clocks = <&spdif_div>;
1089                                                 clock-output-names = "spdif_frac";
1090                                                 /* numerator    denominator */
1091                                                 rockchip,bits = <0 32>;
1092                                                 rockchip,clkops-idx =
1093                                                         <CLKOPS_RATE_FRAC>;
1094                                                 #clock-cells = <0>;
1095                                         };
1096
1097                                 };
1098
1099                                 clk_sel_con23: sel-con@00a0 {
1100                                         compatible = "rockchip,rk3188-selcon";
1101                                         reg = <0x00a0 0x4>;
1102                                         #address-cells = <1>;
1103                                         #size-cells = <1>;
1104
1105                                         dclk_ebc: dclk_ebc_mux {
1106                                                 compatible = "rockchip,rk3188-mux-con";
1107                                                 rockchip,bits = <0 2>;
1108                                                 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
1109                                                 clock-output-names = "dclk_ebc";
1110                                                 #clock-cells = <0>;
1111                                                 #clock-init-cells = <1>;
1112                                         };
1113
1114                                         /* reg[7:2]: reserved */
1115
1116                                         dclk_ebc_div: dclk_ebc_div {
1117                                                 compatible = "rockchip,rk3188-div-con";
1118                                                 rockchip,bits = <8 8>;
1119                                                 clocks = <&dclk_ebc>;
1120                                                 clock-output-names = "dclk_ebc";
1121                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1122                                                 #clock-cells = <0>;
1123                                                 rockchip,clkops-idx =
1124                                                         <CLKOPS_RATE_MUX_DIV>;
1125                                         };
1126
1127                                 };
1128
1129                                 clk_sel_con24: sel-con@00a4 {
1130                                         compatible = "rockchip,rk3188-selcon";
1131                                         reg = <0x00a4 0x4>;
1132                                         #address-cells = <1>;
1133                                         #size-cells = <1>;
1134
1135                                         clk_crypto_div: clk_crypto_div {
1136                                                 compatible = "rockchip,rk3188-div-con";
1137                                                 rockchip,bits = <0 2>;
1138                                                 clocks = <&aclk_cpu>;
1139                                                 clock-output-names = "clk_crypto";
1140                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1141                                                 #clock-cells = <0>;
1142                                                 #clock-init-cells = <1>;
1143                                         };
1144
1145                                         /* reg[7:2]: reserved */
1146
1147                                         clk_saradc: clk_saradc_div {
1148                                                 compatible = "rockchip,rk3188-div-con";
1149                                                 rockchip,bits = <8 8>;
1150                                                 clocks = <&xin24m>;
1151                                                 clock-output-names = "clk_saradc";
1152                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1153                                                 #clock-cells = <0>;
1154                                                 #clock-init-cells = <1>;
1155                                         };
1156
1157                                 };
1158
1159                                 clk_sel_con25: sel-con@00a8 {
1160                                         compatible = "rockchip,rk3188-selcon";
1161                                         reg = <0x00a8 0x4>;
1162                                         #address-cells = <1>;
1163                                         #size-cells = <1>;
1164
1165                                         clk_spi0_div: clk_spi0_div {
1166                                                 compatible = "rockchip,rk3188-div-con";
1167                                                 rockchip,bits = <0 7>;
1168                                                 clocks = <&clk_spi0>;
1169                                                 clock-output-names = "clk_spi0";
1170                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1171                                                 #clock-cells = <0>;
1172                                                 rockchip,clkops-idx =
1173                                                         <CLKOPS_RATE_MUX_DIV>;
1174                                         };
1175
1176                                         /* reg[7]: reserved */
1177
1178                                         clk_spi0: clk_spi0_mux {
1179                                                 compatible = "rockchip,rk3188-mux-con";
1180                                                 rockchip,bits = <8 2>;
1181                                                 clocks = <&clk_cpll>, <&clk_gpll>,<&clk_gpll_div2>;
1182                                                 clock-output-names = "clk_spi0";
1183                                                 #clock-cells = <0>;
1184                                         };
1185
1186                                         /* reg[15:10]: reserved */
1187
1188                                 };
1189
1190                                 clk_sel_con26: sel-con@00ac {
1191                                         compatible = "rockchip,rk3188-selcon";
1192                                         reg = <0x00ac 0x4>;
1193                                         #address-cells = <1>;
1194                                         #size-cells = <1>;
1195
1196                                         ddr_div: ddr_div {
1197                                                 compatible = "rockchip,rk3188-div-con";
1198                                                 rockchip,bits = <0 2>;
1199                                                 clocks = <&clk_ddr>;
1200                                                 clock-output-names = "clk_ddr";
1201                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
1202                                                 rockchip,div-relations =
1203                                                                 <0x0 1
1204                                                                  0x1 2
1205                                                                  0x3 4>;
1206                                                 #clock-cells = <0>;
1207                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
1208                                                                         CLK_SET_RATE_NO_REPARENT)>;
1209                                                 rockchip,clkops-idx = <CLKOPS_RATE_DDR_DIV2>;
1210                                         };
1211
1212                                         /* reg[7:2]: reserved */
1213
1214                                         clk_ddr: ddr_clk_pll_mux {
1215                                                 compatible = "rockchip,rk3188-mux-con";
1216                                                 rockchip,bits = <8 1>;
1217                                                 clocks = <&clk_dpll>, <&dummy>;
1218                                                 clock-output-names = "clk_ddr";
1219                                                 #clock-cells = <0>;
1220                                         };
1221
1222                                         /* reg[15:9]: reserved */
1223                                 };
1224
1225                                 clk_sel_con27: sel-con@00b0 {
1226                                         compatible = "rockchip,rk3188-selcon";
1227                                         reg = <0x00b0 0x4>;
1228                                         #address-cells = <1>;
1229                                         #size-cells = <1>;
1230
1231                                         dclk_lcdc0: dclk_lcdc0_mux {
1232                                                 compatible = "rockchip,rk3188-mux-con";
1233                                                 rockchip,bits = <0 2>;
1234                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>;
1235                                                 clock-output-names = "dclk_lcdc0";
1236                                                 #clock-cells = <0>;
1237                                                 #clock-init-cells = <1>;
1238                                         };
1239
1240                                         /* reg[7:2]: reserved */
1241
1242                                         dclk_lcdc0_div: dclk_lcdc0_div {
1243                                                 compatible = "rockchip,rk3188-div-con";
1244                                                 rockchip,bits = <8 8>;
1245                                                 clocks = <&dclk_lcdc0>;
1246                                                 clock-output-names = "dclk_lcdc0";
1247                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1248                                                 #clock-cells = <0>;
1249                                                 rockchip,clkops-idx =
1250                                                         <CLKOPS_RATE_MUX_DIV>;
1251                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1252                                         };
1253                                 };
1254
1255                                 clk_sel_con28: sel-con@00b4 {
1256                                         compatible = "rockchip,rk3188-selcon";
1257                                         reg = <0x00b4 0x4>;
1258                                         #address-cells = <1>;
1259                                         #size-cells = <1>;
1260
1261                                         sclk_lcdc0: sclk_lcdc0_mux {
1262                                                 compatible = "rockchip,rk3188-mux-con";
1263                                                 rockchip,bits = <0 2>;
1264                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>;
1265                                                 clock-output-names = "sclk_lcdc0";
1266                                                 #clock-cells = <0>;
1267                                                 #clock-init-cells = <1>;
1268                                         };
1269
1270                                         /* reg[7:2]: reserved */
1271
1272                                         sclk_lcdc0_div: sclk_lcdc0_div {
1273                                                 compatible = "rockchip,rk3188-div-con";
1274                                                 rockchip,bits = <8 8>;
1275                                                 clocks = <&sclk_lcdc0>;
1276                                                 clock-output-names = "sclk_lcdc0";
1277                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1278                                                 #clock-cells = <0>;
1279                                                 rockchip,clkops-idx =
1280                                                         <CLKOPS_RATE_MUX_DIV>;
1281                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1282                                         };
1283                                 };
1284
1285                                 clk_sel_con29: sel-con@00b8 {
1286                                         compatible = "rockchip,rk3188-selcon";
1287                                         reg = <0x00b8 0x4>;
1288                                         #address-cells = <1>;
1289                                         #size-cells = <1>;
1290
1291                                         clk_cif_pll: clk_cif_pll_mux {
1292                                                 compatible = "rockchip,rk3188-mux-con";
1293                                                 rockchip,bits = <0 2>;
1294                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
1295                                                 clock-output-names = "clk_cif_pll";
1296                                                 #clock-cells = <0>;
1297                                                 #clock-init-cells = <1>;
1298                                         };
1299
1300                                         clk_cif_out_div: clk_cif_out_div {
1301                                                 compatible = "rockchip,rk3188-div-con";
1302                                                 rockchip,bits = <2 5>;
1303                                                 clocks = <&clk_cif_out>;
1304                                                 clock-output-names = "clk_cif_out";
1305                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1306                                                 #clock-cells = <0>;
1307                                                 rockchip,clkops-idx =
1308                                                         <CLKOPS_RATE_MUX_DIV>;
1309                                         };
1310
1311                                         clk_cif_out: clk_cif_out_mux {
1312                                                 compatible = "rockchip,rk3188-mux-con";
1313                                                 rockchip,bits = <7 1>;
1314                                                 clocks = <&clk_cif_pll>, <&xin24m>;
1315                                                 clock-output-names = "clk_cif_out";
1316                                                 #clock-cells = <0>;
1317                                                 #clock-init-cells = <1>;
1318                                         };
1319
1320                                         pclk_pmu_pre: pclk_pmu_pre_div {
1321                                                 compatible = "rockchip,rk3188-div-con";
1322                                                 rockchip,bits = <8 6>;
1323                                                 clocks = <&clk_cpll>;
1324                                                 clock-output-names = "pclk_pmu_pre";
1325                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1326                                                 #clock-cells = <0>;
1327                                                 #clock-init-cells = <1>;
1328                                         };
1329
1330                                         /* reg[15:14]: reserved */
1331                                 };
1332
1333                                 clk_sel_con30: sel-con@00bc {
1334                                         compatible = "rockchip,rk3188-selcon";
1335                                         reg = <0x00bc 0x4>;
1336                                         #address-cells = <1>;
1337                                         #size-cells = <1>;
1338
1339                                         clk_testout_div: clk_testout_div {
1340                                                 compatible = "rockchip,rk3188-div-con";
1341                                                 rockchip,bits = <0 5>;
1342                                                 clocks = <&dummy>;
1343                                                 clock-output-names = "clk_testout";
1344                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1345                                                 #clock-cells = <0>;
1346                                                 #clock-init-cells = <1>;
1347                                         };
1348
1349                                         /* reg[6:5]: reserved */
1350
1351                                         clk_cif0_in: clk_cif0_in_mux {
1352                                                 compatible = "rockchip,rk3188-mux-con";
1353                                                 rockchip,bits = <7 1>;
1354                                                 clocks = <&pclkin_cif>, <&pclkin_cif_inv>;
1355                                                 clock-output-names = "clk_cif0_in";
1356                                                 #clock-cells = <0>;
1357                                                 #clock-init-cells = <1>;
1358                                         };
1359
1360                                         hclk_vio_pre_div: hclk_vio_pre_div {
1361                                                 compatible = "rockchip,rk3188-div-con";
1362                                                 rockchip,bits = <8 5>;
1363                                                 clocks = <&hclk_vio_pre>;
1364                                                 clock-output-names = "hclk_vio_pre";
1365                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1366                                                 #clock-cells = <0>;
1367                                                 rockchip,clkops-idx =
1368                                                         <CLKOPS_RATE_MUX_DIV>;
1369                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1370                                         };
1371
1372                                         /* reg[13]: reserved */
1373
1374                                         hclk_vio_pre: hclk_vio_pre_mux {
1375                                                 compatible = "rockchip,rk3188-mux-con";
1376                                                 rockchip,bits = <14 2>;
1377                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
1378                                                 clock-output-names = "hclk_vio_pre";
1379                                                 #clock-cells = <0>;
1380                                                 #clock-init-cells = <1>;
1381                                         };
1382
1383                                 };
1384
1385                                 clk_sel_con31: sel-con@00c0 {
1386                                         compatible = "rockchip,rk3188-selcon";
1387                                         reg = <0x00c0 0x4>;
1388                                         #address-cells = <1>;
1389                                         #size-cells = <1>;
1390
1391                                         aclk_vio0_pre_div: aclk_vio0_pre_div {
1392                                                 compatible = "rockchip,rk3188-div-con";
1393                                                 rockchip,bits = <0 5>;
1394                                                 clocks = <&aclk_vio0_pre>;
1395                                                 clock-output-names = "aclk_vio0_pre";
1396                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1397                                                 #clock-cells = <0>;
1398                                                 rockchip,clkops-idx =
1399                                                         <CLKOPS_RATE_MUX_DIV>;
1400                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1401                                         };
1402
1403                                         aclk_vio0_pre: aclk_vio0_pre_mux {
1404                                                 compatible = "rockchip,rk3188-mux-con";
1405                                                 rockchip,bits = <5 3>;
1406                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1407                                                 clock-output-names = "aclk_vio0_pre";
1408                                                 #clock-cells = <0>;
1409                                                 #clock-init-cells = <1>;
1410                                         };
1411
1412                                         aclk_vio1_pre_div: aclk_vio1_pre_div {
1413                                                 compatible = "rockchip,rk3188-div-con";
1414                                                 rockchip,bits = <8 5>;
1415                                                 clocks = <&aclk_vio1_pre>;
1416                                                 clock-output-names = "aclk_vio1_pre";
1417                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1418                                                 #clock-cells = <0>;
1419                                                 rockchip,clkops-idx =
1420                                                         <CLKOPS_RATE_MUX_DIV>;
1421                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1422                                         };
1423
1424                                         aclk_vio1_pre: aclk_vio1_pre_mux {
1425                                                 compatible = "rockchip,rk3188-mux-con";
1426                                                 rockchip,bits = <13 3>;
1427                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1428                                                 clock-output-names = "aclk_vio1_pre";
1429                                                 #clock-cells = <0>;
1430                                                 #clock-init-cells = <1>;
1431                                         };
1432
1433                                 };
1434
1435                                 clk_sel_con32: sel-con@00c4 {
1436                                         compatible = "rockchip,rk3188-selcon";
1437                                         reg = <0x00c4 0x4>;
1438                                         #address-cells = <1>;
1439                                         #size-cells = <1>;
1440
1441                                         clk_vepu_div: clk_vepu_div {
1442                                                 compatible = "rockchip,rk3188-div-con";
1443                                                 rockchip,bits = <0 5>;
1444                                                 clocks = <&clk_vepu>;
1445                                                 clock-output-names = "clk_vepu";
1446                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1447                                                 #clock-cells = <0>;
1448                                                 rockchip,clkops-idx =
1449                                                         <CLKOPS_RATE_MUX_DIV>;
1450                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1451                                         };
1452
1453                                         clk_vepu: clk_vepu_mux {
1454                                                 compatible = "rockchip,rk3188-mux-con";
1455                                                 rockchip,bits = <5 3>;
1456                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1457                                                 clock-output-names = "clk_vepu";
1458                                                 #clock-cells = <0>;
1459                                                 #clock-init-cells = <1>;
1460                                         };
1461
1462                                         clk_vdpu_div: clk_vdpu_div {
1463                                                 compatible = "rockchip,rk3188-div-con";
1464                                                 rockchip,bits = <8 5>;
1465                                                 clocks = <&clk_vdpu>;
1466                                                 clock-output-names = "clk_vdpu";
1467                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1468                                                 #clock-cells = <0>;
1469                                                 rockchip,clkops-idx =
1470                                                         <CLKOPS_RATE_MUX_DIV>;
1471                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1472                                         };
1473
1474                                         clk_vdpu: clk_vdpu_mux {
1475                                                 compatible = "rockchip,rk3188-mux-con";
1476                                                 rockchip,bits = <13 3>;
1477                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1478                                                 clock-output-names = "clk_vdpu";
1479                                                 #clock-cells = <0>;
1480                                                 #clock-init-cells = <1>;
1481                                         };
1482
1483                                 };
1484
1485                                 clk_sel_con34: sel-con@00cc {
1486                                         compatible = "rockchip,rk3188-selcon";
1487                                         reg = <0x00cc 0x4>;
1488                                         #address-cells = <1>;
1489                                         #size-cells = <1>;
1490
1491                                         clk_gpu_div: clk_gpu_div {
1492                                                 compatible = "rockchip,rk3188-div-con";
1493                                                 rockchip,bits = <0 5>;
1494                                                 clocks = <&clk_gpu>;
1495                                                 clock-output-names = "clk_gpu";
1496                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1497                                                 #clock-cells = <0>;
1498                                                 rockchip,clkops-idx =
1499                                                         <CLKOPS_RATE_MUX_DIV>;
1500                                                 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
1501                                         };
1502
1503                                         clk_gpu: clk_gpu_mux {
1504                                                 compatible = "rockchip,rk3188-mux-con";
1505                                                 rockchip,bits = <5 3>;
1506                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1507                                                 clock-output-names = "clk_gpu";
1508                                                 #clock-cells = <0>;
1509                                                 #clock-init-cells = <1>;
1510                                         };
1511
1512                                         clk_hevc_core_div: clk_hevc_core_div {
1513                                                 compatible = "rockchip,rk3188-div-con";
1514                                                 rockchip,bits = <8 5>;
1515                                                 clocks = <&clk_hevc_core>;
1516                                                 clock-output-names = "clk_hevc_core";
1517                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1518                                                 #clock-cells = <0>;
1519                                                 rockchip,clkops-idx =
1520                                                         <CLKOPS_RATE_MUX_DIV>;
1521                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1522                                         };
1523
1524                                         clk_hevc_core: clk_hevc_core_mux {
1525                                                 compatible = "rockchip,rk3188-mux-con";
1526                                                 rockchip,bits = <13 3>;
1527                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1528                                                 clock-output-names = "clk_hevc_core";
1529                                                 #clock-cells = <0>;
1530                                                 #clock-init-cells = <1>;
1531                                         };
1532
1533                                 };
1534
1535                         };
1536
1537
1538                         /* Gate control regs */
1539                         clk_gate_cons {
1540                                 compatible = "rockchip,rk-gate-cons";
1541                                 #address-cells = <1>;
1542                                 #size-cells = <1>;
1543                                 ranges ;
1544
1545                                 clk_gates0: gate-clk@00d0{
1546                                         compatible = "rockchip,rk3188-gate-clk";
1547                                         reg = <0x00d0 0x4>;
1548                                         clocks =
1549                                                 <&clk_core>,            <&dummy>,
1550                                                 <&dummy>,       <&aclk_cpu>,
1551
1552                                                 <&aclk_cpu>,    <&aclk_cpu>,
1553                                                 <&dummy>,               <&clk_core>,
1554
1555                                                 <&dummy>,       <&clk_i2s_2ch_pll>,
1556                                                 <&i2s_2ch_frac>,        <&hclk_vio_pre>,
1557
1558                                                 <&aclk_cpu>,            <&clk_i2s_2ch_out>,
1559                                                 <&clk_i2s_2ch>,         <&dummy>;
1560
1561                                         clock-output-names =
1562                                                 "pclk_dbg",                     "aclk_cpu",      /*clk_cpu_cpll*/
1563                                                 "reserved",             "aclk_cpu_pre",
1564
1565                                                 "hclk_cpu_pre",         "pclk_cpu_pre",
1566                                                 "clk_core",             "aclk_core_pre",
1567
1568                                                 "reserved",             "clk_i2s_2ch_pll",
1569                                                 "i2s_2ch_frac",         "hclk_vio_pre",
1570
1571                                                 "clk_crypto",           "clk_i2s_2ch_out",
1572                                                 "clk_i2s_2ch",          "clk_testout";
1573                                         rockchip,suspend-clkgating-setting=<0x11ff 0x0>;
1574
1575                                         #clock-cells = <1>;
1576                                 };
1577
1578                                 clk_gates1: gate-clk@00d4{
1579                                         compatible = "rockchip,rk3188-gate-clk";
1580                                         reg = <0x00d4 0x4>;
1581                                         clocks =
1582                                                 <&clk_cpll>,            <&dummy>,
1583                                                 <&dummy>,               <&jtag_tck>,
1584
1585                                                 <&aclk_vio1_pre>,               <&xin12m>,
1586                                                 <&xin12m>,              <&clk_mac_pll>,
1587
1588                                                 <&clk_uart0_pll>,               <&uart0_frac>,
1589                                                 <&clk_uart1_div>,               <&uart1_frac>,
1590
1591                                                 <&clk_uart2_div>,               <&uart2_frac>,
1592                                                 <&clk_tsp>,             <&dummy>;
1593
1594                                         clock-output-names =
1595                                                 "pclk_pmu_pre",         "reserved",
1596                                                 "reserved",             "clk_jtag",
1597
1598                                                 "aclk_vio1_pre",                "clk_otgphy0",
1599                                                 "clk_otgphy1",                  "clk_mac_pll",
1600
1601                                                 "clk_uart0_pll",        "uart0_frac",
1602                                                 "clk_uart1_div",        "uart1_frac",
1603
1604                                                 "clk_uart2_div",        "uart2_frac",
1605                                                 "clk_tsp",      "reserved";
1606
1607                                          rockchip,suspend-clkgating-setting=<0x000f 0x0>;
1608                                         #clock-cells = <1>;
1609                                 };
1610
1611                                 clk_gates2: gate-clk@00d8 {
1612                                         compatible = "rockchip,rk3188-gate-clk";
1613                                         reg = <0x00d8 0x4>;
1614                                         clocks =
1615                                                 <&aclk_peri>,           <&aclk_peri>,
1616                                                 <&aclk_peri>,           <&aclk_peri>,
1617
1618                                                 <&clk_mac_ref>,         <&clk_mac_ref>,
1619                                                 <&clk_mac_ref>,         <&clk_mac_ref>,
1620
1621                                                 <&clk_saradc>,          <&clk_spi0>,
1622                                                 <&clk_spdif_pll>,               <&clk_sdmmc0>,
1623
1624                                                 <&spdif_frac>,          <&clk_sdio>,
1625                                                 <&clk_emmc>,            <&xin24m>;
1626                                         clock-output-names =
1627                                                 "aclk_peri",            "aclk_peri_pre",
1628                                                 "hclk_peri_pre",                "pclk_peri_pre",
1629
1630                                                 "clk_mac_ref",          "clk_mac_refout",
1631                                                 "clk_mac_rx",           "clk_mac_tx",
1632
1633                                                 "clk_saradc",           "clk_spi0",
1634                                                 "clk_spdif_pll",                "clk_sdmmc0",
1635
1636                                                 "spdif_frac",           "clk_sdio",
1637                                                 "clk_emmc",             "clk_mipi_24m";
1638                                             rockchip,suspend-clkgating-setting=<0x000f 0x0>;
1639
1640                                         #clock-cells = <1>;
1641                                 };
1642
1643                                 clk_gates3: gate-clk@00dc {
1644                                         compatible = "rockchip,rk3188-gate-clk";
1645                                         reg = <0x00dc 0x4>;
1646                                         clocks =
1647                                                 <&aclk_vio0_pre>,               <&dclk_lcdc0>,
1648                                                 <&sclk_lcdc0>,          <&pclkin_cif>,
1649
1650                                                 <&dclk_ebc>,                    <&hclk_cpu_pre>,
1651                                                 <&hclk_peri_pre>,               <&clk_cif_pll>,
1652
1653                                                 <&pclk_cpu_pre>,                <&clk_vepu>,
1654                                                 <&clk_hevc_core>,               <&clk_vdpu>,
1655
1656                                                 <&hclk_vdpu>,           <&clk_gpu>,
1657                                                 <&aclk_peri>,           <&clk_sfc>;
1658
1659                                         clock-output-names =
1660                                                 "aclk_vio0_pre",                "dclk_lcdc0",
1661                                                 "sclk_lcdc0",           "pclkin_cif",
1662
1663                                                 "dclk_ebc",             "g_hclk_crypto",
1664                                                 "g_hclk_em_peri",               "clk_cif_pll",
1665
1666                                                 "g_pclk_hdmi",          "clk_vepu",
1667                                                 "clk_hevc_core",                "clk_vdpu",
1668
1669                                                 "hclk_vdpu",            "clk_gpu",
1670                                                 "g_hclk_gps",           "clk_sfc";
1671                                        rockchip,suspend-clkgating-setting=<0x0060 0x0000>;
1672
1673                                         #clock-cells = <1>;
1674                                 };
1675
1676                                 clk_gates4: gate-clk@00e0{
1677                                         compatible = "rockchip,rk3188-gate-clk";
1678                                         reg = <0x00e0 0x4>;
1679                                         clocks =
1680                                                 <&hclk_peri_pre>,               <&pclk_peri_pre>,
1681                                                 <&aclk_peri>,           <&aclk_peri>,
1682
1683                                                 <&clk_i2s_8ch_pll>,             <&i2s_8ch_frac>,
1684                                                 <&clk_i2s_8ch>,         <&dummy>,
1685
1686                                                 <&dummy>,               <&dummy>,
1687                                                 <&aclk_cpu>,            <&dummy>,
1688
1689                                                 <&aclk_cpu>,            <&dummy>,
1690                                                 <&dummy>,               <&dummy>;
1691
1692                                         clock-output-names =
1693                                                 "g_hp_axi_matrix",              "g_pp_axi_matrix",
1694                                                 "g_aclk_cpu_peri",              "g_ap_axi_matrix",
1695
1696                                                 "clk_i2s_8ch_pll",              "i2s_8ch_frac",
1697                                                 "clk_i2s_8ch",          "reserved",
1698
1699                                                 "reserved",             "reserved",
1700                                                 "g_aclk_strc_sys",              "reserved",
1701
1702                                                 /* Not use these ddr gates */
1703                                                 "g_aclk_intmem",                "reserved",
1704                                                 "reserved",             "reserved";
1705
1706                                         rockchip,suspend-clkgating-setting = <0xff8f 0x0000>;
1707                                         #clock-cells = <1>;
1708                                 };
1709
1710                                 clk_gates5: gate-clk@00e4 {
1711                                         compatible = "rockchip,rk3188-gate-clk";
1712                                         reg = <0x00e4 0x4>;
1713                                         clocks =
1714                                                 <&pclk_cpu_pre>,                <&aclk_peri>,
1715                                                 <&pclk_peri_pre>,               <&dummy>,
1716
1717                                                 <&pclk_cpu_pre>,                <&dummy>,
1718                                                 <&hclk_cpu_pre>,                <&pclk_cpu_pre>,
1719
1720                                                 <&dummy>,               <&hclk_peri_pre>,
1721                                                 <&hclk_peri_pre>,               <&hclk_peri_pre>,
1722
1723                                                 <&dummy>,               <&hclk_peri_pre>,
1724                                                 <&pclk_cpu_pre>,                <&dummy>;
1725
1726                                         clock-output-names =
1727                                                 "g_pclk_mipiphy",               "g_aclk_dmac",
1728                                                 "g_pclk_efuse", "reserved",
1729
1730                                                 "g_pclk_grf",           "reserved",
1731                                                 "g_hclk_rom",           "g_pclk_ddrupctl",
1732
1733                                                 "reserved",             "g_hclk_nandc",
1734                                                 "g_hclk_sdmmc0",                "g_hclk_sdio",
1735
1736                                                 "reserved",             "g_hclk_otg0",
1737                                                 "g_pclk_acodec",                "reserved";
1738
1739                                         rockchip,suspend-clkgating-setting = <0x00f0 0x0000>;
1740
1741                                         #clock-cells = <1>;
1742                                 };
1743
1744                                 clk_gates6: gate-clk@00e8 {
1745                                         compatible = "rockchip,rk3188-gate-clk";
1746                                         reg = <0x00e8 0x4>;
1747                                         clocks =
1748                                                 <&aclk_vio0_niu>,               <&hclk_vio_niu>,
1749                                                 <&dummy>,               <&dummy>,
1750
1751                                                 <&hclk_vio_niu>,                <&aclk_vio0_niu>,
1752                                                 <&dummy>,               <&dummy>,
1753
1754                                                 <&dummy>,               <&dummy>,
1755                                                 <&hclk_vio_niu>,                        <&aclk_vio0_niu>,
1756
1757                                                 <&hclk_vio_pre>,                <&aclk_vio0_pre>,
1758                                                 <&dummy>,               <&dummy>;
1759
1760                                         clock-output-names =
1761                                                 "g_aclk_lcdc0",         "g_hclk_lcdc0",
1762                                                 "reserved",             "reserved",
1763
1764                                                 "g_hclk_cif",           "g_aclk_cif",
1765                                                 "reserved",             "reserved",
1766
1767                                                 "reserved",             "reserved",
1768                                                 "g_hclk_rga",           "g_aclk_rga",
1769
1770                                                 "hclk_vio_niu",         "aclk_vio0_niu",
1771                                                 "reserved",             "reserved";
1772
1773                                         rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1774
1775                                         #clock-cells = <1>;
1776                                 };
1777
1778                                 clk_gates7: gate-clk@00ec {
1779                                         compatible = "rockchip,rk3188-gate-clk";
1780                                         reg = <0x00ec 0x4>;
1781                                         clocks =
1782                                                 <&hclk_peri_pre>,               <&hclk_peri_pre>,
1783                                                 <&hclk_peri_pre>,               <&hclk_peri_pre>,
1784
1785                                                 <&hclk_peri_pre>,               <&dummy>,
1786                                                 <&dummy>,               <&pclk_peri_pre>,
1787
1788                                                 <&dummy>,               <&dummy>,
1789                                                 <&pclk_peri_pre>,               <&dummy>,
1790
1791                                                 <&pclk_peri_pre>,               <&dummy>,
1792                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>;
1793
1794                                         clock-output-names =
1795                                                 "g_hclk_emmc",          "g_hclk_sfc",
1796                                                 "g_hclk_i2s_2ch",               "g_hclk_host",
1797
1798                                                 "g_hclk_i2s_8ch",               "reserved",
1799                                                 "reserved",             "g_pclk_timer",
1800
1801                                                 "reserved",             "reserved",
1802                                                 "g_pclk_pwm",           "reserved",
1803
1804                                                 "g_pclk_spi0",          "reserved",
1805                                                 "g_pclk_saradc",                "g_pclk_wdt";
1806
1807                                         rockchip,suspend-clkgating-setting = <0x8480 0x0000>;
1808
1809                                         #clock-cells = <1>;
1810                                 };
1811
1812                                 clk_gates8: gate-clk@00f0 {
1813                                         compatible = "rockchip,rk3188-gate-clk";
1814                                         reg = <0x00f0 0x4>;
1815                                         clocks =
1816                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1817                                                 <&pclk_peri_pre>,               <&dummy>,
1818
1819                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1820                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1821
1822                                                 <&dummy>,               <&pclk_peri_pre>,
1823                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1824
1825                                                 <&pclk_peri_pre>,               <&dummy>,
1826                                                 <&dummy>,               <&dummy>;
1827
1828                                         clock-output-names =
1829                                                 "g_pclk_uart0",         "g_pclk_uart1",
1830                                                 "g_pclk_uart2",         "reserved",
1831
1832                                                 "g_pclk_i2c0",          "g_pclk_i2c1",
1833                                                 "g_pclk_i2c2",          "g_pclk_i2c3",
1834
1835                                                 "reserved",             "g_pclk_gpio0",
1836                                                 "g_pclk_gpio1",         "g_pclk_gpio2",
1837
1838                                                 "g_pclk_gpio3",         "reserved",
1839                                                 "reserved",             "reserved";
1840
1841                                         rockchip,suspend-clkgating-setting=<0xff0f 0x0000>;
1842                                         #clock-cells = <1>;
1843                                 };
1844
1845                                 clk_gates9: gate-clk@00f4 {
1846                                         compatible = "rockchip,rk3188-gate-clk";
1847                                         reg = <0x00f4 0x4>;
1848                                         clocks =
1849                                                 <&dummy>,               <&dummy>,
1850                                                 <&pclk_pmu_pre>,                <&pclk_pmu_pre>,
1851
1852                                                 <&dummy>,               <&hclk_vio_niu>,
1853                                                 <&hclk_vio_niu>,                <&hclk_vio_niu>,
1854
1855                                                 <&aclk_vio1_niu>,               <&hclk_vio_niu>,
1856                                                 <&aclk_vio1_pre>,               <&dummy>,
1857
1858                                                 <&pclk_peri_pre>,               <&hclk_peri_pre>,
1859                                                 <&hclk_peri_pre>,               <&aclk_peri>;
1860
1861                                         clock-output-names =
1862                                                 "reserved",             "reserved",
1863                                                 "g_pclk_pmu",           "g_pclk_pmu_noc",
1864
1865                                                 "reserved",             "g_hclk_vio_h2p",
1866                                                 "g_pclk_mipi",          "g_hclk_iep",
1867
1868                                                 "g_aclk_iep",           "g_hclk_ebc",
1869                                                 "aclk_vio1_niu",                "reserved",
1870
1871                                                 "g_pclk_sim_card",              "g_hclk_usb_peri",
1872                                                 "g_hclk_pe_arbi",               "g_aclk_peri_niu";
1873
1874                                         rockchip,suspend-clkgating-setting=<0xf00f 0x0>;
1875
1876                                         #clock-cells = <1>;
1877                                 };
1878
1879                                 clk_gates10: gate-clk@00f8 {
1880                                         compatible = "rockchip,rk3188-gate-clk";
1881                                         reg = <0x00f8 0x4>;
1882                                         clocks =
1883                                                 <&xin24m>,              <&xin24m>,
1884                                                 <&xin24m>,              <&xin24m>,
1885
1886                                                 <&xin24m>,              <&xin24m>,
1887                                                 <&xin24m>,              <&xin24m>,
1888
1889                                                 <&xin24m>,              <&hclk_peri_pre>,
1890                                                 <&aclk_peri>,           <&pclk_peri_pre>,
1891
1892                                                 <&hclk_peri_pre>,               <&clk_tsp_in>,
1893                                                 <&hclk_peri_pre>,               <&clk_nandc>;
1894
1895                                         clock-output-names =
1896                                                 "g_clk_pvtm_core",              "g_clk_pvtm_gpu",
1897                                                 "g_clk_pvtm_func",              "clk_timer0",
1898
1899                                                 "clk_timer1",           "clk_timer2",
1900                                                 "clk_timer3",           "clk_timer4",
1901
1902                                                 "clk_timer5",           "g_hclk_spdif",
1903                                                 "g_aclk_gmac",          "g_pclk_gmac",
1904
1905                                                 "g_hclk_tsp",           "g_clkin0_tsp",
1906                                                 "g_hclk_usbhost",               "clk_nandc";
1907
1908                                         rockchip,suspend-clkgating-setting = <0x0000 0x0>;      /* pwm logic vol */
1909
1910                                         #clock-cells = <1>;
1911                                 };
1912
1913                         };
1914                 };
1915         };
1916 };