arch/arm/boot/dts/rk3126.dtsi

   1 #include "rk312x.dtsi"
   2
   3 &clk_gpll_div2 {
   4         clocks = <&dummy>;
   5 };
   6
   7 &clk_gpll_div3 {
   8         clocks = <&dummy>;
   9 };
  10
  11 &rockchip_clocks_init {
  12         rockchip,clocks-init-parent =
  13                 <&clk_core &clk_apll>, <&aclk_cpu &clk_gpll>,
  14                 <&aclk_peri &clk_gpll>, <&clk_uart0_pll &clk_gpll>,
  15                 <&clk_uart2_pll &clk_gpll>, <&clk_i2s_2ch_pll &clk_gpll>,
  16                 <&clk_i2s_8ch_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
  17                 <&clk_vepu &clk_gpll>, <&clk_vdpu &clk_gpll>,
  18                 <&clk_hevc_core &clk_gpll>, <&aclk_vio0_pre &clk_gpll>,
  19                 <&aclk_vio1_pre &clk_gpll>, <&hclk_vio_pre &clk_gpll>,
  20                 <&sclk_lcdc0 &clk_cpll>, <&clk_gpu &clk_gpll>,
  21                 <&clk_cif_pll &clk_gpll>, <&dclk_ebc &clk_gpll>,
  22                 <&clk_emmc &clk_gpll>, <&clk_sdio &clk_gpll>,
  23                 <&clk_sfc &clk_gpll>, <&clk_sdmmc0 &clk_gpll>,
  24                 <&clk_tsp &clk_gpll>, <&clk_nandc &clk_gpll>,
  25                 <&clk_mac_pll &clk_cpll>;
  26 };
  27
  28 &i2s0 {
  29         /* sdi: 0: from io, 1: from acodec */
  30         sdi_source = <1>;
  31         status = "okay";
  32 };