arch/arm/boot/dts/rk3126.dtsi

   1 #include "rk312x.dtsi"
   2
   3 &clk_gpll_div2 {
   4         clocks = <&dummy>;
   5 };
   6
   7 &clk_gpll_div3 {
   8         clocks = <&dummy>;
   9 };
  10
  11
  12 &aclk_vio0_pre_div {
  13         rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
  14 };
  15
  16 &aclk_vio1_pre_div {
  17         rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
  18 };
  19
  20 &hclk_vio_pre_div {
  21         rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
  22 };
  23
  24 &rockchip_clocks_init {
  25         rockchip,clocks-init-parent =
  26                 <&clk_core &clk_apll>, <&aclk_cpu &clk_gpll>,
  27                 <&aclk_peri &clk_gpll>, <&clk_uart0_pll &clk_gpll>,
  28                 <&clk_uart2_pll &clk_gpll>, <&clk_i2s_2ch_pll &clk_gpll>,
  29                 <&clk_i2s_8ch_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
  30                 <&clk_vepu &clk_gpll>, <&clk_vdpu &clk_gpll>,
  31                 <&clk_hevc_core &clk_gpll>,
  32                 <&sclk_lcdc0 &clk_cpll>, <&clk_gpu &clk_gpll>,
  33                 <&clk_cif_pll &clk_gpll>, <&dclk_ebc &clk_gpll>,
  34                 <&clk_emmc &clk_gpll>, <&clk_sdio &clk_gpll>,
  35                 <&clk_sfc &clk_gpll>, <&clk_sdmmc0 &clk_gpll>,
  36                 <&clk_tsp &clk_gpll>, <&clk_nandc &clk_gpll>,
  37                 <&clk_mac_pll &clk_cpll>;
  38 };
  39
  40 &i2s0 {
  41         /* sdi: 0: from io, 1: from acodec */
  42         sdi_source = <1>;
  43         status = "okay";
  44 };