arch/arm/boot/dts/rk3036.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2
   3 #include "skeleton.dtsi"
   4 #include "rk3036-clocks.dtsi"
   5 #include "rk3036-pinctrl.dtsi"
   6 #include <dt-bindings/suspend/rockchip-pm.h>
   7
   8 / {
   9         compatible = "rockchip,rk3036";
  10         rockchip,sram = <&sram>;
  11         interrupt-parent = <&gic>;
  12
  13         aliases {
  14                 serial0 = &uart0;
  15                 serial1 = &uart1;
  16                 serial2 = &uart2;
  17                 i2c0 = &i2c0;
  18                 i2c1 = &i2c1;
  19                 i2c2 = &i2c2;
  20                 spi0 = &spi0;
  21         };
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 cpu@0 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a7";
  30                         reg = <0xf00>;
  31                 };
  32                 cpu@1 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a7";
  35                         reg = <0xf01>;
  36                 };
  37         };
  38
  39         gic: interrupt-controller@10139000 {
  40                 compatible = "arm,cortex-a15-gic";
  41                 interrupt-controller;
  42                 #interrupt-cells = <3>;
  43                 #address-cells = <0>;
  44                 reg = <0x10139000 0x1000>,
  45                       <0x1013a000 0x1000>;
  46         };
  47
  48         arm-pmu {
  49                 compatible = "arm,cortex-a7-pmu";
  50                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  51                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  52         };
  53
  54         cpu_axi_bus: cpu_axi_bus {
  55                 compatible = "rockchip,cpu_axi_bus";
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 ranges;
  59
  60                 qos {
  61                         #address-cells = <1>;
  62                         #size-cells = <1>;
  63                         ranges;
  64
  65                         core {
  66                                 reg = <0x1012a000 0x20>;
  67                                 rockchip,priority = <3 2>;
  68                         };
  69                         peri {
  70                                 reg = <0x1012c000 0x20>;
  71                         };
  72                         gpu {
  73                                 reg = <0x1012d000 0x20>;
  74                         };
  75                         vpu {
  76                                 reg = <0x1012e000 0x20>;
  77                         };
  78                         hevc {
  79                                 reg = <0x1012e080 0x20>;
  80                         };
  81                         vio {
  82                                 reg = <0x1012f000 0x20>;
  83                                 rockchip,priority = <3 3>;
  84                         };
  85                 };
  86
  87                 msch {
  88                         #address-cells = <1>;
  89                         #size-cells = <1>;
  90                         ranges;
  91
  92                         msch@10128000 {
  93                                 reg = <0x10128000 0x40>;
  94                                 rockchip,read-latency = <0x80>;
  95                         };
  96                 };
  97         };
  98
  99         sram: sram@10080000 {
 100                 compatible = "mmio-sram";
 101                 reg = <0x10080000 0x2000>;
 102                 map-exec;
 103         };
 104
 105         timer {
 106                 compatible = "arm,armv7-timer";
 107                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 108                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 109                 clock-frequency = <24000000>;
 110         };
 111
 112         timer@20044000 {
 113                 compatible = "rockchip,timer";
 114                 reg = <0x20044000 0x20>;
 115                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 116                 rockchip,broadcast = <1>;
 117         };
 118
 119         watchdog: wdt@2004c000 {
 120                 compatible = "rockchip,watch dog";
 121                 reg = <0x2004c000 0x100>;
 122                 clocks = <&clk_gates7 15>;
 123                 clock-names = "pclk_wdt";
 124                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 125                 rockchip,irq = <1>;
 126                 rockchip,timeout = <60>;
 127                 rockchip,atboot = <1>;
 128                 rockchip,debug = <0>;
 129                 status = "disabled";
 130         };
 131
 132         amba {
 133                 #address-cells = <1>;
 134                 #size-cells = <1>;
 135                 compatible = "arm,amba-bus";
 136                 interrupt-parent = <&gic>;
 137                 ranges;
 138
 139                 pdma: pdma@20078000 {
 140                         compatible = "arm,pl330", "arm,primecell";
 141                         reg = <0x20078000 0x4000>;
 142                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 143                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 144                         #dma-cells = <1>;
 145                 };
 146         };
 147
 148         reset: reset@20000110{
 149                 compatible = "rockchip,reset";
 150                 reg = <0x20000110 0x24>;
 151                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 152                 #reset-cells = <1>;
 153         };
 154
 155         nandc: nandc@10500000 {
 156                 compatible = "rockchip,rk-nandc";
 157                 reg = <0x10500000 0x4000>;
 158                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 159                 //pinctrl-names = "default";
 160                 //pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
 161                 nandc_id = <0>;
 162                 clocks = <&clk_nandc>, <&clk_gates5 9>, <&clk_gates10 4>;
 163                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 164         };
 165
 166         nandc0reg: nandc0@10500000 {
 167                 compatible = "rockchip,rk-nandc";
 168                 reg = <0x10500000 0x4000>;
 169         };
 170
 171         spi0: spi@20074000 {
 172                 compatible = "rockchip,rockchip-spi";
 173                 reg = <0x20074000 0x1000>;
 174                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 175                 #address-cells = <1>;
 176                 #size-cells = <0>;
 177                 pinctrl-names = "default";
 178                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 179                 rockchip,spi-src-clk = <0>;
 180                 num-cs = <2>;
 181                 clocks =<&clk_spi0>, <&clk_gates2 9>;
 182                 clock-names = "spi","pclk_spi0";
 183                 dmas = <&pdma 8>, <&pdma 9>;
 184                 #dma-cells = <2>;
 185                 dma-names = "tx", "rx";
 186                 status = "disabled";
 187         };
 188
 189         uart0: serial@20060000 {
 190                 compatible = "rockchip,serial";
 191                 reg = <0x20060000 0x100>;
 192                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 193                 clock-frequency = <24000000>;
 194                 clocks = <&clk_uart0>, <&clk_gates8 0>;
 195                 clock-names = "sclk_uart", "pclk_uart";
 196                 reg-shift = <2>;
 197                 reg-io-width = <4>;
 198                 dmas = <&pdma 2>, <&pdma 3>;
 199                 #dma-cells = <2>;
 200                 pinctrl-names = "default";
 201                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 202                 status = "disabled";
 203         };
 204
 205         uart1: serial@20064000 {
 206                 compatible = "rockchip,serial";
 207                 reg = <0x20064000 0x100>;
 208                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 209                 clock-frequency = <24000000>;
 210                 clocks = <&clk_uart1>, <&clk_gates8 1>;
 211                 clock-names = "sclk_uart", "pclk_uart";
 212                 reg-shift = <2>;
 213                 reg-io-width = <4>;
 214                 dmas = <&pdma 4>, <&pdma 5>;
 215                 #dma-cells = <2>;
 216                 pinctrl-names = "default";
 217                 pinctrl-0 = <&uart1_xfer>;
 218                 status = "disabled";
 219         };
 220
 221         uart2: serial@20068000 {
 222                 compatible = "rockchip,serial";
 223                 reg = <0x20068000 0x100>;
 224                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 225                 clock-frequency = <24000000>;
 226                 clocks = <&clk_uart2>, <&clk_gates8 2>;
 227                 clock-names = "sclk_uart", "pclk_uart";
 228                 reg-shift = <2>;
 229                 reg-io-width = <4>;
 230                 dmas = <&pdma 6>, <&pdma 7>;
 231                 #dma-cells = <2>;
 232                 pinctrl-names = "default";
 233                 pinctrl-0 = <&uart2_xfer>;
 234                 status = "disabled";
 235         };
 236
 237         fiq-debugger {
 238                 compatible = "rockchip,fiq-debugger";
 239                 rockchip,serial-id = <2>;
 240                 rockchip,signal-irq = <106>;
 241                 rockchip,wake-irq = <0>;
 242                 status = "disabled";
 243         };
 244
 245         clocks-init{
 246                 compatible = "rockchip,clocks-init";
 247                 rockchip,clocks-init-parent =
 248                         <&clk_core &clk_apll>, <&aclk_cpu_pre &clk_gpll>,
 249                         <&aclk_peri_pre &clk_gpll>, <&clk_uart_pll &clk_gpll>,
 250                         <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
 251                         <&aclk_vcodec_pre &clk_gpll>, <&clk_hevc_core &clk_gpll>,
 252                         <&aclk_vio_pre &clk_gpll>, <&clk_mac_pll &clk_apll>;
 253                 rockchip,clocks-init-rate =
 254                         <&clk_core 1000000000>, <&clk_gpll 594000000>,
 255                         <&aclk_cpu_pre 150000000>, <&hclk_cpu_pre 75000000>,
 256                         <&pclk_cpu_pre 75000000>,        <&aclk_peri_pre 150000000>,
 257                         <&hclk_peri_pre 75000000>, <&pclk_peri_pre 75000000>,
 258                         <&clk_gpu 300000000>,    <&aclk_vio_pre 300000000>,
 259                         <&hclk_vio_pre 150000000>, <&aclk_vcodec_pre 300000000>,
 260                         <&clk_hevc_core 200000000>, <&clk_mac_pll_div 50000000>,
 261                         <&clk_mac_ref_div 25000000>;
 262         /*      rockchip,clocks-uboot-has-init =
 263                         <&aclk_vio1>;*/
 264         };
 265
 266         clocks-enable {
 267                 compatible = "rockchip,clocks-enable";
 268                 clocks =
 269                                 /*PD_CORE*/
 270                                 <&clk_gates0 0>, <&clk_gates0 7>,
 271
 272                                 /*PD_CPU*/
 273                                 <&clk_gates0 3>, <&clk_gates0 4>,
 274                                 <&clk_gates0 5>,
 275
 276                                 /*TIMER*/
 277                                 <&clk_gates1 0>, <&clk_gates1 1>,
 278                                 <&clk_gates2 4>, <&clk_gates2 5>,
 279
 280                                 /*PD_PERI*/
 281                                 <&clk_gates2 0>, <&hclk_peri_pre>,
 282                                 <&pclk_peri_pre>, <&clk_gates2 1>,
 283
 284                                 /*aclk_cpu_pre*/
 285                                 <&clk_gates4 12>,/*aclk_intmem*/
 286                                 <&clk_gates4 10>,/*aclk_strc_sys*/
 287
 288                                 /*hclk_cpu_pre*/
 289                                 <&clk_gates5 6>,/*hclk_rom*/
 290
 291                                 /*pclk_cpu_pre*/
 292                                 <&clk_gates5 4>,/*pclk_grf*/
 293                                 <&clk_gates5 7>,/*pclk_ddrupctl*/
 294                                 <&clk_gates5 14>,/*pclk_acodec*/
 295                                 <&clk_gates3 8>,/*pclk_hdmi*/
 296
 297                                 /*aclk_peri_pre*/
 298                                 <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
 299                                 <&clk_gates5 1>,/*aclk_dmac2*/
 300                                 <&clk_gates9 15>,/*aclk_peri_niu*/
 301                                 <&clk_gates4 2>,/*aclk_cpu_peri*/
 302
 303                                 /*hclk_peri_pre*/
 304                                 <&clk_gates4 0>,/*hclk_peri_matrix*/
 305                                 <&clk_gates9 13>,/*hclk_usb_peri*/
 306                                 <&clk_gates9 14>,/*hclk_peri_arbi*/
 307
 308                                 /*pclk_peri_pre*/
 309                                 <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
 310
 311                                 /*hclk_vio_pre*/
 312                                 <&clk_gates6 12>,/*hclk_vio_bus*/
 313                                 <&clk_gates9 5>,/*hclk_lcdc*/
 314
 315                                 /*aclk_vio_pre*/
 316                                 <&clk_gates6 13>,/*aclk_vio*/
 317                                 <&clk_gates9 6>,/*aclk_lcdc*/
 318
 319                                 /*UART*/
 320                                 <&clk_gates1 12>,
 321                                 <&clk_gates1 13>,
 322                                 <&clk_gates8 2>,/*pclk_uart2*/
 323
 324                                 <&clk_gpu>,
 325
 326                                 /*jtag*/
 327                                 <&clk_gates1 3>;/*clk_jtag*/
 328         };
 329
 330         i2c0: i2c@20072000 {
 331                 compatible = "rockchip,rk30-i2c";
 332                 reg = <0x20072000 0x1000>;
 333                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 334                 #address-cells = <1>;
 335                 #size-cells = <0>;
 336                 pinctrl-names = "default", "gpio";
 337                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 338                 pinctrl-1 = <&i2c0_gpio>;
 339                 gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
 340                 clocks = <&clk_gates8 4>;
 341                 rockchip,check-idle = <1>;
 342                 status = "disabled";
 343         };
 344
 345         i2c1: i2c@20056000 {
 346                 compatible = "rockchip,rk30-i2c";
 347                 reg = <0x20056000 0x1000>;
 348                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 349                 #address-cells = <1>;
 350                 #size-cells = <0>;
 351                 pinctrl-names = "default", "gpio";
 352                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 353                 pinctrl-1 = <&i2c1_gpio>;
 354                 gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
 355                 clocks = <&clk_gates8 5>;
 356                 rockchip,check-idle = <1>;
 357                 status = "disabled";
 358         };
 359
 360         i2c2: i2c@2005a000 {
 361                 compatible = "rockchip,rk30-i2c";
 362                 reg = <0x2005a000 0x1000>;
 363                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 364                 #address-cells = <1>;
 365                 #size-cells = <0>;
 366                 pinctrl-names = "default", "gpio";
 367                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 368                 pinctrl-1 = <&i2c2_gpio>;
 369                 gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
 370                 clocks = <&clk_gates8 6>;
 371                 rockchip,check-idle = <1>;
 372                 status = "disabled";
 373         };
 374
 375         i2s: i2s@10220000 {
 376                 compatible = "rockchip-i2s";
 377                 reg = <0x10220000 0x1000>;
 378                 i2s-id = <0>;
 379                 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates7 2>;
 380                 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
 381                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 382                 dmas = <&pdma 0>, <&pdma 1>;
 383                 //#dma-cells = <2>;
 384                 dma-names = "tx", "rx";
 385                 //pinctrl-names = "default", "sleep";
 386                 //pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 387                 //pinctrl-1 = <&i2s_gpio>;
 388         };
 389
 390         codec: codec@20030000 {
 391                 compatible = "rk3036-codec";
 392                 reg = <0x20030000 0x1000>;
 393                 spk_ctl_io = <&gpio1 GPIO_A0 0>;
 394                 pinctrl-names = "default";
 395                 pinctrl-0 = <&i2s0_gpio>;
 396
 397                 boot_depop = <1>;
 398                 pa_enable_time = <1000>;
 399                 clocks = <&clk_gates5 14>;
 400                 clock-names = "g_pclk_acodec";
 401         };
 402
 403         spdif: spdif@10204000 {
 404                 compatible = "rockchip-spdif";
 405                 reg = <0x10204000 0x1000>;
 406                 clocks = <&clk_spdif>;
 407                 clock-names = "spdif_mclk";
 408                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 409                 dmas = <&pdma 13>;
 410                 //#dma-cells = <1>;
 411                 dma-names = "tx";
 412                 pinctrl-names = "default";
 413                 pinctrl-0 = <&spdif_tx>;
 414         };
 415
 416         pwm0: pwm@20050000 {
 417                 compatible = "rockchip,rk-pwm";
 418                 reg = <0x20050000 0x10>;
 419                 #pwm-cells = <2>;
 420                 pinctrl-names = "default";
 421                 pinctrl-0 = <&pwm0_pin>;
 422                 clocks = <&clk_gates7 10>;
 423                 clock-names = "pclk_pwm";
 424                 status = "disabled";
 425         };
 426
 427         pwm1: pwm@20050010 {
 428                 compatible = "rockchip,rk-pwm";
 429                 reg = <0x20050010 0x10>;
 430                 #pwm-cells = <2>;
 431                 pinctrl-names = "default";
 432                 pinctrl-0 = <&pwm1_pin>;
 433                 clocks = <&clk_gates7 10>;
 434                 clock-names = "pclk_pwm";
 435                 status = "disabled";
 436         };
 437
 438         pwm2: pwm@20050020 {
 439                 compatible = "rockchip,rk-pwm";
 440                 reg = <0x20050020 0x10>;
 441                 #pwm-cells = <2>;
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&pwm2_pin>;
 444                 clocks = <&clk_gates7 10>;
 445                 clock-names = "pclk_pwm";
 446                 status = "disabled";
 447         };
 448
 449         pwm3: pwm@20050030 {
 450                 compatible = "rockchip,rk-pwm";
 451                 reg = <0x20050030 0x10>;
 452                 #pwm-cells = <2>;
 453                 pinctrl-names = "default";
 454                 pinctrl-0 = <&pwm3_pin>;
 455                 clocks = <&clk_gates7 10>;
 456                 clock-names = "pclk_pwm";
 457                 status = "disabled";
 458         };
 459
 460         remotectl: pwm@20050030 {
 461                 compatible = "rockchip,remotectl-pwm";
 462                 reg = <0x20050030 0x10>;
 463                 #pwm-cells = <2>;
 464                 pinctrl-names = "default";
 465                 pinctrl-0 = <&pwm3_pin>;
 466                 clocks = <&clk_gates7 10>;
 467                 clock-names = "pclk_pwm";
 468                 remote_pwm_id = <3>;
 469                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 470                 status = "okay";
 471         };
 472
 473         emmc: rksdmmc@1021c000 {
 474                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 475                 reg = <0x1021c000 0x4000>;
 476                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 477                 #address-cells = <1>;
 478                 #size-cells = <0>;
 479                 //pinctrl-names = "default",,"suspend";
 480                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 481                 clocks = <&clk_emmc>, <&clk_gates7 0>;
 482                 clock-names = "clk_mmc", "hclk_mmc";
 483                 dmas = <&pdma 12>;
 484                 dma-names = "dw_mci";
 485                 num-slots = <1>;
 486                 fifo-depth = <0x100>;
 487                 bus-width = <8>;
 488         };
 489
 490
 491         sdmmc: rksdmmc@10214000 {
 492                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 493                 reg = <0x10214000 0x4000>;
 494                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 495                 #address-cells = <1>;
 496                 #size-cells = <0>;
 497                 pinctrl-names = "default", "idle", "udbg";
 498                 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 499                 pinctrl-1 = <&sdmmc0_gpio>;
 500                 pinctrl-2 = <&uart2_xfer>;
 501                 cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 502                 clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
 503                 clock-names = "clk_mmc", "hclk_mmc";
 504                 dmas = <&pdma 10>;
 505                 dma-names = "dw_mci";
 506                 num-slots = <1>;
 507                 fifo-depth = <0x100>;
 508                 bus-width = <4>;
 509         };
 510
 511         sdio: rksdmmc@10218000 {
 512                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 513                 reg = <0x10218000 0x4000>;
 514                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 515                 #address-cells = <1>;
 516                 #size-cells = <0>;
 517                 pinctrl-names = "default","idle";
 518                 pinctrl-0 = <&sdio0_clk &sdio0_cmd  &sdio0_bus4>;
 519                 pinctrl-1 = <&sdio0_gpio>;
 520                 clocks = <&clk_sdio>, <&clk_gates5 11>;
 521                 clock-names = "clk_mmc", "hclk_mmc";
 522                 dmas = <&pdma 11>;
 523                 dma-names = "dw_mci";
 524                 num-slots = <1>;
 525                 fifo-depth = <0x100>;
 526                 bus-width = <4>;
 527         };
 528         gpu {
 529                 compatible = "arm,mali400";
 530                 reg = <0x10091000 0x200>,
 531                           <0x10090000 0x100>,
 532                           <0x10093000 0x100>,
 533                           <0x10098000 0x1100>,
 534                           <0x10094000 0x100>;
 535                 reg-names = "Mali_L2",
 536                                         "Mali_GP",
 537                                         "Mali_GP_MMU",
 538                                         "Mali_PP0",
 539                                         "Mali_PP0_MMU";
 540
 541             interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 542                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 543                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 544                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 545             interrupt-names = "Mali_GP_IRQ",
 546                                                   "Mali_GP_MMU_IRQ",
 547                                                   "Mali_PP0_IRQ",
 548                                                   "Mali_PP0_MMU_IRQ";
 549           };
 550         dwc_control_usb: dwc-control-usb@20008000 {
 551                 compatible = "rockchip,rk3036-dwc-control-usb";
 552                 reg = <0x20008000 0x4>;
 553                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 554                 interrupt-names = "otg_bvalid";
 555                 clocks = <&clk_gates9 13>;
 556                 clock-names = "hclk_usb_peri";
 557                 rockchip,remote_wakeup;
 558                 rockchip,usb_irq_wakeup;
 559                 resets = <&reset RK3036_RST_USBPOR>;
 560                 reset-names = "usbphy_por";
 561                 usb_bc{
 562                         compatible = "rockchip,ctrl";
 563                         rk_usb,bvalid   = <0x14c 8 1>;
 564                         rk_usb,iddig    = <0x14c 11 1>;
 565                         rk_usb,line     = <0x14c 9 2>;
 566                         rk_usb,softctrl = <0x17c 0 1>;
 567                         rk_usb,opmode   = <0x17c 2 2>;
 568                         rk_usb,xcvrsel  = <0x17c 4 2>;
 569                         rk_usb,termsel  = <0x17c 6 1>;
 570                 };
 571         };
 572         usb0: usb@10180000 {
 573                 compatible = "rockchip,rk3036_usb20_otg";
 574                 reg = <0x10180000 0x40000>;
 575                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 576                 clocks = <&clk_gates1 5>, <&clk_gates5 13>;
 577                 clock-names = "clk_usbphy0", "hclk_usb0";
 578                 resets = <&reset RK3036_RST_USBOTG0>, <&reset RK3036_RST_UTMI0>,
 579                                 <&reset RK3036_RST_OTGC0>;
 580                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
 581                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
 582                 rockchip,usb-mode = <0>;
 583         };
 584
 585         usb1: usb@101c0000 {
 586                 compatible = "rockchip,rk3036_usb20_host";
 587                 reg = <0x101c0000 0x40000>;
 588                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 589                 clocks = <&clk_gates1 6>, <&clk_gates7 3>;
 590                 clock-names = "clk_usbphy1", "hclk_usb1";
 591                 resets = <&reset RK3036_RST_USBOTG1>, <&reset RK3036_RST_UTMI1>,
 592                                 <&reset RK3036_RST_OTGC1>;
 593                 reset-names = "host_ahb", "host_phy", "host_controller";
 594         };
 595
 596         fb: fb{
 597                 compatible = "rockchip,rk-fb";
 598                 rockchip,disp-mode = <NO_DUAL>;
 599         };
 600
 601         rk_screen: rk_screen{
 602                 compatible = "rockchip,screen";
 603         };
 604
 605         lcdc: lcdc@10118000 {
 606                 compatible = "rockchip,rk3036-lcdc";
 607                 reg = <0x10118000 0x1000>;
 608                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 609                 status = "disabled";
 610                 clocks = <&clk_gates9 6>, <&dclk_lcdc1>, <&clk_gates9 5>;
 611                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 612                 rockchip,iommu-enabled = <1>;
 613         };
 614
 615         hdmi: hdmi@20034000 {
 616                 compatible = "rockchip,rk3036-hdmi";
 617                 reg = <0x20034000 0x4000>;
 618                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 619                 rockchip,hdmi_lcdc_source = <0>;
 620                 pinctrl-names = "default", "gpio";
 621                 pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
 622                 pinctrl-1 = <&hdmi_gpio>;
 623                 clocks = <&clk_gates3 8>;
 624                 clock-names = "pclk_hdmi";
 625                 status = "disabled";
 626         };
 627
 628         tve: tve{
 629                 compatible = "rockchip,rk3036-tve";
 630                 reg = <0x10118200 0x100>;
 631                 status = "disabled";
 632         };
 633
 634         ion {
 635                 compatible = "rockchip,ion";
 636                 #address-cells = <1>;
 637                 #size-cells = <0>;
 638
 639                 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
 640                         compatible = "rockchip,ion-reserve";
 641                         rockchip,ion_heap = <1>;
 642                         reg = <0x00000000 0x00000000>; /* 0MB */
 643                 };
 644                 rockchip,ion-heap@3 { /* VMALLOC HEAP */
 645                         rockchip,ion_heap = <3>;
 646                 };
 647         };
 648
 649         vpu: vpu_service@10108000 {
 650                 compatible = "vpu_service";
 651                 iommu_enabled = <1>;
 652                 reg = <0x10108000 0x800>;
 653                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 654                 interrupt-names = "irq_dec";
 655                 clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>;
 656                 clock-names = "aclk_vcodec", "hclk_vcodec";
 657                 name = "vpu_service";
 658                 status = "okay";
 659         };
 660
 661         hevc: hevc_service@1010c000 {
 662                 compatible = "rockchip,hevc_service";
 663                 iommu_enabled = <1>;
 664                 reg = <0x1010c000 0x400>;
 665                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 666                 interrupt-names = "irq_dec";
 667                 clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>, <&clk_hevc_core>;
 668                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
 669                 name = "hevc_service";
 670                 status = "okay";
 671         };
 672
 673         vop_mmu {
 674                 dbgname = "vop";
 675                 compatible = "rockchip,vop_mmu";
 676                 reg = <0x10118300 0x100>;
 677                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 678                 interrupt-names = "vop_mmu";
 679         };
 680
 681         hevc_mmu {
 682                 dbgname = "hevc";
 683                 compatible = "rockchip,hevc_mmu";
 684                 reg = <0x1010c440 0x40>,
 685                       <0x1010c480 0x40>;
 686                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 687                 interrupt-names = "hevc_mmu";
 688         };
 689
 690         vpu_mmu {
 691                 dbgname = "vpu";
 692                 compatible = "rockchip,vpu_mmu";
 693                 reg = <0x10108800 0x100>;
 694                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 695                 interrupt-names = "vpu_mmu";
 696         };
 697
 698         rockchip_suspend {
 699                 rockchip,ctrbits = <
 700                         (0
 701                          //|RKPM_CTR_PWR_DMNS
 702                         |RKPM_CTR_GTCLKS
 703                         |RKPM_CTR_PLLS
 704                         |RKPM_CTR_IDLESRAM_MD
 705                         |RKPM_CTR_DDR
 706                         |RKPM_CTR_VOLTS
 707                         |RKPM_CTR_VOL_PWM2
 708
 709                         //|RKPM_CTR_GPIOS
 710                         //|RKPM_CTR_SYSCLK_DIV
 711                         //|RKPM_CTR_IDLEAUTO_MD
 712                         //|RKPM_CTR_ARMOFF_LPMD
 713                         //|RKPM_CTR_ARMOFF_LOGDP_LPMD
 714                         )
 715                         >;
 716 /*
 717                 rockchip,pmic-suspend_gpios = <
 718                         RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H)
 719                         >;
 720                 rockchip,pmic-resume_gpios = <
 721                         RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN)
 722                         >;
 723 */
 724         };
 725
 726         vmac: eth@10200000 {
 727                 compatible = "rockchip,vmac";
 728                 reg = <0x10200000 0x4000>;
 729                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 730                 interrupt-names = "macirq";
 731                 clocks = <&clk_mac_pll>, <&clk_mac_ref>,
 732                         <&clk_mac_pll_div>, <&clk_mac_ref_div>,
 733                         <&clk_gates2 6>, <&clk_gates3 5>;
 734                 clock-names = "clk_mac_pll", "clk_mac_ref",
 735                           "clk_mac_pll_div", "clk_mac_ref_div",
 736                           "clk_tx_rx_gate", "hclk_mac";
 737                 pinctrl-names = "default";
 738                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_crs &mac_mdpins>;
 739         };
 740 };