arch/arm/boot/dts/rk3036.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2
   3 #include "skeleton.dtsi"
   4 #include "rk3036-clocks.dtsi"
   5 #include "rk3036-pinctrl.dtsi"
   6
   7 / {
   8         compatible = "rockchip,rk3036";
   9         rockchip,sram = <&sram>;
  10         interrupt-parent = <&gic>;
  11
  12         aliases {
  13                 serial0 = &uart0;
  14                 serial1 = &uart1;
  15                 serial2 = &uart2;
  16                 i2c0 = &i2c0;
  17                 i2c1 = &i2c1;
  18                 i2c2 = &i2c2;
  19                 spi0 = &spi0;
  20         };
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a7";
  29                         reg = <0xf00>;
  30                 };
  31                 cpu@1 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a7";
  34                         reg = <0xf01>;
  35                 };
  36         };
  37
  38         gic: interrupt-controller@10139000 {
  39                 compatible = "arm,cortex-a15-gic";
  40                 interrupt-controller;
  41                 #interrupt-cells = <3>;
  42                 #address-cells = <0>;
  43                 reg = <0x10139000 0x1000>,
  44                       <0x1013a000 0x1000>;
  45         };
  46
  47         arm-pmu {
  48                 compatible = "arm,cortex-a7-pmu";
  49                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  50                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  51         };
  52
  53         sram: sram@10080000 {
  54                 compatible = "mmio-sram";
  55                 reg = <0x10080000 0x2000>;
  56                 map-exec;
  57         };
  58
  59         timer {
  60                 compatible = "arm,armv7-timer";
  61                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  62                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  63                 clock-frequency = <24000000>;
  64         };
  65
  66         watchdog: wdt@2004c000 {
  67                 compatible = "rockchip,watch dog";
  68                 reg = <0x2004c000 0x100>;
  69                 clocks = <&clk_gates7 15>;
  70                 clock-names = "pclk_wdt";
  71                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  72                 rockchip,irq = <1>;
  73                 rockchip,timeout = <60>;
  74                 rockchip,atboot = <1>;
  75                 rockchip,debug = <0>;
  76                 status = "disabled";
  77         };
  78
  79         amba {
  80                 #address-cells = <1>;
  81                 #size-cells = <1>;
  82                 compatible = "arm,amba-bus";
  83                 interrupt-parent = <&gic>;
  84                 ranges;
  85
  86                 pdma: pdma@20078000 {
  87                         compatible = "arm,pl330", "arm,primecell";
  88                         reg = <0x20078000 0x4000>;
  89                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  90                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  91                         #dma-cells = <1>;
  92                 };
  93         };
  94
  95         nandc: nandc@10500000 {
  96                 compatible = "rockchip,rk-nandc";
  97                 reg = <0x10500000 0x4000>;
  98                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
  99                 nandc_id = <0>;
 100                 clocks = <&clk_nandc>, <&clk_gates5 9>;
 101                 clock-names = "clk_nandc", "hclk_nandc";
 102         };
 103
 104         spi0: spi@20074000 {
 105                 compatible = "rockchip,rockchip-spi";
 106                 reg = <0x20074000 0x1000>;
 107                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 108                 #address-cells = <1>;
 109                 #size-cells = <0>;
 110                 //pinctrl-names = "default";
 111                 //pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 112                 rockchip,spi-src-clk = <0>;
 113                 num-cs = <2>;
 114                 //clocks =<&clk_spi0>, <&clk_gates7 12>;
 115                 //clock-names = "spi","pclk_spi0";
 116                 //dmas = <&pdma 8>, <&pdma 9>;
 117                 //#dma-cells = <2>;
 118                 //dma-names = "tx", "rx";
 119                 status = "disabled";
 120         };
 121
 122         uart0: serial@20060000 {
 123                 compatible = "rockchip,serial";
 124                 reg = <0x20060000 0x100>;
 125                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 126                 clock-frequency = <24000000>;
 127                 clocks = <&clk_uart0>, <&clk_gates8 0>;
 128                 clock-names = "sclk_uart", "pclk_uart";
 129                 reg-shift = <2>;
 130                 reg-io-width = <4>;
 131                 dmas = <&pdma 2>, <&pdma 3>;
 132                 #dma-cells = <2>;
 133                 //pinctrl-names = "default";
 134                 //pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 135                 status = "disabled";
 136         };
 137
 138         uart1: serial@20064000 {
 139                 compatible = "rockchip,serial";
 140                 reg = <0x20064000 0x100>;
 141                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 142                 clock-frequency = <24000000>;
 143                 clocks = <&clk_uart1>, <&clk_gates8 1>;
 144                 clock-names = "sclk_uart", "pclk_uart";
 145                 reg-shift = <2>;
 146                 reg-io-width = <4>;
 147                 dmas = <&pdma 4>, <&pdma 5>;
 148                 #dma-cells = <2>;
 149                 //pinctrl-names = "default";
 150                 //pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 151                 status = "disabled";
 152         };
 153
 154         uart2: serial@20068000 {
 155                 compatible = "rockchip,serial";
 156                 reg = <0x20068000 0x100>;
 157                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 158                 clock-frequency = <24000000>;
 159                 clocks = <&clk_uart2>, <&clk_gates8 2>;
 160                 clock-names = "sclk_uart", "pclk_uart";
 161                 reg-shift = <2>;
 162                 reg-io-width = <4>;
 163                 dmas = <&pdma 6>, <&pdma 7>;
 164                 #dma-cells = <2>;
 165                 //pinctrl-names = "default";
 166                 //pinctrl-0 = <&uart2_xfer>;
 167                 status = "disabled";
 168         };
 169
 170         fiq-debugger {
 171                 compatible = "rockchip,fiq-debugger";
 172                 rockchip,serial-id = <2>;
 173                 rockchip,signal-irq = <106>;
 174                 rockchip,wake-irq = <0>;
 175                 status = "disabled";
 176         };
 177
 178         i2c0: i2c@20072000 {
 179                 compatible = "rockchip,rk30-i2c";
 180                 reg = <0x20072000 0x1000>;
 181                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 182                 #address-cells = <1>;
 183                 #size-cells = <0>;
 184                 //pinctrl-names = "default", "gpio";
 185                 //pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 186                 //pinctrl-1 = <&i2c0_gpio>;
 187                 //gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 188                 clocks = <&clk_gates8 4>;
 189                 rockchip,check-idle = <1>;
 190                 status = "disabled";
 191         };
 192
 193         i2c1: i2c@20056000 {
 194                 compatible = "rockchip,rk30-i2c";
 195                 reg = <0x20056000 0x1000>;
 196                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 197                 #address-cells = <1>;
 198                 #size-cells = <0>;
 199                 //pinctrl-names = "default", "gpio";
 200                 //pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 201                 //pinctrl-1 = <&i2c1_gpio>;
 202                 //gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 203                 clocks = <&clk_gates8 5>;
 204                 rockchip,check-idle = <1>;
 205                 status = "disabled";
 206         };
 207
 208         i2c2: i2c@2005a000 {
 209                 compatible = "rockchip,rk30-i2c";
 210                 reg = <0x2005a000 0x1000>;
 211                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 212                 #address-cells = <1>;
 213                 #size-cells = <0>;
 214                 //pinctrl-names = "default", "gpio";
 215                 //pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 216                 //pinctrl-1 = <&i2c2_gpio>;
 217                 //gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 218                 clocks = <&clk_gates8 6>;
 219                 rockchip,check-idle = <1>;
 220                 status = "disabled";
 221         };
 222
 223         i2s: i2s@10220000 {
 224                 compatible = "rockchip-i2s";
 225                 reg = <0x10220000 0x1000>;
 226                 i2s-id = <0>;
 227                 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates7 2>;
 228                 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
 229                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 230                 dmas = <&pdma 0>, <&pdma 1>;
 231                 //#dma-cells = <2>;
 232                 dma-names = "tx", "rx";
 233                 //pinctrl-names = "default", "sleep";
 234                 //pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 235                 //pinctrl-1 = <&i2s_gpio>;
 236         };
 237
 238         spdif: spdif@10204000 {
 239                 compatible = "rockchip-spdif";
 240                 reg = <0x10204000 0x1000>;
 241                 clocks = <&clk_spdif>;
 242                 clock-names = "spdif_mclk";
 243                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 244                 dmas = <&pdma 13>;
 245                 //#dma-cells = <1>;
 246                 dma-names = "tx";
 247                 //pinctrl-names = "default";
 248                 //pinctrl-0 = <&spdif_tx>;
 249         };
 250
 251         pwm0: pwm@20050000 {
 252                 compatible = "rockchip,rk-pwm";
 253                 reg = <0x20050000 0x10>;
 254                 #pwm-cells = <2>;
 255                 //pinctrl-names = "default";
 256                 //pinctrl-0 = <&pwm_pin>;
 257                 clocks = <&clk_gates7 10>;
 258                 clock-names = "pclk_pwm";
 259                 status = "disabled";
 260         };
 261
 262         pwm1: pwm@20050010 {
 263                 compatible = "rockchip,rk-pwm";
 264                 reg = <0x20050010 0x10>;
 265                 #pwm-cells = <2>;
 266                 //pinctrl-names = "default";
 267                 //pinctrl-0 = <&pwm_pin>;
 268                 clocks = <&clk_gates7 10>;
 269                 clock-names = "pclk_pwm";
 270                 status = "disabled";
 271         };
 272
 273         pwm2: pwm@20050020 {
 274                 compatible = "rockchip,rk-pwm";
 275                 reg = <0x20050020 0x10>;
 276                 #pwm-cells = <2>;
 277                 //pinctrl-names = "default";
 278                 //pinctrl-0 = <&pwm_pin>;
 279                 clocks = <&clk_gates7 10>;
 280                 clock-names = "pclk_pwm";
 281                 status = "disabled";
 282         };
 283
 284         pwm3: pwm@20050030 {
 285                 compatible = "rockchip,rk-pwm";
 286                 reg = <0x20050030 0x10>;
 287                 #pwm-cells = <2>;
 288                 //pinctrl-names = "default";
 289                 //pinctrl-0 = <&pwm_pin>;
 290                 clocks = <&clk_gates7 10>;
 291                 clock-names = "pclk_pwm";
 292                 status = "disabled";
 293         };
 294
 295         emmc: rksdmmc@1021c000 {
 296                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 297                 reg = <0x1021c000 0x4000>;
 298                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 299                 #address-cells = <1>;
 300                 #size-cells = <0>;
 301                 //pinctrl-names = "default",,"suspend";
 302                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 303                 clocks = <&clk_emmc>, <&clk_gates7 0>;
 304                 clock-names = "clk_mmc", "hclk_mmc";
 305                 num-slots = <1>;
 306                 fifo-depth = <0x100>;
 307                 bus-width = <8>;
 308         };
 309
 310
 311         sdmmc: rksdmmc@10214000 {
 312                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 313                 reg = <0x10214000 0x4000>;
 314                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 315                 #address-cells = <1>;
 316                 #size-cells = <0>;
 317                 //pinctrl-names = "default", "idle";
 318                 //pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 319                 //pinctrl-1 = <&sdmmc0_gpio>;
 320                 //cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 321                 clocks = <&clk_sdmmc0>, <&clk_gates2 11>;
 322                 clock-names = "clk_mmc", "hclk_mmc";
 323                 num-slots = <1>;
 324                 fifo-depth = <0x100>;
 325                 bus-width = <4>;
 326         };
 327
 328         sdio: rksdmmc@10218000 {
 329                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 330                 reg = <0x10218000 0x4000>;
 331                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 332                 #address-cells = <1>;
 333                 #size-cells = <0>;
 334                 //pinctrl-names = "default","idle";
 335                 //pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_wrprt &sdio_pwr &sdio_bkpwr &sdio_intn &sdio_bus4>;
 336                 //pinctrl-1 = <&sdio_gpio>;
 337                 clocks = <&clk_sdio>, <&clk_gates5 11>;
 338                 clock-names = "clk_mmc", "hclk_mmc";
 339                 num-slots = <1>;
 340                 fifo-depth = <0x100>;
 341                 bus-width = <4>;
 342         };
 343         gpu {
 344                 compatible = "arm,mali400";
 345                 reg = <0x10091000 0x200>,
 346                           <0x10090000 0x100>,
 347                           <0x10093000 0x100>,
 348                           <0x10098000 0x1100>,
 349                           <0x10094000 0x100>;
 350                 reg-names = "Mali_L2",
 351                                         "Mali_GP",
 352                                         "Mali_GP_MMU",
 353                                         "Mali_PP0",
 354                                         "Mali_PP0_MMU";
 355
 356             interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 357                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 358                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 359                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 360             interrupt-names = "Mali_GP_IRQ",
 361                                                   "Mali_GP_MMU_IRQ",
 362                                                   "Mali_PP0_IRQ",
 363                                                   "Mali_PP0_MMU_IRQ";
 364           };
 365         dwc_control_usb: dwc-control-usb@20008000 {
 366                 compatible = "rockchip,rk3188-dwc-control-usb";
 367                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 368                 interrupt-names = "otg_bvalid";
 369                 //gpios = <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D5 GPIO_ACTIVE_LOW>;
 370                 clocks = <&clk_gates9 13>;
 371                 clock-names = "hclk_usb_peri";
 372                 rockchip,remote_wakeup;
 373                 rockchip,usb_irq_wakeup;
 374
 375                 usb_bc{
 376                         compatible = "rockchip,ctrl";
 377                         rk_usb,bvalid   = <0x14c 8 1>;
 378                         rk_usb,iddig    = <0x14c 11 1>;
 379                         rk_usb,line     = <0x14c 9 2>;
 380                         rk_usb,softctrl = <0x17c 0 1>;
 381                         rk_usb,opmode   = <0x17c 2 2>;
 382                         rk_usb,xcvrsel  = <0x17c 4 2>;
 383                         rk_usb,termsel  = <0x118 6 1>;
 384                 };
 385         };
 386         usb0: usb@10180000 {
 387                 compatible = "rockchip,rk3188_usb20_otg";
 388                 reg = <0x10180000 0x40000>;
 389                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 390                 clocks = <&clk_gates1 5>, <&clk_gates5 13>;
 391                 clock-names = "clk_usbphy0", "hclk_usb0";
 392                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
 393                 rockchip,usb-mode = <0>;
 394         };
 395
 396         usb1: usb@101c0000 {
 397                 compatible = "rockchip,rk3188_usb20_host";
 398                 reg = <0x101c0000 0x40000>;
 399                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 400                 clocks = <&clk_gates1 6>, <&clk_gates7 3>;
 401                 clock-names = "clk_usbphy1", "hclk_usb1";
 402         };
 403
 404         hdmi: hdmi@20034000 {
 405                 compatible = "rockchip,rk3036-hdmi";
 406                 reg = <0x20034000 0x4000>;
 407                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 408                 rockchip,hdmi_lcdc_source = <0>;
 409                 pinctrl-names = "default", "gpio";
 410                 pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
 411                 pinctrl-1 = <&hdmi_gpio>;
 412                 clocks = <&clk_gates3 8>;
 413                 clock-names = "pclk_hdmi";
 414                 status = "disabled";
 415         };
 416
 417         vpu: vpu_service@10108000 {
 418                 compatible = "vpu_service";
 419                 reg = <0x10108000 0x800>;
 420                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 421                 interrupt-names = "irq_enc", "irq_dec";
 422                 clocks = <&clk_vdpu>, <&hclk_vdpu>;
 423                 clock-names = "aclk_vcodec", "hclk_vcodec";
 424                 name = "vpu_service";
 425                 status = "disabled";
 426         };
 427
 428         hevc: hevc_service@1010c000 {
 429                 compatible = "rockchip,hevc_service";
 430                 reg = <0x1010c000 0x800>;
 431                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 432                 interrupt-names = "irq_dec";
 433                 clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
 434                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
 435                 name = "hevc_service";
 436                 status = "disabled";
 437
 438         vop_mmu {
 439                 dbgname = "vop";
 440                 compatible = "iommu,vop_mmu";
 441                 reg = <0x10118300 0x100>;
 442                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 443                 interrupt-names = "vop_mmu";
 444         };
 445
 446         hevc_mmu {
 447                 dbgname = "hevc";
 448                 compatible = "iommu,hevc_mmu";
 449                 reg = <0x1010c440 0x100>,
 450                       <0x1010c480 0x100>;
 451                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 452                 interrupt-names = "hevc_mmu";
 453         };
 454
 455         vpu_mmu {
 456                 dbgname = "vpu";
 457                 compatible = "iommu,vpu_mmu";
 458                 reg = <0x10108800 0x100>;
 459                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 460                 interrupt-names = "vpu_mmu";
 461         };
 462 };