arch/arm/boot/dts/rk3036.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3036-cru.h>
  46 #include "skeleton.dtsi"
  47
  48 / {
  49         compatible = "rockchip,rk3036";
  50
  51         interrupt-parent = <&gic>;
  52
  53         aliases {
  54                 i2c0 = &i2c0;
  55                 i2c1 = &i2c1;
  56                 i2c2 = &i2c2;
  57                 mshc0 = &emmc;
  58                 mshc1 = &sdmmc;
  59                 mshc2 = &sdio;
  60                 serial0 = &uart0;
  61                 serial1 = &uart1;
  62                 serial2 = &uart2;
  63                 spi = &spi;
  64         };
  65
  66         memory {
  67                 device_type = "memory";
  68                 reg = <0x60000000 0x40000000>;
  69         };
  70
  71         cpus {
  72                 #address-cells = <1>;
  73                 #size-cells = <0>;
  74                 enable-method = "rockchip,rk3036-smp";
  75
  76                 cpu0: cpu@f00 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a7";
  79                         reg = <0xf00>;
  80                         resets = <&cru SRST_CORE0>;
  81                         operating-points = <
  82                                 /* KHz    uV */
  83                                  816000 1000000
  84                         >;
  85                         clock-latency = <40000>;
  86                         clocks = <&cru ARMCLK>;
  87                 };
  88
  89                 cpu1: cpu@f01 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a7";
  92                         reg = <0xf01>;
  93                         resets = <&cru SRST_CORE1>;
  94                 };
  95         };
  96
  97         amba {
  98                 compatible = "arm,amba-bus";
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101                 ranges;
 102
 103                 pdma: pdma@20078000 {
 104                         compatible = "arm,pl330", "arm,primecell";
 105                         reg = <0x20078000 0x4000>;
 106                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 107                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 108                         #dma-cells = <1>;
 109                         clocks = <&cru ACLK_DMAC2>;
 110                         clock-names = "apb_pclk";
 111                 };
 112         };
 113
 114         arm-pmu {
 115                 compatible = "arm,cortex-a7-pmu";
 116                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 117                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 118                 interrupt-affinity = <&cpu0>, <&cpu1>;
 119         };
 120
 121         display-subsystem {
 122                 compatible = "rockchip,display-subsystem";
 123                 ports = <&vop_out>;
 124         };
 125
 126         timer {
 127                 compatible = "arm,armv7-timer";
 128                 arm,cpu-registers-not-fw-configured;
 129                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 130                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 131                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
 132                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 133                 clock-frequency = <24000000>;
 134         };
 135
 136         xin24m: oscillator {
 137                 compatible = "fixed-clock";
 138                 clock-frequency = <24000000>;
 139                 clock-output-names = "xin24m";
 140                 #clock-cells = <0>;
 141         };
 142
 143         bus_intmem@10080000 {
 144                 compatible = "mmio-sram";
 145                 reg = <0x10080000 0x2000>;
 146                 #address-cells = <1>;
 147                 #size-cells = <1>;
 148                 ranges = <0 0x10080000 0x2000>;
 149
 150                 smp-sram@0 {
 151                         compatible = "rockchip,rk3066-smp-sram";
 152                         reg = <0x00 0x10>;
 153                 };
 154         };
 155
 156         vop: vop@10118000 {
 157                 compatible = "rockchip,rk3036-vop";
 158                 reg = <0x10118000 0x19c>;
 159                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 160                 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
 161                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 162                 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
 163                 reset-names = "axi", "ahb", "dclk";
 164                 iommus = <&vop_mmu>;
 165                 status = "disabled";
 166
 167                 vop_out: port {
 168                         #address-cells = <1>;
 169                         #size-cells = <0>;
 170                         vop_out_hdmi: endpoint@0 {
 171                                 reg = <0>;
 172                                 remote-endpoint = <&hdmi_in_vop>;
 173                         };
 174                 };
 175         };
 176
 177         vop_mmu: iommu@10118300 {
 178                 compatible = "rockchip,iommu";
 179                 reg = <0x10118300 0x100>;
 180                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 181                 interrupt-names = "vop_mmu";
 182                 #iommu-cells = <0>;
 183                 status = "disabled";
 184         };
 185
 186         gic: interrupt-controller@10139000 {
 187                 compatible = "arm,gic-400";
 188                 interrupt-controller;
 189                 #interrupt-cells = <3>;
 190                 #address-cells = <0>;
 191
 192                 reg = <0x10139000 0x1000>,
 193                       <0x1013a000 0x1000>,
 194                       <0x1013c000 0x2000>,
 195                       <0x1013e000 0x2000>;
 196                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 197         };
 198
 199         usb_otg: usb@10180000 {
 200                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 201                                 "snps,dwc2";
 202                 reg = <0x10180000 0x40000>;
 203                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 204                 clocks = <&cru HCLK_OTG0>;
 205                 clock-names = "otg";
 206                 dr_mode = "otg";
 207                 g-np-tx-fifo-size = <16>;
 208                 g-rx-fifo-size = <275>;
 209                 g-tx-fifo-size = <256 128 128 64 64 32>;
 210                 g-use-dma;
 211                 status = "disabled";
 212         };
 213
 214         usb_host: usb@101c0000 {
 215                 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 216                                 "snps,dwc2";
 217                 reg = <0x101c0000 0x40000>;
 218                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&cru HCLK_OTG1>;
 220                 clock-names = "otg";
 221                 dr_mode = "host";
 222                 status = "disabled";
 223         };
 224
 225         emac: ethernet@10200000 {
 226                 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
 227                 reg = <0x10200000 0x4000>;
 228                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 229                 #address-cells = <1>;
 230                 #size-cells = <0>;
 231                 rockchip,grf = <&grf>;
 232                 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
 233                 clock-names = "hclk", "macref", "macclk";
 234                 /*
 235                  * Fix the emac parent clock is DPLL instead of APLL.
 236                  * since that will cause some unstable things if the cpufreq
 237                  * is working. (e.g: the accurate 50MHz what mac_ref need)
 238                  */
 239                 assigned-clocks = <&cru SCLK_MACPLL>;
 240                 assigned-clock-parents = <&cru PLL_DPLL>;
 241                 max-speed = <100>;
 242                 phy-mode = "rmii";
 243                 status = "disabled";
 244         };
 245
 246         sdmmc: dwmmc@10214000 {
 247                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 248                 reg = <0x10214000 0x4000>;
 249                 clock-frequency = <37500000>;
 250                 clock-freq-min-max = <400000 37500000>;
 251                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 252                 clock-names = "biu", "ciu";
 253                 fifo-depth = <0x100>;
 254                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 255                 status = "disabled";
 256         };
 257
 258         sdio: dwmmc@10218000 {
 259                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 260                 reg = <0x10218000 0x4000>;
 261                 clock-freq-min-max = <400000 37500000>;
 262                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 263                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 264                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 265                 fifo-depth = <0x100>;
 266                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 267                 status = "disabled";
 268         };
 269
 270         emmc: dwmmc@1021c000 {
 271                 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 272                 reg = <0x1021c000 0x4000>;
 273                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 274                 bus-width = <8>;
 275                 cap-mmc-highspeed;
 276                 clock-frequency = <37500000>;
 277                 clock-freq-min-max = <400000 37500000>;
 278                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 279                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 280                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 281                 default-sample-phase = <158>;
 282                 disable-wp;
 283                 dmas = <&pdma 12>;
 284                 dma-names = "rx-tx";
 285                 fifo-depth = <0x100>;
 286                 mmc-ddr-1_8v;
 287                 non-removable;
 288                 num-slots = <1>;
 289                 pinctrl-names = "default";
 290                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 291                 status = "disabled";
 292         };
 293
 294         i2s: i2s@10220000 {
 295                 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
 296                 reg = <0x10220000 0x4000>;
 297                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 298                 #address-cells = <1>;
 299                 #size-cells = <0>;
 300                 clock-names = "i2s_clk", "i2s_hclk";
 301                 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
 302                 dmas = <&pdma 0>, <&pdma 1>;
 303                 dma-names = "tx", "rx";
 304                 pinctrl-names = "default";
 305                 pinctrl-0 = <&i2s_bus>;
 306                 status = "disabled";
 307         };
 308
 309         cru: clock-controller@20000000 {
 310                 compatible = "rockchip,rk3036-cru";
 311                 reg = <0x20000000 0x1000>;
 312                 rockchip,grf = <&grf>;
 313                 #clock-cells = <1>;
 314                 #reset-cells = <1>;
 315                 assigned-clocks = <&cru PLL_GPLL>;
 316                 assigned-clock-rates = <594000000>;
 317         };
 318
 319         grf: syscon@20008000 {
 320                 compatible = "rockchip,rk3036-grf", "syscon";
 321                 reg = <0x20008000 0x1000>;
 322         };
 323
 324         acodec: acodec-ana@20030000 {
 325                 compatible = "rk3036-codec";
 326                 reg = <0x20030000 0x4000>;
 327                 rockchip,grf = <&grf>;
 328                 clock-names = "acodec_pclk";
 329                 clocks = <&cru PCLK_ACODEC>;
 330                 status = "disabled";
 331         };
 332
 333         hdmi: hdmi@20034000 {
 334                 compatible = "rockchip,rk3036-inno-hdmi";
 335                 reg = <0x20034000 0x4000>;
 336                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 337                 clocks = <&cru  PCLK_HDMI>;
 338                 clock-names = "pclk";
 339                 rockchip,grf = <&grf>;
 340                 pinctrl-names = "default";
 341                 pinctrl-0 = <&hdmi_ctl>;
 342                 status = "disabled";
 343
 344                 hdmi_in: port {
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                         hdmi_in_vop: endpoint@0 {
 348                                 reg = <0>;
 349                                 remote-endpoint = <&vop_out_hdmi>;
 350                         };
 351                 };
 352         };
 353
 354         timer: timer@20044000 {
 355                 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
 356                 reg = <0x20044000 0x20>;
 357                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 358                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 359                 clock-names = "timer", "pclk";
 360         };
 361
 362         pwm0: pwm@20050000 {
 363                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 364                 reg = <0x20050000 0x10>;
 365                 #pwm-cells = <3>;
 366                 clocks = <&cru PCLK_PWM>;
 367                 clock-names = "pwm";
 368                 pinctrl-names = "default";
 369                 pinctrl-0 = <&pwm0_pin>;
 370                 status = "disabled";
 371         };
 372
 373         pwm1: pwm@20050010 {
 374                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 375                 reg = <0x20050010 0x10>;
 376                 #pwm-cells = <3>;
 377                 clocks = <&cru PCLK_PWM>;
 378                 clock-names = "pwm";
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&pwm1_pin>;
 381                 status = "disabled";
 382         };
 383
 384         pwm2: pwm@20050020 {
 385                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 386                 reg = <0x20050020 0x10>;
 387                 #pwm-cells = <3>;
 388                 clocks = <&cru PCLK_PWM>;
 389                 clock-names = "pwm";
 390                 pinctrl-names = "default";
 391                 pinctrl-0 = <&pwm2_pin>;
 392                 status = "disabled";
 393         };
 394
 395         pwm3: pwm@20050030 {
 396                 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
 397                 reg = <0x20050030 0x10>;
 398                 #pwm-cells = <2>;
 399                 clocks = <&cru PCLK_PWM>;
 400                 clock-names = "pwm";
 401                 pinctrl-names = "default";
 402                 pinctrl-0 = <&pwm3_pin>;
 403                 status = "disabled";
 404         };
 405
 406         i2c1: i2c@20056000 {
 407                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 408                 reg = <0x20056000 0x1000>;
 409                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 410                 #address-cells = <1>;
 411                 #size-cells = <0>;
 412                 clock-names = "i2c";
 413                 clocks = <&cru PCLK_I2C1>;
 414                 pinctrl-names = "default";
 415                 pinctrl-0 = <&i2c1_xfer>;
 416                 status = "disabled";
 417         };
 418
 419         i2c2: i2c@2005a000 {
 420                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 421                 reg = <0x2005a000 0x1000>;
 422                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 423                 #address-cells = <1>;
 424                 #size-cells = <0>;
 425                 clock-names = "i2c";
 426                 clocks = <&cru PCLK_I2C2>;
 427                 pinctrl-names = "default";
 428                 pinctrl-0 = <&i2c2_xfer>;
 429                 status = "disabled";
 430         };
 431
 432         uart0: serial@20060000 {
 433                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 434                 reg = <0x20060000 0x100>;
 435                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 436                 reg-shift = <2>;
 437                 reg-io-width = <4>;
 438                 clock-frequency = <24000000>;
 439                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 440                 clock-names = "baudclk", "apb_pclk";
 441                 pinctrl-names = "default";
 442                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 443                 status = "disabled";
 444         };
 445
 446         uart1: serial@20064000 {
 447                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 448                 reg = <0x20064000 0x100>;
 449                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 450                 reg-shift = <2>;
 451                 reg-io-width = <4>;
 452                 clock-frequency = <24000000>;
 453                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 454                 clock-names = "baudclk", "apb_pclk";
 455                 pinctrl-names = "default";
 456                 pinctrl-0 = <&uart1_xfer>;
 457                 status = "disabled";
 458         };
 459
 460         uart2: serial@20068000 {
 461                 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
 462                 reg = <0x20068000 0x100>;
 463                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 464                 reg-shift = <2>;
 465                 reg-io-width = <4>;
 466                 clock-frequency = <24000000>;
 467                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 468                 clock-names = "baudclk", "apb_pclk";
 469                 pinctrl-names = "default";
 470                 pinctrl-0 = <&uart2_xfer>;
 471                 status = "disabled";
 472         };
 473
 474         i2c0: i2c@20072000 {
 475                 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 476                 reg = <0x20072000 0x1000>;
 477                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 478                 #address-cells = <1>;
 479                 #size-cells = <0>;
 480                 clock-names = "i2c";
 481                 clocks = <&cru PCLK_I2C0>;
 482                 pinctrl-names = "default";
 483                 pinctrl-0 = <&i2c0_xfer>;
 484                 status = "disabled";
 485         };
 486
 487         spi: spi@20074000 {
 488                 compatible = "rockchip,rockchip-spi";
 489                 reg = <0x20074000 0x1000>;
 490                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 491                 clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
 492                 clock-names = "apb-pclk","spi_pclk";
 493                 dmas = <&pdma 8>, <&pdma 9>;
 494                 dma-names = "tx", "rx";
 495                 pinctrl-names = "default";
 496                 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
 497                 #address-cells = <1>;
 498                 #size-cells = <0>;
 499                 status = "disabled";
 500         };
 501
 502         pinctrl: pinctrl {
 503                 compatible = "rockchip,rk3036-pinctrl";
 504                 rockchip,grf = <&grf>;
 505                 #address-cells = <1>;
 506                 #size-cells = <1>;
 507                 ranges;
 508
 509                 gpio0: gpio0@2007c000 {
 510                         compatible = "rockchip,gpio-bank";
 511                         reg = <0x2007c000 0x100>;
 512                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 513                         clocks = <&cru PCLK_GPIO0>;
 514
 515                         gpio-controller;
 516                         #gpio-cells = <2>;
 517
 518                         interrupt-controller;
 519                         #interrupt-cells = <2>;
 520                 };
 521
 522                 gpio1: gpio1@20080000 {
 523                         compatible = "rockchip,gpio-bank";
 524                         reg = <0x20080000 0x100>;
 525                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 526                         clocks = <&cru PCLK_GPIO1>;
 527
 528                         gpio-controller;
 529                         #gpio-cells = <2>;
 530
 531                         interrupt-controller;
 532                         #interrupt-cells = <2>;
 533                 };
 534
 535                 gpio2: gpio2@20084000 {
 536                         compatible = "rockchip,gpio-bank";
 537                         reg = <0x20084000 0x100>;
 538                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 539                         clocks = <&cru PCLK_GPIO2>;
 540
 541                         gpio-controller;
 542                         #gpio-cells = <2>;
 543
 544                         interrupt-controller;
 545                         #interrupt-cells = <2>;
 546                 };
 547
 548                 pcfg_pull_default: pcfg_pull_default {
 549                         bias-pull-pin-default;
 550                 };
 551
 552                 pcfg_pull_none: pcfg-pull-none {
 553                         bias-disable;
 554                 };
 555
 556                 pwm0 {
 557                         pwm0_pin: pwm0-pin {
 558                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
 559                         };
 560                 };
 561
 562                 pwm1 {
 563                         pwm1_pin: pwm1-pin {
 564                                 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
 565                         };
 566                 };
 567
 568                 pwm2 {
 569                         pwm2_pin: pwm2-pin {
 570                                 rockchip,pins = <0 1 2 &pcfg_pull_none>;
 571                         };
 572                 };
 573
 574                 pwm3 {
 575                         pwm3_pin: pwm3-pin {
 576                                 rockchip,pins = <0 27 1 &pcfg_pull_none>;
 577                         };
 578                 };
 579
 580                 sdmmc {
 581                         sdmmc_clk: sdmmc-clk {
 582                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
 583                         };
 584
 585                         sdmmc_cmd: sdmmc-cmd {
 586                                 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
 587                         };
 588
 589                         sdmmc_cd: sdmcc-cd {
 590                                 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
 591                         };
 592
 593                         sdmmc_bus1: sdmmc-bus1 {
 594                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
 595                         };
 596
 597                         sdmmc_bus4: sdmmc-bus4 {
 598                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
 599                                                 <1 19 RK_FUNC_1 &pcfg_pull_default>,
 600                                                 <1 20 RK_FUNC_1 &pcfg_pull_default>,
 601                                                 <1 21 RK_FUNC_1 &pcfg_pull_default>;
 602                         };
 603                 };
 604
 605                 sdio {
 606                         sdio_bus1: sdio-bus1 {
 607                                 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
 608                         };
 609
 610                         sdio_bus4: sdio-bus4 {
 611                                 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
 612                                                 <0 12 RK_FUNC_1 &pcfg_pull_default>,
 613                                                 <0 13 RK_FUNC_1 &pcfg_pull_default>,
 614                                                 <0 14 RK_FUNC_1 &pcfg_pull_default>;
 615                         };
 616
 617                         sdio_cmd: sdio-cmd {
 618                                 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
 619                         };
 620
 621                         sdio_clk: sdio-clk {
 622                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
 623                         };
 624                 };
 625
 626                 emmc {
 627                         /*
 628                          * We run eMMC at max speed; bump up drive strength.
 629                          * We also have external pulls, so disable the internal ones.
 630                          */
 631                         emmc_clk: emmc-clk {
 632                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
 633                         };
 634
 635                         emmc_cmd: emmc-cmd {
 636                                 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
 637                         };
 638
 639                         emmc_bus8: emmc-bus8 {
 640                                 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
 641                                                 <1 25 RK_FUNC_2 &pcfg_pull_default>,
 642                                                 <1 26 RK_FUNC_2 &pcfg_pull_default>,
 643                                                 <1 27 RK_FUNC_2 &pcfg_pull_default>,
 644                                                 <1 28 RK_FUNC_2 &pcfg_pull_default>,
 645                                                 <1 29 RK_FUNC_2 &pcfg_pull_default>,
 646                                                 <1 30 RK_FUNC_2 &pcfg_pull_default>,
 647                                                 <1 31 RK_FUNC_2 &pcfg_pull_default>;
 648                         };
 649                 };
 650
 651                 emac {
 652                         emac_xfer: emac-xfer {
 653                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
 654                                                 <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
 655                                                 <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
 656                                                 <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
 657                                                 <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
 658                                                 <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
 659                                                 <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
 660                                                 <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
 661                         };
 662
 663                         emac_mdio: emac-mdio {
 664                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
 665                                                 <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
 666                         };
 667                 };
 668
 669                 i2c0 {
 670                         i2c0_xfer: i2c0-xfer {
 671                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
 672                                                 <0 1 RK_FUNC_1 &pcfg_pull_none>;
 673                         };
 674                 };
 675
 676                 i2c1 {
 677                         i2c1_xfer: i2c1-xfer {
 678                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
 679                                                 <0 3 RK_FUNC_1 &pcfg_pull_none>;
 680                         };
 681                 };
 682
 683                 i2c2 {
 684                         i2c2_xfer: i2c2-xfer {
 685                                 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
 686                                                 <2 21 RK_FUNC_1 &pcfg_pull_none>;
 687                         };
 688                 };
 689
 690                 i2s {
 691                         i2s_bus: i2s-bus {
 692                                 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
 693                                                 <1 1 RK_FUNC_1 &pcfg_pull_default>,
 694                                                 <1 2 RK_FUNC_1 &pcfg_pull_default>,
 695                                                 <1 3 RK_FUNC_1 &pcfg_pull_default>,
 696                                                 <1 4 RK_FUNC_1 &pcfg_pull_default>,
 697                                                 <1 5 RK_FUNC_1 &pcfg_pull_default>;
 698                         };
 699                 };
 700
 701                 hdmi {
 702                         hdmi_ctl: hdmi-ctl {
 703                                 rockchip,pins = <1 8  RK_FUNC_1 &pcfg_pull_none>,
 704                                                 <1 9  RK_FUNC_1 &pcfg_pull_none>,
 705                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>,
 706                                                 <1 11 RK_FUNC_1 &pcfg_pull_none>;
 707                         };
 708                 };
 709
 710                 uart0 {
 711                         uart0_xfer: uart0-xfer {
 712                                 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
 713                                                 <0 17 RK_FUNC_1 &pcfg_pull_none>;
 714                         };
 715
 716                         uart0_cts: uart0-cts {
 717                                 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
 718                         };
 719
 720                         uart0_rts: uart0-rts {
 721                                 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
 722                         };
 723                 };
 724
 725                 uart1 {
 726                         uart1_xfer: uart1-xfer {
 727                                 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
 728                                                 <2 23 RK_FUNC_1 &pcfg_pull_none>;
 729                         };
 730                         /* no rts / cts for uart1 */
 731                 };
 732
 733                 uart2 {
 734                         uart2_xfer: uart2-xfer {
 735                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
 736                                                 <1 19 RK_FUNC_2 &pcfg_pull_none>;
 737                         };
 738                         /* no rts / cts for uart2 */
 739                 };
 740
 741                 spi {
 742                         spi_txd:spi-txd {
 743                                 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
 744                         };
 745
 746                         spi_rxd:spi-rxd {
 747                                 rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
 748                         };
 749
 750                         spi_clk:spi-clk {
 751                                 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
 752                         };
 753
 754                         spi_cs0:spi-cs0 {
 755                                 rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
 756
 757                         };
 758
 759                         spi_cs1:spi-cs1 {
 760                                 rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;
 761
 762                         };
 763                 };
 764         };
 765 };