arch/arm/boot/dts/rk3036.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2
   3 #include "skeleton.dtsi"
   4 #include "rk3036-clocks.dtsi"
   5
   6 / {
   7         compatible = "rockchip,rk3036";
   8         rockchip,sram = <&sram>;
   9         interrupt-parent = <&gic>;
  10
  11         aliases {
  12                 serial0 = &uart0;
  13                 serial1 = &uart1;
  14                 serial2 = &uart2;
  15                 i2c0 = &i2c0;
  16                 i2c1 = &i2c1;
  17                 i2c2 = &i2c2;
  18                 spi0 = &spi0;
  19         };
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu@0 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a7";
  28                         reg = <0xf00>;
  29                 };
  30                 cpu@1 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a7";
  33                         reg = <0xf01>;
  34                 };
  35         };
  36
  37         gic: interrupt-controller@10139000 {
  38                 compatible = "arm,cortex-a15-gic";
  39                 interrupt-controller;
  40                 #interrupt-cells = <3>;
  41                 #address-cells = <0>;
  42                 reg = <0x10139000 0x1000>,
  43                       <0x1013a000 0x1000>;
  44         };
  45
  46         arm-pmu {
  47                 compatible = "arm,cortex-a7-pmu";
  48                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  49                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  50         };
  51
  52         sram: sram@10080000 {
  53                 compatible = "mmio-sram";
  54                 reg = <0x10080000 0x2000>;
  55                 map-exec;
  56         };
  57
  58         timer {
  59                 compatible = "arm,armv7-timer";
  60                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  61                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  62                 clock-frequency = <24000000>;
  63         };
  64
  65         watchdog: wdt@2004c000 {
  66                 compatible = "rockchip,watch dog";
  67                 reg = <0x2004c000 0x100>;
  68                 clocks = <&clk_gates7 15>;
  69                 clock-names = "pclk_wdt";
  70                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  71                 rockchip,irq = <1>;
  72                 rockchip,timeout = <60>;
  73                 rockchip,atboot = <1>;
  74                 rockchip,debug = <0>;
  75                 status = "disabled";
  76         };
  77
  78         amba {
  79                 #address-cells = <1>;
  80                 #size-cells = <1>;
  81                 compatible = "arm,amba-bus";
  82                 interrupt-parent = <&gic>;
  83                 ranges;
  84
  85                 pdma: pdma@20078000 {
  86                         compatible = "arm,pl330", "arm,primecell";
  87                         reg = <0x20078000 0x4000>;
  88                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  89                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  90                         #dma-cells = <1>;
  91                 };
  92         };
  93
  94         nandc: nandc@10500000 {
  95                 compatible = "rockchip,rk-nandc";
  96                 reg = <0x10500000 0x4000>;
  97                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
  98                 nandc_id = <0>;
  99                 clocks = <&clk_nandc>, <&clk_gates5 9>;
 100                 clock-names = "clk_nandc", "hclk_nandc";
 101         };
 102
 103         spi0: spi@20074000 {
 104                 compatible = "rockchip,rockchip-spi";
 105                 reg = <0x20074000 0x1000>;
 106                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 107                 #address-cells = <1>;
 108                 #size-cells = <0>;
 109                 //pinctrl-names = "default";
 110                 //pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 111                 rockchip,spi-src-clk = <0>;
 112                 num-cs = <2>;
 113                 //clocks =<&clk_spi0>, <&clk_gates7 12>;
 114                 //clock-names = "spi","pclk_spi0";
 115                 //dmas = <&pdma 8>, <&pdma 9>;
 116                 //#dma-cells = <2>;
 117                 //dma-names = "tx", "rx";
 118                 status = "disabled";
 119         };
 120
 121         uart0: serial@20060000 {
 122                 compatible = "rockchip,serial";
 123                 reg = <0x20060000 0x100>;
 124                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 125                 clock-frequency = <24000000>;
 126                 clocks = <&clk_uart0>, <&clk_gates8 0>;
 127                 clock-names = "sclk_uart", "pclk_uart";
 128                 reg-shift = <2>;
 129                 reg-io-width = <4>;
 130                 dmas = <&pdma 2>, <&pdma 3>;
 131                 #dma-cells = <2>;
 132                 //pinctrl-names = "default";
 133                 //pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 134                 status = "disabled";
 135         };
 136
 137         uart1: serial@20064000 {
 138                 compatible = "rockchip,serial";
 139                 reg = <0x20064000 0x100>;
 140                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 141                 clock-frequency = <24000000>;
 142                 clocks = <&clk_uart1>, <&clk_gates8 1>;
 143                 clock-names = "sclk_uart", "pclk_uart";
 144                 reg-shift = <2>;
 145                 reg-io-width = <4>;
 146                 dmas = <&pdma 4>, <&pdma 5>;
 147                 #dma-cells = <2>;
 148                 //pinctrl-names = "default";
 149                 //pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 150                 status = "disabled";
 151         };
 152
 153         uart2: serial@20068000 {
 154                 compatible = "rockchip,serial";
 155                 reg = <0x20068000 0x100>;
 156                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 157                 clock-frequency = <24000000>;
 158                 clocks = <&clk_uart2>, <&clk_gates8 2>;
 159                 clock-names = "sclk_uart", "pclk_uart";
 160                 reg-shift = <2>;
 161                 reg-io-width = <4>;
 162                 dmas = <&pdma 6>, <&pdma 7>;
 163                 #dma-cells = <2>;
 164                 //pinctrl-names = "default";
 165                 //pinctrl-0 = <&uart2_xfer>;
 166                 status = "disabled";
 167         };
 168
 169         fiq-debugger {
 170                 compatible = "rockchip,fiq-debugger";
 171                 rockchip,serial-id = <2>;
 172                 rockchip,signal-irq = <106>;
 173                 rockchip,wake-irq = <0>;
 174                 status = "disabled";
 175         };
 176
 177         i2c0: i2c@20072000 {
 178                 compatible = "rockchip,rk30-i2c";
 179                 reg = <0x20072000 0x1000>;
 180                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 181                 #address-cells = <1>;
 182                 #size-cells = <0>;
 183                 //pinctrl-names = "default", "gpio";
 184                 //pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 185                 //pinctrl-1 = <&i2c0_gpio>;
 186                 //gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 187                 clocks = <&clk_gates8 4>;
 188                 rockchip,check-idle = <1>;
 189                 status = "disabled";
 190         };
 191
 192         i2c1: i2c@20056000 {
 193                 compatible = "rockchip,rk30-i2c";
 194                 reg = <0x20056000 0x1000>;
 195                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 196                 #address-cells = <1>;
 197                 #size-cells = <0>;
 198                 //pinctrl-names = "default", "gpio";
 199                 //pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 200                 //pinctrl-1 = <&i2c1_gpio>;
 201                 //gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 202                 clocks = <&clk_gates8 5>;
 203                 rockchip,check-idle = <1>;
 204                 status = "disabled";
 205         };
 206
 207         i2c2: i2c@2005a000 {
 208                 compatible = "rockchip,rk30-i2c";
 209                 reg = <0x2005a000 0x1000>;
 210                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 211                 #address-cells = <1>;
 212                 #size-cells = <0>;
 213                 //pinctrl-names = "default", "gpio";
 214                 //pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 215                 //pinctrl-1 = <&i2c2_gpio>;
 216                 //gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 217                 clocks = <&clk_gates8 6>;
 218                 rockchip,check-idle = <1>;
 219                 status = "disabled";
 220         };
 221
 222         i2s: i2s@10220000 {
 223                 compatible = "rockchip-i2s";
 224                 reg = <0x10220000 0x1000>;
 225                 i2s-id = <0>;
 226                 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates7 2>;
 227                 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
 228                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 229                 dmas = <&pdma 0>, <&pdma 1>;
 230                 //#dma-cells = <2>;
 231                 dma-names = "tx", "rx";
 232                 //pinctrl-names = "default", "sleep";
 233                 //pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 234                 //pinctrl-1 = <&i2s_gpio>;
 235         };
 236
 237         spdif: spdif@10204000 {
 238                 compatible = "rockchip-spdif";
 239                 reg = <0x10204000 0x1000>;
 240                 clocks = <&clk_spdif>;
 241                 clock-names = "spdif_mclk";
 242                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 243                 dmas = <&pdma 13>;
 244                 //#dma-cells = <1>;
 245                 dma-names = "tx";
 246                 //pinctrl-names = "default";
 247                 //pinctrl-0 = <&spdif_tx>;
 248         };
 249
 250         pwm0: pwm@20050000 {
 251                 compatible = "rockchip,rk-pwm";
 252                 reg = <0x20050000 0x10>;
 253                 #pwm-cells = <2>;
 254                 //pinctrl-names = "default";
 255                 //pinctrl-0 = <&pwm_pin>;
 256                 clocks = <&clk_gates7 10>;
 257                 clock-names = "pclk_pwm";
 258                 status = "disabled";
 259         };
 260
 261         pwm1: pwm@20050010 {
 262                 compatible = "rockchip,rk-pwm";
 263                 reg = <0x20050010 0x10>;
 264                 #pwm-cells = <2>;
 265                 //pinctrl-names = "default";
 266                 //pinctrl-0 = <&pwm_pin>;
 267                 clocks = <&clk_gates7 10>;
 268                 clock-names = "pclk_pwm";
 269                 status = "disabled";
 270         };
 271
 272         pwm2: pwm@20050020 {
 273                 compatible = "rockchip,rk-pwm";
 274                 reg = <0x20050020 0x10>;
 275                 #pwm-cells = <2>;
 276                 //pinctrl-names = "default";
 277                 //pinctrl-0 = <&pwm_pin>;
 278                 clocks = <&clk_gates7 10>;
 279                 clock-names = "pclk_pwm";
 280                 status = "disabled";
 281         };
 282
 283         pwm3: pwm@20050030 {
 284                 compatible = "rockchip,rk-pwm";
 285                 reg = <0x20050030 0x10>;
 286                 #pwm-cells = <2>;
 287                 //pinctrl-names = "default";
 288                 //pinctrl-0 = <&pwm_pin>;
 289                 clocks = <&clk_gates7 10>;
 290                 clock-names = "pclk_pwm";
 291                 status = "disabled";
 292         };
 293
 294         emmc: rksdmmc@1021c000 {
 295                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 296                 reg = <0x1021c000 0x4000>;
 297                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 298                 #address-cells = <1>;
 299                 #size-cells = <0>;
 300                 //pinctrl-names = "default",,"suspend";
 301                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 302                 clocks = <&clk_emmc>, <&clk_gates7 0>;
 303                 clock-names = "clk_mmc", "hclk_mmc";
 304                 num-slots = <1>;
 305                 fifo-depth = <0x100>;
 306                 bus-width = <8>;
 307         };
 308
 309
 310         sdmmc: rksdmmc@10214000 {
 311                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 312                 reg = <0x10214000 0x4000>;
 313                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 314                 #address-cells = <1>;
 315                 #size-cells = <0>;
 316                 //pinctrl-names = "default", "idle";
 317                 //pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 318                 //pinctrl-1 = <&sdmmc0_gpio>;
 319                 //cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 320                 clocks = <&clk_sdmmc0>, <&clk_gates2 11>;
 321                 clock-names = "clk_mmc", "hclk_mmc";
 322                 num-slots = <1>;
 323                 fifo-depth = <0x100>;
 324                 bus-width = <4>;
 325         };
 326
 327         sdio: rksdmmc@10218000 {
 328                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 329                 reg = <0x10218000 0x4000>;
 330                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 331                 #address-cells = <1>;
 332                 #size-cells = <0>;
 333                 //pinctrl-names = "default","idle";
 334                 //pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_wrprt &sdio_pwr &sdio_bkpwr &sdio_intn &sdio_bus4>;
 335                 //pinctrl-1 = <&sdio_gpio>;
 336                 clocks = <&clk_sdio>, <&clk_gates5 11>;
 337                 clock-names = "clk_mmc", "hclk_mmc";
 338                 num-slots = <1>;
 339                 fifo-depth = <0x100>;
 340                 bus-width = <4>;
 341         };
 342         gpu {
 343                       compatible = "arm,mali400";
 344                       reg = <0x10090000 0x10000>;
 345                   interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 346                            <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
 347                                                    <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 348                           interrupt-names = "GP", "MMU", "PP";
 349           };
 350
 351 };